| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 404 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
408 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
412 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
416 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
421 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
425 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
429 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
433 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
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| D | ARMISelLowering.cpp | 142 setOperationAction(ISD::SREM, VT, Expand); in addTypeForNEON()
783 setOperationAction(ISD::SREM, MVT::i32, Expand); in ARMTargetLowering()
787 setOperationAction(ISD::SREM, MVT::i64, Custom); in ARMTargetLowering()
6860 case ISD::SREM: return LowerREM(Op.getNode(), DAG); in LowerOperation()
6922 case ISD::SREM: in ReplaceNodeResults()
11524 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemLibcall()
11527 N->getOpcode() == ISD::SREM; in getDivRemLibcall()
11542 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemArgList()
11545 N->getOpcode() == ISD::SREM; in getDivRemArgList()
11616 bool isSigned = N->getOpcode() == ISD::SREM; in LowerREM()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDILISelLowering.cpp | 119 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand); in InitAMDILLowering()
655 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM8()
673 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS); in LowerSREM16()
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| D | AMDGPUISelLowering.cpp | 90 case ISD::SREM: return LowerSREM(Op, DAG); in LowerOperation()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
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| /external/llvm/test/CodeGen/ARM/ |
| D | divmod-eabi.ll | 3 ; Both "none-eabi" and "androideabi" must lower SREM/UREM to __aeabi_{u,i}divmod
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1662 case ISD::SREM: in selectDivRem()
1683 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
1786 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
1787 return selectDivRem(I, ISD::SREM); in fastSelectInstruction()
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| D | MipsSEISelLowering.cpp | 170 setOperationAction(ISD::SREM, MVT::i32, Legal); in MipsSETargetLowering()
217 setOperationAction(ISD::SREM, MVT::i64, Legal); in MipsSETargetLowering()
267 setOperationAction(ISD::SREM, Ty, Legal); in addMSAIntType()
2024 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| D | MipsISelLowering.cpp | 315 setOperationAction(ISD::SREM, MVT::i32, Expand); in MipsTargetLowering()
319 setOperationAction(ISD::SREM, MVT::i64, Expand); in MipsTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 182 case ISD::SREM: return "srem"; in getOperationName()
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| D | SelectionDAGBuilder.h | 782 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); } in visitSRem()
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| D | LegalizeVectorOps.cpp | 266 case ISD::SREM: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 125 case ISD::SREM: in ScalarizeVectorResult()
685 case ISD::SREM: in SplitVectorResult()
2053 case ISD::SREM: in WidenVectorResult()
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| D | SelectionDAG.cpp | 2417 case ISD::SREM: in computeKnownBits()
3217 case ISD::SREM: in FoldValue()
3486 case ISD::SREM: in getNode()
3814 case ISD::SREM: in getNode()
3842 case ISD::SREM: in getNode()
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| D | LegalizeDAG.cpp | 3450 case ISD::SREM: { in ExpandNode()
3452 bool isSigned = Node->getOpcode() == ISD::SREM; in ExpandNode()
4161 case ISD::SREM: in ConvertNodeToLibcall()
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| D | FastISel.cpp | 1561 return selectBinaryOp(I, ISD::SREM); in selectOperator()
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| D | LegalizeIntegerTypes.cpp | 122 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N); break; in PromoteIntegerResult()
1325 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break; in ExpandIntegerResult()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 119 setOperationAction(ISD::SREM, MVT::i64, Expand); in BPFTargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 155 setOperationAction(ISD::SREM, MVT::i8, Expand); in MSP430TargetLowering()
161 setOperationAction(ISD::SREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 888 case ISD::SREM: in canOpTrap()
1564 case SRem: return ISD::SREM; in InstructionOpcodeToISD()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4441 case ISD::SREM: in selectRem()
4889 if (!selectBinaryOp(I, ISD::SREM)) in fastSelectInstruction()
4890 return selectRem(I, ISD::SREM); in fastSelectInstruction()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1690 { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1749 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC, in HexagonTargetLowering()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 242 setOperationAction(ISD::SREM, VT, Expand); in AMDGPUTargetLowering()
313 setOperationAction(ISD::SREM, VT, Expand); in AMDGPUTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1510 setOperationAction(ISD::SREM, MVT::i32, Expand); in SparcTargetLowering()
1517 setOperationAction(ISD::SREM, MVT::i64, Expand); in SparcTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 371 def srem : SDNode<"ISD::SREM" , SDTIntBinOp>;
|