| /external/llvm/lib/Target/ARM/ |
| D | ARMTargetTransformInfo.cpp | 405 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost}, in getArithmeticInstrCost()
409 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
413 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
417 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
422 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost}, in getArithmeticInstrCost()
426 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost}, in getArithmeticInstrCost()
430 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost}, in getArithmeticInstrCost()
434 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost}, in getArithmeticInstrCost()
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| D | ARMISelLowering.cpp | 143 setOperationAction(ISD::UREM, VT, Expand); in addTypeForNEON()
784 setOperationAction(ISD::UREM, MVT::i32, Expand); in ARMTargetLowering()
788 setOperationAction(ISD::UREM, MVT::i64, Custom); in ARMTargetLowering()
6861 case ISD::UREM: return LowerREM(Op.getNode(), DAG); in LowerOperation()
6923 case ISD::UREM: in ReplaceNodeResults()
11524 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemLibcall()
11542 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) && in getDivRemArgList()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 195 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | AMDGPUISelLowering.cpp | 41 setOperationAction(ISD::UREM, MVT::i32, Expand); in AMDGPUTargetLowering()
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| D | AMDILISelLowering.cpp | 725 SDValue r20 = DAG.getNode(ISD::UREM, DL, OVT, r0, r1); in LowerSREM32()
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| /external/llvm/test/CodeGen/ARM/ |
| D | divmod-eabi.ll | 3 ; Both "none-eabi" and "androideabi" must lower SREM/UREM to __aeabi_{u,i}divmod
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| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 1666 case ISD::UREM: in selectDivRem()
1683 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM) in selectDivRem()
1790 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
1791 return selectDivRem(I, ISD::UREM); in fastSelectInstruction()
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| D | MipsSEISelLowering.cpp | 171 setOperationAction(ISD::UREM, MVT::i32, Legal); in MipsSETargetLowering()
218 setOperationAction(ISD::UREM, MVT::i64, Legal); in MipsSETargetLowering()
273 setOperationAction(ISD::UREM, Ty, Legal); in addMSAIntType()
2030 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), in lowerINTRINSIC_WO_CHAIN()
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| D | MipsISelLowering.cpp | 317 setOperationAction(ISD::UREM, MVT::i32, Expand); in MipsTargetLowering()
321 setOperationAction(ISD::UREM, MVT::i64, Expand); in MipsTargetLowering()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 183 case ISD::UREM: return "urem"; in getOperationName()
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| D | SelectionDAGBuilder.h | 781 void visitURem(const User &I) { visitBinary(I, ISD::UREM); } in visitURem()
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| D | FastISel.cpp | 439 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) && in selectBinaryOp()
1563 return selectBinaryOp(I, ISD::UREM); in selectOperator()
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| D | LegalizeVectorOps.cpp | 267 case ISD::UREM: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 128 case ISD::UREM: in ScalarizeVectorResult()
684 case ISD::UREM: in SplitVectorResult()
2054 case ISD::UREM: in WidenVectorResult()
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| D | SelectionDAG.cpp | 2441 case ISD::UREM: { in computeKnownBits()
3209 case ISD::UREM: in FoldValue()
3481 case ISD::UREM: in getNode()
3813 case ISD::UREM: in getNode()
3841 case ISD::UREM: in getNode()
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| D | LegalizeIntegerTypes.cpp | 125 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break; in PromoteIntegerResult()
1328 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break; in ExpandIntegerResult()
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| /external/llvm/lib/Target/BPF/ |
| D | BPFISelLowering.cpp | 120 setOperationAction(ISD::UREM, MVT::i64, Expand); in BPFTargetLowering()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 152 setOperationAction(ISD::UREM, MVT::i8, Expand); in MSP430TargetLowering()
158 setOperationAction(ISD::UREM, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 889 case ISD::UREM: in canOpTrap()
1563 case URem: return ISD::UREM; in InstructionOpcodeToISD()
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| /external/llvm/docs/ |
| D | ExtendingLLVM.rst | 110 legal operations. The case for ``ISD::UREM`` for expanding a remainder into
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| /external/llvm/lib/Target/AMDGPU/ |
| D | AMDGPUISelLowering.cpp | 273 setOperationAction(ISD::UREM, MVT::i32, Expand); in AMDGPUTargetLowering()
314 setOperationAction(ISD::UREM, VT, Expand); in AMDGPUTargetLowering()
1682 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo); in LowerUDIVREM64()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64FastISel.cpp | 4444 case ISD::UREM: in selectRem()
4893 if (!selectBinaryOp(I, ISD::UREM)) in fastSelectInstruction()
4894 return selectRem(I, ISD::UREM); in fastSelectInstruction()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1690 { ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM, in HexagonTargetLowering()
1749 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::ADDC, in HexagonTargetLowering()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 1509 setOperationAction(ISD::UREM, MVT::i32, Expand); in SparcTargetLowering()
1516 setOperationAction(ISD::UREM, MVT::i64, Expand); in SparcTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 372 def urem : SDNode<"ISD::UREM" , SDTIntBinOp>;
|