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Searched refs:getKillRegState (Results 1 – 25 of 48) sorted by relevance

12

/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp298 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
306 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
310 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
321 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
338 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
342 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
386 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
389 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
392 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
395 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset()
118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg()
119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp54 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
64 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
91 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
DMLxExpansionPass.cpp294 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction()
295 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction()
305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction()
306 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction()
308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
DARMLoadStoreOptimizer.cpp690 .addReg(Base, getKillRegState(KillOldBase)); in CreateLoadStoreMulti()
693 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti()
703 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4) in CreateLoadStoreMulti()
708 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset) in CreateLoadStoreMulti()
712 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset) in CreateLoadStoreMulti()
752 .addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
762 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti()
768 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
788 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second)) in CreateLoadStoreDouble()
789 .addReg(Regs[1].first, getKillRegState(Regs[1].second)); in CreateLoadStoreDouble()
[all …]
DARMBaseInstrInfo.cpp677 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
695 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyToCPSR()
711 .addReg(SrcReg, getKillRegState(KillSrc)))); in copyPhysReg()
732 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
734 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
864 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
868 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
876 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
881 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
892 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
[all …]
DThumb2InstrInfo.cpp121 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
142 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
155 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI); in storeRegToStackSlot()
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp382 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstructionImpl()
383 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstructionImpl()
864 .addReg(CRReg), getKillRegState(KillSrc); in copyPhysReg()
876 .addReg(SrcReg), getKillRegState(KillSrc); in copyPhysReg()
881 .addReg(SrcReg), getKillRegState(KillSrc); in copyPhysReg()
923 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
925 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
944 getKillRegState(isKill)), in StoreRegToStackSlot()
950 getKillRegState(isKill)), in StoreRegToStackSlot()
955 getKillRegState(isKill)), in StoreRegToStackSlot()
[all …]
DPPCRegisterInfo.cpp390 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in lowerDynamicAlloc()
398 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
415 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg)) in lowerDynamicAlloc()
423 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg)); in lowerDynamicAlloc()
483 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerCRSpilling()
570 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerCRBitSpilling()
660 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill())); in lowerVRSAVESpilling()
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp1545 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); in copyPhysRegTuple()
1573 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
1576 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
1597 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
1602 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1613 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
1623 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1691 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
1695 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
1716 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
[all …]
DAArch64AdvSIMDScalarPass.cpp287 .addReg(Src, getKillRegState(IsKill)); in insertCopy()
357 .addReg(Src0, getKillRegState(true), SubReg0) in transformInstruction()
358 .addReg(Src1, getKillRegState(true), SubReg1); in transformInstruction()
DAArch64FastISel.cpp349 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
387 .addReg(TmpReg, getKillRegState(true)); in materializeFP()
1272 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rr()
1273 .addReg(RHSReg, getKillRegState(RHSIsKill)); in emitAddSub_rr()
1316 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_ri()
1357 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rs()
1358 .addReg(RHSReg, getKillRegState(RHSIsKill)) in emitAddSub_rs()
1400 .addReg(LHSReg, getKillRegState(LHSIsKill)) in emitAddSub_rx()
1401 .addReg(RHSReg, getKillRegState(RHSIsKill)) in emitAddSub_rx()
1459 .addReg(LHSReg, getKillRegState(LHSIsKill)); in emitFCmp()
[all …]
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1802 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r()
1805 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r()
1825 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
1826 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr()
1829 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr()
1830 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr()
1851 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
1852 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr()
1853 .addReg(Op2, getKillRegState(Op2IsKill)); in fastEmitInst_rrr()
1856 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.cpp78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst()
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst()
148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst()
191 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
DXCoreInstrInfo.cpp341 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
353 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
376 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.cpp40 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
56 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp55 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
59 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
102 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/external/llvm/lib/Target/Hexagon/
DHexagonNewValueJump.cpp644 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
645 .addReg(cmpOp2, getKillRegState(MO2IsKill)) in runOnMachineFunction()
655 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
661 .addReg(cmpReg1, getKillRegState(MO1IsKill)) in runOnMachineFunction()
DHexagonCopyToCombine.cpp641 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineIR()
688 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRI()
737 unsigned LoRegKillFlag = getKillRegState(LoOperand.isKill()); in emitCombineRR()
738 unsigned HiRegKillFlag = getKillRegState(HiOperand.isKill()); in emitCombineRR()
DHexagonInstrInfo.cpp638 addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
644 addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
650 addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
655 addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
661 getKillRegState(KillSrc)). in copyPhysReg()
663 getKillRegState(KillSrc)); in copyPhysReg()
669 addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
686 getKillRegState(KillSrc)); in copyPhysReg()
690 getKillRegState(KillSrc)); in copyPhysReg()
719 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
[all …]
DHexagonStoreWidening.cpp442 .addReg(MR.getReg(), getKillRegState(MR.isKill())) in createWideStores()
464 .addReg(MR.getReg(), getKillRegState(MR.isKill())) in createWideStores()
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg()
129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) in copyPhysReg()
173 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
244 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) in storeRegToStack()
558 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); in expandPseudoMTLoHi()
559 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); in expandPseudoMTLoHi()
569 unsigned KillSrc = getKillRegState(Src.isKill()); in expandCvtFPInt()
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.cpp49 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/external/llvm/lib/Target/SystemZ/
DSystemZInstrInfo.cpp184 .addReg(SrcReg, getKillRegState(KillSrc)); in emitGRX32Move()
190 .addReg(SrcReg, getKillRegState(KillSrc)) in emitGRX32Move()
589 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
603 .addReg(SrcReg, getKillRegState(isKill)), in storeRegToStackSlot()
715 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()); in convertToThreeAddress()
747 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg()) in convertToThreeAddress()
/external/llvm/lib/CodeGen/
DTargetInstrInfo.cpp730 .addReg(RegX, getKillRegState(KillX)) in reassociateOps()
731 .addReg(RegY, getKillRegState(KillY)); in reassociateOps()
734 .addReg(RegA, getKillRegState(KillA)) in reassociateOps()
735 .addReg(NewVR, getKillRegState(true)); in reassociateOps()

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