Home
last modified time | relevance | path

Searched refs:ins (Results 1 – 25 of 380) sorted by relevance

12345678910>>...16

/external/llvm/lib/Target/PowerPC/
DPPCInstrSPE.td73 def EVLDD : EVXForm_D<769, (outs gprc:$RT), (ins spe8dis:$dst),
75 def EVLDW : EVXForm_D<771, (outs gprc:$RT), (ins spe8dis:$dst),
77 def EVLDH : EVXForm_D<773, (outs gprc:$RT), (ins spe8dis:$dst),
79 def EVLHHESPLAT : EVXForm_D<777, (outs gprc:$RT), (ins spe2dis:$dst),
81 def EVLHHOUSPLAT : EVXForm_D<781, (outs gprc:$RT), (ins spe2dis:$dst),
83 def EVLHHOSSPLAT : EVXForm_D<783, (outs gprc:$RT), (ins spe2dis:$dst),
85 def EVLWHE : EVXForm_D<785, (outs gprc:$RT), (ins spe4dis:$dst),
87 def EVLWHOU : EVXForm_D<789, (outs gprc:$RT), (ins spe4dis:$dst),
89 def EVLWHOS : EVXForm_D<791, (outs gprc:$RT), (ins spe4dis:$dst),
91 def EVLWWSPLAT : EVXForm_D<793, (outs gprc:$RT), (ins spe4dis:$dst),
[all …]
DPPCInstr64Bit.td86 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
89 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
92 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
97 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
100 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
107 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
112 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
114 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
119 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
121 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
[all …]
DPPCInstrInfo.td1020 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins u16imm:$amt), "#ADJCALLSTACKDOWN $amt",
1022 def ADJCALLSTACKUP : Pseudo<(outs), (ins u16imm:$amt1, u16imm:$amt2), "#ADJCALLSTACKUP $amt1 $amt…
1026 def UPDATE_VRSAVE : Pseudo<(outs gprc:$rD), (ins gprc:$rS),
1031 def DYNALLOC : Pseudo<(outs gprc:$result), (ins gprc:$negsize, memri:$fpsi), "#DYNALLOC",
1034 def DYNAREAOFFSET : Pseudo<(outs i32imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET",
1044 def SELECT_CC_I4 : Pseudo<(outs gprc:$dst), (ins crrc:$cond,
1048 def SELECT_CC_I8 : Pseudo<(outs g8rc:$dst), (ins crrc:$cond,
1052 def SELECT_CC_F4 : Pseudo<(outs f4rc:$dst), (ins crrc:$cond, f4rc:$T, f4rc:$F,
1055 def SELECT_CC_F8 : Pseudo<(outs f8rc:$dst), (ins crrc:$cond, f8rc:$T, f8rc:$F,
1058 def SELECT_CC_VRRC: Pseudo<(outs vrrc:$dst), (ins crrc:$cond, vrrc:$T, vrrc:$F,
[all …]
/external/v8/test/test262/
Dtest262.status74 'built-ins/Promise/reject-function-name': [FAIL],
75 'built-ins/Promise/resolve-function-name': [FAIL],
76 'built-ins/Promise/all/resolve-element-function-name': [FAIL],
77 'built-ins/Promise/executor-function-name': [FAIL],
78 'built-ins/Proxy/revocable/revocation-function-name': [FAIL],
108 'built-ins/RegExp/prototype/Symbol.match/coerce-global': [SKIP],
111 'built-ins/RegExp/prototype/Symbol.replace/y-init-lastindex': [FAIL],
112 'built-ins/RegExp/prototype/Symbol.replace/y-set-lastindex': [FAIL],
116 'built-ins/RegExp/prototype/Symbol.match/builtin-failure-set-lastindex-err': [PASS, FAIL],
117 'built-ins/RegExp/prototype/Symbol.match/builtin-failure-y-set-lastindex-err': [PASS, FAIL],
[all …]
/external/llvm/lib/Target/XCore/
DXCoreInstrFormats.td13 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
19 dag InOperandList = ins;
27 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : InstXCore<0, outs, ins, asmstr, pattern> {
36 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
37 : InstXCore<2, outs, ins, asmstr, pattern> {
45 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : _F3R<opc, outs, ins, asmstr, pattern> {
50 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
51 : InstXCore<4, outs, ins, asmstr, pattern> {
[all …]
DXCoreInstrInfo.td222 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
225 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
231 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
233 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
239 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
242 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
248 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
253 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
260 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
263 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrFormatsV60.td42 class CVI_VA_Resource<dag outs, dag ins, string asmstr,
45 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
48 class CVI_VA_DV_Resource<dag outs, dag ins, string asmstr,
51 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA_DV>,
54 class CVI_VX_Resource_long<dag outs, dag ins, string asmstr,
57 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
60 class CVI_VX_Resource_late<dag outs, dag ins, string asmstr,
63 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
66 class CVI_VX_Resource<dag outs, dag ins, string asmstr,
69 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
[all …]
DHexagonInstrFormats.td79 class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
85 dag InOperandList = ins;
210 class LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
212 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
215 class LDInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
217 : LDInst<outs, ins, asmstr, pattern, cstr>;
219 class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
221 : LDInst<outs, ins, asmstr, pattern, cstr>;
225 class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
227 : LDInst<outs, ins, asmstr, pattern, cstr>;
[all …]
DHexagonInstrFormatsV4.td50 dag InOperandList = (ins);
108 class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
110 : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNV>, OpcodeHexagon;
112 class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
114 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
117 class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
119 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
123 class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
125 : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
128 class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
[all …]
/external/llvm/lib/Target/X86/
DX86InstrSystem.td18 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", [(X86rdtsc)], IIC_RDTSC>,
22 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", [(X86rdtscp)]>, TB;
27 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
28 def UD2B : I<0xB9, RawFrm, (outs), (ins), "ud2b", []>, TB;
31 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", [], IIC_HLT>;
32 def RSM : I<0xAA, RawFrm, (outs), (ins), "rsm", [], IIC_RSM>, TB;
36 def INTO : I<0xce, RawFrm, (outs), (ins), "into", []>;
37 def INT3 : I<0xcc, RawFrm, (outs), (ins), "int3",
47 def INT : Ii8<0xcd, RawFrm, (outs), (ins u8imm:$trap), "int\t$trap",
51 def SYSCALL : I<0x05, RawFrm, (outs), (ins), "syscall", [], IIC_SYSCALL>, TB;
[all …]
DX86InstrFPStack.td78 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
80 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
82 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
84 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
86 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
88 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
90 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
92 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
94 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
121 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
[all …]
DX86InstrControl.td24 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
27 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
30 def RETW : I <0xC3, RawFrm, (outs), (ins),
33 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
37 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
41 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
44 def LRETL : I <0xCB, RawFrm, (outs), (ins),
46 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
48 def LRETW : I <0xCB, RawFrm, (outs), (ins),
50 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
[all …]
DX86InstrFormats.td220 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
233 dag InOperandList = ins;
340 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
343 : X86Inst<o, f, NoImm, outs, ins, asm, itin, d> {
347 class Ii8 <bits<8> o, Format f, dag outs, dag ins, string asm,
350 : X86Inst<o, f, Imm8, outs, ins, asm, itin, d> {
354 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
356 : X86Inst<o, f, Imm8PCRel, outs, ins, asm, itin> {
360 class Ii16<bits<8> o, Format f, dag outs, dag ins, string asm,
362 : X86Inst<o, f, Imm16, outs, ins, asm, itin> {
[all …]
DX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
26 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
29 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
33 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
34 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
37 def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, TB;
39 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
41 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
42 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
[all …]
DX86InstrShiftRotate.td20 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
23 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
26 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
29 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
39 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
43 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
48 (ins GR64:$src1, u8imm:$src2),
57 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
59 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430InstrFormats.td54 class MSP430Inst<dag outs, dag ins, SizeVal sz, Format f,
61 dag InOperandList = ins;
78 dag outs, dag ins, string asmstr, list<dag> pattern>
79 : MSP430Inst<outs, ins, sz, DoubleOpFrm, asmstr> {
93 dag outs, dag ins, string asmstr, list<dag> pattern>
94 : IForm<opcode, dest, 1, src, sz, outs, ins, asmstr, pattern>;
97 dag outs, dag ins, string asmstr, list<dag> pattern>
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
101 dag outs, dag ins, string asmstr, list<dag> pattern>
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
[all …]
DMSP430InstrInfo.td116 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt),
119 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
125 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
129 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
134 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
137 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
140 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
143 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
146 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
149 def Srl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
[all …]
/external/llvm/lib/Target/Sparc/
DSparcInstrFormats.td10 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern>
21 dag InOperandList = ins;
34 class F2<dag outs, dag ins, string asmstr, list<dag> pattern>
35 : InstSP<outs, ins, asmstr, pattern> {
45 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
46 : F2<outs, ins, asmstr, pattern> {
54 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
55 list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : InstSP<outs, ins, asmstr, pattern> {
[all …]
DSparcInstrInfo.td253 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
257 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
266 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
269 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
277 (outs RC:$dst), (ins MEMrr:$addr),
281 (outs RC:$dst), (ins MEMri:$addr),
290 F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
304 def LDSTUBrr : F3_1<3, 0b001101, (outs IntRegs:$dst), (ins MEMrr:$addr),
306 def LDSTUBri : F3_2<3, 0b001101, (outs IntRegs:$dst), (ins MEMri:$addr),
309 (ins MEMrr:$addr, i8imm:$asi),
[all …]
/external/iptables/utils/
Dnfbpf_compile.c18 struct bpf_insn *ins; in main() local
46 ins = program.bf_insns; in main()
47 for (i = 0; i < program.bf_len-1; ++ins, ++i) in main()
48 printf("%u %u %u %u,", ins->code, ins->jt, ins->jf, ins->k); in main()
50 printf("%u %u %u %u\n", ins->code, ins->jt, ins->jf, ins->k); in main()
/external/llvm/test/CodeGen/Mips/
Dinterrupt-attr.ll9 ; CHECK: ins $27, $zero, 8, 1
10 ; CHECK: ins $27, $zero, 1, 4
11 ; CHECK: ins $27, $zero, 29, 1
79 ; CHECK: ins $27, $zero, 8, 2
80 ; CHECK: ins $27, $zero, 1, 4
81 ; CHECK: ins $27, $zero, 29, 1
99 ; CHECK: ins $27, $zero, 8, 3
100 ; CHECK: ins $27, $zero, 1, 4
101 ; CHECK: ins $27, $zero, 29, 1
119 ; CHECK: ins $27, $zero, 8, 4
[all …]
/external/llvm/lib/Target/Mips/
DMips16InstrFormats.td36 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
43 let InOperandList = ins;
55 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
57 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
72 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
74 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
82 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
84 MipsInst16_32<outs, ins, asmstr, pattern, itin>
92 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
93 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
[all …]
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrConv.td18 def I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src),
22 def I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src),
25 def I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src),
40 def I32_TRUNC_S_F32 : I<(outs I32:$dst), (ins F32:$src),
43 def I32_TRUNC_U_F32 : I<(outs I32:$dst), (ins F32:$src),
46 def I64_TRUNC_S_F32 : I<(outs I64:$dst), (ins F32:$src),
49 def I64_TRUNC_U_F32 : I<(outs I64:$dst), (ins F32:$src),
52 def I32_TRUNC_S_F64 : I<(outs I32:$dst), (ins F64:$src),
55 def I32_TRUNC_U_F64 : I<(outs I32:$dst), (ins F64:$src),
58 def I64_TRUNC_S_F64 : I<(outs I64:$dst), (ins F64:$src),
[all …]
/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.td641 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
665 class SOP1_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
666 SOP1 <outs, ins, "", pattern>,
672 class SOP1_Real_si <sop1 op, string opName, dag outs, dag ins, string asm> :
673 SOP1 <outs, ins, asm, []>,
680 class SOP1_Real_vi <sop1 op, string opName, dag outs, dag ins, string asm> :
681 SOP1 <outs, ins, asm, []>,
688 multiclass SOP1_m <sop1 op, string opName, dag outs, dag ins, string asm,
691 def "" : SOP1_Pseudo <opName, outs, ins, pattern>;
693 def _si : SOP1_Real_si <op, opName, outs, ins, asm>;
[all …]
/external/mesa3d/src/gallium/drivers/radeon/
DSIInstrInfo.td31 class InstSI <dag outs, dag ins, string asm, list<dag> pattern> :
32 AMDGPUInst<outs, ins, asm, pattern> {
42 class Enc32 <dag outs, dag ins, string asm, list<dag> pattern> :
43 InstSI <outs, ins, asm, pattern> {
48 class Enc64 <dag outs, dag ins, string asm, list<dag> pattern> :
49 InstSI <outs, ins, asm, pattern> {
114 (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm,
145 class MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
146 Enc64 <outs, ins, asm, pattern> {
182 class MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> :
[all …]

12345678910>>...16