| /external/e2fsprogs/lib/ss/ |
| D | request_tbl.c | 54 register ssrt **rt1, **rt2; in ss_delete_request_table() local
59 for (rt2 = rt1; *rt1; rt1++) { in ss_delete_request_table()
61 *rt2++ = *rt1; in ss_delete_request_table()
65 *rt2 = (ssrt *)NULL; in ss_delete_request_table()
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| /external/llvm/test/Verifier/ |
| D | recursive-type-3.ll | 3 %rt2 = type { i32, { i8, %rt2*, i8 }, i32 }
9 %0 = alloca %rt2
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| D | recursive-type-1.ll | 3 %rt2 = type { i32, { i8, %rt2, i8 }, i32 }
10 %0 = alloca %rt2
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| D | recursive-type-2.ll | 3 %rt1 = type { i32, { i8, %rt2, i8 }, i32 }
4 %rt2 = type { i64, { i6, %rt3 } }
12 %0 = alloca %rt2
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| /external/llvm/test/CodeGen/AArch64/ |
| D | returnaddr.ll | 11 define i8* @rt2() nounwind readnone {
13 ; CHECK-LABEL: rt2:
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| D | arm64-returnaddr.ll | 12 define i8* @rt2() nounwind readnone {
14 ; CHECK-LABEL: rt2:
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| /external/llvm/test/CodeGen/ARM/ |
| D | arm-returnaddr.ll | 16 define i8* @rt2() nounwind readnone {
18 ; CHECK-LABEL: rt2:
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| /external/vixl/src/vixl/a64/ |
| D | simulator-a64.cc | 1176 unsigned rt2 = instr->Rt2(); in LoadStorePairHelper() local
1186 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || (rt != rt2)); in LoadStorePairHelper()
1193 set_wreg(rt2, Memory::Read<uint32_t>(address2), NoRegLog); in LoadStorePairHelper()
1198 set_sreg(rt2, Memory::Read<float>(address2), NoRegLog); in LoadStorePairHelper()
1203 set_xreg(rt2, Memory::Read<uint64_t>(address2), NoRegLog); in LoadStorePairHelper()
1208 set_dreg(rt2, Memory::Read<double>(address2), NoRegLog); in LoadStorePairHelper()
1213 set_qreg(rt2, Memory::Read<qreg_t>(address2), NoRegLog); in LoadStorePairHelper()
1218 set_xreg(rt2, Memory::Read<int32_t>(address2), NoRegLog); in LoadStorePairHelper()
1223 Memory::Write<uint32_t>(address2, wreg(rt2)); in LoadStorePairHelper()
1228 Memory::Write<float>(address2, sreg(rt2)); in LoadStorePairHelper()
[all …]
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| D | assembler-a64.cc | 1448 const CPURegister& rt2, in ldp() argument
1450 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2)); in ldp()
1455 const CPURegister& rt2, in stp() argument
1457 LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2)); in stp()
1462 const Register& rt2, in ldpsw() argument
1465 LoadStorePair(rt, rt2, src, LDPSW_x); in ldpsw()
1470 const CPURegister& rt2, in LoadStorePair() argument
1474 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2)); in LoadStorePair()
1475 VIXL_ASSERT(AreSameSizeAndType(rt, rt2)); in LoadStorePair()
1479 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | in LoadStorePair()
[all …]
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| D | macro-assembler-a64.h | 53 V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2)) \
54 V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \
55 V(Ldpsw, CPURegister&, rt, rt2, LDPSW_x)
747 const CPURegister& rt2,
1434 void Ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) { in Ldaxp() argument
1436 VIXL_ASSERT(!rt.Aliases(rt2)); in Ldaxp()
1438 ldaxp(rt, rt2, src); in Ldaxp()
1456 const CPURegister& rt2, in Ldnp() argument
1460 ldnp(rt, rt2, src); in Ldnp()
1541 void Ldxp(const Register& rt, const Register& rt2, const MemOperand& src) { in Ldxp() argument
[all …]
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| D | assembler-a64.h | 1812 void ldp(const CPURegister& rt, const CPURegister& rt2,
1816 void stp(const CPURegister& rt, const CPURegister& rt2,
1820 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src);
1823 void ldnp(const CPURegister& rt, const CPURegister& rt2,
1827 void stnp(const CPURegister& rt, const CPURegister& rt2,
1863 const Register& rt2,
1867 void ldxp(const Register& rt, const Register& rt2, const MemOperand& src);
1890 const Register& rt2,
1894 void ldaxp(const Register& rt, const Register& rt2, const MemOperand& src);
3796 static Instr Rt2(CPURegister rt2) { in Rt2() argument
[all …]
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| D | macro-assembler-a64.cc | 1566 const CPURegister& rt2, in LSPAIR_MACRO_LIST()
1584 LoadStorePair(rt, rt2, addr, op); in LSPAIR_MACRO_LIST()
1591 LoadStorePair(rt, rt2, MemOperand(temp), op); in LSPAIR_MACRO_LIST()
1593 LoadStorePair(rt, rt2, MemOperand(base), op); in LSPAIR_MACRO_LIST()
1598 LoadStorePair(rt, rt2, MemOperand(base), op); in LSPAIR_MACRO_LIST()
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| /external/pdfium/xfa/src/fxfa/src/app/ |
| D | xfa_ffpageview.cpp | 325 CFX_RectF rt1, rt2; in XFA_TabOrderWidgetComparator() local
327 pWidget2->GetWidgetRect(rt2); in XFA_TabOrderWidgetComparator()
328 FX_FLOAT x1 = rt1.left, y1 = rt1.top, x2 = rt2.left, y2 = rt2.top; in XFA_TabOrderWidgetComparator()
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| /external/v8/src/arm64/ |
| D | assembler-arm64-inl.h | 909 const CPURegister& rt2) {
910 DCHECK(AreSameSizeAndType(rt, rt2));
911 USE(rt2);
933 const CPURegister& rt2) {
934 DCHECK(AreSameSizeAndType(rt, rt2));
935 USE(rt2);
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| D | assembler-arm64.h | 1385 void ldp(const CPURegister& rt, const CPURegister& rt2,
1389 void stp(const CPURegister& rt, const CPURegister& rt2,
1393 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src);
1726 static Instr Rt2(CPURegister rt2) { in Rt2() argument
1727 DCHECK(rt2.code() != kSPRegInternalCode); in Rt2()
1728 return rt2.code() << Rt2_offset; in Rt2()
1886 void LoadStorePair(const CPURegister& rt, const CPURegister& rt2,
1939 const CPURegister& rt2);
1942 const CPURegister& rt2);
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| D | simulator-arm64.cc | 1721 unsigned rt2 = instr->Rt2(); in LoadStorePairHelper() local
1748 DCHECK(((op & LoadStorePairLBit) == 0) || (rt != rt2)); in LoadStorePairHelper()
1756 set_wreg_no_log(rt2, MemoryRead<uint32_t>(address2)); in LoadStorePairHelper()
1762 set_sreg_no_log(rt2, MemoryRead<float>(address2)); in LoadStorePairHelper()
1768 set_xreg_no_log(rt2, MemoryRead<uint64_t>(address2)); in LoadStorePairHelper()
1774 set_dreg_no_log(rt2, MemoryRead<double>(address2)); in LoadStorePairHelper()
1780 set_xreg_no_log(rt2, MemoryRead<int32_t>(address2)); in LoadStorePairHelper()
1786 MemoryWrite<uint32_t>(address2, wreg(rt2)); in LoadStorePairHelper()
1792 MemoryWrite<float>(address2, sreg(rt2)); in LoadStorePairHelper()
1798 MemoryWrite<uint64_t>(address2, xreg(rt2)); in LoadStorePairHelper()
[all …]
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| D | assembler-arm64.cc | 1575 const CPURegister& rt2, in ldp() argument
1577 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2)); in ldp()
1582 const CPURegister& rt2, in stp() argument
1584 LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2)); in stp()
1589 const Register& rt2, in ldpsw() argument
1592 LoadStorePair(rt, rt2, src, LDPSW_x); in ldpsw()
1597 const CPURegister& rt2, in LoadStorePair() argument
1601 DCHECK(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2)); in LoadStorePair()
1602 DCHECK(AreSameSizeAndType(rt, rt2)); in LoadStorePair()
1606 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | in LoadStorePair()
[all …]
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| D | macro-assembler-arm64.h | 67 V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2)) \
68 V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \
69 V(Ldpsw, CPURegister&, rt, rt2, LDPSW_x)
310 void LoadStorePairMacro(const CPURegister& rt, const CPURegister& rt2,
480 const CPURegister& rt2,
540 const CPURegister& rt2,
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| D | macro-assembler-arm64.cc | 594 const CPURegister& rt2, in LoadStorePairMacro() argument
607 LoadStorePair(rt, rt2, addr, op); in LoadStorePairMacro()
614 LoadStorePair(rt, rt2, MemOperand(temp), op); in LoadStorePairMacro()
616 LoadStorePair(rt, rt2, MemOperand(base), op); in LoadStorePairMacro()
621 LoadStorePair(rt, rt2, MemOperand(base), op); in LoadStorePairMacro()
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| /external/libnl/lib/route/ |
| D | neightbl.c | 257 char rt[32], rt2[32]; in neightbl_dump_line() local
262 nl_msec2str(pa->ntp_retrans_time, rt2, sizeof(rt2))); in neightbl_dump_line()
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| /external/vixl/doc/ |
| D | supported-instructions.md | 547 void ldaxp(const Register& rt, const Register& rt2, const MemOperand& src)
575 void ldnp(const CPURegister& rt, const CPURegister& rt2,
583 void ldp(const CPURegister& rt, const CPURegister& rt2,
591 void ldpsw(const Register& rt, const Register& rt2, const MemOperand& src)
722 void ldxp(const Register& rt, const Register& rt2, const MemOperand& src)
1105 const Register& rt2,
1134 void stnp(const CPURegister& rt, const CPURegister& rt2,
1142 void stp(const CPURegister& rt, const CPURegister& rt2,
1200 const Register& rt2,
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| /external/pcre/dist/sljit/ |
| D | sljitNativeARM_64.c | 54 #define RT2(rt2) (reg_map[rt2] << 10) argument
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| /external/webrtc/webrtc/p2p/base/ |
| D | p2ptransportchannel_unittest.cc | 184 const std::string& rt2, const std::string& rp2, int wait) in Result()
186 local_type2(lt2), local_proto2(lp2), remote_type2(rt2), in Result()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 3257 list<dag> pattern, bits<4> rt2 = 0b1111>
3261 let Inst{11-8} = rt2;
3272 list<dag> pattern, bits<4> rt2 = 0b1111>
3276 let Inst{11-8} = rt2;
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| /external/hyphenation-patterns/hu/ |
| D | hyph-hu.pat.txt | 1220 .űrt2
9043 bért2
9433 bórt2
11073 dárt2
16497 égért2
23075 húrt2
27701 kárt2
28958 kört2
30050 lárt2
35099 nárt2
[all …]
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