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/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_complex.txt6 # CHECK: r17:16 = vxaddsubh(r21:20, r31:30):sat
8 # CHECK: r17:16 = vxsubaddh(r21:20, r31:30):sat
10 # CHECK: r17:16 = vxaddsubh(r21:20, r31:30):rnd:>>1:sat
12 # CHECK: r17:16 = vxsubaddh(r21:20, r31:30):rnd:>>1:sat
16 # CHECK: r17:16 = vxaddsubw(r21:20, r31:30):sat
18 # CHECK: r17:16 = vxsubaddw(r21:20, r31:30):sat
22 # CHECK: r17:16 = cmpy(r21, r31):sat
24 # CHECK: r17:16 = cmpy(r21, r31):<<1:sat
26 # CHECK: r17:16 = cmpy(r21, r31*):sat
28 # CHECK: r17:16 = cmpy(r21, r31*):<<1:sat
[all …]
Dxtype_mpy.txt30 # CHECK: r17:16 = vmpyweh(r21:20, r31:30):sat
32 # CHECK: r17:16 = vmpyweh(r21:20, r31:30):<<1:sat
34 # CHECK: r17:16 = vmpywoh(r21:20, r31:30):sat
36 # CHECK: r17:16 = vmpywoh(r21:20, r31:30):<<1:sat
38 # CHECK: r17:16 = vmpyweh(r21:20, r31:30):rnd:sat
40 # CHECK: r17:16 = vmpyweh(r21:20, r31:30):<<1:rnd:sat
42 # CHECK: r17:16 = vmpywoh(r21:20, r31:30):rnd:sat
44 # CHECK: r17:16 = vmpywoh(r21:20, r31:30):<<1:rnd:sat
46 # CHECK: r17:16 += vmpyweh(r21:20, r31:30):sat
48 # CHECK: r17:16 += vmpyweh(r21:20, r31:30):<<1:sat
[all …]
Dxtype_alu.txt10 # CHECK: r17 = abs(r21):sat
30 # CHECK: r17:16 = add(r21:20, r31:30):sat
42 # CHECK: r17 = add(r21.l, r31.l):sat
44 # CHECK: r17 = add(r21.l, r31.h):sat
54 # CHECK: r17 = add(r21.l, r31.l):sat:<<16
56 # CHECK: r17 = add(r21.l, r31.h):sat:<<16
58 # CHECK: r17 = add(r21.h, r31.l):sat:<<16
60 # CHECK: r17 = add(r21.h, r31.h):sat:<<16
150 # CHECK: r17 = neg(r21):sat
154 # CHECK: r17 = round(r21:20):sat
[all …]
Dalu32_alu.txt10 # CHECK: r17 = add(r21, r31):sat
38 # CHECK: r17 = sub(r31, r21):sat
62 # CHECK: r17 = vaddh(r21, r31):sat
64 # CHECK: r17 = vadduh(r21, r31):sat
78 # CHECK: r17 = vsubh(r31, r21):sat
80 # CHECK: r17 = vsubuh(r31, r21):sat
/external/mesa3d/src/mesa/program/
Dprogram_lexer.l166 sat (_SAT)?
186 ABS{sz}{cc}{sat} { return_opcode( 1, VECTOR_OP, ABS, 3); }
187 ADD{sz}{cc}{sat} { return_opcode( 1, BIN_OP, ADD, 3); }
190 CMP{sat} { return_opcode(require_ARB_fp, TRI_OP, CMP, 3); }
191 COS{szf}{cc}{sat} { return_opcode(require_ARB_fp, SCALAR_OP, COS, 3); }
193 DDX{szf}{cc}{sat} { return_opcode(require_NV_fp, VECTOR_OP, DDX, 3); }
194 DDY{szf}{cc}{sat} { return_opcode(require_NV_fp, VECTOR_OP, DDY, 3); }
195 DP3{sz}{cc}{sat} { return_opcode( 1, BIN_OP, DP3, 3); }
196 DP4{sz}{cc}{sat} { return_opcode( 1, BIN_OP, DP4, 3); }
197 DPH{sz}{cc}{sat} { return_opcode( 1, BIN_OP, DPH, 3); }
[all …]
/external/llvm/test/MC/Hexagon/
Dv60-alu.s38 #CHECK: 1caeca00 { v1:0.h = vsub(v11:10.h,{{ *}}v15:14.h):sat }
39 v1:0.h=vsub(v11:10.h,v15:14.h):sat
41 #CHECK: 1ca8c43e { v31:30.w = vsub(v5:4.w,{{ *}}v9:8.w):sat }
42 v31:30.w=vsub(v5:4.w,v9:8.w):sat
50 #CHECK: 1c79c350 { v16.h = vsub(v3.h,{{ *}}v25.h):sat }
51 v16.h=vsub(v3.h,v25.h):sat
53 #CHECK: 1c7fd364 { v4.w = vsub(v19.w,{{ *}}v31.w):sat }
54 v4.w=vsub(v19.w,v31.w):sat
56 #CHECK: 1c67d816 { v22.ub = vsub(v24.ub,{{ *}}v7.ub):sat }
57 v22.ub=vsub(v24.ub,v7.ub):sat
[all …]
Dv60-vmpy1.s5 #CHECK: 1939c223 { v3.w = vdmpy(v3:2.h,{{ *}}r25.uh,{{ *}}#1):sat }
6 v3.w=vdmpy(v3:2.h,r25.uh,#1):sat
8 #CHECK: 1936de0d { v13.w = vdmpy(v30.h,{{ *}}r22.uh):sat }
9 v13.w=vdmpy(v30.h,r22.uh):sat
53 #CHECK: 1925d86b { v11.w = vdmpy(v25:24.h,{{ *}}r5.h):sat }
54 v11.w=vdmpy(v25:24.h,r5.h):sat
56 #CHECK: 1925c255 { v21.w = vdmpy(v2.h,{{ *}}r5.h):sat }
57 v21.w=vdmpy(v2.h,r5.h):sat
59 #CHECK: 1941d424 { v4.h = vmpy(v20.h,{{ *}}r1.h):<<1:sat }
60 v4.h=vmpy(v20.h,r1.h):<<1:sat
[all …]
Dv60-vmpy-acc.s5 #CHECK: 1936ee37 { v23.w += vdmpy(v15:14.h,r22.uh,#1):sat }
6 v23.w += vdmpy(v15:14.h,r22.uh,#1):sat
8 #CHECK: 193bf90f { v15.w += vdmpy(v25.h,r27.uh):sat }
9 v15.w += vdmpy(v25.h,r27.uh):sat
56 #CHECK: 1934fc62 { v2.w += vdmpy(v28.h,r20.h):sat }
57 v2.w += vdmpy(v28.h,r20.h):sat
59 #CHECK: 1925fe5f { v31.w += vdmpy(v31:30.h,r5.h):sat }
60 v31.w += vdmpy(v31:30.h,r5.h):sat
65 #CHECK: 1948e306 { v7:6.w += vmpy(v3.h,r8.h):sat }
66 v7:6.w += vmpy(v3.h,r8.h):sat
[all …]
Dv60-permute.s5 #CHECK: 1fd2d5cf { v15.b = vpack(v21.h{{ *}},{{ *}}v18.h):sat }
6 v15.b=vpack(v21.h,v18.h):sat
8 #CHECK: 1fd7d7a2 { v2.ub = vpack(v23.h{{ *}},{{ *}}v23.h):sat }
9 v2.ub=vpack(v23.h,v23.h):sat
17 #CHECK: 1fc9c5ed { v13.uh = vpack(v5.w{{ *}},{{ *}}v9.w):sat }
18 v13.uh=vpack(v5.w,v9.w):sat
20 #CHECK: 1ff1d81f { v31.h = vpack(v24.w{{ *}},{{ *}}v17.w):sat }
21 v31.h=vpack(v24.w,v17.w):sat
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_complex.ll13 ; CHECK: = vxaddsubh({{.*}}, {{.*}}):sat
20 ; CHECK: = vxsubaddh({{.*}}, {{.*}}):sat
27 ; CHECK: = vxaddsubh({{.*}}, {{.*}}):rnd:>>1:sat
34 ; CHECK: = vxsubaddh({{.*}}, {{.*}}):rnd:>>1:sat
42 ; CHECK: = vxaddsubw({{.*}}, {{.*}}):sat
49 ; CHECK: = vxsubaddw({{.*}}, {{.*}}):sat
57 ; CHECK: = cmpy({{.*}}, {{.*}}):sat
64 ; CHECK: = cmpy({{.*}}, {{.*}}):<<1:sat
71 ; CHECK: = cmpy({{.*}}, {{.*}}*):sat
78 ; CHECK: = cmpy({{.*}}, {{.*}}*):<<1:sat
[all …]
Dxtype_mpy.ll50 ; CHECK: = vmpyweh({{.*}}, {{.*}}):sat
57 ; CHECK: = vmpyweh({{.*}}, {{.*}}):<<1:sat
64 ; CHECK: = vmpywoh({{.*}}, {{.*}}):sat
71 ; CHECK: = vmpywoh({{.*}}, {{.*}}):<<1:sat
78 ; CHECK: = vmpyweh({{.*}}, {{.*}}):rnd:sat
85 ; CHECK: = vmpyweh({{.*}}, {{.*}}):<<1:rnd:sat
92 ; CHECK: = vmpywoh({{.*}}, {{.*}}):rnd:sat
99 ; CHECK: = vmpywoh({{.*}}, {{.*}}):<<1:rnd:sat
107 ; CHECK: = vmpyweuh({{.*}}, {{.*}}):sat
114 ; CHECK: = vmpyweuh({{.*}}, {{.*}}):<<1:sat
[all …]
Dxtype_alu.ll29 ; CHECK: = abs({{.*}}):sat
87 ; CHECK: = add({{.*}}, {{.*}}):sat
104 declare i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32, i32)
106 %z = call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %a, i32 %b)
109 ; CHECK: = add({{.*}}.l, {{.*}}.l):sat
111 declare i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32, i32)
113 %z = call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %a, i32 %b)
116 ; CHECK: = add({{.*}}.l, {{.*}}.h):sat
146 declare i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32, i32)
148 %z = call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %a, i32 %b)
[all …]
/external/mesa3d/src/gallium/drivers/nv30/
Dnvfx_fragprog.c206 if (insn.sat) in nvfx_fp_emit()
447 int mask, sat, unit = 0; in nvfx_fragprog_parse_instruction() local
528 sat = (finst->Instruction.Saturate == TGSI_SAT_ZERO_ONE); in nvfx_fragprog_parse_instruction()
532 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, abs(src[0]), none, none)); in nvfx_fragprog_parse_instruction()
535 nvfx_fp_emit(fpc, arith(sat, ADD, dst, mask, src[0], src[1], none)); in nvfx_fragprog_parse_instruction()
540 nvfx_fp_emit(fpc, arith(sat, MOV, dst, mask, neg(tmp), none, none)); in nvfx_fragprog_parse_instruction()
547 insn = arith(sat, MOV, dst, mask, src[2], none, none); in nvfx_fragprog_parse_instruction()
551 insn = arith(sat, MOV, dst, mask, src[1], none, none); in nvfx_fragprog_parse_instruction()
556 nvfx_fp_emit(fpc, arith(sat, COS, dst, mask, src[0], none, none)); in nvfx_fragprog_parse_instruction()
561 …nvfx_fp_emit(fpc, arith(sat, DDX, tmp.reg, NVFX_FP_MASK_X | NVFX_FP_MASK_Y, swz(src[0], Z, W, Z, W… in nvfx_fragprog_parse_instruction()
[all …]
Dnvfx_vertprog.c315 if(insn.sat) { in nvfx_vp_emit()
468 boolean sat = FALSE; in nvfx_vertprog_parse_instruction() local
544 sat = TRUE; in nvfx_vertprog_parse_instruction()
552 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, abs(src[0]), none, none)); in nvfx_vertprog_parse_instruction()
555 nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, src[0], none, src[1])); in nvfx_vertprog_parse_instruction()
563 nvfx_vp_emit(vpc, arith(sat, VEC, MOV, dst, mask, neg(tmp), none, none)); in nvfx_vertprog_parse_instruction()
570 insn = arith(sat, VEC, MOV, dst, mask, src[2], none, none); in nvfx_vertprog_parse_instruction()
574 insn = arith(sat, VEC, MOV, dst, mask, src[1], none, none); in nvfx_vertprog_parse_instruction()
579 nvfx_vp_emit(vpc, arith(sat, SCA, COS, dst, mask, none, none, src[0])); in nvfx_vertprog_parse_instruction()
584 …nvfx_vp_emit(vpc, arith(sat, VEC, ADD, dst, mask, swz(tmp, X, X, X, X), none, swz(tmp, Y, Y, Y, Y)… in nvfx_vertprog_parse_instruction()
[all …]
Dnvfx_shader.h441 uint8_t sat : 1; member
452 nvfx_insn(boolean sat, unsigned op, int unit, struct nvfx_reg dst, unsigned mask, struct nvfx_src s… in nvfx_insn() argument
458 .sat = sat, in nvfx_insn()
/external/llvm/test/CodeGen/Hexagon/
Dusr-ovf-dep.ll5 ; Check that the two ":sat" instructions are in the same packet.
8 ; CHECK: :sat
9 ; CHECK-NEXT: :sat
17 %0 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %Rs, i32 %Ru)
18 %1 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %Rt, i32 %Ru)
24 declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #1
Dalu64.ll180 ; CHECK: = add(r1:0, r3:2):sat
260 ; CHECK: = add(r0.l, r1.l):sat
263 %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.ll(i32 %Rs, i32 %Rt)
268 ; CHECK: = add(r0.l, r1.h):sat
271 %0 = tail call i32 @llvm.hexagon.A2.addh.l16.sat.hl(i32 %Rs, i32 %Rt)
308 ; CHECK: = add(r0.l, r1.l):sat:<<16
311 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.ll(i32 %Rs, i32 %Rt)
316 ; CHECK: = add(r0.l, r1.h):sat:<<16
319 %0 = tail call i32 @llvm.hexagon.A2.addh.h16.sat.lh(i32 %Rs, i32 %Rt)
324 ; CHECK: = add(r0.h, r1.l):sat:<<16
[all …]
/external/robolectric/v1/src/main/java/com/xtremelabs/robolectric/shadows/
DShadowColorMatrix.java38 public void setSaturation(float sat) { in setSaturation() argument
42 final float invSat = 1 - sat; in setSaturation()
47 m[0] = R + sat; in setSaturation()
52 m[6] = G + sat; in setSaturation()
57 m[12] = B + sat; in setSaturation()
/external/skia/src/effects/
DSkColorMatrix.cpp148 void SkColorMatrix::setSaturation(SkScalar sat) { in setSaturation() argument
151 const SkScalar R = kHueR * (1 - sat); in setSaturation()
152 const SkScalar G = kHueG * (1 - sat); in setSaturation()
153 const SkScalar B = kHueB * (1 - sat); in setSaturation()
155 setrow(fMat + 0, R + sat, G, B); in setSaturation()
156 setrow(fMat + 5, R, G + sat, B); in setSaturation()
157 setrow(fMat + 10, R, G, B + sat); in setSaturation()
/external/autotest/client/site_tests/hardware_SAT/
Dhardware_SAT.py124 sat = utils.run('stressapptest' + args)
125 logging.debug(sat.stdout)
126 if not re.search('Status: PASS', sat.stdout):
127 raise error.TestFail(sat.stdout)
/external/autotest/client/site_tests/hardware_GobiGPS/
Dhardware_GobiGPS.py46 sat = fields[0]
48 sats_seen[sat] = True
49 sats_signal[sat] = fields[3]
51 sats_seen[sat] = True
/external/clang/test/CodeGen/
Dstruct-matching-constraint.c6 void b(uint16x8_t sat, uint16x8_t luma) in b() argument
10 :"=w"(luma), "=w"(sat) in b()
/external/llvm/test/CodeGen/Mips/msa/
Dbit.ll12 %1 = tail call <16 x i8> @llvm.mips.sat.s.b(<16 x i8> %0, i32 7)
17 declare <16 x i8> @llvm.mips.sat.s.b(<16 x i8>, i32) nounwind
31 %1 = tail call <8 x i16> @llvm.mips.sat.s.h(<8 x i16> %0, i32 7)
36 declare <8 x i16> @llvm.mips.sat.s.h(<8 x i16>, i32) nounwind
50 %1 = tail call <4 x i32> @llvm.mips.sat.s.w(<4 x i32> %0, i32 7)
55 declare <4 x i32> @llvm.mips.sat.s.w(<4 x i32>, i32) nounwind
69 %1 = tail call <2 x i64> @llvm.mips.sat.s.d(<2 x i64> %0, i32 7)
74 declare <2 x i64> @llvm.mips.sat.s.d(<2 x i64>, i32) nounwind
88 %1 = tail call <16 x i8> @llvm.mips.sat.u.b(<16 x i8> %0, i32 7)
93 declare <16 x i8> @llvm.mips.sat.u.b(<16 x i8>, i32) nounwind
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonIntrinsics.td156 //Rd=mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:rnd][:sat]
208 //Rx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
301 //Rxx [-+]= mpy[u](Rs.[H|L],Rt.[H|L])[:<<1][:sat]
344 // Vector complex multiply imaginary: Rdd=vcmpyi(Rss,Rtt)[:<<1]:sat
348 // Vector complex multiply real: Rdd=vcmpyr(Rss,Rtt)[:<<1]:sat
352 // Vector dual multiply: Rdd=vdmpy(Rss,Rtt)[:<<1]:sat
356 // Vector multiply even halfwords: Rdd=vmpyeh(Rss,Rtt)[:<<1]:sat
360 //Rdd=vmpywoh(Rss,Rtt)[:<<1][:rnd]:sat
366 //Rdd=vmpyweh(Rss,Rtt)[:<<1][:rnd]:sat
372 //Rdd=vmpywouh(Rss,Rtt)[:<<1][:rnd]:sat
[all …]
/external/dng_sdk/source/
Ddng_camera_profile.cpp380 for (uint32 sat = 0; sat < sats; sat++) in FingerprintHueSatMap() local
385 map.GetDelta (hue, sat, val, modify); in FingerprintHueSatMap()
881 for (uint32 sat = skipSat0 ? 1 : 0; sat < sats; sat++) in ReadHueSatMap() local
890 hueSatMap.SetDelta (hue, sat, val, modify); in ReadHueSatMap()

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