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Searched refs:setMemRefs (Results 1 – 25 of 37) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp435 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandVLD()
488 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandVST()
578 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandLaneOp()
679 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMOV32BitImm()
680 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMOV32BitImm()
728 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMOV32BitImm()
729 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMOV32BitImm()
990 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI()
1005 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI()
1104 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in ExpandMI()
[all …]
DARMInstrInfo.cpp132 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandLoadStackGuard()
DARMISelDAGToDAG.cpp1918 cast<MachineSDNode>(VLd)->setMemRefs(MemOp, MemOp + 1); in SelectVLD()
2038 cast<MachineSDNode>(VSt)->setMemRefs(MemOp, MemOp + 1); in SelectVST()
2061 cast<MachineSDNode>(VStA)->setMemRefs(MemOp, MemOp + 1); in SelectVST()
2080 cast<MachineSDNode>(VStB)->setMemRefs(MemOp, MemOp + 1); in SelectVST()
2185 cast<MachineSDNode>(VLdLn)->setMemRefs(MemOp, MemOp + 1); in SelectVLDSTLane()
2271 cast<MachineSDNode>(VLdDup)->setMemRefs(MemOp, MemOp + 1); in SelectVLDDup()
3079 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1); in Select()
3146 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1); in Select()
DARMLoadStoreOptimizer.cpp1212 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in MergeBaseUpdateLSMultiple()
1428 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); in MergeBaseUpdateLSDouble()
2003 MI->setMemRefs(MemBegin, MemEnd); in concatenateMemOperands()
DThumb2SizeReduction.cpp531 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in ReduceLoadStore()
/external/llvm/lib/Target/Hexagon/
DHexagonISelDAGToDAG.cpp273 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoadSignExtend64()
295 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoadSignExtend64()
329 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoadZeroExtend64()
356 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoadZeroExtend64()
440 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoad()
473 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedLoad()
548 cast<MachineSDNode>(Result)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedStore()
587 cast<MachineSDNode>(Result_1)->setMemRefs(MemOp, MemOp + 1); in SelectIndexedStore()
DHexagonInstrInfo.cpp825 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandPostRAPseudo()
832 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandPostRAPseudo()
856 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandPostRAPseudo()
871 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandPostRAPseudo()
886 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in expandPostRAPseudo()
DHexagonEarlyIfConv.cpp730 MIB.setMemRefs(MMOBegin, MMOEnd); in predicateInstr()
DHexagonExpandCondsets.cpp929 MB.setMemRefs(MemRefs, MemRefs+NR); in predicateAt()
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h159 const MachineInstrBuilder &setMemRefs(MachineInstr::mmo_iterator b, in setMemRefs() function
161 MI->setMemRefs(b, e); in setMemRefs()
DMachineInstr.h1173 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
/external/llvm/lib/CodeGen/
DImplicitNullChecks.cpp373 MIB.setMemRefs(LoadMI->memoperands_begin(), LoadMI->memoperands_end()); in insertFaultingLoad()
DTargetInstrInfo.cpp526 NewMI->setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in foldMemoryOperand()
808 NewMI->setMemRefs(LoadMI->memoperands_begin(), in foldMemoryOperand()
813 NewMI->setMemRefs(MI->memoperands_begin(), in foldMemoryOperand()
/external/llvm/lib/Target/Mips/
DMipsInstrInfo.cpp286 MIB.setMemRefs(I->memoperands_begin(), I->memoperands_end()); in genInstrWithNewOpc()
/external/llvm/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp157 cast<MachineSDNode>(node)->setMemRefs(MemOp, MemOp + 1); in Select()
/external/llvm/lib/Target/MSP430/
DMSP430ISelDAGToDAG.cpp368 cast<MachineSDNode>(ResNode)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectIndexedBinOp()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.cpp252 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in buildScratchLoadStore()
DSIInstrInfo.cpp2196 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in legalizeOperands()
2210 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in legalizeOperands()
2416 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); in moveSMRDToVALU()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp891 cast<MachineSDNode>(NVPTXLD)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectLoad()
1277 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectLoadVector()
2045 cast<MachineSDNode>(LD)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectLDGLDU()
2276 cast<MachineSDNode>(NVPTXST)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectStore()
2651 cast<MachineSDNode>(ST)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectStoreVector()
2901 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectStoreRetval()
3057 cast<MachineSDNode>(Ret)->setMemRefs(MemRefs0, MemRefs0 + 1); in SelectStoreParam()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGSDNodes.cpp160 MN->setMemRefs(Begin, End); in CloneNodeWithValues()
DInstrEmitter.cpp808 MIB.setMemRefs(cast<MachineSDNode>(Node)->memoperands_begin(), in EmitMachineNode()
/external/llvm/lib/Target/AArch64/
DAArch64ISelDAGToDAG.cpp1380 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1); in SelectStoreLane()
1415 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1); in SelectPostStoreLane()
2452 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1); in Select()
2472 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1); in Select()
DAArch64LoadStoreOptimizer.cpp568 MI->setMemRefs(MemBegin, MemEnd); in concatenateMemOperands()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp2000 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); in selectAtomicLoadArith()
2964 Result->setMemRefs(MemOp, MemOp + 2); in Select()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp8418 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjSetJmp()
8434 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjSetJmp()
8469 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjSetJmp()
8536 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjLongJmp()
8548 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjLongJmp()
8560 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjLongJmp()
8572 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjLongJmp()
8581 MIB.setMemRefs(MMOBegin, MMOEnd); in emitEHSjLjLongJmp()

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