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Searched refs:v32i1 (Results 1 – 11 of 11) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineValueType.h63 v32i1 = 17, // 32 x i1 enumerator
314 case v32i1: in getVectorElementType()
377 case v32i1: in getVectorNumElements()
454 case v32i1: in getSizeInBits()
590 if (NumElements == 32) return MVT::v32i1; in getVectorVT()
DValueTypes.td40 def v32i1 : ValueType<32 , 17>; // 32 x i1 vector value
/external/llvm/lib/IR/
DValueTypes.cpp144 case MVT::v32i1: return "v32i1"; in getEVTString()
222 case MVT::v32i1: return VectorType::get(Type::getInt1Ty(Context), 32); in getTypeForEVT()
/external/llvm/utils/TableGen/
DCodeGenTarget.cpp77 case MVT::v32i1: return "MVT::v32i1"; in getEnumName()
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td485 def VK32 : RegisterClass<"X86", [v32i1], 32, (add VK16)> {let Size = 32;}
493 def VK32WM : RegisterClass<"X86", [v32i1], 32, (add VK16WM)> {let Size = 32;}
DX86CallingConv.td50 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
293 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
566 CCIfType<[v32i1], CCPromoteToType<v32i8>>,
DX86InstrAVX512.td2066 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1,i32mem>,
2093 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
2094 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
2130 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
2132 def : Pat<(v32i1 (bitconvert (i32 (load addr:$src)))),
2188 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
2258 def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
2359 def : Pat<(xor (xor VK32:$src1, VK32:$src2), (v32i1 immAllOnesV)),
2398 defm KUNPCKWD : avx512_mask_unpck<"wd", VK32, v32i1, VK16, HasBWI>, PS;
2465 defm D : avx512_mask_setop<VK32, v32i1, Val>;
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DX86ISelLowering.cpp1622 addRegisterClass(MVT::v32i1, &X86::VK32RegClass); in X86TargetLowering()
1627 setOperationAction(ISD::SETCC, MVT::v32i1, Custom); in X86TargetLowering()
1636 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i1, Custom); in X86TargetLowering()
1640 setOperationAction(ISD::INSERT_SUBVECTOR, MVT::v32i1, Custom); in X86TargetLowering()
1646 setOperationAction(ISD::SELECT, MVT::v32i1, Custom); in X86TargetLowering()
1656 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v32i1, Custom); in X86TargetLowering()
1662 setOperationAction(ISD::TRUNCATE, MVT::v32i1, Custom); in X86TargetLowering()
1665 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v32i1, Custom); in X86TargetLowering()
1883 case 32: return MVT::v32i1; in getSetCCResultType()
1902 case 32: return MVT::v32i1; in getSetCCResultType()
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DX86InstrCompiler.td554 defm _V32I1 : CMOVrr_PSEUDO<VK32, v32i1>;
/external/llvm/include/llvm/IR/
DIntrinsics.td162 def llvm_v32i1_ty : LLVMType<v32i1>; // 32 x i1
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1788 for (MVT NativeVT : {MVT::v2i1, MVT::v4i1, MVT::v8i1, MVT::v32i1, MVT::v64i1, in HexagonTargetLowering()