Searched refs:v64i16 (Results 1 – 12 of 12) sorted by relevance
/external/llvm/include/llvm/CodeGen/ |
D | MachineValueType.h | 84 v64i16 = 36, // 64 x i16 enumerator 266 SimpleTy == MVT::v64i16 || SimpleTy == MVT::v32i32 || in is1024BitVector() 333 case v64i16: in getVectorElementType() 375 case v64i16: in getVectorNumElements() 498 case v64i16: in getSizeInBits() 613 if (NumElements == 64) return MVT::v64i16; in getVectorVT()
|
D | ValueTypes.td | 61 def v64i16 : ValueType<1024,36>; // 64 x i16 vector value
|
/external/llvm/lib/Target/Hexagon/ |
D | HexagonIntrinsicsV60.td | 127 def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))), 128 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1), 147 def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))), 148 (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1), 830 def: Pat<(v64i16 (trunc v64i32:$Vdd)), 831 (v64i16 (V6_vpackwh_sat_128B
|
D | HexagonISelLowering.cpp | 203 if (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_Hexagon_VarArg() 348 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector() 371 (LocVT == MVT::v16i64 || LocVT == MVT::v32i32 || LocVT == MVT::v64i16 || in CC_HexagonVector() 415 } else if (LocVT == MVT::v128i8 || LocVT == MVT::v64i16 || in RetCC_Hexagon() 546 ty == MVT::v16i64 || ty == MVT::v32i32 || ty == MVT::v64i16 || in IsHvxVectorType() 886 VT == MVT::v64i16 || VT == MVT::v128i8); in getIndexedAddressParts() 1090 RegVT == MVT::v64i16 || RegVT == MVT::v128i8))) { in LowerFormalArguments() 1098 RegVT == MVT::v64i16 || RegVT == MVT::v128i8)) { in LowerFormalArguments() 1571 addRegisterClass(MVT::v64i16, &Hexagon::VecDblRegsRegClass); in HexagonTargetLowering() 1577 addRegisterClass(MVT::v64i16, &Hexagon::VectorRegs128BRegClass); in HexagonTargetLowering() [all …]
|
D | HexagonRegisterInfo.td | 221 [v128i8, v64i16, v32i32, v16i64], 1024, 225 [v128i8, v64i16, v32i32, v16i64], 1024,
|
D | HexagonISelDAGToDAG.cpp | 415 LoadedVT == MVT::v64i16 || LoadedVT == MVT::v128i8) { in SelectIndexedLoad() 532 StoredVT == MVT::v64i16 || StoredVT == MVT::v128i8) { in SelectIndexedStore() 573 StoredVT == MVT::v64i16 || StoredVT == MVT::v128i8) in SelectIndexedStore()
|
D | HexagonInstrInfoV60.td | 781 defm : STrivv_pats <v64i16, v128i16>; 815 defm : vS32b_ai_pats <v32i16, v64i16>; 840 defm : LDrivv_pats <v64i16, v128i16>; 868 defm : vL32b_ai_pats <v32i16, v64i16>;
|
D | HexagonInstrInfoVector.td | 84 defm : bitconvert_dblvec<v64i16, v128i8>;
|
D | HexagonInstrInfo.cpp | 2292 VT == MVT::v64i16 || VT == MVT::v128i8) { in isValidAutoIncImm()
|
/external/llvm/lib/IR/ |
D | ValueTypes.cpp | 163 case MVT::v64i16: return "v64i16"; in getEVTString() 241 case MVT::v64i16: return VectorType::get(Type::getInt16Ty(Context), 64); in getTypeForEVT()
|
/external/llvm/utils/TableGen/ |
D | CodeGenTarget.cpp | 96 case MVT::v64i16: return "MVT::v64i16"; in getEnumName()
|
/external/llvm/include/llvm/IR/ |
D | Intrinsics.td | 183 def llvm_v64i16_ty : LLVMType<v64i16>; // 64 x i16
|