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Searched refs:A (Results 1 – 25 of 1139) sorted by relevance

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/toolchain/binutils/binutils-2.25/opcodes/
Diq2000-desc.c215 #define A(a) (1 << CGEN_HW_##a) macro
224 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
229 #undef A
234 #define A(a) (1 << CGEN_IFLD_##a) macro
250 { IQ2000_F_RD_RS, "f-rd-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
251 { IQ2000_F_RD_RT, "f-rd-rt", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
252 { IQ2000_F_RT_RS, "f-rt-rs", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
253 { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
254 …{ IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }…
255 …{ IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } …
[all …]
Depiphany-desc.c313 #define A(a) (1 << CGEN_HW_##a) macro
322 …GISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { {…
323 …EGISTERS, CGEN_ASM_KEYWORD, (PTR) & epiphany_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { {…
378 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
379 { "h-memaddr", HW_H_MEMADDR, CGEN_ASM_NONE, 0, { 0|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
387 #undef A
392 #define A(a) (1 << CGEN_IFLD_##a) macro
410 …{ EPIPHANY_F_SIMM8, "f-simm8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 }…
411 …{ EPIPHANY_F_SIMM24, "f-simm24", 0, 32, 31, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), …
426 { EPIPHANY_F_DC_9_1, "f-dc-9-1", 0, 32, 9, 1, { 0|A(RESERVED), { { { (1<<MACH_BASE), 0 } } } } },
[all …]
Dmep-desc.c559 #define A(a) (1 << CGEN_HW_##a) macro
568 …{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x…
569 …{ "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_gpr, { 0|A(PROFILE)|A(CACHE_ADDR),…
570 …{ "h-csr", HW_H_CSR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_csr, { 0|A(PROFILE), { { { (1<<MAC…
573 …{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr, { 0|A(VIRTUAL), { { { (1<<MACH_B…
576 …{ "h-cr-ivc2", HW_H_CR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_cr_ivc2, { 0|A(VIRTUAL), {…
577 …{ "h-ccr-ivc2", HW_H_CCR_IVC2, CGEN_ASM_KEYWORD, (PTR) & mep_cgen_opval_h_ccr_ivc2, { 0|A(VIRTUAL)…
581 #undef A
586 #define A(a) (1 << CGEN_IFLD_##a) macro
606 …{ MEP_F_CSRN, "f-csrn", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xd0" } } …
[all …]
Dor1k-desc.c277 #define A(a) (1 << CGEN_HW_##a) macro
286 …{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<MACH_OR6…
287 …{ "h-fsr", HW_H_FSR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fsr, { 0|A(VIRTUAL), { { { (1<<MA…
288 …{ "h-fdr", HW_H_FDR, CGEN_ASM_KEYWORD, (PTR) & or1k_cgen_opval_h_fdr, { 0|A(VIRTUAL), { { { (1<<MA…
289 …{ "h-spr", HW_H_SPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)|(1<<M…
291 …{ "h-sys-vr", HW_H_SYS_VR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32ND)…
292 …{ "h-sys-upr", HW_H_SYS_UPR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MACH_OR32N…
293 …{ "h-sys-cpucfgr", HW_H_SYS_CPUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<MA…
294 …{ "h-sys-dmmucfgr", HW_H_SYS_DMMUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<…
295 …{ "h-sys-immucfgr", HW_H_SYS_IMMUCFGR, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_OR32)|(1<<…
[all …]
Dfr30-desc.c254 #define A(a) (1 << CGEN_HW_##a) macro
263 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
264 …{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & fr30_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE…
286 #undef A
291 #define A(a) (1 << CGEN_IFLD_##a) macro
320 { FR30_F_I20, "f-i20", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
321 { FR30_F_I32, "f-i32", 16, 32, 0, 32, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
328 { FR30_F_REL9, "f-rel9", 0, 16, 8, 8, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
332 { FR30_F_REL12, "f-rel12", 0, 16, 5, 11, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
340 #undef A
[all …]
Dmt-desc.c189 #define A(a) (1 << CGEN_HW_##a) macro
199 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
203 #undef A
208 #define A(a) (1 << CGEN_IFLD_##a) macro
218 { MT_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
219 { MT_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
220 { MT_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
221 { MT_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
224 { MT_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } } },
284 { MT_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } } },
[all …]
Diq2000-opc.c226 #define A(a) (1 << CGEN_INSN_##a) macro
1891 #undef A
2279 #define A(a) (1 << CGEN_INSN_##a) macro
2291 { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2296 { 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2301 { 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2306 { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2311 { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2316 { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2321 { 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
[all …]
Dfrv-desc.c1842 #define A(a) (1 << CGEN_HW_##a) macro
1852 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
1870 …{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(PROFILE), { { { (1<<MA…
1871 …W_H_GR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFILE), { { {…
1872 …{ "h-gr_hi", HW_H_GR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFI…
1873 …{ "h-gr_lo", HW_H_GR_LO, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_gr_names, { 0|A(VIRTUAL)|A(PROFI…
1874 …{ "h-fr", HW_H_FR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(PROFILE), { { { (1<<MA…
1875 …W_H_FR_DOUBLE, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFILE), { { {…
1876 …{ "h-fr_int", HW_H_FR_INT, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PRO…
1877 …{ "h-fr_hi", HW_H_FR_HI, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fr_names, { 0|A(VIRTUAL)|A(PROFI…
[all …]
Depiphany-opc.c207 #define A(a) (1 << CGEN_INSN_##a) macro
1434 #undef A
2098 #define A(a) (1 << CGEN_INSN_##a) macro
2110 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2115 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2120 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2125 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2130 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2135 { 0|A(RELAXED)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
2140 { 0|A(RELAXABLE)|A(COND_CTI)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
[all …]
Dxc16x-desc.c625 #define A(a) (1 << CGEN_HW_##a) macro
634 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
635 …{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFIL…
636 …{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFIL…
637 …{ "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PRO…
638 …{ "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PRO…
639 …{ "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PRO…
640 … CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { {…
641 …EN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { {…
642 …{ "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(…
[all …]
Dxstormy16-desc.c221 #define A(a) (1 << CGEN_HW_##a) macro
230 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
232 …{ "h-Rb", HW_H_RB, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), { {…
233 …{ "h-Rbj", HW_H_RBJ, CGEN_ASM_KEYWORD, (PTR) & xstormy16_cgen_opval_gr_Rb_names, { 0|A(VIRTUAL), {…
234 { "h-Rpsw", HW_H_RPSW, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
235 { "h-z8", HW_H_Z8, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
236 { "h-z16", HW_H_Z16, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
237 { "h-cy", HW_H_CY, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
238 { "h-hc", HW_H_HC, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
239 { "h-ov", HW_H_OV, CGEN_ASM_NONE, 0, { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } } } } },
[all …]
Dm32r-desc.c229 #define A(a) (1 << CGEN_HW_##a) macro
238 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
242 …{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE…
254 #undef A
259 #define A(a) (1 << CGEN_IFLD_##a) macro
278 …{ M32R_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } }…
279 { M32R_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { { { (1<<MACH_BASE), 0 } } } } },
280 …{ M32R_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } …
281 …{ M32R_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } …
282 …{ M32R_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }…
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic54x/
Dall-opcodes.s267 ABS A, A ; 1
268 ABS A, B ; 2
269 ABS A ; 3
270 ABS B, A ; 4
274 ADD #00000h, 16, A, A ; 1
275 ADD #00001h, 16, A, B ; 2
276 ADD #00002h, 16, A ; 3
277 ADD #00003h, 16, B, A ; 4
281 ADD 00h, 16, A, A ; 1
282 ADD 01h, 16, A, B ; 2
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/
Dlb.d32 [ ]*54: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
34 [ ]*58: [A-Z0-9_]*LO[A-Z0-9_]* .data.*
36 [ ]*5c: [A-Z0-9_]*HI[A-Z0-9_]* big_external_data_label
38 [ ]*60: [A-Z0-9_]*LO[A-Z0-9_]* big_external_data_label
40 [ ]*64: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_data_label
42 [ ]*68: [A-Z0-9_]*HI[A-Z0-9_]* big_external_common
44 [ ]*6c: [A-Z0-9_]*LO[A-Z0-9_]* big_external_common
46 [ ]*70: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_common
48 [ ]*74: [A-Z0-9_]*HI[A-Z0-9_]* .bss.*
50 [ ]*78: [A-Z0-9_]*LO[A-Z0-9_]* .bss.*
[all …]
Dsb.d32 [ ]*54: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
34 [ ]*58: [A-Z0-9_]*LO[A-Z0-9_]* .data.*
36 [ ]*5c: [A-Z0-9_]*HI[A-Z0-9_]* big_external_data_label
38 [ ]*60: [A-Z0-9_]*LO[A-Z0-9_]* big_external_data_label
40 [ ]*64: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_data_label
42 [ ]*68: [A-Z0-9_]*HI[A-Z0-9_]* big_external_common
44 [ ]*6c: [A-Z0-9_]*LO[A-Z0-9_]* big_external_common
46 [ ]*70: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_common
48 [ ]*74: [A-Z0-9_]*HI[A-Z0-9_]* .bss.*
50 [ ]*78: [A-Z0-9_]*LO[A-Z0-9_]* .bss.*
[all …]
Dla.d28 [ ]*[0-9a-f]+: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
30 [ ]*[0-9a-f]+: [A-Z0-9_]*LO[A-Z0-9_]* .data.*
32 [ ]*[0-9a-f]+: [A-Z0-9_]*HI[A-Z0-9_]* big_external_data_label
34 [ ]*[0-9a-f]+: [A-Z0-9_]*LO[A-Z0-9_]* big_external_data_label
36 [ ]*[0-9a-f]+: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_data_label
38 [ ]*[0-9a-f]+: [A-Z0-9_]*HI[A-Z0-9_]* big_external_common
40 [ ]*[0-9a-f]+: [A-Z0-9_]*LO[A-Z0-9_]* big_external_common
42 [ ]*[0-9a-f]+: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_common
44 [ ]*[0-9a-f]+: [A-Z0-9_]*HI[A-Z0-9_]* .bss.*
46 [ ]*[0-9a-f]+: [A-Z0-9_]*LO[A-Z0-9_]* .bss.*
[all …]
Dulw.d31 [ ]*50: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
33 [ ]*54: [A-Z0-9_]*LO[A-Z0-9_]* .data.*
37 [ ]*60: [A-Z0-9_]*HI[A-Z0-9_]* big_external_data_label
39 [ ]*64: [A-Z0-9_]*LO[A-Z0-9_]* big_external_data_label
43 [ ]*70: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_data_label
47 [ ]*7c: [A-Z0-9_]*HI[A-Z0-9_]* big_external_common
49 [ ]*80: [A-Z0-9_]*LO[A-Z0-9_]* big_external_common
53 [ ]*8c: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_common
57 [ ]*98: [A-Z0-9_]*HI[A-Z0-9_]* .bss.*
59 [ ]*9c: [A-Z0-9_]*LO[A-Z0-9_]* .bss.*
[all …]
Dusd.d31 [ ]*50: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
33 [ ]*54: [A-Z0-9_]*LO[A-Z0-9_]* .data.*
37 [ ]*60: [A-Z0-9_]*HI[A-Z0-9_]* big_external_data_label
39 [ ]*64: [A-Z0-9_]*LO[A-Z0-9_]* big_external_data_label
43 [ ]*70: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_data_label
47 [ ]*7c: [A-Z0-9_]*HI[A-Z0-9_]* big_external_common
49 [ ]*80: [A-Z0-9_]*LO[A-Z0-9_]* big_external_common
53 [ ]*8c: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_common
57 [ ]*98: [A-Z0-9_]*HI[A-Z0-9_]* .bss.*
59 [ ]*9c: [A-Z0-9_]*LO[A-Z0-9_]* .bss.*
[all …]
Duld.d31 [ ]*50: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
33 [ ]*54: [A-Z0-9_]*LO[A-Z0-9_]* .data.*
37 [ ]*60: [A-Z0-9_]*HI[A-Z0-9_]* big_external_data_label
39 [ ]*64: [A-Z0-9_]*LO[A-Z0-9_]* big_external_data_label
43 [ ]*70: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_data_label
47 [ ]*7c: [A-Z0-9_]*HI[A-Z0-9_]* big_external_common
49 [ ]*80: [A-Z0-9_]*LO[A-Z0-9_]* big_external_common
53 [ ]*8c: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_common
57 [ ]*98: [A-Z0-9_]*HI[A-Z0-9_]* .bss.*
59 [ ]*9c: [A-Z0-9_]*LO[A-Z0-9_]* .bss.*
[all …]
Dusw.d31 [ ]*50: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
33 [ ]*54: [A-Z0-9_]*LO[A-Z0-9_]* .data.*
37 [ ]*60: [A-Z0-9_]*HI[A-Z0-9_]* big_external_data_label
39 [ ]*64: [A-Z0-9_]*LO[A-Z0-9_]* big_external_data_label
43 [ ]*70: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_data_label
47 [ ]*7c: [A-Z0-9_]*HI[A-Z0-9_]* big_external_common
49 [ ]*80: [A-Z0-9_]*LO[A-Z0-9_]* big_external_common
53 [ ]*8c: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_common
57 [ ]*98: [A-Z0-9_]*HI[A-Z0-9_]* .bss.*
59 [ ]*9c: [A-Z0-9_]*LO[A-Z0-9_]* .bss.*
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Dulh.d47 [ ]*90: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
49 [ ]*94: [A-Z0-9_]*LO[A-Z0-9_]* .data.*
55 [ ]*a8: [A-Z0-9_]*HI[A-Z0-9_]* big_external_data_label
57 [ ]*ac: [A-Z0-9_]*LO[A-Z0-9_]* big_external_data_label
63 [ ]*c0: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_data_label
69 [ ]*d4: [A-Z0-9_]*HI[A-Z0-9_]* big_external_common
71 [ ]*d8: [A-Z0-9_]*LO[A-Z0-9_]* big_external_common
77 [ ]*ec: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_common
83 [ ]*100: [A-Z0-9_]*HI[A-Z0-9_]* .bss.*
85 [ ]*104: [A-Z0-9_]*LO[A-Z0-9_]* .bss.*
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Dush.d48 [ ]*94: [A-Z0-9_]*HI[A-Z0-9_]* .data.*
50 [ ]*98: [A-Z0-9_]*LO[A-Z0-9_]* .data.*
58 [ ]*b4: [A-Z0-9_]*HI[A-Z0-9_]* big_external_data_label
60 [ ]*b8: [A-Z0-9_]*LO[A-Z0-9_]* big_external_data_label
68 [ ]*d4: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_data_label
76 [ ]*f0: [A-Z0-9_]*HI[A-Z0-9_]* big_external_common
78 [ ]*f4: [A-Z0-9_]*LO[A-Z0-9_]* big_external_common
86 [ ]*110: [A-Z0-9_]*GPREL[A-Z0-9_]* small_external_common
94 [ ]*12c: [A-Z0-9_]*HI[A-Z0-9_]* .bss.*
96 [ ]*130: [A-Z0-9_]*LO[A-Z0-9_]* .bss.*
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/toolchain/binutils/binutils-2.25/libiberty/
Dmd5.c67 ctx->A = (md5_uint32) 0x67452301; in md5_init_ctx()
86 buffer[0] = SWAP (ctx->A); in md5_read_ctx()
287 md5_uint32 A = ctx->A; in md5_process_block() local
303 md5_uint32 A_save = A; in md5_process_block()
336 OP (A, B, C, D, 7, (md5_uint32) 0xd76aa478); in md5_process_block()
337 OP (D, A, B, C, 12, (md5_uint32) 0xe8c7b756); in md5_process_block()
338 OP (C, D, A, B, 17, (md5_uint32) 0x242070db); in md5_process_block()
339 OP (B, C, D, A, 22, (md5_uint32) 0xc1bdceee); in md5_process_block()
340 OP (A, B, C, D, 7, (md5_uint32) 0xf57c0faf); in md5_process_block()
341 OP (D, A, B, C, 12, (md5_uint32) 0x4787c62a); in md5_process_block()
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/toolchain/binutils/binutils-2.25/include/opcode/
Dconvex.h45 #define A 4 macro
169 {17,0,a1r,A,0,0}, /* ldea */
195 {25,0,a1r,A,0,0}, /* pfork */
200 {18,5,a1r,A,0,0}, /* ld.b */
201 {18,6,a1r,A,0,0}, /* ld.h */
202 {18,7,a1r,A,0,0}, /* ld.w */
203 {27,7,a1r,A,0,0}, /* incr.w */
204 {21,5,a2r,A,0,0}, /* st.b */
205 {21,6,a2r,A,0,0}, /* st.h */
206 {21,7,a2r,A,0,0}, /* st.w */
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/toolchain/binutils/binutils-2.25/gold/
Darm-reloc.def15 // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 // table below. A relocation definition has the following information:
65 RD(PC24 , STATIC , Y, ARM , ((S + A) | T) - P , Y, -1, Y)
66 RD(ABS32 , STATIC , N, DATA , (S + A) | T , Y, -1, N)
67 RD(REL32 , STATIC , N, DATA , ((S + A) | T) - P , Y, -1, N)
68 RD(LDR_PC_G0 , STATIC , N, ARM , S + A - P , Y, 0, Y)
69 RD(ABS16 , STATIC , N, DATA , S + A , Y, -1, Y)
70 RD(ABS12 , STATIC , N, ARM , S + A , Y, -1, Y)
71 RD(THM_ABS5 , STATIC , N, THM16, S + A , Y, -1, Y)
72 RD(ABS8 , STATIC , N, DATA , S + A , Y, -1, Y)
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