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Searched refs:HW_H_UINT (Results 1 – 25 of 28) sorted by relevance

12

/toolchain/binutils/binutils-2.25/opcodes/
Dmt-desc.c195 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
336 { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
340 { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
344 { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
348 { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
352 { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
356 { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
360 { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
364 { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
368 { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
[all …]
Dxstormy16-desc.c227 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
390 { "imm2", XSTORMY16_OPERAND_IMM2, HW_H_UINT, 10, 2,
394 { "imm3", XSTORMY16_OPERAND_IMM3, HW_H_UINT, 4, 3,
398 { "imm3b", XSTORMY16_OPERAND_IMM3B, HW_H_UINT, 17, 3,
402 { "imm4", XSTORMY16_OPERAND_IMM4, HW_H_UINT, 8, 4,
406 { "imm8", XSTORMY16_OPERAND_IMM8, HW_H_UINT, 8, 8,
410 { "imm8small", XSTORMY16_OPERAND_IMM8SMALL, HW_H_UINT, 8, 8,
418 { "imm16", XSTORMY16_OPERAND_IMM16, HW_H_UINT, 16, 16,
422 { "lmem8", XSTORMY16_OPERAND_LMEM8, HW_H_UINT, 8, 8,
426 { "hmem8", XSTORMY16_OPERAND_HMEM8, HW_H_UINT, 8, 8,
[all …]
Dfr30-desc.c260 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
418 { "u4", FR30_OPERAND_U4, HW_H_UINT, 8, 4,
422 { "u4c", FR30_OPERAND_U4C, HW_H_UINT, 12, 4,
426 { "u8", FR30_OPERAND_U8, HW_H_UINT, 8, 8,
430 { "i8", FR30_OPERAND_I8, HW_H_UINT, 4, 8,
434 { "udisp6", FR30_OPERAND_UDISP6, HW_H_UINT, 8, 4,
454 { "u10", FR30_OPERAND_U10, HW_H_UINT, 8, 8,
458 { "i32", FR30_OPERAND_I32, HW_H_UINT, 0, 32,
466 { "i20", FR30_OPERAND_I20, HW_H_UINT, 0, 20,
470 { "dir8", FR30_OPERAND_DIR8, HW_H_UINT, 8, 8,
[all …]
Dxc16x-desc.c631 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
792 { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
796 { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
800 { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
804 { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
840 { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
844 { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
864 { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
868 { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
872 { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
[all …]
Dlm32-opinst.c60 { INPUT, "uimm", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM), 0, 0 },
66 { INPUT, "hi16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (HI16), 0, 0 },
73 { INPUT, "f_r0", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
110 { INPUT, "f_r0", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
111 { INPUT, "f_r1", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
112 { INPUT, "f_r2", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
143 { INPUT, "lo16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (LO16), 0, 0 },
188 { INPUT, "user", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (USER), 0, 0 },
194 { INPUT, "f_csr", HW_H_UINT, CGEN_MODE_UINT, 0, 0, 0 },
219 { INPUT, "lo16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (LO16), 0, 0 },
[all …]
Diq2000-desc.c221 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
346 { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
350 { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
366 { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
370 { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
374 { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
378 { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
382 { "_index", IQ2000_OPERAND__INDEX, HW_H_UINT, 8, 9,
386 { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
390 { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
[all …]
Dip2k-desc.c272 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
338 { "addr16cjp", IP2K_OPERAND_ADDR16CJP, HW_H_UINT, 12, 13,
350 { "bitno", IP2K_OPERAND_BITNO, HW_H_UINT, 11, 3,
354 { "addr16p", IP2K_OPERAND_ADDR16P, HW_H_UINT, 2, 3,
358 { "addr16h", IP2K_OPERAND_ADDR16H, HW_H_UINT, 7, 8,
362 { "addr16l", IP2K_OPERAND_ADDR16L, HW_H_UINT, 7, 8,
366 { "reti3", IP2K_OPERAND_RETI3, HW_H_UINT, 2, 3,
Dlm32-desc.c221 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
292 { "shift", LM32_OPERAND_SHIFT, HW_H_UINT, 4, 5,
300 { "uimm", LM32_OPERAND_UIMM, HW_H_UINT, 15, 16,
316 { "user", LM32_OPERAND_USER, HW_H_UINT, 10, 11,
320 { "exception", LM32_OPERAND_EXCEPTION, HW_H_UINT, 25, 26,
324 { "hi16", LM32_OPERAND_HI16, HW_H_UINT, 15, 16,
328 { "lo16", LM32_OPERAND_LO16, HW_H_UINT, 15, 16,
Dmep-desc.c565 …{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } } } } },
1042 { "csrn-idx", MEP_OPERAND_CSRN_IDX, HW_H_UINT, 8, 5,
1066 { "cccc", MEP_OPERAND_CCCC, HW_H_UINT, 8, 4,
1086 { "pcabs24a2", MEP_OPERAND_PCABS24A2, HW_H_UINT, 5, 23,
1098 { "uimm16", MEP_OPERAND_UIMM16, HW_H_UINT, 16, 16,
1102 { "code16", MEP_OPERAND_CODE16, HW_H_UINT, 16, 16,
1110 { "uimm2", MEP_OPERAND_UIMM2, HW_H_UINT, 10, 2,
1122 { "addr24a4", MEP_OPERAND_ADDR24A4, HW_H_UINT, 8, 22,
1126 { "code24", MEP_OPERAND_CODE24, HW_H_UINT, 4, 24,
1130 { "callnum", MEP_OPERAND_CALLNUM, HW_H_UINT, 5, 4,
[all …]
Dm32r-opinst.c60 { INPUT, "uimm16", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM16), 0, 0 },
392 { INPUT, "imm1", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (IMM1), 0, 0 },
424 { INPUT, "uimm5", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM5), 0, 0 },
503 { INPUT, "uimm4", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM4), 0, 0 },
564 { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM8), 0, 0 },
570 { INPUT, "uimm8", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM8), 0, 0 },
579 { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
586 { INPUT, "uimm3", HW_H_UINT, CGEN_MODE_UINT, OP_ENT (UIMM3), 0, 0 },
Dm32r-desc.c235 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
350 { "uimm3", M32R_OPERAND_UIMM3, HW_H_UINT, 5, 3,
354 { "uimm4", M32R_OPERAND_UIMM4, HW_H_UINT, 12, 4,
358 { "uimm5", M32R_OPERAND_UIMM5, HW_H_UINT, 11, 5,
362 { "uimm8", M32R_OPERAND_UIMM8, HW_H_UINT, 8, 8,
366 { "uimm16", M32R_OPERAND_UIMM16, HW_H_UINT, 16, 16,
370 { "imm1", M32R_OPERAND_IMM1, HW_H_UINT, 15, 1,
Depiphany-desc.c319 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
864 { "disp3", EPIPHANY_OPERAND_DISP3, HW_H_UINT, 9, 3,
868 { "trapnum6", EPIPHANY_OPERAND_TRAPNUM6, HW_H_UINT, 15, 6,
872 { "swi_num", EPIPHANY_OPERAND_SWI_NUM, HW_H_UINT, 15, 6,
876 { "disp11", EPIPHANY_OPERAND_DISP11, HW_H_UINT, 9, 11,
880 { "shift", EPIPHANY_OPERAND_SHIFT, HW_H_UINT, 9, 5,
892 { "direction", EPIPHANY_OPERAND_DIRECTION, HW_H_UINT, 20, 1,
896 { "dpmi", EPIPHANY_OPERAND_DPMI, HW_H_UINT, 24, 1,
Dfrv-desc.c1848 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
2224 { "eir", FRV_OPERAND_EIR, HW_H_UINT, 17, 6,
2232 { "u16", FRV_OPERAND_U16, HW_H_UINT, 15, 16,
2248 { "u6", FRV_OPERAND_U6, HW_H_UINT, 5, 6,
2256 { "cond", FRV_OPERAND_COND, HW_H_UINT, 8, 1,
2260 { "ccond", FRV_OPERAND_CCOND, HW_H_UINT, 12, 1,
2264 { "hint", FRV_OPERAND_HINT, HW_H_UINT, 17, 2,
2276 { "LI", FRV_OPERAND_LI, HW_H_UINT, 25, 1,
2280 { "lock", FRV_OPERAND_LOCK, HW_H_UINT, 25, 1,
2284 { "debug", FRV_OPERAND_DEBUG, HW_H_UINT, 25, 1,
[all …]
Dlm32-desc.h149 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dm32r-desc.h178 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dip2k-desc.h199 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dfr30-desc.h201 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dmt-desc.h187 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dxstormy16-desc.h228 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dm32c-desc.c706 …{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { …
1449 { "Regsetpop", M32C_OPERAND_REGSETPOP, HW_H_UINT, 8, 8,
1453 { "Regsetpush", M32C_OPERAND_REGSETPUSH, HW_H_UINT, 8, 8,
1465 { "Dsp-8-u6", M32C_OPERAND_DSP_8_U6, HW_H_UINT, 8, 6,
1469 { "Dsp-8-u8", M32C_OPERAND_DSP_8_U8, HW_H_UINT, 8, 8,
1473 { "Dsp-8-u16", M32C_OPERAND_DSP_8_U16, HW_H_UINT, 8, 16,
1485 { "Dsp-8-u24", M32C_OPERAND_DSP_8_U24, HW_H_UINT, 8, 24,
1489 { "Dsp-10-u6", M32C_OPERAND_DSP_10_U6, HW_H_UINT, 10, 6,
1493 { "Dsp-16-u8", M32C_OPERAND_DSP_16_U8, HW_H_UINT, 16, 8,
1497 { "Dsp-16-u16", M32C_OPERAND_DSP_16_U16, HW_H_UINT, 16, 16,
[all …]
Diq2000-desc.h244 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Depiphany-desc.h269 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dmep-desc.h208 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dxc16x-desc.h317 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator
Dm32c-desc.h174 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR enumerator

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