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/toolchain/binutils/binutils-2.25/opcodes/
Dia64-opc-m.c25 #define M IA64_TYPE_M, 1 macro
120 {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}, EMPTY},
125 {"mov", M, OpX3X4X2YZ(0, 0, 1, 0, 1, 1), {DAHR, IMMU16}, EMPTY},
132 {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}, EMPTY},
133 {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}, EMPTY},
134 {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV, 0, NULL},
135 {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV, 0, NULL},
137 {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS, 0, NULL},
138 {"alloc", M, OpX3 (1, 6), {R1, SOF, SOL, SOR}, PSEUDO|FIRST|NO_PRED|MOD_RRBS, 0, NULL},
140 {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV, 0, NULL},
[all …]
Dm68k-dis.c399 #define M(n0,n1,n2,n3,n4,n5,n6,n70,n71,n72,n73,n74) \ in m68k_valid_ea() macro
406 mask = M (1,1,1,1,1,1,1,1,1,1,1,1); in m68k_valid_ea()
409 mask = M (0,0,1,1,1,1,1,1,1,0,0,0); in m68k_valid_ea()
412 mask = M (1,1,1,1,1,1,1,1,1,0,0,0); in m68k_valid_ea()
415 mask = M (1,0,1,1,1,1,1,1,1,1,1,1); in m68k_valid_ea()
418 mask = M (1,0,1,1,1,1,1,1,1,1,1,0); in m68k_valid_ea()
421 mask = M (0,0,1,0,0,1,1,1,1,1,1,0); in m68k_valid_ea()
424 mask = M (0,0,1,0,0,1,1,1,1,0,0,0); in m68k_valid_ea()
427 mask = M (1,0,1,1,1,1,1,1,1,0,0,0); in m68k_valid_ea()
430 mask = M (1,0,1,0,0,1,1,1,1,0,0,0); in m68k_valid_ea()
[all …]
Dia64-ic.tbl70 mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM
71 mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP]
72 mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE]
73 mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV]
74 mov-from-AR-CFLG; IC:mov-from-AR-M[Field(ar3) == CFLG]
75 mov-from-AR-CSD; IC:mov-from-AR-M[Field(ar3) == CSD]
77 mov-from-AR-EFLAG; IC:mov-from-AR-M[Field(ar3) == EFLAG]
78 mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR]
79 mov-from-AR-FDR; IC:mov-from-AR-M[Field(ar3) == FDR]
80 mov-from-AR-FIR; IC:mov-from-AR-M[Field(ar3) == FIR]
[all …]
Dmmix-opc.c85 #define M mmix_type_memaccess_block macro
136 {"lda", Z (0x22), OP (regs_z_opt), M},
220 {"ldvts", Z (0x98), OP (regs_z_opt), M},
247 {"syncd", Z (0xb8), OP (x_regs_z), M},
250 {"prest", Z (0xba), OP (x_regs_z), M},
253 {"syncid", Z (0xbc), OP (x_regs_z), M},
318 | 0xffff, OP (save), M},
320 | 0xffff00, OP (unsave), M},
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/
Dinvalid-ar.l2 .*:2: Error: AR 0 can only be accessed by M-unit
3 .*:3: Error: AR 1 can only be accessed by M-unit
4 .*:4: Error: AR 2 can only be accessed by M-unit
5 .*:5: Error: AR 3 can only be accessed by M-unit
6 .*:6: Error: AR 4 can only be accessed by M-unit
7 .*:7: Error: AR 5 can only be accessed by M-unit
8 .*:8: Error: AR 6 can only be accessed by M-unit
9 .*:9: Error: AR 7 can only be accessed by M-unit
10 .*:10: Error: AR 8 can only be accessed by M-unit
11 .*:11: Error: AR 9 can only be accessed by M-unit
[all …]
/toolchain/binutils/binutils-2.25/libiberty/
Dsha1.c307 #define M(I) ( tm = x[I&0x0f] ^ x[(I-14)&0x0f] \ in sha1_process_block() macro
311 #define R(A,B,C,D,E,F,K,M) do { E += rol( A, 5 ) \ in sha1_process_block() argument
314 + M; \ in sha1_process_block()
344 R( e, a, b, c, d, F1, K1, M(16) ); in sha1_process_block()
345 R( d, e, a, b, c, F1, K1, M(17) ); in sha1_process_block()
346 R( c, d, e, a, b, F1, K1, M(18) ); in sha1_process_block()
347 R( b, c, d, e, a, F1, K1, M(19) ); in sha1_process_block()
348 R( a, b, c, d, e, F2, K2, M(20) ); in sha1_process_block()
349 R( e, a, b, c, d, F2, K2, M(21) ); in sha1_process_block()
350 R( d, e, a, b, c, F2, K2, M(22) ); in sha1_process_block()
[all …]
Dsafe-ctype.c151 #define M (const unsigned short) (nv|sp |cn) /* cursor movement: \f \v */ macro
162 C, T, V, M, M, V, C, C, /* BS HT LF VT FF CR SO SI */
/toolchain/binutils/binutils-2.25/include/opcode/
Di960.h123 #define M 0x7f /* Memory operand (MEMA & MEMB format instructions) */ macro
132 #define MEMOP(od) (od == M) /* TRUE if operand is a memory operand*/
263 { 0x80000000, "ldob", I_BASE, MEM1, 2, { M, R, 0 } },
264 { 0x82000000, "stob", I_BASE, MEM1, 2, { R, M, 0 } },
265 { 0x84000000, "bx", I_BASE, MEM1, 1, { M, 0, 0 } },
266 { 0x85000000, "balx", I_BASE, MEM1, 2, { M, R, 0 } },
267 { 0x86000000, "callx", I_BASE, MEM1, 1, { M, 0, 0 } },
268 { 0x88000000, "ldos", I_BASE, MEM2, 2, { M, R, 0 } },
269 { 0x8a000000, "stos", I_BASE, MEM2, 2, { R, M, 0 } },
270 { 0x8c000000, "lda", I_BASE, MEM1, 2, { M, R, 0 } },
[all …]
Daarch64.h932 #define DEBUG_TRACE(M, ...) \ argument
935 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
938 #define DEBUG_TRACE_IF(C, M, ...) \ argument
941 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
944 #define DEBUG_TRACE(M, ...) ; argument
945 #define DEBUG_TRACE_IF(C, M, ...) ; argument
/toolchain/binutils/binutils-2.25/bfd/
Dcpu-z80.c47 #define M(n) &arch_info_struct[n] macro
51 N (bfd_mach_z80strict, "z80-strict", FALSE, M(1)),
52 N (bfd_mach_z80, "z80", FALSE, M(2)),
53 N (bfd_mach_z80full, "z80-full", FALSE, M(3)),
57 const bfd_arch_info_type bfd_z80_arch = N (0, "z80-any", TRUE, M(0));
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/macros/
Dstrings.s1 .macro M arg1 macro
7 M "\\\"foo\\\""
11 M "bar"
15 M baz
/toolchain/binutils/binutils-2.25/ld/testsuite/ld-mmix/
Dgreg-6.d48 0+23 l \*REG\* 0+ M
65 0+33 l \*REG\* 0+ M
82 0+43 l \*REG\* 0+ M
99 0+53 l \*REG\* 0+ M
116 0+63 l \*REG\* 0+ M
133 0+73 l \*REG\* 0+ M
150 0+83 l \*REG\* 0+ M
167 0+93 l \*REG\* 0+ M
184 0+a3 l \*REG\* 0+ M
201 0+b3 l \*REG\* 0+ M
[all …]
Dgreg-7.d48 0+24 l \*REG\* 0+ M
65 0+34 l \*REG\* 0+ M
82 0+44 l \*REG\* 0+ M
99 0+54 l \*REG\* 0+ M
116 0+64 l \*REG\* 0+ M
133 0+74 l \*REG\* 0+ M
150 0+84 l \*REG\* 0+ M
167 0+94 l \*REG\* 0+ M
184 0+a4 l \*REG\* 0+ M
201 0+b4 l \*REG\* 0+ M
[all …]
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/frv/
Dfr450-media-issue.s1 ; M-1 first
15 ; M-2 first
29 ; M-3 first
43 ; M-4 first
57 ; M-5 first
71 ; M-6 first
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/
Dpr12198-2.d1 # name: PR12198 - Only select v6S-M when v6-M is selected (2)
10 Tag_CPU_arch: v6S-M
Darch7em-bad.d1 #name: Valid v7E-M, invalid v7-M
Darchv6s-m-bad.d1 #name: Valid v6S-M, invalid v6-M
Dpr12198-1.d1 # name: PR12198 - Only select v6S-M when v6-M is selected (1)
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/
Darithmetic.s112 r2.h = r7.l * r6.H (M, iu);
114 R0.H = r1.L * r1.H (M);
115 r1 = r7.H * r6.L (M, is);
135 a1 = r1.L * r0.H (M);
137 A1 = R7.H * R6.L (M, W32);
154 r2.h = (A1 = r0.H * r3.L) (M, Iss2);
158 r5.h = (a1 -= r3.H * r7.L) (M, tFu);
171 R5 = (A1 = r2.H * r3.H) (M, fu);
Darithmetic.d91 c4: 94 c3 be 40 R2.H = R7.L \* R6.H \(M, IU\);
93 cc: 14 c2 09 40 R0.H = R1.L \* R1.H \(M\);
94 d0: 1c c3 3e 80 R1 = R7.H \* R6.L \(M, IS\);
96 d8: 1c c2 b0 c0 R3 = R6.H \* R0.H \(M\);
109 f8: 10 c0 08 58 A1 = R1.L \* R0.H \(M\);
111 100: 70 c0 3e 98 A1 = R7.H \* R6.L \(M, W32\);
125 130: 34 c1 83 98 R2.H = \(A1 = R0.H \* R3.L\) \(M, ISS2\);
129 140: d6 c0 5f 99 R5.H = \(A1 -= R3.H \* R7.L\) \(M, TFU\);
139 160: 9c c0 13 d9 R5 = \(A1 = R2.H \* R3.H\) \(M, FU\);
143 170: 1e c1 17 59 R5 = \(A1 -= R2.L \* R7.H\) \(M, IS\);
Dvector.d61 94: 94 c2 5a e1 R5.H = R3.H \* R2.H \(M\), R5.L = R3.L \* R2.L \(FU\);
70 b8: 90 c0 1c c8 A1 = R3.H \* R4.H \(M\), A0 \+= R3.L \* R4.L \(FU\);
78 d8: 14 c0 3c a8 R0.H = \(A1 = R7.H \* R4.L\) \(M\), R0.L = \(A0 \+= R7.L \* R4.L\);
79 dc: 94 c0 5a e9 R5.H = \(A1 = R3.H \* R2.H\) \(M\), R5.L = \(A0 \+= R3.L \* R2.L\) \(FU\);
81 e4: 1c c0 b7 d0 R3 = \(A1 = R6.H \* R7.H\) \(M\), A0 -= R6.L \* R7.L;
82 e8: 1c c0 3c 2e R1 = \(A1 = R7.L \* R4.L\) \(M\), R0 = \(A0 \+= R7.H \* R4.H\);
88 100: 9c c0 1f e9 R5 = \(A1 = R3.H \* R7.H\) \(M\), R4 = \(A0 \+= R3.L \* R7.L\) \(FU\);
/toolchain/binutils/binutils-2.25/binutils/testsuite/binutils-all/windres/
Ddialogid.rsd11 0060 00000000 00000000 4d000050 0b000b00 ........M..P....
13 0080 53004e00 41004d00 45000000 ffff6c00 S.N.A.M.E.....l.
16 00b0 41005300 53004e00 41004d00 45000000 A.S.S.N.A.M.E...
/toolchain/binutils/binutils-2.25/ld/scripttempl/
Delf32cr16c.sc29 rom : ORIGIN = 1M, LENGTH = 3M
30 ram : ORIGIN = 4M, LENGTH = 10M
/toolchain/binutils/binutils-2.25/cpu/
Dfrv.opc697 /* M-2 or M-5 in slot m2 or m3 cannot coexist with M-2 in slot m1 or m2
702 /* M-4 in slot m2 or m3 cannot coexist with M-4 in slot m1 or m2
743 /* Cannot coexist with F-5, F-6, or M-7 insn. */
748 /* Cannot coexist with F-7, or M-7 insn. */
752 /* Cannot coexist with F-1, F-2, F-6, F-7, or M-7 insn. */
759 /* Cannot coexist with F-1, F-2, F-5, F-6, or M-7 insn. */
766 /* Cannot coexist with F-3, F-5, F-7, or M-7 insn. */
772 /* Cannot coexist with M-7 insn. */
776 /* Cannot coexist with M-5, M-6 or M-7 insn. */
781 /* Cannot coexist with M-6 insn. */
[all …]
Dfrv.cpu424 (unit u-media-3-acc "Media unit for M-3 using ACC" ()
1799 M-1 M-2
1813 M-1 M-2 M-3 M-4 M-5 M-6
1828 M-1 M-2 M-3 M-4 M-5 M-6 M-7 M-8
1843 M-1 M-2 M-3 M-4 M-5
7761 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
7762 (FR400-MAJOR M-1) (FR450-MAJOR M-1))
7772 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
7773 (FR400-MAJOR M-1) (FR450-MAJOR M-1))
7783 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
[all …]

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