1; Fujitsu FRV opcode support, for GNU Binutils. -*- Scheme -*- 2; 3; Copyright 2000, 2001, 2003, 2004, 2007, 2009 Free Software Foundation, Inc. 4; 5; Contributed by Red Hat Inc; developed under contract from Fujitsu. 6; 7; This file is part of the GNU Binutils. 8; 9; This program is free software; you can redistribute it and/or modify 10; it under the terms of the GNU General Public License as published by 11; the Free Software Foundation; either version 3 of the License, or 12; (at your option) any later version. 13; 14; This program is distributed in the hope that it will be useful, 15; but WITHOUT ANY WARRANTY; without even the implied warranty of 16; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17; GNU General Public License for more details. 18; 19; You should have received a copy of the GNU General Public License 20; along with this program; if not, write to the Free Software 21; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, 22; MA 02110-1301, USA. 23 24(include "simplify.inc") 25 26; define-arch must appear first 27 28(define-arch 29 (name frv) ; name of cpu architecture 30 (comment "Fujitsu FRV") 31 (insn-lsb0? #t) 32 (machs frv fr550 fr500 fr450 fr400 tomcat simple) 33 (isas frv) 34) 35 36(define-isa 37 (name frv) 38 (base-insn-bitsize 32) 39 ; Initial bitnumbers to decode insns by. 40 (decode-assist (24 23 22 21 20 19 18)) 41 (liw-insns 1) ; The frv fetches up to 1 insns at a time. 42 (parallel-insns 8) ; The frv executes up to 8 insns at a time. 43) 44 45; Cpu family definitions. 46; 47(define-cpu 48 ; cpu names must be distinct from the architecture name and machine names. 49 ; The "b" suffix stands for "base" and is the convention. 50 ; The "f" suffix stands for "family" and is the convention. 51 (name frvbf) 52 (comment "Fujitsu FRV base family") 53 (endian big) 54 (word-bitsize 32) 55) 56 57; Generic FR-V machine. Supports the entire architecture 58(define-mach 59 (name frv) 60 (comment "Generic FRV cpu") 61 (cpu frvbf) 62) 63(define-model 64 (name frv) (comment "Generic FRV model") (attrs) 65 (mach frv) 66 67 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 68 69 ; `state' is a list of variables for recording model state 70 ; (state) 71 72 (unit u-exec "Execution Unit" () 73 1 1 ; issue done 74 () ; state 75 () ; inputs 76 () ; outputs 77 () ; profile action (default) 78 ) 79) 80 81; FR550 machine 82(define-mach 83 (name fr550) 84 (comment "FR550 cpu") 85 (cpu frvbf) 86) 87(define-model 88 (name fr550) (comment "FR550 model") (attrs) 89 (mach fr550) 90 91 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 92 93 ; `state' is a list of variables for recording model state 94 (state 95 ; State items 96 ; These are all masks with each bit representing one register. 97 (prev-fr-load DI) ; Previous use of FR register was target of a load 98 (prev-fr-complex-1 DI) ; Previous use of FR register has variable latency 99 (prev-fr-complex-2 DI) ; Previous use of FR register has variable latency 100 (prev-ccr-complex DI) ; Previous use of CCR register has variable latency 101 (prev-acc-mmac DI) ; Previous use of ACC register was a MMAC category 102 (cur-fr-load DI) ; Current use of FR register was target of a load 103 (cur-fr-complex-1 DI) ; Current use of FR register has variable latency 104 (cur-fr-complex-2 DI) ; Current use of FR register has variable latency 105 (cur-ccr-complex SI) ; Current use of CCR register has variable latency 106 (cur-acc-mmac DI) ; Current use of ACC register was a MMAC category 107 ) 108 ; Basic unit for instructions with no latency penalties 109 (unit u-exec "Execution Unit" () 110 1 1 ; issue done 111 () ; state 112 () ; inputs 113 () ; outputs 114 () ; profile action (default) 115 ) 116 ; Basic integer insn unit 117 (unit u-integer "Integer Unit" () 118 1 1 ; issue done 119 () ; state 120 ((GRi INT -1) (GRj INT -1)) ; inputs 121 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 122 () ; profile action (default) 123 ) 124 ; Integer multiplication unit 125 (unit u-imul "Integer Multiplication Unit" () 126 1 1 ; issue done 127 () ; state 128 ((GRi INT -1) (GRj INT -1)) ; inputs 129 ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs 130 () ; profile action (default) 131 ) 132 ; Integer division unit 133 (unit u-idiv "Integer Division Unit" () 134 1 1 ; issue done 135 () ; state 136 ((GRi INT -1) (GRj INT -1)) ; inputs 137 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 138 () ; profile action (default) 139 ) 140 ; Branch unit 141 (unit u-branch "Branch Unit" () 142 1 1 ; issue done 143 () ; state 144 ((GRi INT -1) (GRj INT -1) 145 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 146 ((pc)) ; outputs 147 () ; profile action (default) 148 ) 149 ; Trap unit 150 (unit u-trap "Trap Unit" () 151 1 1 ; issue done 152 () ; state 153 ((GRi INT -1) (GRj INT -1) 154 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 155 () ; outputs 156 () ; profile action (default) 157 ) 158 ; Condition code check unit 159 (unit u-check "Check Unit" () 160 1 1 ; issue done 161 () ; state 162 ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs 163 () ; outputs 164 () ; profile action (default) 165 ) 166 ; Float Arithmetic unit 167 (unit u-float-arith "Float Arithmetic unit" () 168 1 1 ; issue done 169 () ; state 170 ((FRi INT -1) (FRj INT -1) ; inputs 171 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 172 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 173 () ; profile action (default) 174 ) 175 ; Float Dual Arithmetic unit 176 (unit u-float-dual-arith "Float Arithmetic unit" () 177 ; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI 178 1 3 ; issue done 179 () ; state 180 ((FRi INT -1) (FRj INT -1) ; inputs 181 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 182 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 183 () ; profile action (default) 184 ) 185 ; Float Div unit 186 (unit u-float-div "Float Div unit" () 187 1 1 ; issue done 188 () ; state 189 ((FRi INT -1) (FRj INT -1)) ; inputs 190 ((FRk INT -1)) ; outputs 191 () ; profile action (default) 192 ) 193 ; Float Square Root unit 194 (unit u-float-sqrt "Float Square Root unit" () 195 1 1 ; issue done 196 () ; state 197 ((FRj INT -1) (FRdoublej INT -1)) ; inputs 198 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 199 () ; profile action (default) 200 ) 201 ; Float Compare unit 202 (unit u-float-compare "Float Compare unit" () 203 1 1 ; issue done 204 () ; state 205 ((FRi INT -1) (FRj INT -1) 206 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 207 ((FCCi_2 INT -1)) ; outputs 208 () ; profile action (default) 209 ) 210 ; Dual Float Compare unit 211 (unit u-float-dual-compare "Float Dual Compare unit" () 212 ; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI 213 1 3 ; issue done 214 () ; state 215 ((FRi INT -1) (FRj INT -1)) ; inputs 216 ((FCCi_2 INT -1)) ; outputs 217 () ; profile action (default) 218 ) 219 ; FR Move to GR unit 220 (unit u-fr2gr "FR Move to GR Unit" () 221 1 1 ; issue done 222 () ; state 223 ((FRintk INT -1)) ; inputs 224 ((GRj INT -1)) ; outputs 225 () ; profile action (default) 226 ) 227 ; GR Move to FR unit 228 (unit u-gr2fr "GR Move to FR Unit" () 229 1 1 ; issue done 230 () ; state 231 ((GRj INT -1)) ; inputs 232 ((FRintk INT -1)) ; outputs 233 () ; profile action (default) 234 ) 235 ; SPR Move to GR unit 236 (unit u-spr2gr "SPR Move to GR Unit" () 237 1 1 ; issue done 238 () ; state 239 ((spr INT -1)) ; inputs 240 ((GRj INT -1)) ; outputs 241 () ; profile action (default) 242 ) 243 ; GR Move to SPR unit 244 (unit u-gr2spr "GR Move to SPR Unit" () 245 1 1 ; issue done 246 () ; state 247 ((GRj INT -1)) ; inputs 248 ((spr INT -1)) ; outputs 249 () ; profile action (default) 250 ) 251 ; GR set half unit 252 (unit u-set-hilo "GR Set Half" () 253 1 1 ; issue done 254 () ; state 255 () ; inputs 256 ((GRkhi INT -1) (GRklo INT -1)) ; outputs 257 () ; profile action (default) 258 ) 259 ; GR load unit 260 (unit u-gr-load "GR Load Unit" () 261 1 1 ; issue done 262 () ; state 263 ((GRi INT -1) (GRj INT -1)) ; inputs 264 ((GRk INT -1) (GRdoublek INT -1)) ; outputs 265 () ; profile action (default) 266 ) 267 ; GR store unit 268 (unit u-gr-store "GR Store Unit" () 269 1 1 ; issue done 270 () ; state 271 ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs 272 () ; outputs 273 () ; profile action (default) 274 ) 275 ; FR load unit 276 (unit u-fr-load "FR Load Unit" () 277 1 1 ; issue done 278 () ; state 279 ((GRi INT -1) (GRj INT -1)) ; inputs 280 ((FRintk INT -1) (FRdoublek INT -1)) ; outputs 281 () ; profile action (default) 282 ) 283 ; FR store unit 284 (unit u-fr-store "FR Store Unit" () 285 1 1 ; issue done 286 () ; state 287 ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs 288 () ; outputs 289 () ; profile action (default) 290 ) 291 ; Swap unit 292 (unit u-swap "Swap Unit" () 293 1 1 ; issue done 294 () ; state 295 ((GRi INT -1) (GRj INT -1)) ; inputs 296 ((GRk INT -1)) ; outputs 297 () ; profile action (default) 298 ) 299 ; FR Move to FR unit 300 (unit u-fr2fr "FR Move to FR Unit" () 301 1 1 ; issue done 302 () ; state 303 ((FRi INT -1)) ; inputs 304 ((FRk INT -1)) ; outputs 305 () ; profile action (default) 306 ) 307 ; Clrgr unit 308 (unit u-clrgr "Clrgr Unit" () 309 1 1 ; issue done 310 () ; state 311 ((GRk INT -1)) ; inputs 312 () ; outputs 313 () ; profile action (default) 314 ) 315 ; Clrfr unit 316 (unit u-clrfr "Clrfr Unit" () 317 1 1 ; issue done 318 () ; state 319 ((FRk INT -1)) ; inputs 320 () ; outputs 321 () ; profile action (default) 322 ) 323 ; Insn cache invalidate unit 324 (unit u-ici "Insn cache invalidate unit" () 325 1 1 ; issue done 326 () ; state 327 ((GRi INT -1) (GRj INT -1)) ; inputs 328 () ; outputs 329 () ; profile action (default) 330 ) 331 ; Data cache invalidate unit 332 (unit u-dci "Data cache invalidate unit" () 333 1 1 ; issue done 334 () ; state 335 ((GRi INT -1) (GRj INT -1)) ; inputs 336 () ; outputs 337 () ; profile action (default) 338 ) 339 ; Data cache flush unit 340 (unit u-dcf "Data cache flush unit" () 341 1 1 ; issue done 342 () ; state 343 ((GRi INT -1) (GRj INT -1)) ; inputs 344 () ; outputs 345 () ; profile action (default) 346 ) 347 ; Insn cache preload unit 348 (unit u-icpl "Insn cache preload unit" () 349 1 1 ; issue done 350 () ; state 351 ((GRi INT -1) (GRj INT -1)) ; inputs 352 () ; outputs 353 () ; profile action (default) 354 ) 355 ; Data cache preload unit 356 (unit u-dcpl "Data cache preload unit" () 357 1 1 ; issue done 358 () ; state 359 ((GRi INT -1) (GRj INT -1)) ; inputs 360 () ; outputs 361 () ; profile action (default) 362 ) 363 ; Insn cache unlock unit 364 (unit u-icul "Insn cache unlock unit" () 365 1 1 ; issue done 366 () ; state 367 ((GRi INT -1) (GRj INT -1)) ; inputs 368 () ; outputs 369 () ; profile action (default) 370 ) 371 ; Data cache unlock unit 372 (unit u-dcul "Data cache unlock unit" () 373 1 1 ; issue done 374 () ; state 375 ((GRi INT -1) (GRj INT -1)) ; inputs 376 () ; outputs 377 () ; profile action (default) 378 ) 379 ; commit unit 380 (unit u-commit "Commit Unit" () 381 1 1 ; issue done 382 () ; state 383 ((GRk INT -1) (FRk INT -1)) ; inputs 384 () ; outputs 385 () ; profile action (default) 386 ) 387 ; Float Conversion unit 388 (unit u-float-convert "Float Conversion unit" () 389 1 1 ; issue done 390 () ; state 391 ((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs 392 ((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs 393 () ; profile action (default) 394 ) 395 ; Media units 396 (unit u-media "Media unit" () 397 1 1 ; issue done 398 () ; state 399 ((FRinti INT -1) (FRintj INT -1)) ; inputs 400 ((FRintk INT -1)) ; outputs 401 () ; profile action (default) 402 ) 403 (unit u-media-quad "Media-quad unit" () 404 1 1 ; issue done 405 () ; state 406 ((FRintieven INT -1) (FRintjeven INT -1)) ; inputs 407 ((FRintkeven INT -1)) ; outputs 408 () ; profile action (default) 409 ) 410 (unit u-media-dual-expand "Media Dual Expand unit" () 411 1 1 ; issue done 412 () ; state 413 ((FRinti INT -1)) ; inputs 414 ((FRintkeven INT -1)) ; outputs 415 () ; profile action (default) 416 ) 417 (unit u-media-3-dual "Media-3-dual unit" () 418 1 1 ; issue done 419 () ; state 420 ((FRinti INT -1)) ; inputs 421 ((FRintk INT -1)) ; outputs 422 () ; profile action (default) 423 ) 424 (unit u-media-3-acc "Media unit for M-3 using ACC" () 425 1 1 ; issue done 426 () ; state 427 ((FRintj INT -1) (ACC40Si INT -1)) ; inputs 428 ((FRintk INT -1)) ; outputs 429 () ; profile action (default) 430 ) 431 (unit u-media-3-acc-dual "Media-3-acc-dual unit" () 432 1 1 ; issue done 433 () ; state 434 ((ACC40Si INT -1)) ; inputs 435 ((FRintkeven INT -1)) ; outputs 436 () ; profile action (default) 437 ) 438 (unit u-media-3-wtacc "Media-3-wtacc unit" () 439 1 1 ; issue done 440 () ; state 441 ((FRinti INT -1) (ACC40Sk INT -1)) ; inputs 442 () ; outputs 443 () ; profile action (default) 444 ) 445 (unit u-media-3-mclracc "Media-3-mclracc unit" () 446 1 1 ; issue done 447 () ; state 448 () ; inputs 449 () ; outputs 450 () ; profile action (default) 451 ) 452 (unit u-media-set "Media set" () 453 1 1 ; issue done 454 () ; state 455 () ; inputs 456 ((FRintk INT -1)) ; outputs 457 () ; profile action (default) 458 ) 459 (unit u-media-4 "Media-4 unit" () 460 1 1 ; issue done 461 () ; state 462 ((FRinti INT -1) (FRintj INT -1)) ; inputs 463 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 464 () ; profile action (default) 465 ) 466 (unit u-media-4-acc "Media-4-acc unit" () 467 1 1 ; issue done 468 () ; state 469 ((ACC40Si INT -1)) ; inputs 470 ((ACC40Sk INT -1)) ; outputs 471 () ; profile action (default) 472 ) 473 (unit u-media-4-acc-dual "Media-4-acc-dual unit" () 474 1 1 ; issue done 475 () ; state 476 ((ACC40Si INT -1)) ; inputs 477 ((ACC40Sk INT -1)) ; outputs 478 () ; profile action (default) 479 ) 480 (unit u-media-4-add-sub "Media-4-add-sub unit" () 481 1 1 ; issue done 482 () ; state 483 ((ACC40Si INT -1)) ; inputs 484 ((ACC40Sk INT -1)) ; outputs 485 () ; profile action (default) 486 ) 487 (unit u-media-4-add-sub-dual "Media-4-add-sub-dual unit" () 488 1 1 ; issue done 489 () ; state 490 ((ACC40Si INT -1)) ; inputs 491 ((ACC40Sk INT -1)) ; outputs 492 () ; profile action (default) 493 ) 494 (unit u-media-4-quad "Media-4-quad unit" () 495 1 1 ; issue done 496 () ; state 497 ((FRintieven INT -1) (FRintjeven INT -1)) ; inputs 498 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 499 () ; profile action (default) 500 ) 501) 502 503; FR500 machine. 504(define-mach 505 (name fr500) 506 (comment "FR500 cpu") 507 (cpu frvbf) 508) 509(define-model 510 (name fr500) (comment "FR500 model") (attrs) 511 (mach fr500) 512 513 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 514 515 ; `state' is a list of variables for recording model state 516 (state 517 ; State items 518 ; These are all masks with each bit representing one register. 519 (prev-fpop DI) ; Previous use of FR register was floating point insn 520 (prev-media DI) ; Previous use of FR register was a media insn 521 (prev-cc-complex DI) ; Previous use of ICC register was not simple 522 (cur-fpop DI) ; Current use of FR register was floating point insn 523 (cur-media DI) ; Current use of FR register was a media insn 524 (cur-cc-complex DI) ; Current use of ICC register was not simple 525 ) 526 ; Basic unit for instructions with no latency penalties 527 (unit u-exec "Execution Unit" () 528 1 1 ; issue done 529 () ; state 530 () ; inputs 531 () ; outputs 532 () ; profile action (default) 533 ) 534 ; Basic integer insn unit 535 (unit u-integer "Integer Unit" () 536 1 1 ; issue done 537 () ; state 538 ((GRi INT -1) (GRj INT -1)) ; inputs 539 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 540 () ; profile action (default) 541 ) 542 ; Integer multiplication unit 543 (unit u-imul "Integer Multiplication Unit" () 544 1 1 ; issue done 545 () ; state 546 ((GRi INT -1) (GRj INT -1)) ; inputs 547 ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs 548 () ; profile action (default) 549 ) 550 ; Integer division unit 551 (unit u-idiv "Integer Division Unit" () 552 1 1 ; issue done 553 () ; state 554 ((GRi INT -1) (GRj INT -1)) ; inputs 555 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 556 () ; profile action (default) 557 ) 558 ; Branch unit 559 (unit u-branch "Branch Unit" () 560 1 1 ; issue done 561 () ; state 562 ((GRi INT -1) (GRj INT -1) 563 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 564 ((pc)) ; outputs 565 () ; profile action (default) 566 ) 567 ; Trap unit 568 (unit u-trap "Trap Unit" () 569 1 1 ; issue done 570 () ; state 571 ((GRi INT -1) (GRj INT -1) 572 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 573 () ; outputs 574 () ; profile action (default) 575 ) 576 ; Condition code check unit 577 (unit u-check "Check Unit" () 578 1 1 ; issue done 579 () ; state 580 ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs 581 () ; outputs 582 () ; profile action (default) 583 ) 584 ; Clrgr unit 585 (unit u-clrgr "Clrgr Unit" () 586 1 1 ; issue done 587 () ; state 588 ((GRk INT -1)) ; inputs 589 () ; outputs 590 () ; profile action (default) 591 ) 592 ; Clrfr unit 593 (unit u-clrfr "Clrfr Unit" () 594 1 1 ; issue done 595 () ; state 596 ((FRk INT -1)) ; inputs 597 () ; outputs 598 () ; profile action (default) 599 ) 600 ; GR set half unit 601 (unit u-set-hilo "GR Set Half" () 602 1 1 ; issue done 603 () ; state 604 () ; inputs 605 ((GRkhi INT -1) (GRklo INT -1)) ; outputs 606 () ; profile action (default) 607 ) 608 ; GR load unit -- TODO doesn't handle quad 609 (unit u-gr-load "GR Load Unit" () 610 1 1 ; issue done 611 () ; state 612 ((GRi INT -1) (GRj INT -1)) ; inputs 613 ((GRk INT -1) (GRdoublek INT -1)) ; outputs 614 () ; profile action (default) 615 ) 616 ; GR store unit -- TODO doesn't handle quad 617 (unit u-gr-store "GR Store Unit" () 618 1 1 ; issue done 619 () ; state 620 ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs 621 () ; outputs 622 () ; profile action (default) 623 ) 624 ; GR recovering store unit -- TODO doesn't handle quad 625 (unit u-gr-r-store "GR Recovering Store Unit" () 626 1 1 ; issue done 627 () ; state 628 ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs 629 () ; outputs 630 () ; profile action (default) 631 ) 632 ; FR load unit -- TODO doesn't handle quad 633 (unit u-fr-load "FR Load Unit" () 634 1 1 ; issue done 635 () ; state 636 ((GRi INT -1) (GRj INT -1)) ; inputs 637 ((FRintk INT -1) (FRdoublek INT -1)) ; outputs 638 () ; profile action (default) 639 ) 640 ; FR store unit -- TODO doesn't handle quad 641 (unit u-fr-store "FR Store Unit" () 642 1 1 ; issue done 643 () ; state 644 ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs 645 () ; outputs 646 () ; profile action (default) 647 ) 648 ; FR recovering store unit -- TODO doesn't handle quad 649 (unit u-fr-r-store "FR Recovering Store Unit" () 650 1 1 ; issue done 651 () ; state 652 ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs 653 () ; outputs 654 () ; profile action (default) 655 ) 656 ; Swap unit 657 (unit u-swap "Swap Unit" () 658 1 1 ; issue done 659 () ; state 660 ((GRi INT -1) (GRj INT -1)) ; inputs 661 ((GRk INT -1)) ; outputs 662 () ; profile action (default) 663 ) 664 ; FR Move to FR unit 665 (unit u-fr2fr "FR Move to FR Unit" () 666 1 1 ; issue done 667 () ; state 668 ((FRi INT -1)) ; inputs 669 ((FRk INT -1)) ; outputs 670 () ; profile action (default) 671 ) 672 ; FR Move to GR unit 673 (unit u-fr2gr "FR Move to GR Unit" () 674 1 1 ; issue done 675 () ; state 676 ((FRintk INT -1)) ; inputs 677 ((GRj INT -1)) ; outputs 678 () ; profile action (default) 679 ) 680 ; SPR Move to GR unit 681 (unit u-spr2gr "SPR Move to GR Unit" () 682 1 1 ; issue done 683 () ; state 684 ((spr INT -1)) ; inputs 685 ((GRj INT -1)) ; outputs 686 () ; profile action (default) 687 ) 688 ; GR Move to FR unit 689 (unit u-gr2fr "GR Move to FR Unit" () 690 1 1 ; issue done 691 () ; state 692 ((GRj INT -1)) ; inputs 693 ((FRintk INT -1)) ; outputs 694 () ; profile action (default) 695 ) 696 ; GR Move to SPR unit 697 (unit u-gr2spr "GR Move to SPR Unit" () 698 1 1 ; issue done 699 () ; state 700 ((GRj INT -1)) ; inputs 701 ((spr INT -1)) ; outputs 702 () ; profile action (default) 703 ) 704 ; Float Arithmetic unit 705 (unit u-float-arith "Float Arithmetic unit" () 706 1 1 ; issue done 707 () ; state 708 ((FRi INT -1) (FRj INT -1) ; inputs 709 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 710 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 711 () ; profile action (default) 712 ) 713 ; Float Dual Arithmetic unit 714 (unit u-float-dual-arith "Float Arithmetic unit" () 715 1 1 ; issue done 716 () ; state 717 ((FRi INT -1) (FRj INT -1) ; inputs 718 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 719 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 720 () ; profile action (default) 721 ) 722 ; Float Div unit 723 (unit u-float-div "Float Div unit" () 724 1 1 ; issue done 725 () ; state 726 ((FRi INT -1) (FRj INT -1)) ; inputs 727 ((FRk INT -1)) ; outputs 728 () ; profile action (default) 729 ) 730 ; Float Square Root unit 731 (unit u-float-sqrt "Float Square Root unit" () 732 1 1 ; issue done 733 () ; state 734 ((FRj INT -1) (FRdoublej INT -1)) ; inputs 735 ((FRk INT -1) (FRdoublek INT -1)) ; outputs 736 () ; profile action (default) 737 ) 738 ; Float Dual Square Root unit 739 (unit u-float-dual-sqrt "Float Dual Square Root unit" () 740 1 1 ; issue done 741 () ; state 742 ((FRj INT -1)) ; inputs 743 ((FRk INT -1)) ; outputs 744 () ; profile action (default) 745 ) 746 ; Float Compare unit 747 (unit u-float-compare "Float Compare unit" () 748 1 1 ; issue done 749 () ; state 750 ((FRi INT -1) (FRj INT -1) 751 (FRdoublei INT -1) (FRdoublej INT -1)) ; inputs 752 ((FCCi_2 INT -1)) ; outputs 753 () ; profile action (default) 754 ) 755 ; Dual Float Compare unit 756 (unit u-float-dual-compare "Float Dual Compare unit" () 757 1 1 ; issue done 758 () ; state 759 ((FRi INT -1) (FRj INT -1)) ; inputs 760 ((FCCi_2 INT -1)) ; outputs 761 () ; profile action (default) 762 ) 763 ; Float Conversion unit 764 (unit u-float-convert "Float Conversion unit" () 765 1 1 ; issue done 766 () ; state 767 ((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs 768 ((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs 769 () ; profile action (default) 770 ) 771 ; Dual Float Conversion unit 772 (unit u-float-dual-convert "Float Dual Conversion unit" () 773 1 1 ; issue done 774 () ; state 775 ((FRj INT -1) (FRintj INT -1)) ; inputs 776 ((FRk INT -1) (FRintk INT -1)) ; outputs 777 () ; profile action (default) 778 ) 779 ; Media unit 780 (unit u-media "Media unit" () 781 1 1 ; issue done 782 () ; state 783 ((FRinti INT -1) (FRintj INT -1) (ACC40Si INT -1) (ACCGi INT -1)) ; inputs 784 ((FRintk INT -1) (ACC40Sk INT -1) (ACC40Uk INT -1) (ACCGk INT -1)) ; outputs 785 () ; profile action (default) 786 ) 787 ; Media Quad Arithmetic unit 788 (unit u-media-quad-arith "Media Quad Arithmetic unit" () 789 1 1 ; issue done 790 () ; state 791 ((FRinti INT -1) (FRintj INT -1)) ; inputs 792 ((FRintk INT -1)) ; outputs 793 () ; profile action (default) 794 ) 795 ; Media Dual Multiplication unit 796 (unit u-media-dual-mul "Media Dual Multiplication unit" () 797 1 1 ; issue done 798 () ; state 799 ((FRinti INT -1) (FRintj INT -1)) ; inputs 800 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 801 () ; profile action (default) 802 ) 803 ; Media Quad Multiplication unit 804 (unit u-media-quad-mul "Media Quad Multiplication unit" () 805 1 1 ; issue done 806 () ; state 807 ((FRinti INT -1) (FRintj INT -1)) ; inputs 808 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 809 () ; profile action (default) 810 ) 811 ; Media Quad Complex unit 812 (unit u-media-quad-complex "Media Quad Complex unit" () 813 1 1 ; issue done 814 () ; state 815 ((FRinti INT -1) (FRintj INT -1)) ; inputs 816 ((ACC40Sk INT -1)) ; outputs 817 () ; profile action (default) 818 ) 819 ; Media Dual Expand unit 820 (unit u-media-dual-expand "Media Dual Expand unit" () 821 1 1 ; issue done 822 () ; state 823 ((FRinti INT -1)) ; inputs 824 ((FRintk INT -1)) ; outputs 825 () ; profile action (default) 826 ) 827 ; Media Dual Unpack unit 828 (unit u-media-dual-unpack "Media Dual Unpack unit" () 829 1 1 ; issue done 830 () ; state 831 ((FRinti INT -1)) ; inputs 832 ((FRintk INT -1)) ; outputs 833 () ; profile action (default) 834 ) 835 ; Media Dual byte to half unit 836 (unit u-media-dual-btoh "Media Byte to byte" () 837 1 1 ; issue done 838 () ; state 839 ((FRintj INT -1)) ; inputs 840 ((FRintk INT -1)) ; outputs 841 () ; profile action (default) 842 ) 843 ; Media Dual half to byte unit 844 (unit u-media-dual-htob "Media Half to byte" () 845 1 1 ; issue done 846 () ; state 847 ((FRintj INT -1)) ; inputs 848 ((FRintk INT -1)) ; outputs 849 () ; profile action (default) 850 ) 851 ; Media Dual byte to half unit extended 852 (unit u-media-dual-btohe "Media Byte to byte extended" () 853 1 1 ; issue done 854 () ; state 855 ((FRintj INT -1)) ; inputs 856 ((FRintk INT -1)) ; outputs 857 () ; profile action (default) 858 ) 859 ; Barrier unit 860 (unit u-barrier "Barrier unit" () 861 1 1 ; issue done 862 () ; state 863 () ; inputs 864 () ; outputs 865 () ; profile action (default) 866 ) 867 ; Memory Barrier unit 868 (unit u-membar "Memory Barrier unit" () 869 1 1 ; issue done 870 () ; state 871 () ; inputs 872 () ; outputs 873 () ; profile action (default) 874 ) 875 ; Insn cache invalidate unit 876 (unit u-ici "Insn cache invalidate unit" () 877 1 1 ; issue done 878 () ; state 879 ((GRi INT -1) (GRj INT -1)) ; inputs 880 () ; outputs 881 () ; profile action (default) 882 ) 883 ; Data cache invalidate unit 884 (unit u-dci "Data cache invalidate unit" () 885 1 1 ; issue done 886 () ; state 887 ((GRi INT -1) (GRj INT -1)) ; inputs 888 () ; outputs 889 () ; profile action (default) 890 ) 891 ; Data cache flush unit 892 (unit u-dcf "Data cache flush unit" () 893 1 1 ; issue done 894 () ; state 895 ((GRi INT -1) (GRj INT -1)) ; inputs 896 () ; outputs 897 () ; profile action (default) 898 ) 899 ; Insn cache preload unit 900 (unit u-icpl "Insn cache preload unit" () 901 1 1 ; issue done 902 () ; state 903 ((GRi INT -1) (GRj INT -1)) ; inputs 904 () ; outputs 905 () ; profile action (default) 906 ) 907 ; Data cache preload unit 908 (unit u-dcpl "Data cache preload unit" () 909 1 1 ; issue done 910 () ; state 911 ((GRi INT -1) (GRj INT -1)) ; inputs 912 () ; outputs 913 () ; profile action (default) 914 ) 915 ; Insn cache unlock unit 916 (unit u-icul "Insn cache unlock unit" () 917 1 1 ; issue done 918 () ; state 919 ((GRi INT -1) (GRj INT -1)) ; inputs 920 () ; outputs 921 () ; profile action (default) 922 ) 923 ; Data cache unlock unit 924 (unit u-dcul "Data cache unlock unit" () 925 1 1 ; issue done 926 () ; state 927 ((GRi INT -1) (GRj INT -1)) ; inputs 928 () ; outputs 929 () ; profile action (default) 930 ) 931 ; commit unit 932 (unit u-commit "Commit Unit" () 933 1 1 ; issue done 934 () ; state 935 ((GRk INT -1) (FRk INT -1)) ; inputs 936 () ; outputs 937 () ; profile action (default) 938 ) 939) 940 941; Tomcat machine. Early version of fr500 machine 942(define-mach 943 (name tomcat) 944 (comment "Tomcat -- early version of fr500") 945 (cpu frvbf) 946) 947(define-model 948 (name tomcat) (comment "Tomcat model") (attrs) 949 (mach tomcat) 950 951 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 952 953 ; `state' is a list of variables for recording model state 954 ; (state) 955 956 (unit u-exec "Execution Unit" () 957 1 1 ; issue done 958 () ; state 959 () ; inputs 960 () ; outputs 961 () ; profile action (default) 962 ) 963) 964 965; FR400 machine 966(define-mach 967 (name fr400) 968 (comment "FR400 cpu") 969 (cpu frvbf) 970) 971(define-model 972 (name fr400) (comment "FR400 model") (attrs) 973 (mach fr400) 974 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 975 ; `state' is a list of variables for recording model state 976 (state 977 ; State items 978 ; These are all masks with each bit representing one register. 979 (prev-fp-load DI) ; Previous use of FR register was floating point load 980 (prev-fr-p4 DI) ; Previous use of FR register was media unit 4 981 (prev-fr-p6 DI) ; Previous use of FR register was media unit 6 982 (prev-acc-p2 DI) ; Previous use of ACC register was media unit 2 983 (prev-acc-p4 DI) ; Previous use of ACC register was media unit 4 984 (cur-fp-load DI) ; Current use of FR register is floating point load 985 (cur-fr-p4 DI) ; Current use of FR register is media unit 4 986 (cur-fr-p6 DI) ; Current use of FR register is media unit 6 987 (cur-acc-p2 DI) ; Current use of ACC register is media unit 2 988 (cur-acc-p4 DI) ; Current use of ACC register is media unit 4 989 ) 990 (unit u-exec "Execution Unit" () 991 1 1 ; issue done 992 () ; state 993 () ; inputs 994 () ; outputs 995 () ; profile action (default) 996 ) 997 ; Basic integer insn unit 998 (unit u-integer "Integer Unit" () 999 1 1 ; issue done 1000 () ; state 1001 ((GRi INT -1) (GRj INT -1)) ; inputs 1002 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 1003 () ; profile action (default) 1004 ) 1005 ; Integer multiplication unit 1006 (unit u-imul "Integer Multiplication Unit" () 1007 1 1 ; issue done 1008 () ; state 1009 ((GRi INT -1) (GRj INT -1)) ; inputs 1010 ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs 1011 () ; profile action (default) 1012 ) 1013 ; Integer division unit 1014 (unit u-idiv "Integer Division Unit" () 1015 1 1 ; issue done 1016 () ; state 1017 ((GRi INT -1) (GRj INT -1)) ; inputs 1018 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 1019 () ; profile action (default) 1020 ) 1021 ; Branch unit 1022 (unit u-branch "Branch Unit" () 1023 1 1 ; issue done 1024 () ; state 1025 ((GRi INT -1) (GRj INT -1) 1026 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 1027 ((pc)) ; outputs 1028 () ; profile action (default) 1029 ) 1030 ; Trap unit 1031 (unit u-trap "Trap Unit" () 1032 1 1 ; issue done 1033 () ; state 1034 ((GRi INT -1) (GRj INT -1) 1035 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 1036 () ; outputs 1037 () ; profile action (default) 1038 ) 1039 ; Condition code check unit 1040 (unit u-check "Check Unit" () 1041 1 1 ; issue done 1042 () ; state 1043 ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs 1044 () ; outputs 1045 () ; profile action (default) 1046 ) 1047 ; GR set half unit 1048 (unit u-set-hilo "GR Set Half" () 1049 1 1 ; issue done 1050 () ; state 1051 () ; inputs 1052 ((GRkhi INT -1) (GRklo INT -1)) ; outputs 1053 () ; profile action (default) 1054 ) 1055 ; GR load unit -- TODO doesn't handle quad 1056 (unit u-gr-load "GR Load Unit" () 1057 1 1 ; issue done 1058 () ; state 1059 ((GRi INT -1) (GRj INT -1)) ; inputs 1060 ((GRk INT -1) (GRdoublek INT -1)) ; outputs 1061 () ; profile action (default) 1062 ) 1063 ; GR store unit -- TODO doesn't handle quad 1064 (unit u-gr-store "GR Store Unit" () 1065 1 1 ; issue done 1066 () ; state 1067 ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs 1068 () ; outputs 1069 () ; profile action (default) 1070 ) 1071 ; FR load unit -- TODO doesn't handle quad 1072 (unit u-fr-load "FR Load Unit" () 1073 1 1 ; issue done 1074 () ; state 1075 ((GRi INT -1) (GRj INT -1)) ; inputs 1076 ((FRintk INT -1) (FRdoublek INT -1)) ; outputs 1077 () ; profile action (default) 1078 ) 1079 ; FR store unit -- TODO doesn't handle quad 1080 (unit u-fr-store "FR Store Unit" () 1081 1 1 ; issue done 1082 () ; state 1083 ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs 1084 () ; outputs 1085 () ; profile action (default) 1086 ) 1087 ; Swap unit 1088 (unit u-swap "Swap Unit" () 1089 1 1 ; issue done 1090 () ; state 1091 ((GRi INT -1) (GRj INT -1)) ; inputs 1092 ((GRk INT -1)) ; outputs 1093 () ; profile action (default) 1094 ) 1095 ; FR Move to GR unit 1096 (unit u-fr2gr "FR Move to GR Unit" () 1097 1 1 ; issue done 1098 () ; state 1099 ((FRintk INT -1)) ; inputs 1100 ((GRj INT -1)) ; outputs 1101 () ; profile action (default) 1102 ) 1103 ; SPR Move to GR unit 1104 (unit u-spr2gr "SPR Move to GR Unit" () 1105 1 1 ; issue done 1106 () ; state 1107 ((spr INT -1)) ; inputs 1108 ((GRj INT -1)) ; outputs 1109 () ; profile action (default) 1110 ) 1111 ; GR Move to FR unit 1112 (unit u-gr2fr "GR Move to FR Unit" () 1113 1 1 ; issue done 1114 () ; state 1115 ((GRj INT -1)) ; inputs 1116 ((FRintk INT -1)) ; outputs 1117 () ; profile action (default) 1118 ) 1119 ; GR Move to SPR unit 1120 (unit u-gr2spr "GR Move to SPR Unit" () 1121 1 1 ; issue done 1122 () ; state 1123 ((GRj INT -1)) ; inputs 1124 ((spr INT -1)) ; outputs 1125 () ; profile action (default) 1126 ) 1127 ; Media unit M1 -- see table 13-8 in the fr400 LSI 1128 (unit u-media-1 "Media-1 unit" () 1129 1 1 ; issue done 1130 () ; state 1131 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1132 ((FRintk INT -1)) ; outputs 1133 () ; profile action (default) 1134 ) 1135 (unit u-media-1-quad "Media-1-quad unit" () 1136 1 1 ; issue done 1137 () ; state 1138 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1139 ((FRintk INT -1)) ; outputs 1140 () ; profile action (default) 1141 ) 1142 (unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" () 1143 1 1 ; issue done 1144 () ; state 1145 () ; inputs 1146 ((FRkhi INT -1) (FRklo INT -1)) ; outputs 1147 () ; profile action (default) 1148 ) 1149 ; Media unit M2 -- see table 13-8 in the fr400 LSI 1150 (unit u-media-2 "Media-2 unit" () 1151 1 1 ; issue done 1152 () ; state 1153 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1154 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 1155 () ; profile action (default) 1156 ) 1157 (unit u-media-2-quad "Media-2-quad unit" () 1158 1 1 ; issue done 1159 () ; state 1160 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1161 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 1162 () ; profile action (default) 1163 ) 1164 (unit u-media-2-acc "Media-2-acc unit" () 1165 1 1 ; issue done 1166 () ; state 1167 ((ACC40Si INT -1)) ; inputs 1168 ((ACC40Sk INT -1)) ; outputs 1169 () ; profile action (default) 1170 ) 1171 (unit u-media-2-acc-dual "Media-2-acc-dual unit" () 1172 1 1 ; issue done 1173 () ; state 1174 ((ACC40Si INT -1)) ; inputs 1175 ((ACC40Sk INT -1)) ; outputs 1176 () ; profile action (default) 1177 ) 1178 (unit u-media-2-add-sub "Media-2-add-sub unit" () 1179 1 1 ; issue done 1180 () ; state 1181 ((ACC40Si INT -1)) ; inputs 1182 ((ACC40Sk INT -1)) ; outputs 1183 () ; profile action (default) 1184 ) 1185 (unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" () 1186 1 1 ; issue done 1187 () ; state 1188 ((ACC40Si INT -1)) ; inputs 1189 ((ACC40Sk INT -1)) ; outputs 1190 () ; profile action (default) 1191 ) 1192 ; Media unit M3 -- see table 13-8 in the fr400 LSI 1193 (unit u-media-3 "Media-3 unit" () 1194 1 1 ; issue done 1195 () ; state 1196 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1197 ((FRintk INT -1)) ; outputs 1198 () ; profile action (default) 1199 ) 1200 (unit u-media-3-dual "Media-3-dual unit" () 1201 1 1 ; issue done 1202 () ; state 1203 ((FRinti INT -1)) ; inputs 1204 ((FRintk INT -1)) ; outputs 1205 () ; profile action (default) 1206 ) 1207 (unit u-media-3-quad "Media-3-quad unit" () 1208 1 1 ; issue done 1209 () ; state 1210 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1211 ((FRintk INT -1)) ; outputs 1212 () ; profile action (default) 1213 ) 1214 ; Media unit M4 -- see table 13-8 in the fr400 LSI 1215 (unit u-media-4 "Media-4 unit" () 1216 1 1 ; issue done 1217 () ; state 1218 ((ACC40Si INT -1) (FRintj INT -1)) ; inputs 1219 ((ACC40Sk INT -1) (FRintk INT -1)) ; outputs 1220 () ; profile action (default) 1221 ) 1222 (unit u-media-4-accg "Media-4-accg unit" () 1223 1 1 ; issue done 1224 () ; state 1225 ((ACCGi INT -1) (FRinti INT -1)) ; inputs 1226 ((ACCGk INT -1) (FRintk INT -1)) ; outputs 1227 () ; profile action (default) 1228 ) 1229 (unit u-media-4-acc-dual "Media-4-acc-dual unit" () 1230 1 1 ; issue done 1231 () ; state 1232 ((ACC40Si INT -1)) ; inputs 1233 ((FRintk INT -1)) ; outputs 1234 () ; profile action (default) 1235 ) 1236 ; Media unit M6 -- see table 13-8 in the fr400 LSI 1237 (unit u-media-6 "Media-6 unit" () 1238 1 1 ; issue done 1239 () ; state 1240 ((FRinti INT -1)) ; inputs 1241 ((FRintk INT -1)) ; outputs 1242 () ; profile action (default) 1243 ) 1244 ; Media unit M7 -- see table 13-8 in the fr400 LSI 1245 (unit u-media-7 "Media-1 unit" () 1246 1 1 ; issue done 1247 () ; state 1248 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1249 ((FCCk INT -1)) ; outputs 1250 () ; profile action (default) 1251 ) 1252 ; Media Dual Expand unit 1253 (unit u-media-dual-expand "Media Dual Expand unit" () 1254 1 1 ; issue done 1255 () ; state 1256 ((FRinti INT -1)) ; inputs 1257 ((FRintk INT -1)) ; outputs 1258 () ; profile action (default) 1259 ) 1260 ; Media Dual half to byte unit 1261 (unit u-media-dual-htob "Media Half to byte" () 1262 1 1 ; issue done 1263 () ; state 1264 ((FRintj INT -1)) ; inputs 1265 ((FRintk INT -1)) ; outputs 1266 () ; profile action (default) 1267 ) 1268 ; Barrier unit 1269 (unit u-barrier "Barrier unit" () 1270 1 1 ; issue done 1271 () ; state 1272 () ; inputs 1273 () ; outputs 1274 () ; profile action (default) 1275 ) 1276 ; Memory Barrier unit 1277 (unit u-membar "Memory Barrier unit" () 1278 1 1 ; issue done 1279 () ; state 1280 () ; inputs 1281 () ; outputs 1282 () ; profile action (default) 1283 ) 1284 ; Insn cache invalidate unit 1285 (unit u-ici "Insn cache invalidate unit" () 1286 1 1 ; issue done 1287 () ; state 1288 ((GRi INT -1) (GRj INT -1)) ; inputs 1289 () ; outputs 1290 () ; profile action (default) 1291 ) 1292 ; Data cache invalidate unit 1293 (unit u-dci "Data cache invalidate unit" () 1294 1 1 ; issue done 1295 () ; state 1296 ((GRi INT -1) (GRj INT -1)) ; inputs 1297 () ; outputs 1298 () ; profile action (default) 1299 ) 1300 ; Data cache flush unit 1301 (unit u-dcf "Data cache flush unit" () 1302 1 1 ; issue done 1303 () ; state 1304 ((GRi INT -1) (GRj INT -1)) ; inputs 1305 () ; outputs 1306 () ; profile action (default) 1307 ) 1308 ; Insn cache preload unit 1309 (unit u-icpl "Insn cache preload unit" () 1310 1 1 ; issue done 1311 () ; state 1312 ((GRi INT -1) (GRj INT -1)) ; inputs 1313 () ; outputs 1314 () ; profile action (default) 1315 ) 1316 ; Data cache preload unit 1317 (unit u-dcpl "Data cache preload unit" () 1318 1 1 ; issue done 1319 () ; state 1320 ((GRi INT -1) (GRj INT -1)) ; inputs 1321 () ; outputs 1322 () ; profile action (default) 1323 ) 1324 ; Insn cache unlock unit 1325 (unit u-icul "Insn cache unlock unit" () 1326 1 1 ; issue done 1327 () ; state 1328 ((GRi INT -1) (GRj INT -1)) ; inputs 1329 () ; outputs 1330 () ; profile action (default) 1331 ) 1332 ; Data cache unlock unit 1333 (unit u-dcul "Data cache unlock unit" () 1334 1 1 ; issue done 1335 () ; state 1336 ((GRi INT -1) (GRj INT -1)) ; inputs 1337 () ; outputs 1338 () ; profile action (default) 1339 ) 1340) 1341 1342; FR450 machine 1343(define-mach 1344 (name fr450) 1345 (comment "FR450 cpu") 1346 (cpu frvbf) 1347) 1348(define-model 1349 (name fr450) (comment "FR450 model") (attrs) 1350 (mach fr450) 1351 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 1352 ; `state' is a list of variables for recording model state 1353 (state 1354 ; State items 1355 ; These are all masks with each bit representing one register. 1356 (prev-fp-load DI) ; Previous use of FR register was floating point load 1357 (prev-fr-p4 DI) ; Previous use of FR register was media unit 4 1358 (prev-fr-p6 DI) ; Previous use of FR register was media unit 6 1359 (prev-acc-p2 DI) ; Previous use of ACC register was media unit 2 1360 (prev-acc-p4 DI) ; Previous use of ACC register was media unit 4 1361 (cur-fp-load DI) ; Current use of FR register is floating point load 1362 (cur-fr-p4 DI) ; Current use of FR register is media unit 4 1363 (cur-fr-p6 DI) ; Current use of FR register is media unit 6 1364 (cur-acc-p2 DI) ; Current use of ACC register is media unit 2 1365 (cur-acc-p4 DI) ; Current use of ACC register is media unit 4 1366 ) 1367 (unit u-exec "Execution Unit" () 1368 1 1 ; issue done 1369 () ; state 1370 () ; inputs 1371 () ; outputs 1372 () ; profile action (default) 1373 ) 1374 ; Basic integer insn unit 1375 (unit u-integer "Integer Unit" () 1376 1 1 ; issue done 1377 () ; state 1378 ((GRi INT -1) (GRj INT -1)) ; inputs 1379 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 1380 () ; profile action (default) 1381 ) 1382 ; Integer multiplication unit 1383 (unit u-imul "Integer Multiplication Unit" () 1384 1 1 ; issue done 1385 () ; state 1386 ((GRi INT -1) (GRj INT -1)) ; inputs 1387 ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs 1388 () ; profile action (default) 1389 ) 1390 ; Integer division unit 1391 (unit u-idiv "Integer Division Unit" () 1392 1 1 ; issue done 1393 () ; state 1394 ((GRi INT -1) (GRj INT -1)) ; inputs 1395 ((GRk INT -1) (ICCi_1 INT -1)) ; outputs 1396 () ; profile action (default) 1397 ) 1398 ; Branch unit 1399 (unit u-branch "Branch Unit" () 1400 1 1 ; issue done 1401 () ; state 1402 ((GRi INT -1) (GRj INT -1) 1403 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 1404 ((pc)) ; outputs 1405 () ; profile action (default) 1406 ) 1407 ; Trap unit 1408 (unit u-trap "Trap Unit" () 1409 1 1 ; issue done 1410 () ; state 1411 ((GRi INT -1) (GRj INT -1) 1412 (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs 1413 () ; outputs 1414 () ; profile action (default) 1415 ) 1416 ; Condition code check unit 1417 (unit u-check "Check Unit" () 1418 1 1 ; issue done 1419 () ; state 1420 ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs 1421 () ; outputs 1422 () ; profile action (default) 1423 ) 1424 ; GR set half unit 1425 (unit u-set-hilo "GR Set Half" () 1426 1 1 ; issue done 1427 () ; state 1428 () ; inputs 1429 ((GRkhi INT -1) (GRklo INT -1)) ; outputs 1430 () ; profile action (default) 1431 ) 1432 ; GR load unit -- TODO doesn't handle quad 1433 (unit u-gr-load "GR Load Unit" () 1434 1 1 ; issue done 1435 () ; state 1436 ((GRi INT -1) (GRj INT -1)) ; inputs 1437 ((GRk INT -1) (GRdoublek INT -1)) ; outputs 1438 () ; profile action (default) 1439 ) 1440 ; GR store unit -- TODO doesn't handle quad 1441 (unit u-gr-store "GR Store Unit" () 1442 1 1 ; issue done 1443 () ; state 1444 ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs 1445 () ; outputs 1446 () ; profile action (default) 1447 ) 1448 ; FR load unit -- TODO doesn't handle quad 1449 (unit u-fr-load "FR Load Unit" () 1450 1 1 ; issue done 1451 () ; state 1452 ((GRi INT -1) (GRj INT -1)) ; inputs 1453 ((FRintk INT -1) (FRdoublek INT -1)) ; outputs 1454 () ; profile action (default) 1455 ) 1456 ; FR store unit -- TODO doesn't handle quad 1457 (unit u-fr-store "FR Store Unit" () 1458 1 1 ; issue done 1459 () ; state 1460 ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs 1461 () ; outputs 1462 () ; profile action (default) 1463 ) 1464 ; Swap unit 1465 (unit u-swap "Swap Unit" () 1466 1 1 ; issue done 1467 () ; state 1468 ((GRi INT -1) (GRj INT -1)) ; inputs 1469 ((GRk INT -1)) ; outputs 1470 () ; profile action (default) 1471 ) 1472 ; FR Move to GR unit 1473 (unit u-fr2gr "FR Move to GR Unit" () 1474 1 1 ; issue done 1475 () ; state 1476 ((FRintk INT -1)) ; inputs 1477 ((GRj INT -1)) ; outputs 1478 () ; profile action (default) 1479 ) 1480 ; SPR Move to GR unit 1481 (unit u-spr2gr "SPR Move to GR Unit" () 1482 1 1 ; issue done 1483 () ; state 1484 ((spr INT -1)) ; inputs 1485 ((GRj INT -1)) ; outputs 1486 () ; profile action (default) 1487 ) 1488 ; GR Move to FR unit 1489 (unit u-gr2fr "GR Move to FR Unit" () 1490 1 1 ; issue done 1491 () ; state 1492 ((GRj INT -1)) ; inputs 1493 ((FRintk INT -1)) ; outputs 1494 () ; profile action (default) 1495 ) 1496 ; GR Move to SPR unit 1497 (unit u-gr2spr "GR Move to SPR Unit" () 1498 1 1 ; issue done 1499 () ; state 1500 ((GRj INT -1)) ; inputs 1501 ((spr INT -1)) ; outputs 1502 () ; profile action (default) 1503 ) 1504 ; Media unit M1 -- see table 14-8 in the fr450 LSI 1505 (unit u-media-1 "Media-1 unit" () 1506 1 1 ; issue done 1507 () ; state 1508 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1509 ((FRintk INT -1)) ; outputs 1510 () ; profile action (default) 1511 ) 1512 (unit u-media-1-quad "Media-1-quad unit" () 1513 1 1 ; issue done 1514 () ; state 1515 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1516 ((FRintk INT -1)) ; outputs 1517 () ; profile action (default) 1518 ) 1519 (unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" () 1520 1 1 ; issue done 1521 () ; state 1522 () ; inputs 1523 ((FRkhi INT -1) (FRklo INT -1)) ; outputs 1524 () ; profile action (default) 1525 ) 1526 ; Media unit M2 -- see table 14-8 in the fr450 LSI 1527 (unit u-media-2 "Media-2 unit" () 1528 1 1 ; issue done 1529 () ; state 1530 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1531 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 1532 () ; profile action (default) 1533 ) 1534 (unit u-media-2-quad "Media-2-quad unit" () 1535 1 1 ; issue done 1536 () ; state 1537 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1538 ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs 1539 () ; profile action (default) 1540 ) 1541 (unit u-media-2-acc "Media-2-acc unit" () 1542 1 1 ; issue done 1543 () ; state 1544 ((ACC40Si INT -1)) ; inputs 1545 ((ACC40Sk INT -1)) ; outputs 1546 () ; profile action (default) 1547 ) 1548 (unit u-media-2-acc-dual "Media-2-acc-dual unit" () 1549 1 1 ; issue done 1550 () ; state 1551 ((ACC40Si INT -1)) ; inputs 1552 ((ACC40Sk INT -1)) ; outputs 1553 () ; profile action (default) 1554 ) 1555 (unit u-media-2-add-sub "Media-2-add-sub unit" () 1556 1 1 ; issue done 1557 () ; state 1558 ((ACC40Si INT -1)) ; inputs 1559 ((ACC40Sk INT -1)) ; outputs 1560 () ; profile action (default) 1561 ) 1562 (unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" () 1563 1 1 ; issue done 1564 () ; state 1565 ((ACC40Si INT -1)) ; inputs 1566 ((ACC40Sk INT -1)) ; outputs 1567 () ; profile action (default) 1568 ) 1569 ; Media unit M3 -- see table 14-8 in the fr450 LSI 1570 (unit u-media-3 "Media-3 unit" () 1571 1 1 ; issue done 1572 () ; state 1573 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1574 ((FRintk INT -1)) ; outputs 1575 () ; profile action (default) 1576 ) 1577 (unit u-media-3-dual "Media-3-dual unit" () 1578 1 1 ; issue done 1579 () ; state 1580 ((FRinti INT -1)) ; inputs 1581 ((FRintk INT -1)) ; outputs 1582 () ; profile action (default) 1583 ) 1584 (unit u-media-3-quad "Media-3-quad unit" () 1585 1 1 ; issue done 1586 () ; state 1587 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1588 ((FRintk INT -1)) ; outputs 1589 () ; profile action (default) 1590 ) 1591 ; Media unit M4 -- see table 14-8 in the fr450 LSI 1592 (unit u-media-4 "Media-4 unit" () 1593 1 1 ; issue done 1594 () ; state 1595 ((ACC40Si INT -1) (FRintj INT -1)) ; inputs 1596 ((ACC40Sk INT -1) (FRintk INT -1)) ; outputs 1597 () ; profile action (default) 1598 ) 1599 (unit u-media-4-accg "Media-4-accg unit" () 1600 1 1 ; issue done 1601 () ; state 1602 ((ACCGi INT -1) (FRinti INT -1)) ; inputs 1603 ((ACCGk INT -1) (FRintk INT -1)) ; outputs 1604 () ; profile action (default) 1605 ) 1606 (unit u-media-4-acc-dual "Media-4-acc-dual unit" () 1607 1 1 ; issue done 1608 () ; state 1609 ((ACC40Si INT -1)) ; inputs 1610 ((FRintk INT -1)) ; outputs 1611 () ; profile action (default) 1612 ) 1613 (unit u-media-4-mclracca "Media-4 unit for MCLRACC with #A=1" () 1614 1 1 ; issue done 1615 () ; state 1616 () ; inputs 1617 () ; outputs 1618 () ; profile action (default) 1619 ) 1620 ; Media unit M6 -- see table 14-8 in the fr450 LSI 1621 (unit u-media-6 "Media-6 unit" () 1622 1 1 ; issue done 1623 () ; state 1624 ((FRinti INT -1)) ; inputs 1625 ((FRintk INT -1)) ; outputs 1626 () ; profile action (default) 1627 ) 1628 ; Media unit M7 -- see table 14-8 in the fr450 LSI 1629 (unit u-media-7 "Media-1 unit" () 1630 1 1 ; issue done 1631 () ; state 1632 ((FRinti INT -1) (FRintj INT -1)) ; inputs 1633 ((FCCk INT -1)) ; outputs 1634 () ; profile action (default) 1635 ) 1636 ; Media Dual Expand unit 1637 (unit u-media-dual-expand "Media Dual Expand unit" () 1638 1 1 ; issue done 1639 () ; state 1640 ((FRinti INT -1)) ; inputs 1641 ((FRintk INT -1)) ; outputs 1642 () ; profile action (default) 1643 ) 1644 ; Media Dual half to byte unit 1645 (unit u-media-dual-htob "Media Half to byte" () 1646 1 1 ; issue done 1647 () ; state 1648 ((FRintj INT -1)) ; inputs 1649 ((FRintk INT -1)) ; outputs 1650 () ; profile action (default) 1651 ) 1652 ; Barrier unit 1653 (unit u-barrier "Barrier unit" () 1654 1 1 ; issue done 1655 () ; state 1656 () ; inputs 1657 () ; outputs 1658 () ; profile action (default) 1659 ) 1660 ; Memory Barrier unit 1661 (unit u-membar "Memory Barrier unit" () 1662 1 1 ; issue done 1663 () ; state 1664 () ; inputs 1665 () ; outputs 1666 () ; profile action (default) 1667 ) 1668 ; Insn cache invalidate unit 1669 (unit u-ici "Insn cache invalidate unit" () 1670 1 1 ; issue done 1671 () ; state 1672 ((GRi INT -1) (GRj INT -1)) ; inputs 1673 () ; outputs 1674 () ; profile action (default) 1675 ) 1676 ; Data cache invalidate unit 1677 (unit u-dci "Data cache invalidate unit" () 1678 1 1 ; issue done 1679 () ; state 1680 ((GRi INT -1) (GRj INT -1)) ; inputs 1681 () ; outputs 1682 () ; profile action (default) 1683 ) 1684 ; Data cache flush unit 1685 (unit u-dcf "Data cache flush unit" () 1686 1 1 ; issue done 1687 () ; state 1688 ((GRi INT -1) (GRj INT -1)) ; inputs 1689 () ; outputs 1690 () ; profile action (default) 1691 ) 1692 ; Insn cache preload unit 1693 (unit u-icpl "Insn cache preload unit" () 1694 1 1 ; issue done 1695 () ; state 1696 ((GRi INT -1) (GRj INT -1)) ; inputs 1697 () ; outputs 1698 () ; profile action (default) 1699 ) 1700 ; Data cache preload unit 1701 (unit u-dcpl "Data cache preload unit" () 1702 1 1 ; issue done 1703 () ; state 1704 ((GRi INT -1) (GRj INT -1)) ; inputs 1705 () ; outputs 1706 () ; profile action (default) 1707 ) 1708 ; Insn cache unlock unit 1709 (unit u-icul "Insn cache unlock unit" () 1710 1 1 ; issue done 1711 () ; state 1712 ((GRi INT -1) (GRj INT -1)) ; inputs 1713 () ; outputs 1714 () ; profile action (default) 1715 ) 1716 ; Data cache unlock unit 1717 (unit u-dcul "Data cache unlock unit" () 1718 1 1 ; issue done 1719 () ; state 1720 ((GRi INT -1) (GRj INT -1)) ; inputs 1721 () ; outputs 1722 () ; profile action (default) 1723 ) 1724) 1725 1726; Simple machine - single issue integer machine 1727(define-mach 1728 (name simple) 1729 (comment "Simple single issue integer cpu") 1730 (cpu frvbf) 1731) 1732(define-model 1733 (name simple) (comment "Simple model") (attrs) 1734 (mach simple) 1735 (pipeline all "" () ((fetch) (decode) (execute) (writeback))) 1736 ; `state' is a list of variables for recording model state 1737 (state) 1738 (unit u-exec "Execution Unit" () 1739 1 1 ; issue done 1740 () ; state 1741 () ; inputs 1742 () ; outputs 1743 () ; profile action (default) 1744 ) 1745) 1746 1747; The instruction fetch/execute cycle. 1748; 1749; This is how to fetch and decode an instruction. 1750; Leave it out for now 1751 1752; (define-extract (const SI 0)) 1753 1754; This is how to execute a decoded instruction. 1755; Leave it out for now 1756 1757; (define-execute (const SI 0)) 1758 1759; An attribute to describe which unit an insn runs in. 1760(define-attr 1761 (for insn) 1762 (type enum) 1763 (name UNIT) 1764 (comment "parallel execution pipeline selection") 1765 ; The order of declaration is significant. 1766 ; See the *_unit_mapping tables in frv.opc 1767 ; Keep variations on the same unit together. 1768 ; Keep the '01' variant immediately after the '1' variant in each unit. 1769 ; Keep the 'ALL' variations immediately after the last numbered variant in each unit. 1770 (values NIL 1771 I0 I1 I01 I2 I3 IALL 1772 FM0 FM1 FM01 FM2 FM3 FMALL FMLOW 1773 B0 B1 B01 1774 C 1775 MULT-DIV ; multiply/division slotted differently on different machines 1776 IACC ; iacc multiply slotted differently on different machines 1777 LOAD ; loads slotted differently on different machines 1778 STORE ; store slotted differently on different machines 1779 SCAN ; scan, scani slotted differently on different machines 1780 DCPL ; dcpl slotted differently on different machines 1781 MDUALACC ; media dual acc slotted differently on different machines 1782 MDCUTSSI ; mdcutssi insn slotted differently on different machines 1783 MCLRACC-1; mclracc A==1 slotted differently on different machines 1784 NUM_UNITS 1785 ) 1786) 1787; Attributes to describe major categories of insns 1788(define-attr 1789 (for insn) 1790 (type enum) 1791 (name FR400-MAJOR) 1792 (comment "fr400 major insn categories") 1793 ; The order of declaration is significant. Keep variations on the same major 1794 ; together. 1795 (values NONE 1796 I-1 I-2 I-3 I-4 I-5 1797 B-1 B-2 B-3 B-4 B-5 B-6 1798 C-1 C-2 1799 M-1 M-2 1800 ) 1801) 1802(define-attr 1803 (for insn) 1804 (type enum) 1805 (name FR450-MAJOR) 1806 (comment "fr450 major insn categories") 1807 ; The order of declaration is significant. Keep variations on the same major 1808 ; together. 1809 (values NONE 1810 I-1 I-2 I-3 I-4 I-5 1811 B-1 B-2 B-3 B-4 B-5 B-6 1812 C-1 C-2 1813 M-1 M-2 M-3 M-4 M-5 M-6 1814 ) 1815) 1816(define-attr 1817 (for insn) 1818 (type enum) 1819 (name FR500-MAJOR) 1820 (comment "fr500 major insn categories") 1821 ; The order of declaration is significant. Keep variations on the same major 1822 ; together. 1823 (values NONE 1824 I-1 I-2 I-3 I-4 I-5 I-6 1825 B-1 B-2 B-3 B-4 B-5 B-6 1826 C-1 C-2 1827 F-1 F-2 F-3 F-4 F-5 F-6 F-7 F-8 1828 M-1 M-2 M-3 M-4 M-5 M-6 M-7 M-8 1829 ) 1830) 1831(define-attr 1832 (for insn) 1833 (type enum) 1834 (name FR550-MAJOR) 1835 (comment "fr550 major insn categories") 1836 ; The order of declaration is significant. Keep variations on the same major 1837 ; together. 1838 (values NONE 1839 I-1 I-2 I-3 I-4 I-5 I-6 I-7 I-8 1840 B-1 B-2 B-3 B-4 B-5 B-6 1841 C-1 C-2 1842 F-1 F-2 F-3 F-4 1843 M-1 M-2 M-3 M-4 M-5 1844 ) 1845) 1846; Privileged insn 1847(define-attr 1848 (for insn) 1849 (type boolean) 1850 (name PRIVILEGED) 1851 (comment "insn only allowed in supervisor mode") 1852) 1853; Non-Excepting insn 1854(define-attr 1855 (for insn) 1856 (type boolean) 1857 (name NON-EXCEPTING) 1858 (comment "non-excepting insn") 1859) 1860; Conditional insn 1861(define-attr 1862 (for insn) 1863 (type boolean) 1864 (name CONDITIONAL) 1865 (comment "conditional insn") 1866) 1867; insn accesses FR registers 1868(define-attr 1869 (for insn) 1870 (type boolean) 1871 (name FR-ACCESS) 1872 (comment "insn accesses FR registers") 1873) 1874; insn preserves MSR.OVF 1875(define-attr 1876 (for insn) 1877 (type boolean) 1878 (name PRESERVE-OVF) 1879 (comment "Preserve value of MSR.OVF") 1880) 1881; "Audio" instruction provided by the fr405 but not the original fr400 core. 1882(define-attr 1883 (for insn) 1884 (type boolean) 1885 (name AUDIO) 1886 (comment "Audio instruction added with FR405") 1887) 1888; null attribute -- used as a place holder for where an attribue is required. 1889(define-attr 1890 (for insn) 1891 (type boolean) 1892 (name NA) 1893 (comment "placeholder attribute") 1894 (attrs META) ; do not define in any generated file for now 1895) 1896 1897; IDOC attribute for instruction documentation. 1898 1899(define-attr 1900 (for insn) 1901 (type enum) 1902 (name IDOC) 1903 (comment "insn kind for documentation") 1904 (attrs META) 1905 (values 1906 (MEM - () "Memory") 1907 (ALU - () "ALU") 1908 (FPU - () "FPU") 1909 (BR - () "Branch") 1910 (PRIV - () "Priviledged") 1911 (MISC - () "Miscellaneous") 1912 ) 1913) 1914 1915; Instruction fields. 1916; 1917; Attributes: 1918; PCREL-ADDR: pc relative value (for reloc and disassembly purposes) 1919; ABS-ADDR: absolute address (for reloc and disassembly purposes?) 1920; RESERVED: bits are not used to decode insn, must be all 0 1921(dnf f-pack "packing bit" () 31 1) 1922(dnf f-op "primary opcode" () 24 7) 1923(dnf f-ope1 "extended opcode" () 11 6) 1924(dnf f-ope2 "extended opcode" () 9 4) 1925(dnf f-ope3 "extended opcode" () 15 3) 1926(dnf f-ope4 "extended opcode" () 7 2) 1927 1928(dnf f-GRi "source register 1" () 17 6) 1929(dnf f-GRj "source register 2" () 5 6) 1930(dnf f-GRk "destination register" () 30 6) 1931 1932(dnf f-FRi "source register 1" () 17 6) 1933(dnf f-FRj "source register 2" () 5 6) 1934(dnf f-FRk "destination register" () 30 6) 1935 1936(dnf f-CPRi "source register 1" () 17 6) 1937(dnf f-CPRj "source register 2" () 5 6) 1938(dnf f-CPRk "destination register" () 30 6) 1939 1940(dnf f-ACCGi "source register" () 17 6) 1941(dnf f-ACCGk "destination register" () 30 6) 1942 1943(dnf f-ACC40Si "40 bit signed accumulator" () 17 6) 1944(dnf f-ACC40Ui "40 bit unsigned accumulator" () 17 6) 1945(dnf f-ACC40Sk "40 bit accumulator" () 30 6) 1946(dnf f-ACC40Uk "40 bit accumulator" () 30 6) 1947 1948(dnf f-CRi "source register" () 14 3) 1949(dnf f-CRj "source register" () 2 3) 1950(dnf f-CRk "destination register" () 27 3) 1951(dnf f-CCi "condition register" () 11 3) 1952 1953(df f-CRj_int "target cr for ck insns" () 26 2 UINT 1954 ((value pc) (sub WI value 4)) 1955 ((value pc) (add WI value 4)) 1956) 1957(dnf f-CRj_float "target cr for fck insns" () 26 2) 1958 1959(dnf f-ICCi_1 "condition register" () 11 2) 1960(dnf f-ICCi_2 "condition register" () 26 2) 1961(dnf f-ICCi_3 "condition register" () 1 2) 1962(dnf f-FCCi_1 "condition register" () 11 2) 1963(dnf f-FCCi_2 "condition register" () 26 2) 1964(dnf f-FCCi_3 "condition register" () 1 2) 1965(dnf f-FCCk "condition register" () 26 2) 1966(dnf f-eir "exception insn register" () 17 6) 1967 1968(df f-s10 "10 bit sign extended" () 9 10 INT #f #f) 1969(df f-s12 "12 bit sign extended" () 11 12 INT #f #f) 1970(df f-d12 "12 bit sign extended" () 11 12 INT #f #f) 1971(df f-u16 "16 bit unsigned" () 15 16 UINT #f #f) 1972(df f-s16 "16 bit sign extended" () 15 16 INT #f #f) 1973(df f-s6 "6 bit signed" () 5 6 INT #f #f) 1974(df f-s6_1 "6 bit signed" () 11 6 INT #f #f) 1975(df f-u6 "6 bit unsigned" () 5 6 UINT #f #f) 1976(df f-s5 "5 bit signed" () 4 5 INT #f #f) 1977 1978(df f-u12-h "upper 6 bits of u12" () 17 6 INT #f #f) 1979(df f-u12-l "lower 6 bits of u12" () 5 6 UINT #f #f) 1980(dnmf f-u12 "12 bit signed immediate" () INT 1981 (f-u12-h f-u12-l) 1982 (sequence () ; insert 1983 (set (ifield f-u12-h) (sra SI (ifield f-u12) 6)) 1984 (set (ifield f-u12-l) (and (ifield f-u12) #x3f)) 1985 ) 1986 (sequence () ; extract 1987 (set (ifield f-u12) (or (sll (ifield f-u12-h) 6) 1988 (ifield f-u12-l))) 1989 ) 1990) 1991 1992(dnf f-int-cc "integer branch conditions" () 30 4) 1993(dnf f-flt-cc "floating branch conditions" () 30 4) 1994(df f-cond "conditional arithmetic" () 8 1 UINT #f #f) 1995(df f-ccond "lr branch condition" () 12 1 UINT #f #f) 1996(df f-hint "2 bit branch prediction hint" () 17 2 UINT #f #f) 1997(df f-LI "link indicator" () 25 1 UINT #f #f) 1998(df f-lock "cache lock indicator" () 25 1 UINT #f #f) 1999(df f-debug "debug mode indicator" () 25 1 UINT #f #f) 2000(df f-A "all accumulator bit" () 17 1 UINT #f #f) 2001(df f-ae "cache all entries indicator" () 25 1 UINT #f #f) 2002 2003(dnf f-spr-h "upper 6 bits of spr" () 30 6) 2004(dnf f-spr-l "lower 6 bits of spr" () 17 6) 2005(dnmf f-spr "special purpose register" () UINT 2006 (f-spr-h f-spr-l) 2007 (sequence () ; insert 2008 (set (ifield f-spr-h) (srl (ifield f-spr) (const 6))) 2009 (set (ifield f-spr-l) (and (ifield f-spr) (const #x3f))) 2010 ) 2011 (sequence () ; extract 2012 (set (ifield f-spr) (or (sll (ifield f-spr-h) (const 6)) 2013 (ifield f-spr-l))) 2014 ) 2015) 2016 2017(df f-label16 "18 bit pc relative signed offset" (PCREL-ADDR) 15 16 INT 2018 ((value pc) (sra WI (sub WI value pc) (const 2))) 2019 ((value pc) (add WI (sll WI value (const 2)) pc)) 2020) 2021 2022(df f-labelH6 "upper 6 bits of label24" () 30 6 INT #f #f) 2023(dnf f-labelL18 "lower 18 bits of label24" () 17 18) 2024(dnmf f-label24 "26 bit signed offset" (PCREL-ADDR) INT 2025 (f-labelH6 f-labelL18) 2026 ; insert 2027 (sequence () 2028 (set (ifield f-labelH6) 2029 (sra WI (sub (ifield f-label24) pc) (const 20))) 2030 (set (ifield f-labelL18) 2031 (and (srl (sub (ifield f-label24) pc) (const 2)) 2032 (const #x3ffff))) 2033 ) 2034 ; extract 2035 (sequence () 2036 (set (ifield f-label24) 2037 (add (sll (or (sll (ifield f-labelH6) (const 18)) 2038 (ifield f-labelL18)) 2039 (const 2)) 2040 pc))) 2041) 2042 2043(dnf f-LRAE "Load Real Address E flag" () 5 1) 2044(dnf f-LRAD "Load Real Address D flag" () 4 1) 2045(dnf f-LRAS "Load Real Address S flag" () 3 1) 2046 2047(dnf f-TLBPRopx "TLB Probe operation number" () 28 3) 2048(dnf f-TLBPRL "TLB Probe L flag" () 25 1) 2049 2050(dnf f-ICCi_1-null "null field" (RESERVED) 11 2) 2051(dnf f-ICCi_2-null "null field" (RESERVED) 26 2) 2052(dnf f-ICCi_3-null "null field" (RESERVED) 1 2) 2053(dnf f-FCCi_1-null "null field" (RESERVED) 11 2) 2054(dnf f-FCCi_2-null "null field" (RESERVED) 26 2) 2055(dnf f-FCCi_3-null "null field" (RESERVED) 1 2) 2056(dnf f-rs-null "null field" (RESERVED) 17 6) 2057(dnf f-GRi-null "null field" (RESERVED) 17 6) 2058(dnf f-GRj-null "null field" (RESERVED) 5 6) 2059(dnf f-GRk-null "null field" (RESERVED) 30 6) 2060(dnf f-FRi-null "null field" (RESERVED) 17 6) 2061(dnf f-FRj-null "null field" (RESERVED) 5 6) 2062(dnf f-ACCj-null "null field" (RESERVED) 5 6) 2063(dnf f-rd-null "null field" (RESERVED) 30 6) 2064(dnf f-cond-null "null field" (RESERVED) 30 4) 2065(dnf f-ccond-null "null field" (RESERVED) 12 1) 2066(dnf f-s12-null "null field" (RESERVED) 11 12) 2067(dnf f-label16-null "null field" (RESERVED) 15 16) 2068(dnf f-misc-null-1 "null field" (RESERVED) 30 5) 2069(dnf f-misc-null-2 "null field" (RESERVED) 11 6) 2070(dnf f-misc-null-3 "null field" (RESERVED) 11 4) 2071(dnf f-misc-null-4 "null field" (RESERVED) 17 2) 2072(dnf f-misc-null-5 "null field" (RESERVED) 17 16) 2073(dnf f-misc-null-6 "null field" (RESERVED) 30 3) 2074(dnf f-misc-null-7 "null field" (RESERVED) 17 3) 2075(dnf f-misc-null-8 "null field" (RESERVED) 5 3) 2076(dnf f-misc-null-9 "null field" (RESERVED) 5 4) 2077(dnf f-misc-null-10 "null field" (RESERVED) 16 5) 2078(dnf f-misc-null-11 "null field" (RESERVED) 5 1) 2079 2080(dnf f-LRA-null "null field" (RESERVED) 2 3) 2081(dnf f-TLBPR-null "null field" (RESERVED) 30 2) 2082 2083(dnf f-LI-off "null field" (RESERVED) 25 1) 2084(dnf f-LI-on "null field" (RESERVED) 25 1) 2085 2086; Relocation annotations. 2087(dsh h-reloc-ann "relocation annotation" () (register BI)) 2088(dnf f-reloc-ann "relocation annotation" () 0 0) 2089 2090(define-pmacro (dann xname xcomment xmode xparse xprint) 2091 (define-operand 2092 (name xname) 2093 (comment xcomment) 2094 (type h-reloc-ann) 2095 (index f-reloc-ann) 2096 (mode xmode) 2097 (handlers (parse xparse) (print xprint)) 2098 ) 2099 ) 2100 2101 2102; Enums. 2103 2104; insn-op: 2105; FIXME: should use die macro or some such 2106(define-normal-insn-enum insn-op "insn op enums" () OP_ f-op 2107 ( 2108 "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" 2109 "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F" 2110 "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F" 2111 "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F" 2112 "40" "41" "42" "43" "44" "45" "46" "47" "48" "49" "4A" "4B" "4C" "4D" "4E" "4F" 2113 "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "5A" "5B" "5C" "5D" "5E" "5F" 2114 "60" "61" "62" "63" "64" "65" "66" "67" "68" "69" "6A" "6B" "6C" "6D" "6E" "6F" 2115 "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" "7A" "7B" "7C" "7D" "7E" "7F" 2116 ) 2117) 2118 2119(define-normal-insn-enum insn-ope1 "insn ope enums" () OPE1_ f-ope1 2120 ( 2121 "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" 2122 "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F" 2123 "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F" 2124 "30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F" 2125 ) 2126) 2127 2128(define-normal-insn-enum insn-ope2 "insn ope enums" () OPE2_ f-ope2 2129 ( 2130 "00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F" 2131 ) 2132) 2133 2134(define-normal-insn-enum insn-ope3 "insn ope enums" () OPE3_ f-ope3 2135 ( 2136 "00" "01" "02" "03" "04" "05" "06" "07" 2137 ) 2138) 2139 2140(define-normal-insn-enum insn-ope4 "insn ope enums" () OPE4_ f-ope4 2141 ( 2142 "0" "1" "2" "3" 2143 ) 2144) 2145 2146; int-cc: integer branch conditions 2147; FIXME: should use die macro or some such 2148(define-normal-insn-enum int-cc "integer branch cond enums" () ICC_ f-int-cc 2149 ( 2150 "nev" "c" "v" "lt" "eq" "ls" "n" "le" 2151 "ra" "nc" "nv" "ge" "ne" "hi" "p" "gt" 2152 ) 2153) 2154 2155; flt-cc: floating-point/media branch conditions 2156; FIXME: should use die macro or some such 2157(define-normal-insn-enum flt-cc "float branch cond enums" () FCC_ f-flt-cc 2158 ("nev" "u" "gt" "ug" "lt" "ul" "lg" "ne" 2159 "eq" "ue" "ge" "uge" "le" "ule" "o" "ra") 2160) 2161 2162; Hardware pieces. 2163; These entries list the elements of the raw hardware. 2164; They're also used to provide tables and other elements of the assembly 2165; language. 2166(dnh h-pc "program counter" (PC PROFILE) (pc) () () ()) 2167 2168; The PSR. The individual fields are referenced more than the entire 2169; register, so reference them directly. We can assemble the 2170; entire register contents when necessary. 2171; 2172(dsh h-psr_imple "PSR.IMPLE" () (register UQI)) 2173(dsh h-psr_ver "PSR.VER" () (register UQI)) 2174(dsh h-psr_ice "PSR.ICE bit" () (register BI)) 2175(dsh h-psr_nem "PSR.NEM bit" () (register BI)) 2176(dsh h-psr_cm "PSR.CM bit" () (register BI)) 2177(dsh h-psr_be "PSR.BE bit" () (register BI)) 2178(dsh h-psr_esr "PSR.ESR bit" () (register BI)) 2179(dsh h-psr_ef "PSR.EF bit" () (register BI)) 2180(dsh h-psr_em "PSR.EM bit" () (register BI)) 2181(dsh h-psr_pil "PSR.PIL " () (register UQI)) 2182(dsh h-psr_ps "PSR.PS bit" () (register BI)) 2183(dsh h-psr_et "PSR.ET bit" () (register BI)) 2184 2185; PSR.S requires special handling because the shadow registers (SR0-SR4) must 2186; be switched with GR4-GR7 when changing from user to supervisor mode or 2187; vice-versa. 2188(define-hardware 2189 (name h-psr_s) 2190 (comment "PSR.S bit") 2191 (attrs) 2192 (type register BI) 2193 (get) 2194 (set (newval) (c-call VOID "@cpu@_h_psr_s_set_handler" newval)) 2195) 2196 2197; The TBR. The individual bits are referenced more than the entire 2198; register, so reference them directly. We can assemble the 2199; entire register contents when necessary. 2200; 2201(dsh h-tbr_tba "TBR.TBA" () (register UWI)) 2202(dsh h-tbr_tt "TBR.TT" () (register UQI)) 2203 2204; The BPSR. The individual bits are referenced more than the entire 2205; register, so reference them directly. We can assemble the 2206; entire register contents when necessary. 2207; 2208(dsh h-bpsr_bs "PSR.S bit" () (register BI)) 2209(dsh h-bpsr_bet "PSR.ET bit" () (register BI)) 2210 2211; General registers 2212; 2213(define-keyword 2214 (name gr-names) 2215 (print-name h-gr) 2216 (prefix "") 2217 (values 2218 (sp 1) (fp 2) 2219 (gr0 0)(gr1 1)(gr2 2)(gr3 3)(gr4 4)(gr5 5)(gr6 6)(gr7 7) 2220 (gr8 8)(gr9 9)(gr10 10)(gr11 11)(gr12 12)(gr13 13)(gr14 14)(gr15 15) 2221 (gr16 16)(gr17 17)(gr18 18)(gr19 19)(gr20 20)(gr21 21)(gr22 22)(gr23 23) 2222 (gr24 24)(gr25 25)(gr26 26)(gr27 27)(gr28 28)(gr29 29)(gr30 30)(gr31 31) 2223 (gr32 32)(gr33 33)(gr34 34)(gr35 35)(gr36 36)(gr37 37)(gr38 38)(gr39 39) 2224 (gr40 40)(gr41 41)(gr42 42)(gr43 43)(gr44 44)(gr45 45)(gr46 46)(gr47 47) 2225 (gr48 48)(gr49 49)(gr50 50)(gr51 51)(gr52 52)(gr53 53)(gr54 54)(gr55 55) 2226 (gr56 56)(gr57 57)(gr58 58)(gr59 59)(gr60 60)(gr61 61)(gr62 62)(gr63 63) 2227 ) 2228) 2229 2230(define-hardware 2231 (name h-gr) 2232 (comment "general registers") 2233 (attrs PROFILE) 2234 (type register USI (64)) 2235 (indices extern-keyword gr-names) 2236 (get (index) (c-call WI "@cpu@_h_gr_get_handler" index)) 2237 (set (index newval) (c-call VOID "@cpu@_h_gr_set_handler" index newval)) 2238) 2239 2240; General Registers as double words 2241; These registers are shadowed onto h-gr 2242(define-hardware 2243 (name h-gr_double) 2244 (comment "general registers as double words") 2245 (attrs PROFILE VIRTUAL) 2246 (type register DI (32)) 2247 ; FIXME: Need constraint to prohibit odd numbers. 2248 (indices extern-keyword gr-names) 2249 (get (index) 2250 (c-call DI "@cpu@_h_gr_double_get_handler" index)) 2251 (set (index newval) 2252 (c-call VOID "@cpu@_h_gr_double_set_handler" index newval)) 2253) 2254 2255; General Registers as high and low half words 2256; These registers are shadowed onto h-gr 2257(define-hardware 2258 (name h-gr_hi) 2259 (comment "general registers as high half word") 2260 (attrs PROFILE VIRTUAL) 2261 (type register UHI (64)) 2262 (indices extern-keyword gr-names) 2263 (get (index) (c-call UHI "@cpu@_h_gr_hi_get_handler" index)) 2264 (set (index newval) (c-call VOID "@cpu@_h_gr_hi_set_handler" index newval)) 2265) 2266(define-hardware 2267 (name h-gr_lo) 2268 (comment "general registers as low half word") 2269 (attrs PROFILE VIRTUAL) 2270 (type register UHI (64)) 2271 (indices extern-keyword gr-names) 2272 (get (index) (c-call UHI "@cpu@_h_gr_lo_get_handler" index)) 2273 (set (index newval) (c-call VOID "@cpu@_h_gr_lo_set_handler" index newval)) 2274) 2275 2276; Floating Point Registers 2277(define-keyword 2278 (name fr-names) 2279 (print-name h-fr) 2280 (prefix "") 2281 (values 2282 (fr0 0)(fr1 1)(fr2 2)(fr3 3)(fr4 4)(fr5 5)(fr6 6)(fr7 7) 2283 (fr8 8)(fr9 9)(fr10 10)(fr11 11)(fr12 12)(fr13 13)(fr14 14)(fr15 15) 2284 (fr16 16)(fr17 17)(fr18 18)(fr19 19)(fr20 20)(fr21 21)(fr22 22)(fr23 23) 2285 (fr24 24)(fr25 25)(fr26 26)(fr27 27)(fr28 28)(fr29 29)(fr30 30)(fr31 31) 2286 (fr32 32)(fr33 33)(fr34 34)(fr35 35)(fr36 36)(fr37 37)(fr38 38)(fr39 39) 2287 (fr40 40)(fr41 41)(fr42 42)(fr43 43)(fr44 44)(fr45 45)(fr46 46)(fr47 47) 2288 (fr48 48)(fr49 49)(fr50 50)(fr51 51)(fr52 52)(fr53 53)(fr54 54)(fr55 55) 2289 (fr56 56)(fr57 57)(fr58 58)(fr59 59)(fr60 60)(fr61 61)(fr62 62)(fr63 63) 2290 ) 2291) 2292 2293(define-hardware 2294 (name h-fr) 2295 (comment "floating point registers") 2296 (attrs PROFILE) 2297 (type register SF (64)) 2298 (indices extern-keyword fr-names) 2299 (get (index) (c-call SF "@cpu@_h_fr_get_handler" index)) 2300 (set (index newval) (c-call VOID "@cpu@_h_fr_set_handler" index newval)) 2301) 2302 2303; Floating Point Registers as double precision 2304; These registers are shadowed onto h-fr 2305 2306(define-hardware 2307 (name h-fr_double) 2308 (comment "floating point registers as double precision") 2309 (attrs PROFILE VIRTUAL) 2310 (type register DF (32)) 2311 ; FIXME: Need constraint to prohibit odd numbers. 2312 (indices extern-keyword fr-names) 2313 (get (index) 2314 (c-call DF "@cpu@_h_fr_double_get_handler" index)) 2315 (set (index newval) 2316 (c-call VOID "@cpu@_h_fr_double_set_handler" index newval)) 2317) 2318 2319; Floating Point Registers as integer words. 2320; These registers are shadowed onto h-fr 2321 2322(define-hardware 2323 (name h-fr_int) 2324 (comment "floating point registers as integers") 2325 (attrs PROFILE VIRTUAL) 2326 (type register USI (64)) 2327 (indices extern-keyword fr-names) 2328 (get (index) 2329 (c-call USI "@cpu@_h_fr_int_get_handler" index)) 2330 (set (index newval) 2331 (c-call VOID "@cpu@_h_fr_int_set_handler" index newval)) 2332) 2333 2334; Floating Point Registers as high and low half words 2335; These registers are shadowed onto h-fr 2336(define-hardware 2337 (name h-fr_hi) 2338 (comment "floating point registers as unsigned high half word") 2339 (attrs PROFILE VIRTUAL) 2340 (type register UHI (64)) 2341 (indices extern-keyword fr-names) 2342 (get (regno) (srl (reg h-fr_int regno) 16)) 2343 (set (regno newval) (set (reg h-fr_int regno) 2344 (or (and (reg h-fr_int regno) #xffff) 2345 (sll newval 16)))) 2346) 2347(define-hardware 2348 (name h-fr_lo) 2349 (comment "floating point registers as unsigned low half word") 2350 (attrs PROFILE VIRTUAL) 2351 (type register UHI (64)) 2352 (indices extern-keyword fr-names) 2353 (get (regno) (and (reg h-fr_int regno) #xffff)) 2354 (set (regno newval) (set (reg h-fr_int regno) 2355 (or (and (reg h-fr_int regno) #xffff0000) 2356 (and newval #xffff)))) 2357) 2358 2359; Floating Point Registers as unsigned bytes 2360; These registers are shadowed onto h-fr 2361(define-hardware 2362 (name h-fr_0) 2363 (comment "floating point registers as unsigned byte 0") 2364 (attrs PROFILE VIRTUAL) 2365 (type register UHI (64)) 2366 (indices extern-keyword fr-names) 2367 (get (regno) (and (reg h-fr_int regno) #xff)) 2368 (set (regno newval) 2369 (sequence () 2370 (if (gt USI newval #xff) 2371 (set newval #xff)) 2372 (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffffff00) 2373 newval)))) 2374) 2375(define-hardware 2376 (name h-fr_1) 2377 (comment "floating point registers as unsigned byte 1") 2378 (attrs PROFILE VIRTUAL) 2379 (type register UHI (64)) 2380 (indices extern-keyword fr-names) 2381 (get (regno) (and (srl (reg h-fr_int regno) 8) #xff)) 2382 (set (regno newval) 2383 (sequence () 2384 (if (gt USI newval #xff) 2385 (set newval #xff)) 2386 (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffff00ff) 2387 (sll newval 8))))) 2388) 2389(define-hardware 2390 (name h-fr_2) 2391 (comment "floating point registers as unsigned byte 2") 2392 (attrs PROFILE VIRTUAL) 2393 (type register UHI (64)) 2394 (indices extern-keyword fr-names) 2395 (get (regno) (and (srl (reg h-fr_int regno) 16) #xff)) 2396 (set (regno newval) 2397 (sequence () 2398 (if (gt USI newval #xff) 2399 (set newval #xff)) 2400 (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xff00ffff) 2401 (sll newval 16))))) 2402) 2403(define-hardware 2404 (name h-fr_3) 2405 (comment "floating point registers as unsigned byte 3") 2406 (attrs PROFILE VIRTUAL) 2407 (type register UHI (64)) 2408 (indices extern-keyword fr-names) 2409 (get (regno) (and (srl (reg h-fr_int regno) 24) #xff)) 2410 (set (regno newval) 2411 (sequence () 2412 (if (gt USI newval #xff) 2413 (set newval #xff)) 2414 (set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #x00ffffff) 2415 (sll newval 24))))) 2416) 2417; Coprocessor Registers 2418; 2419(define-keyword 2420 (name cpr-names) 2421 (print-name h-cpr) 2422 (prefix "") 2423 (values 2424(cpr0 0)(cpr1 1)(cpr2 2)(cpr3 3)(cpr4 4)(cpr5 5)(cpr6 6)(cpr7 7) 2425(cpr8 8)(cpr9 9)(cpr10 10)(cpr11 11)(cpr12 12)(cpr13 13)(cpr14 14)(cpr15 15) 2426(cpr16 16)(cpr17 17)(cpr18 18)(cpr19 19)(cpr20 20)(cpr21 21)(cpr22 22)(cpr23 23) 2427(cpr24 24)(cpr25 25)(cpr26 26)(cpr27 27)(cpr28 28)(cpr29 29)(cpr30 30)(cpr31 31) 2428(cpr32 32)(cpr33 33)(cpr34 34)(cpr35 35)(cpr36 36)(cpr37 37)(cpr38 38)(cpr39 39) 2429(cpr40 40)(cpr41 41)(cpr42 42)(cpr43 43)(cpr44 44)(cpr45 45)(cpr46 46)(cpr47 47) 2430(cpr48 48)(cpr49 49)(cpr50 50)(cpr51 51)(cpr52 52)(cpr53 53)(cpr54 54)(cpr55 55) 2431(cpr56 56)(cpr57 57)(cpr58 58)(cpr59 59)(cpr60 60)(cpr61 61)(cpr62 62)(cpr63 63) 2432 ) 2433) 2434 2435(define-hardware 2436 (name h-cpr) 2437 (comment "coprocessor registers") 2438 (attrs PROFILE (MACH frv)) 2439 (type register WI (64)) 2440 (indices extern-keyword cpr-names) 2441) 2442 2443; Coprocessor Registers as double words 2444; These registers are shadowed onto h-cpr 2445(define-hardware 2446 (name h-cpr_double) 2447 (comment "coprocessor registers as double words") 2448 (attrs PROFILE VIRTUAL (MACH frv)) 2449 (type register DI (32)) 2450 ; FIXME: Need constraint to prohibit odd numbers. 2451 (indices extern-keyword cpr-names) 2452 (get (index) 2453 (c-call DI "@cpu@_h_cpr_double_get_handler" index)) 2454 (set (index newval) 2455 (c-call VOID "@cpu@_h_cpr_double_set_handler" index newval)) 2456) 2457 2458; Special Purpose Registers 2459; 2460(define-keyword 2461 (name spr-names) 2462 (print-name h-spr) 2463 (prefix "") 2464 (values 2465 (psr 0) (pcsr 1) (bpcsr 2) (tbr 3) (bpsr 4) 2466 2467 (hsr0 16) (hsr1 17) (hsr2 18) (hsr3 19) 2468 (hsr4 20) (hsr5 21) (hsr6 22) (hsr7 23) 2469 (hsr8 24) (hsr9 25) (hsr10 26) (hsr11 27) 2470 (hsr12 28) (hsr13 29) (hsr14 30) (hsr15 31) 2471 (hsr16 32) (hsr17 33) (hsr18 34) (hsr19 35) 2472 (hsr20 36) (hsr21 37) (hsr22 38) (hsr23 39) 2473 (hsr24 40) (hsr25 41) (hsr26 42) (hsr27 43) 2474 (hsr28 44) (hsr29 45) (hsr30 46) (hsr31 47) 2475 (hsr32 48) (hsr33 49) (hsr34 50) (hsr35 51) 2476 (hsr36 52) (hsr37 53) (hsr38 54) (hsr39 55) 2477 (hsr40 56) (hsr41 57) (hsr42 58) (hsr43 59) 2478 (hsr44 60) (hsr45 61) (hsr46 62) (hsr47 63) 2479 (hsr48 64) (hsr49 65) (hsr50 66) (hsr51 67) 2480 (hsr52 68) (hsr53 69) (hsr54 70) (hsr55 71) 2481 (hsr56 72) (hsr57 73) (hsr58 74) (hsr59 75) 2482 (hsr60 76) (hsr61 77) (hsr62 78) (hsr63 79) 2483 2484 (ccr 256) (cccr 263) (lr 272) (lcr 273) (iacc0h 280) (iacc0l 281) (isr 288) 2485 2486 (neear0 352) (neear1 353) (neear2 354) (neear3 355) 2487 (neear4 356) (neear5 357) (neear6 358) (neear7 359) 2488 (neear8 360) (neear9 361) (neear10 362) (neear11 363) 2489 (neear12 364) (neear13 365) (neear14 366) (neear15 367) 2490 (neear16 368) (neear17 369) (neear18 370) (neear19 371) 2491 (neear20 372) (neear21 373) (neear22 374) (neear23 375) 2492 (neear24 376) (neear25 377) (neear26 378) (neear27 379) 2493 (neear28 380) (neear29 381) (neear30 382) (neear31 383) 2494 2495 (nesr0 384) (nesr1 385) (nesr2 386) (nesr3 387) 2496 (nesr4 388) (nesr5 389) (nesr6 390) (nesr7 391) 2497 (nesr8 392) (nesr9 393) (nesr10 394) (nesr11 395) 2498 (nesr12 396) (nesr13 397) (nesr14 398) (nesr15 399) 2499 (nesr16 400) (nesr17 401) (nesr18 402) (nesr19 403) 2500 (nesr20 404) (nesr21 405) (nesr22 406) (nesr23 407) 2501 (nesr24 408) (nesr25 409) (nesr26 410) (nesr27 411) 2502 (nesr28 412) (nesr29 413) (nesr30 414) (nesr31 415) 2503 2504 (necr 416) 2505 2506 (gner0 432) (gner1 433) 2507 2508 (fner0 434) (fner1 435) 2509 2510 (epcr0 512) (epcr1 513) (epcr2 514) (epcr3 515) 2511 (epcr4 516) (epcr5 517) (epcr6 518) (epcr7 519) 2512 (epcr8 520) (epcr9 521) (epcr10 522) (epcr11 523) 2513 (epcr12 524) (epcr13 525) (epcr14 526) (epcr15 527) 2514 (epcr16 528) (epcr17 529) (epcr18 530) (epcr19 531) 2515 (epcr20 532) (epcr21 533) (epcr22 534) (epcr23 535) 2516 (epcr24 536) (epcr25 537) (epcr26 538) (epcr27 539) 2517 (epcr28 540) (epcr29 541) (epcr30 542) (epcr31 543) 2518 (epcr32 544) (epcr33 545) (epcr34 546) (epcr35 547) 2519 (epcr36 548) (epcr37 549) (epcr38 550) (epcr39 551) 2520 (epcr40 552) (epcr41 553) (epcr42 554) (epcr43 555) 2521 (epcr44 556) (epcr45 557) (epcr46 558) (epcr47 559) 2522 (epcr48 560) (epcr49 561) (epcr50 562) (epcr51 563) 2523 (epcr52 564) (epcr53 565) (epcr54 566) (epcr55 567) 2524 (epcr56 568) (epcr57 569) (epcr58 570) (epcr59 571) 2525 (epcr60 572) (epcr61 573) (epcr62 574) (epcr63 575) 2526 2527 (esr0 576) (esr1 577) (esr2 578) (esr3 579) 2528 (esr4 580) (esr5 581) (esr6 582) (esr7 583) 2529 (esr8 584) (esr9 585) (esr10 586) (esr11 587) 2530 (esr12 588) (esr13 589) (esr14 590) (esr15 591) 2531 (esr16 592) (esr17 593) (esr18 594) (esr19 595) 2532 (esr20 596) (esr21 597) (esr22 598) (esr23 599) 2533 (esr24 600) (esr25 601) (esr26 602) (esr27 603) 2534 (esr28 604) (esr29 605) (esr30 606) (esr31 607) 2535 (esr32 608) (esr33 609) (esr34 610) (esr35 611) 2536 (esr36 612) (esr37 613) (esr38 614) (esr39 615) 2537 (esr40 616) (esr41 617) (esr42 618) (esr43 619) 2538 (esr44 620) (esr45 621) (esr46 622) (esr47 623) 2539 (esr48 624) (esr49 625) (esr50 626) (esr51 627) 2540 (esr52 628) (esr53 629) (esr54 630) (esr55 631) 2541 (esr56 632) (esr57 633) (esr58 634) (esr59 635) 2542 (esr60 636) (esr61 637) (esr62 638) (esr63 639) 2543 2544 (eir0 640) (eir1 641) (eir2 642) (eir3 643) 2545 (eir4 644) (eir5 645) (eir6 646) (eir7 647) 2546 (eir8 648) (eir9 649) (eir10 650) (eir11 651) 2547 (eir12 652) (eir13 653) (eir14 654) (eir15 655) 2548 (eir16 656) (eir17 657) (eir18 658) (eir19 659) 2549 (eir20 660) (eir21 661) (eir22 662) (eir23 663) 2550 (eir24 664) (eir25 665) (eir26 666) (eir27 667) 2551 (eir28 668) (eir29 669) (eir30 670) (eir31 671) 2552 2553 (esfr0 672) (esfr1 673) 2554 2555 (sr0 768) (sr1 769) (sr2 770) (sr3 771) 2556 2557 (scr0 832) (scr1 833) (scr2 834) (scr3 835) 2558 2559 (fsr0 1024) (fsr1 1025) (fsr2 1026) (fsr3 1027) 2560 (fsr4 1028) (fsr5 1029) (fsr6 1030) (fsr7 1031) 2561 (fsr8 1032) (fsr9 1033) (fsr10 1034) (fsr11 1035) 2562 (fsr12 1036) (fsr13 1037) (fsr14 1038) (fsr15 1039) 2563 (fsr16 1040) (fsr17 1041) (fsr18 1042) (fsr19 1043) 2564 (fsr20 1044) (fsr21 1045) (fsr22 1046) (fsr23 1047) 2565 (fsr24 1048) (fsr25 1049) (fsr26 1050) (fsr27 1051) 2566 (fsr28 1052) (fsr29 1053) (fsr30 1054) (fsr31 1055) 2567 (fsr32 1056) (fsr33 1057) (fsr34 1058) (fsr35 1059) 2568 (fsr36 1060) (fsr37 1061) (fsr38 1062) (fsr39 1063) 2569 (fsr40 1064) (fsr41 1065) (fsr42 1066) (fsr43 1067) 2570 (fsr44 1068) (fsr45 1069) (fsr46 1070) (fsr47 1071) 2571 (fsr48 1072) (fsr49 1073) (fsr50 1074) (fsr51 1075) 2572 (fsr52 1076) (fsr53 1077) (fsr54 1078) (fsr55 1079) 2573 (fsr56 1080) (fsr57 1081) (fsr58 1082) (fsr59 1083) 2574 (fsr60 1084) (fsr61 1085) (fsr62 1086) (fsr63 1087) 2575 2576 ; FQ0-FQ31 are 64 bit registers. 2577 ; These names allow access to the upper 32 bits of the FQ registers. 2578 (fqop0 1088) (fqop1 1090) (fqop2 1092) (fqop3 1094) 2579 (fqop4 1096) (fqop5 1098) (fqop6 1100) (fqop7 1102) 2580 (fqop8 1104) (fqop9 1106) (fqop10 1108) (fqop11 1110) 2581 (fqop12 1112) (fqop13 1114) (fqop14 1116) (fqop15 1118) 2582 (fqop16 1120) (fqop17 1122) (fqop18 1124) (fqop19 1126) 2583 (fqop20 1128) (fqop21 1130) (fqop22 1132) (fqop23 1134) 2584 (fqop24 1136) (fqop25 1138) (fqop26 1140) (fqop27 1142) 2585 (fqop28 1144) (fqop29 1146) (fqop30 1148) (fqop31 1150) 2586 ; These names allow access to the lower 32 bits of the FQ registers. 2587 (fqst0 1089) (fqst1 1091) (fqst2 1093) (fqst3 1095) 2588 (fqst4 1097) (fqst5 1099) (fqst6 1101) (fqst7 1103) 2589 (fqst8 1105) (fqst9 1107) (fqst10 1109) (fqst11 1111) 2590 (fqst12 1113) (fqst13 1115) (fqst14 1117) (fqst15 1119) 2591 (fqst16 1121) (fqst17 1123) (fqst18 1125) (fqst19 1127) 2592 (fqst20 1129) (fqst21 1131) (fqst22 1133) (fqst23 1135) 2593 (fqst24 1137) (fqst25 1139) (fqst26 1141) (fqst27 1143) 2594 (fqst28 1145) (fqst29 1147) (fqst30 1149) (fqst31 1151) 2595 ; These also access the lower 32 bits of the FQ registers. 2596 ; These are not accessible as spr registers (see LSI appendix - section 13.4) 2597; (fq0 1089) (fq1 1091) (fq2 1093) (fq3 1095) 2598; (fq4 1097) (fq5 1099) (fq6 1101) (fq7 1103) 2599; (fq8 1105) (fq9 1107) (fq10 1109) (fq11 1111) 2600; (fq12 1113) (fq13 1115) (fq14 1117) (fq15 1119) 2601; (fq16 1121) (fq17 1123) (fq18 1125) (fq19 1127) 2602; (fq20 1129) (fq21 1131) (fq22 1133) (fq23 1135) 2603; (fq24 1137) (fq25 1139) (fq26 1141) (fq27 1143) 2604; (fq28 1145) (fq29 1147) (fq30 1149) (fq31 1151) 2605 2606 (mcilr0 1272) (mcilr1 1273) 2607 2608 (msr0 1280) (msr1 1281) (msr2 1282) (msr3 1283) 2609 (msr4 1284) (msr5 1285) (msr6 1286) (msr7 1287) 2610 (msr8 1288) (msr9 1289) (msr10 1290) (msr11 1291) 2611 (msr12 1292) (msr13 1293) (msr14 1294) (msr15 1295) 2612 (msr16 1296) (msr17 1297) (msr18 1298) (msr19 1299) 2613 (msr20 1300) (msr21 1301) (msr22 1302) (msr23 1303) 2614 (msr24 1304) (msr25 1305) (msr26 1306) (msr27 1307) 2615 (msr28 1308) (msr29 1309) (msr30 1310) (msr31 1311) 2616 (msr32 1312) (msr33 1313) (msr34 1314) (msr35 1315) 2617 (msr36 1316) (msr37 1317) (msr38 1318) (msr39 1319) 2618 (msr40 1320) (msr41 1321) (msr42 1322) (msr43 1323) 2619 (msr44 1324) (msr45 1325) (msr46 1326) (msr47 1327) 2620 (msr48 1328) (msr49 1329) (msr50 1330) (msr51 1331) 2621 (msr52 1332) (msr53 1333) (msr54 1334) (msr55 1335) 2622 (msr56 1336) (msr57 1337) (msr58 1338) (msr59 1339) 2623 (msr60 1340) (msr61 1341) (msr62 1342) (msr63 1343) 2624 2625 ; MQ0-MQ31 are 64 bit registers. 2626 ; These names allow access to the upper 32 bits of the MQ registers. 2627 (mqop0 1344) (mqop1 1346) (mqop2 1348) (mqop3 1350) 2628 (mqop4 1352) (mqop5 1354) (mqop6 1356) (mqop7 1358) 2629 (mqop8 1360) (mqop9 1362) (mqop10 1364) (mqop11 1366) 2630 (mqop12 1368) (mqop13 1370) (mqop14 1372) (mqop15 1374) 2631 (mqop16 1376) (mqop17 1378) (mqop18 1380) (mqop19 1382) 2632 (mqop20 1384) (mqop21 1386) (mqop22 1388) (mqop23 1390) 2633 (mqop24 1392) (mqop25 1394) (mqop26 1396) (mqop27 1398) 2634 (mqop28 1400) (mqop29 1402) (mqop30 1404) (mqop31 1406) 2635 ; These names allow access to the lower 32 bits of the MQ registers. 2636 (mqst0 1345) (mqst1 1347) (mqst2 1349) (mqst3 1351) 2637 (mqst4 1353) (mqst5 1355) (mqst6 1357) (mqst7 1359) 2638 (mqst8 1361) (mqst9 1363) (mqst10 1365) (mqst11 1367) 2639 (mqst12 1369) (mqst13 1371) (mqst14 1373) (mqst15 1375) 2640 (mqst16 1377) (mqst17 1379) (mqst18 1381) (mqst19 1383) 2641 (mqst20 1385) (mqst21 1387) (mqst22 1389) (mqst23 1391) 2642 (mqst24 1393) (mqst25 1395) (mqst26 1397) (mqst27 1399) 2643 (mqst28 1401) (mqst29 1403) (mqst30 1405) (mqst31 1407) 2644 ; These also access the lower 32 bits of the MQ registers. 2645 ; These are not accessible as spr registers (see LSI appendix - section 13.4) 2646; (mq0 1345) (mq1 1347) (mq2 1349) (mq3 1351) 2647; (mq4 1353) (mq5 1355) (mq6 1357) (mq7 1359) 2648; (mq8 1361) (mq9 1363) (mq10 1365) (mq11 1367) 2649; (mq12 1369) (mq13 1371) (mq14 1373) (mq15 1375) 2650; (mq16 1377) (mq17 1379) (mq18 1381) (mq19 1383) 2651; (mq20 1385) (mq21 1387) (mq22 1389) (mq23 1391) 2652; (mq24 1393) (mq25 1395) (mq26 1397) (mq27 1399) 2653; (mq28 1401) (mq29 1403) (mq30 1405) (mq31 1407) 2654 2655 ; These are not accessible as spr registers (see LSI appendix - section 13.4) 2656; (acc0 1408) (acc1 1409) (acc2 1410) (acc3 1411) 2657; (acc4 1412) (acc5 1413) (acc6 1414) (acc7 1415) 2658; (acc8 1416) (acc9 1417) (acc10 1418) (acc11 1419) 2659; (acc12 1420) (acc13 1421) (acc14 1422) (acc15 1423) 2660; (acc16 1424) (acc17 1425) (acc18 1426) (acc19 1427) 2661; (acc20 1428) (acc21 1429) (acc22 1430) (acc23 1431) 2662; (acc24 1432) (acc25 1433) (acc26 1434) (acc27 1435) 2663; (acc28 1436) (acc29 1437) (acc30 1438) (acc31 1439) 2664; (acc32 1440) (acc33 1441) (acc34 1442) (acc35 1443) 2665; (acc36 1444) (acc37 1445) (acc38 1446) (acc39 1447) 2666; (acc40 1448) (acc41 1449) (acc42 1450) (acc43 1451) 2667; (acc44 1452) (acc45 1453) (acc46 1454) (acc47 1455) 2668; (acc48 1456) (acc49 1457) (acc50 1458) (acc51 1459) 2669; (acc52 1460) (acc53 1461) (acc54 1462) (acc55 1463) 2670; (acc56 1464) (acc57 1465) (acc58 1466) (acc59 1467) 2671; (acc60 1468) (acc61 1469) (acc62 1470) (acc63 1471) 2672 2673; (accg0 1472) (accg1 1473) (accg2 1474) (accg3 1475) 2674; (accg4 1476) (accg5 1477) (accg6 1478) (accg7 1479) 2675; (accg8 1480) (accg9 1481) (accg10 1482) (accg11 1483) 2676; (accg12 1484) (accg13 1485) (accg14 1486) (accg15 1487) 2677; (accg16 1488) (accg17 1489) (accg18 1490) (accg19 1491) 2678; (accg20 1492) (accg21 1493) (accg22 1494) (accg23 1495) 2679; (accg24 1496) (accg25 1497) (accg26 1498) (accg27 1499) 2680; (accg28 1500) (accg29 1501) (accg30 1502) (accg31 1503) 2681; (accg32 1504) (accg33 1505) (accg34 1506) (accg35 1507) 2682; (accg36 1508) (accg37 1509) (accg38 1510) (accg39 1511) 2683; (accg40 1512) (accg41 1513) (accg42 1514) (accg43 1515) 2684; (accg44 1516) (accg45 1517) (accg46 1518) (accg47 1519) 2685; (accg48 1520) (accg49 1521) (accg50 1522) (accg51 1523) 2686; (accg52 1524) (accg53 1525) (accg54 1526) (accg55 1527) 2687; (accg56 1528) (accg57 1529) (accg58 1530) (accg59 1531) 2688; (accg60 1532) (accg61 1533) (accg62 1534) (accg63 1535) 2689 2690 (ear0 1536) (ear1 1537) (ear2 1538) (ear3 1539) 2691 (ear4 1540) (ear5 1541) (ear6 1542) (ear7 1543) 2692 (ear8 1544) (ear9 1545) (ear10 1546) (ear11 1547) 2693 (ear12 1548) (ear13 1549) (ear14 1550) (ear15 1551) 2694 (ear16 1552) (ear17 1553) (ear18 1554) (ear19 1555) 2695 (ear20 1556) (ear21 1557) (ear22 1558) (ear23 1559) 2696 (ear24 1560) (ear25 1561) (ear26 1562) (ear27 1563) 2697 (ear28 1564) (ear29 1565) (ear30 1566) (ear31 1567) 2698 (ear32 1568) (ear33 1569) (ear34 1570) (ear35 1571) 2699 (ear36 1572) (ear37 1573) (ear38 1574) (ear39 1575) 2700 (ear40 1576) (ear41 1577) (ear42 1578) (ear43 1579) 2701 (ear44 1580) (ear45 1581) (ear46 1582) (ear47 1583) 2702 (ear48 1584) (ear49 1585) (ear50 1586) (ear51 1587) 2703 (ear52 1588) (ear53 1589) (ear54 1590) (ear55 1591) 2704 (ear56 1592) (ear57 1593) (ear58 1594) (ear59 1595) 2705 (ear60 1596) (ear61 1597) (ear62 1598) (ear63 1599) 2706 2707 (edr0 1600) (edr1 1601) (edr2 1602) (edr3 1603) 2708 (edr4 1604) (edr5 1605) (edr6 1606) (edr7 1607) 2709 (edr8 1608) (edr9 1609) (edr10 1610) (edr11 1611) 2710 (edr12 1612) (edr13 1613) (edr14 1614) (edr15 1615) 2711 (edr16 1616) (edr17 1617) (edr18 1618) (edr19 1619) 2712 (edr20 1620) (edr21 1621) (edr22 1622) (edr23 1623) 2713 (edr24 1624) (edr25 1625) (edr26 1626) (edr27 1627) 2714 (edr28 1628) (edr29 1629) (edr30 1630) (edr31 1631) 2715 (edr32 1632) (edr33 1636) (edr34 1634) (edr35 1635) 2716 (edr36 1636) (edr37 1637) (edr38 1638) (edr39 1639) 2717 (edr40 1640) (edr41 1641) (edr42 1642) (edr43 1643) 2718 (edr44 1644) (edr45 1645) (edr46 1646) (edr47 1647) 2719 (edr48 1648) (edr49 1649) (edr50 1650) (edr51 1651) 2720 (edr52 1652) (edr53 1653) (edr54 1654) (edr55 1655) 2721 (edr56 1656) (edr57 1657) (edr58 1658) (edr59 1659) 2722 (edr60 1660) (edr61 1661) (edr62 1662) (edr63 1663) 2723 2724 (iamlr0 1664) (iamlr1 1665) (iamlr2 1666) (iamlr3 1667) 2725 (iamlr4 1668) (iamlr5 1669) (iamlr6 1670) (iamlr7 1671) 2726 (iamlr8 1672) (iamlr9 1673) (iamlr10 1674) (iamlr11 1675) 2727 (iamlr12 1676) (iamlr13 1677) (iamlr14 1678) (iamlr15 1679) 2728 (iamlr16 1680) (iamlr17 1681) (iamlr18 1682) (iamlr19 1683) 2729 (iamlr20 1684) (iamlr21 1685) (iamlr22 1686) (iamlr23 1687) 2730 (iamlr24 1688) (iamlr25 1689) (iamlr26 1690) (iamlr27 1691) 2731 (iamlr28 1692) (iamlr29 1693) (iamlr30 1694) (iamlr31 1695) 2732 (iamlr32 1696) (iamlr33 1697) (iamlr34 1698) (iamlr35 1699) 2733 (iamlr36 1700) (iamlr37 1701) (iamlr38 1702) (iamlr39 1703) 2734 (iamlr40 1704) (iamlr41 1705) (iamlr42 1706) (iamlr43 1707) 2735 (iamlr44 1708) (iamlr45 1709) (iamlr46 1710) (iamlr47 1711) 2736 (iamlr48 1712) (iamlr49 1713) (iamlr50 1714) (iamlr51 1715) 2737 (iamlr52 1716) (iamlr53 1717) (iamlr54 1718) (iamlr55 1719) 2738 (iamlr56 1720) (iamlr57 1721) (iamlr58 1722) (iamlr59 1723) 2739 (iamlr60 1724) (iamlr61 1725) (iamlr62 1726) (iamlr63 1727) 2740 2741 (iampr0 1728) (iampr1 1729) (iampr2 1730) (iampr3 1731) 2742 (iampr4 1732) (iampr5 1733) (iampr6 1734) (iampr7 1735) 2743 (iampr8 1736) (iampr9 1737) (iampr10 1738) (iampr11 1739) 2744 (iampr12 1740) (iampr13 1741) (iampr14 1742) (iampr15 1743) 2745 (iampr16 1744) (iampr17 1745) (iampr18 1746) (iampr19 1747) 2746 (iampr20 1748) (iampr21 1749) (iampr22 1750) (iampr23 1751) 2747 (iampr24 1752) (iampr25 1753) (iampr26 1754) (iampr27 1755) 2748 (iampr28 1756) (iampr29 1757) (iampr30 1758) (iampr31 1759) 2749 (iampr32 1760) (iampr33 1761) (iampr34 1762) (iampr35 1763) 2750 (iampr36 1764) (iampr37 1765) (iampr38 1766) (iampr39 1767) 2751 (iampr40 1768) (iampr41 1769) (iampr42 1770) (iampr43 1771) 2752 (iampr44 1772) (iampr45 1773) (iampr46 1774) (iampr47 1775) 2753 (iampr48 1776) (iampr49 1777) (iampr50 1778) (iampr51 1779) 2754 (iampr52 1780) (iampr53 1781) (iampr54 1782) (iampr55 1783) 2755 (iampr56 1784) (iampr57 1785) (iampr58 1786) (iampr59 1787) 2756 (iampr60 1788) (iampr61 1789) (iampr62 1790) (iampr63 1791) 2757 2758 (damlr0 1792) (damlr1 1793) (damlr2 1794) (damlr3 1795) 2759 (damlr4 1796) (damlr5 1797) (damlr6 1798) (damlr7 1799) 2760 (damlr8 1800) (damlr9 1801) (damlr10 1802) (damlr11 1803) 2761 (damlr12 1804) (damlr13 1805) (damlr14 1806) (damlr15 1807) 2762 (damlr16 1808) (damlr17 1809) (damlr18 1810) (damlr19 1811) 2763 (damlr20 1812) (damlr21 1813) (damlr22 1814) (damlr23 1815) 2764 (damlr24 1816) (damlr25 1817) (damlr26 1818) (damlr27 1819) 2765 (damlr28 1820) (damlr29 1821) (damlr30 1822) (damlr31 1823) 2766 (damlr32 1824) (damlr33 1825) (damlr34 1826) (damlr35 1827) 2767 (damlr36 1828) (damlr37 1829) (damlr38 1830) (damlr39 1831) 2768 (damlr40 1832) (damlr41 1833) (damlr42 1834) (damlr43 1835) 2769 (damlr44 1836) (damlr45 1837) (damlr46 1838) (damlr47 1839) 2770 (damlr48 1840) (damlr49 1841) (damlr50 1842) (damlr51 1843) 2771 (damlr52 1844) (damlr53 1845) (damlr54 1846) (damlr55 1847) 2772 (damlr56 1848) (damlr57 1849) (damlr58 1850) (damlr59 1851) 2773 (damlr60 1852) (damlr61 1853) (damlr62 1854) (damlr63 1855) 2774 2775 (dampr0 1856) (dampr1 1857) (dampr2 1858) (dampr3 1859) 2776 (dampr4 1860) (dampr5 1861) (dampr6 1862) (dampr7 1863) 2777 (dampr8 1864) (dampr9 1865) (dampr10 1866) (dampr11 1867) 2778 (dampr12 1868) (dampr13 1869) (dampr14 1870) (dampr15 1871) 2779 (dampr16 1872) (dampr17 1873) (dampr18 1874) (dampr19 1875) 2780 (dampr20 1876) (dampr21 1877) (dampr22 1878) (dampr23 1879) 2781 (dampr24 1880) (dampr25 1881) (dampr26 1882) (dampr27 1883) 2782 (dampr28 1884) (dampr29 1885) (dampr30 1886) (dampr31 1887) 2783 (dampr32 1888) (dampr33 1889) (dampr34 1890) (dampr35 1891) 2784 (dampr36 1892) (dampr37 1893) (dampr38 1894) (dampr39 1895) 2785 (dampr40 1896) (dampr41 1897) (dampr42 1898) (dampr43 1899) 2786 (dampr44 1900) (dampr45 1901) (dampr46 1902) (dampr47 1903) 2787 (dampr48 1904) (dampr49 1905) (dampr50 1906) (dampr51 1907) 2788 (dampr52 1908) (dampr53 1909) (dampr54 1910) (dampr55 1911) 2789 (dampr56 1912) (dampr57 1913) (dampr58 1914) (dampr59 1915) 2790 (dampr60 1916) (dampr61 1917) (dampr62 1918) (dampr63 1919) 2791 2792 (amcr 1920) (stbar 1921) (mmcr 1922) 2793 (iamvr1 1925) (damvr1 1927) 2794 (cxnr 1936) (ttbr 1937) (tplr 1938) (tppr 1939) 2795 (tpxr 1940) 2796 (timerh 1952) (timerl 1953) (timerd 1954) 2797 (dcr 2048) (brr 2049) (nmar 2050) (btbr 2051) 2798 2799 (ibar0 2052) (ibar1 2053) (ibar2 2054) (ibar3 2055) 2800 (dbar0 2056) (dbar1 2057) (dbar2 2058) (dbar3 2059) 2801 2802 (dbdr00 2060) (dbdr01 2061) (dbdr02 2062) (dbdr03 2063) 2803 (dbdr10 2064) (dbdr11 2065) (dbdr12 2066) (dbdr13 2067) 2804 (dbdr20 2068) (dbdr21 2069) (dbdr22 2070) (dbdr23 2071) 2805 (dbdr30 2072) (dbdr31 2073) (dbdr32 2074) (dbdr33 2075) 2806 2807 (dbmr00 2076) (dbmr01 2077) (dbmr02 2078) (dbmr03 2079) 2808 (dbmr10 2080) (dbmr11 2081) (dbmr12 2082) (dbmr13 2083) 2809 (dbmr20 2084) (dbmr21 2085) (dbmr22 2086) (dbmr23 2087) 2810 (dbmr30 2088) (dbmr31 2089) (dbmr32 2090) (dbmr33 2091) 2811 2812 (cpcfr 2304) (cpcr 2305) (cpsr 2306) (cptr 2307) 2813 (cphsr0 2308) (cphsr1 2309) (cpesr0 2320) (cpesr1 2321) 2814 (cpemr0 2322) (cpemr1 2323) 2815 2816 (iperr0 2324) (iperr1 2325) (ipjsr 2326) (ipjrr 2327) 2817 (ipcsr0 2336) (ipcsr1 2337) (ipcwer0 2338) (ipcwer1 2339) 2818 (ipcwr 2340) 2819 2820 (mbhsr 2352) (mbssr 2353) (mbrsr 2354) (mbsdr 2355) 2821 (mbrdr 2356) (mbsmr 2357) (mbstr0 2359) (mbstr1 2360) 2822 2823 (slpr 2368) (sldr 2369) (slhsr 2370) (sltr 2371) 2824 (slwr 2372) 2825 2826 (ihsr8 3848) (ihsr9 3849) (ihsr10 3850) 2827 ) 2828) 2829 2830(define-hardware 2831 (name h-spr) 2832 (comment "special purpose registers") 2833 (attrs PROFILE) 2834 (type register UWI (4096)) 2835 (indices extern-keyword spr-names) 2836 (get (index) (c-call UWI "@cpu@_h_spr_get_handler" index)) 2837 (set (index newval) (c-call VOID "@cpu@_h_spr_set_handler" index newval)) 2838) 2839 2840(define-pmacro (spr-pcsr) (reg h-spr 1)) 2841(define-pmacro (spr-bpcsr) (reg h-spr 2)) 2842(define-pmacro (spr-lr) (reg h-spr 272)) 2843(define-pmacro (spr-lcr) (reg h-spr 273)) 2844(define-pmacro (spr-iacc0h) (reg h-spr 280)) 2845(define-pmacro (spr-iacc0l) (reg h-spr 281)) 2846(define-pmacro (spr-sr0) (reg h-spr 768)) 2847(define-pmacro (spr-sr1) (reg h-spr 769)) 2848(define-pmacro (spr-sr2) (reg h-spr 770)) 2849(define-pmacro (spr-sr3) (reg h-spr 771)) 2850 2851; Accumulator guard. Actually a subset of the SPR registers, but those SPRs 2852; are read-only in most insns. This hardware element is used by those insns 2853; which have direct access (mwtaccg, mrdaccg). 2854(define-keyword 2855 (name accg-names) 2856 (print-name h-accg) 2857 (prefix "") 2858 (values 2859 (accg0 0)(accg1 1)(accg2 2)(accg3 3) 2860 (accg4 4)(accg5 5)(accg6 6)(accg7 7) 2861 (accg8 8)(accg9 9)(accg10 10)(accg11 11) 2862 (accg12 12)(accg13 13)(accg14 14)(accg15 15) 2863 (accg16 16)(accg17 17)(accg18 18)(accg19 19) 2864 (accg20 20)(accg21 21)(accg22 22)(accg23 23) 2865 (accg24 24)(accg25 25)(accg26 26)(accg27 27) 2866 (accg28 28)(accg29 29)(accg30 30)(accg31 31) 2867 (accg32 32)(accg33 33)(accg34 34)(accg35 35) 2868 (accg36 36)(accg37 37)(accg38 38)(accg39 39) 2869 (accg40 40)(accg41 41)(accg42 42)(accg43 43) 2870 (accg44 44)(accg45 45)(accg46 46)(accg47 47) 2871 (accg48 48)(accg49 49)(accg50 50)(accg51 51) 2872 (accg52 52)(accg53 53)(accg54 54)(accg55 55) 2873 (accg56 56)(accg57 57)(accg58 58)(accg59 59) 2874 (accg60 60)(accg61 61)(accg62 62)(accg63 63) 2875 ) 2876) 2877 2878(define-hardware 2879 (name h-accg) 2880 (comment "accumulator guard") 2881 (attrs PROFILE VIRTUAL) 2882 (type register UWI (64)) 2883 (indices extern-keyword accg-names) 2884 (get (index) 2885 (and (reg h-spr (add index 1472)) #xff)) 2886 (set (index newval) 2887 (set (raw-reg UWI h-spr (add index 1472)) (and newval #xff))) 2888) 2889 2890; 40 bit accumulator. Composed of ACCG and ACC registers concatenated, but 2891; referenced more often as the composed 40 bits. 2892(define-keyword 2893 (name acc-names) 2894 (print-name h-acc40) 2895 (prefix "") 2896 (values 2897(acc0 0)(acc1 1)(acc2 2)(acc3 3)(acc4 4)(acc5 5)(acc6 6)(acc7 7) 2898(acc8 8)(acc9 9)(acc10 10)(acc11 11)(acc12 12)(acc13 13)(acc14 14)(acc15 15) 2899(acc16 16)(acc17 17)(acc18 18)(acc19 19)(acc20 20)(acc21 21)(acc22 22)(acc23 23) 2900(acc24 24)(acc25 25)(acc26 26)(acc27 27)(acc28 28)(acc29 29)(acc30 30)(acc31 31) 2901(acc32 32)(acc33 33)(acc34 34)(acc35 35)(acc36 36)(acc37 37)(acc38 38)(acc39 39) 2902(acc40 40)(acc41 41)(acc42 42)(acc43 43)(acc44 44)(acc45 45)(acc46 46)(acc47 47) 2903(acc48 48)(acc49 49)(acc50 50)(acc51 51)(acc52 52)(acc53 53)(acc54 54)(acc55 55) 2904(acc56 56)(acc57 57)(acc58 58)(acc59 59)(acc60 60)(acc61 61)(acc62 62)(acc63 63) 2905 ) 2906) 2907 2908(define-hardware 2909 (name h-acc40S) 2910 (comment "40 bit signed accumulator") 2911 (attrs PROFILE VIRTUAL) 2912 (type register DI (64)) 2913 (indices extern-keyword acc-names) 2914 ; The accumlator is made up of two 32 bit registers, accgi/acci. 2915 ; We want to extract this as a combined 40 signed bits 2916 (get (index) 2917 (or DI 2918 (sll DI (ext DI (trunc QI (reg h-spr (add index 1472)))) 2919 32) 2920 (zext DI (reg h-spr (add index 1408))))) 2921 ; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions 2922 ; on ACC and ACCG registers 2923 (set (index newval) 2924 (sequence () 2925 (c-call VOID "frv_check_spr_write_access" (add index 1408)) 2926 (set (raw-reg UWI h-spr 2927 (add index 1472)) (and (srl newval 32) #xff)) 2928 (set (raw-reg UWI h-spr 2929 (add index 1408)) (trunc USI newval)))) 2930) 2931 2932(define-hardware 2933 (name h-acc40U) 2934 (comment "40 bit unsigned accumulator") 2935 (attrs PROFILE VIRTUAL) 2936 (type register UDI (64)) 2937 (indices extern-keyword acc-names) 2938 ; The accumlator is made up of two 32 bit registers, accgi/acci. 2939 ; We want to extract this as a combined 40 unsigned bits 2940 (get (index) 2941 (or DI 2942 (sll DI (zext DI (reg h-spr (add index 1472))) 32) 2943 (zext DI (reg h-spr (add index 1408))))) 2944 ; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions 2945 ; on ACC and ACCG registers 2946 (set (index newval) 2947 (sequence () 2948 (c-call VOID "frv_check_spr_write_access" (add index 1408)) 2949 (set (raw-reg UWI h-spr 2950 (add index 1472)) (and (srl newval 32) #xff)) 2951 (set (raw-reg UWI h-spr 2952 (add index 1408)) (trunc USI newval)))) 2953) 2954; 64-bit signed accumulator. Composed of iacc0h and iacc0l registers 2955; concatenated, but referenced more often as the composed 64 bits. 2956(define-keyword 2957 ; This is totally hokey -- I have to have an index! 2958 (name iacc0-names) 2959 (print-name h-iacc0) 2960 (prefix "") 2961 (values (iacc0 0)) 2962) 2963 2964(define-hardware 2965 (name h-iacc0) 2966 (comment "64 bit signed accumulator") 2967 (attrs PROFILE VIRTUAL (MACH fr400,fr450)) 2968 (type register DI (1)) 2969 (indices extern-keyword iacc0-names) 2970 ; The single 64-bit integer accumulator is made up of two 32 bit 2971 ; registers, iacc0h and iacc0l. We want to extract this as a 2972 ; combined 64 signed bits. 2973 (get (idx) (or DI (sll DI (ext DI (spr-iacc0h)) 32) (zext DI (spr-iacc0l)))) 2974 (set (idx newval) 2975 (sequence () 2976 (set (spr-iacc0h) (trunc SI (srl newval 32))) 2977 (set (spr-iacc0l) (trunc SI newval)))) 2978) 2979 2980; Integer condition code registers (CCR) 2981; 2982; The individual sub registers bits of the CCR are referenced more often than 2983; the entire register so set them directly. We can assemble the 2984; entire register when necessary. 2985; 2986(define-keyword 2987 (name iccr-names) 2988 (print-name h-iccr) 2989 (prefix "") 2990 (values (icc0 0) (icc1 1) (icc2 2) (icc3 3)) 2991) 2992 2993(define-hardware 2994 (name h-iccr) 2995 (comment "Integer condition code registers") 2996 (attrs PROFILE) 2997 (type register UQI (4)) 2998 (indices extern-keyword iccr-names) 2999) 3000 3001; Floating point condition code registers (CCR) 3002; 3003; The individual sub registers bits of the CCR are referenced more often than 3004; the entire register so set them directly. We can assemble the 3005; entire register when necessary. 3006; 3007(define-keyword 3008 (name fccr-names) 3009 (print-name h-fccr) 3010 (prefix "") 3011 (values (fcc0 0) (fcc1 1) (fcc2 2) (fcc3 3)) 3012) 3013 3014(define-hardware 3015 (name h-fccr) 3016 (comment "Floating point condition code registers") 3017 (attrs PROFILE) 3018 (type register UQI (4)) 3019 (indices extern-keyword fccr-names) 3020) 3021 3022; C condition code registers (CCCR) 3023; 3024(define-keyword 3025 (name cccr-names) 3026 (print-name h-cccr) 3027 (prefix "") 3028 (values (cc0 0) (cc1 1) (cc2 2) (cc3 3) (cc4 4) (cc5 5) (cc6 6) (cc7 7)) 3029) 3030 3031(define-hardware 3032 (name h-cccr) 3033 (comment "Condition code registers") 3034 (attrs PROFILE) 3035 (type register UQI (8)) 3036 (indices extern-keyword cccr-names) 3037) 3038 3039; Dummy hardware used to define packing bit on insns 3040; 3041(define-hardware 3042 (name h-pack) 3043 (comment "Packing bit dummy hardware") 3044 (type immediate (UINT 1)) 3045 (values keyword "" (("" 1) (".p" 0) (".P" 0))) 3046) 3047; Dummy hardware used to define hint field for branches always taken 3048; 3049(define-hardware 3050 (name h-hint-taken) 3051 (comment "Branch taken hint dummy hardware") 3052 (type immediate (UINT 1)) 3053 ; The order of these is important. We want '2' to get written by default, 3054 ; but we also want the docoder/disassembler to allow the values '0', '1' and 3055 ; '3'. 3056 (values keyword "" (("" 2) ("" 0) ("" 1) ("" 3))) 3057) 3058; Dummy hardware used to define hint field for branches never taken 3059; 3060(define-hardware 3061 (name h-hint-not-taken) 3062 (comment "Branch not taken hint dummy hardware") 3063 (type immediate (UINT 1)) 3064 ; The order of these is important. We want '0' to get written by default, 3065 ; but we also want the docoder/disassembler to allow the values '1', '2' and 3066 ; '3'. 3067 (values keyword "" (("" 0) ("" 1) ("" 2) ("" 3))) 3068) 3069 3070; Instruction Operands. 3071; These entries provide a layer between the assembler and the raw hardware 3072; description, and are used to refer to hardware elements in the semantic 3073; code. Usually there's a bit of over-specification, but in more complicated 3074; instruction sets there isn't. 3075 3076; FRV specific operand attributes: 3077 3078(define-attr 3079 (for operand) 3080 (type boolean) 3081 (name HASH-PREFIX) 3082 (comment "immediates have an optional '#' prefix") 3083) 3084 3085; ??? Convention says this should be o-sr, but then the insn definitions 3086; should refer to o-sr which is clumsy. The "o-" could be implicit, but 3087; then it should be implicit for all the symbols here, but then there would 3088; be confusion between (f-)simm8 and (h-)simm8. 3089; So for now the rule is exactly as it appears here. 3090 3091; dnmop: define-normal-mode-operand: temporary, pending potential removal 3092; of modes from h/w. 3093(define-pmacro (dnmop xname xcomment xattrs xtype xindex xmode) 3094 (define-operand 3095 (name xname) 3096 (comment xcomment) 3097 (.splice attrs (.unsplice xattrs)) 3098 (type xtype) 3099 (index xindex) 3100 (mode xmode) 3101 ) 3102) 3103 3104; dnpmop: define-normal-parsed-mode-operand: Normal mode operand with parse handler 3105(define-pmacro (dnpmop xname xcomment xattrs xtype xindex xmode xparse) 3106 (define-operand 3107 (name xname) 3108 (comment xcomment) 3109 (.splice attrs (.unsplice xattrs)) 3110 (type xtype) 3111 (index xindex) 3112 (mode xmode) 3113 (handlers (parse xparse)) 3114 ) 3115) 3116 3117(dnop pack "packing bit" () h-pack f-pack) 3118 3119(dnmop GRi "source register 1" () h-gr f-GRi SI) 3120(dnmop GRj "source register 2" () h-gr f-GRj SI) 3121(dnmop GRk "destination register" () h-gr f-GRk SI) 3122(dnmop GRkhi "destination register" () h-gr_hi f-GRk UHI) 3123(dnmop GRklo "destination register" () h-gr_lo f-GRk UHI) 3124(dnpmop GRdoublek "destination register" () h-gr_double f-GRk DI "even_register") 3125(dnmop ACC40Si "signed accumulator" () h-acc40S f-ACC40Si DI) 3126(dnmop ACC40Ui "unsigned accumulator" () h-acc40U f-ACC40Ui UDI) 3127(dnmop ACC40Sk "target accumulator" () h-acc40S f-ACC40Sk DI) 3128(dnmop ACC40Uk "target accumulator" () h-acc40U f-ACC40Uk UDI) 3129(dnmop ACCGi "source register" () h-accg f-ACCGi UWI) 3130(dnmop ACCGk "target register" () h-accg f-ACCGk UWI) 3131 3132(dnmop CPRi "source register" ((MACH frv)) h-cpr f-CPRi SI) 3133(dnmop CPRj "source register" ((MACH frv)) h-cpr f-CPRj SI) 3134(dnmop CPRk "destination register" ((MACH frv)) h-cpr f-CPRk SI) 3135(dnpmop CPRdoublek "destination register" ((MACH frv)) h-cpr_double f-CPRk DI "even_register") 3136 3137; floating point operands 3138(dnmop FRinti "source register 1" () h-fr_int f-FRi SI) 3139(dnmop FRintj "source register 2" () h-fr_int f-FRj SI) 3140(dnmop FRintk "target register" () h-fr_int f-FRk SI) 3141(dnmop FRi "source register 1" () h-fr f-FRi SF) 3142(dnmop FRj "source register 2" () h-fr f-FRj SF) 3143(dnmop FRk "destination register" () h-fr f-FRk SF) 3144(dnmop FRkhi "destination register" () h-fr_hi f-FRk UHI) 3145(dnmop FRklo "destination register" () h-fr_lo f-FRk UHI) 3146(dnpmop FRdoublei "source register 1" () h-fr_double f-FRi DF "even_register") 3147(dnpmop FRdoublej "source register 2" () h-fr_double f-FRj DF "even_register") 3148(dnpmop FRdoublek "target register" () h-fr_double f-FRk DF "even_register") 3149 3150(dnop CRi "source register 1" () h-cccr f-CRi) 3151(dnop CRj "source register 2" () h-cccr f-CRj) 3152(dnop CRj_int "destination register" () h-cccr f-CRj_int) 3153(dnop CRj_float "destination register" () h-cccr f-CRj_float) 3154(dnop CRk "destination register" () h-cccr f-CRk) 3155(dnop CCi "condition register" () h-cccr f-CCi) 3156 3157(dnop ICCi_1 "condition register" () h-iccr f-ICCi_1) 3158(dnop ICCi_2 "condition register" () h-iccr f-ICCi_2) 3159(dnop ICCi_3 "condition register" () h-iccr f-ICCi_3) 3160(dnop FCCi_1 "condition register" () h-fccr f-FCCi_1) 3161(dnop FCCi_2 "condition register" () h-fccr f-FCCi_2) 3162(dnop FCCi_3 "condition register" () h-fccr f-FCCi_3) 3163(dnop FCCk "condition register" () h-fccr f-FCCk) 3164 3165(dnop eir "exception insn reg" () h-uint f-eir) 3166(dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10) 3167(dnop u16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-u16) 3168(dnop s16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-s16) 3169(dnop s6 "6 bit signed immediate" (HASH-PREFIX) h-sint f-s6) 3170(dnop s6_1 "6 bit signed immediate" (HASH-PREFIX) h-sint f-s6_1) 3171(dnop u6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-u6) 3172(dnop s5 "5 bit signed immediate" (HASH-PREFIX) h-sint f-s5) 3173(dnop cond "conditional arithmetic" (HASH-PREFIX) h-uint f-cond) 3174(dnop ccond "lr branch condition" (HASH-PREFIX) h-uint f-ccond) 3175(dnop hint "2 bit branch predictor" (HASH-PREFIX) h-uint f-hint) 3176(dnop hint_taken "2 bit branch predictor" () h-hint-taken f-hint) 3177(dnop hint_not_taken "2 bit branch predictor" () h-hint-not-taken f-hint) 3178 3179(dnop LI "link indicator" () h-uint f-LI) 3180(dnop lock "cache lock indicator" (HASH-PREFIX) h-uint f-lock) 3181(dnop debug "debug mode indicator" (HASH-PREFIX) h-uint f-debug) 3182(dnop ae "all entries indicator" (HASH-PREFIX) h-uint f-ae) 3183 3184(dnop label16 "18 bit pc relative address" () h-iaddr f-label16) 3185 3186(dnop LRAE "Load Real Address E flag" () h-uint f-LRAE) 3187(dnop LRAD "Load Real Address D flag" () h-uint f-LRAD) 3188(dnop LRAS "Load Real Address S flag" () h-uint f-LRAS) 3189 3190(dnop TLBPRopx "TLB Probe operation number" () h-uint f-TLBPRopx) 3191(dnop TLBPRL "TLB Probe L flag" () h-uint f-TLBPRL) 3192 3193(define-operand 3194 (name A0) 3195 (comment "A==0 operand of mclracc") 3196 (attrs) 3197 (type h-uint) 3198 (index f-A) 3199 (mode USI) 3200 (handlers (parse "A0")) 3201) 3202 3203(define-operand 3204 (name A1) 3205 (comment "A==1 operand of mclracc") 3206 (attrs) 3207 (type h-uint) 3208 (index f-A) 3209 (mode USI) 3210 (handlers (parse "A1")) 3211) 3212 3213(define-operand 3214 (name FRintieven) 3215 (comment "(even) source register 1") 3216 (attrs) 3217 (type h-fr_int) 3218 (index f-FRi) 3219 (mode SI) 3220 (handlers (parse "even_register")) 3221) 3222 3223(define-operand 3224 (name FRintjeven) 3225 (comment "(even) source register 2") 3226 (attrs) 3227 (type h-fr_int) 3228 (index f-FRj) 3229 (mode SI) 3230 (handlers (parse "even_register")) 3231) 3232 3233(define-operand 3234 (name FRintkeven) 3235 (comment "(even) target register") 3236 (attrs) 3237 (type h-fr_int) 3238 (index f-FRk) 3239 (mode SI) 3240 (handlers (parse "even_register")) 3241) 3242 3243(define-operand 3244 (name d12) 3245 (comment "12 bit signed immediate") 3246 (attrs) 3247 (type h-sint) 3248 (index f-d12) 3249 (handlers (parse "d12")) 3250) 3251 3252(define-operand 3253 (name s12) 3254 (comment "12 bit signed immediate") 3255 (attrs HASH-PREFIX) 3256 (type h-sint) 3257 (index f-d12) 3258 (handlers (parse "s12")) 3259) 3260 3261(define-operand 3262 (name u12) 3263 (comment "12 bit signed immediate") 3264 (attrs HASH-PREFIX) 3265 (type h-sint) 3266 (index f-u12) 3267 (handlers (parse "u12")) 3268) 3269 3270(define-operand 3271 (name spr) 3272 (comment "special purpose register") 3273 (attrs) 3274 (type h-spr) 3275 (index f-spr) 3276 (handlers (parse "spr") (print "spr")) 3277) 3278 3279(define-operand 3280 (name ulo16) 3281 (comment "16 bit unsigned immediate, for #lo()") 3282 (attrs) 3283 (type h-uint) 3284 (index f-u16) 3285 (handlers (parse "ulo16") (print "lo")) 3286) 3287 3288(define-operand 3289 (name slo16) 3290 (comment "16 bit unsigned immediate, for #lo()") 3291 (attrs) 3292 (type h-sint) 3293 (index f-s16) 3294 (handlers (parse "uslo16") (print "lo")) 3295) 3296 3297(define-operand 3298 (name uhi16) 3299 (comment "16 bit unsigned immediate, for #hi()") 3300 (attrs) 3301 (type h-uint) 3302 (index f-u16) 3303 (handlers (parse "uhi16") (print "hi")) 3304) 3305 3306(define-operand 3307 (name label24) 3308 (comment "26 bit pc relative address") 3309 (attrs) 3310 (type h-iaddr) 3311 (index f-label24) 3312 (mode SI) 3313 (handlers (parse "call_label")) 3314) 3315 3316; operands representing hardware 3317; 3318(dnop psr_esr "PSR.ESR bit" (SEM-ONLY) h-psr_esr f-nil) 3319(dnop psr_s "PSR.S bit" (SEM-ONLY) h-psr_s f-nil) 3320(dnop psr_ps "PSR.PS bit" (SEM-ONLY) h-psr_ps f-nil) 3321(dnop psr_et "PSR.ET bit" (SEM-ONLY) h-psr_et f-nil) 3322 3323(dnop bpsr_bs "BPSR.BS bit" (SEM-ONLY) h-bpsr_bs f-nil) 3324(dnop bpsr_bet "BPSR.BET bit" (SEM-ONLY) h-bpsr_bet f-nil) 3325 3326(dnop tbr_tba "TBR.TBA" (SEM-ONLY) h-tbr_tba f-nil) 3327(dnop tbr_tt "TBR.TT" (SEM-ONLY) h-tbr_tt f-nil) 3328 3329; Null operands 3330; 3331(define-pmacro (ICCi_1-null) (f-ICCi_1-null 0)) 3332(define-pmacro (ICCi_2-null) (f-ICCi_2-null 0)) 3333(define-pmacro (ICCi_3-null) (f-ICCi_3-null 0)) 3334(define-pmacro (FCCi_1-null) (f-FCCi_1-null 0)) 3335(define-pmacro (FCCi_2-null) (f-FCCi_2-null 0)) 3336(define-pmacro (FCCi_3-null) (f-FCCi_3-null 0)) 3337(define-pmacro (rs-null) (f-rs-null 0)) 3338(define-pmacro (GRi-null) (f-GRi-null 0)) 3339(define-pmacro (GRj-null) (f-GRj-null 0)) 3340(define-pmacro (GRk-null) (f-GRk-null 0)) 3341(define-pmacro (FRi-null) (f-FRi-null 0)) 3342(define-pmacro (FRj-null) (f-FRj-null 0)) 3343(define-pmacro (ACCj-null) (f-ACCj-null 0)) 3344(define-pmacro (rd-null) (f-rd-null 0)) 3345(define-pmacro (cond-null) (f-cond-null 0)) 3346(define-pmacro (ccond-null) (f-ccond-null 0)) 3347(define-pmacro (s12-null) (f-s12-null 0)) 3348(define-pmacro (label16-null) (f-label16-null 0)) 3349(define-pmacro (misc-null-1) (f-misc-null-1 0)) 3350(define-pmacro (misc-null-2) (f-misc-null-2 0)) 3351(define-pmacro (misc-null-3) (f-misc-null-3 0)) 3352(define-pmacro (misc-null-4) (f-misc-null-4 0)) 3353(define-pmacro (misc-null-5) (f-misc-null-5 0)) 3354(define-pmacro (misc-null-6) (f-misc-null-6 0)) 3355(define-pmacro (misc-null-7) (f-misc-null-7 0)) 3356(define-pmacro (misc-null-8) (f-misc-null-8 0)) 3357(define-pmacro (misc-null-9) (f-misc-null-9 0)) 3358(define-pmacro (misc-null-10) (f-misc-null-10 0)) 3359(define-pmacro (misc-null-11) (f-misc-null-11 0)) 3360 3361(define-pmacro (LRA-null) (f-LRA-null 0)) 3362(define-pmacro (TLBPR-null) (f-TLBPR-null 0)) 3363 3364(define-pmacro (LI-on) (f-LI-on 1)) 3365(define-pmacro (LI-off) (f-LI-off 0)) 3366 3367; Instruction definitions. 3368; 3369; Notes: 3370; - dni is short for "define-normal-instruction" 3371; - Macros are used to represent each insn format. These should be used as much 3372; as possible unless an insn has exceptional behaviour 3373; 3374 3375; Commonly used Macros 3376; 3377; Specific registers 3378; 3379 3380; Integer condition code manipulation 3381; 3382(define-pmacro (set-z-and-n icc x) 3383 (if (eq x 0) 3384 (set icc (or (and icc #x7) #x4)) 3385 (if (lt x 0) 3386 (set icc (or (and icc #xb) #x8)) 3387 (set icc (and icc #x3)))) 3388) 3389 3390(define-pmacro (set-n icc val) 3391 (if (eq val 0) 3392 (set icc (and icc #x7)) 3393 (set icc (or icc #x8))) 3394) 3395 3396(define-pmacro (set-z icc val) 3397 (if (eq val 0) 3398 (set icc (and icc #xb)) 3399 (set icc (or icc #x4))) 3400) 3401 3402(define-pmacro (set-v icc val) 3403 (if (eq val 0) 3404 (set icc (and icc #xd)) 3405 (set icc (or icc #x2))) 3406) 3407 3408(define-pmacro (set-c icc val) 3409 (if (eq val 0) 3410 (set icc (and icc #xe)) 3411 (set icc (or icc #x1))) 3412) 3413 3414(define-pmacro (nbit icc) 3415 (trunc BI (srl (and icc #x8) 3)) 3416) 3417 3418(define-pmacro (zbit icc) 3419 (trunc BI (srl (and icc #x4) 2)) 3420) 3421 3422(define-pmacro (vbit icc) 3423 (trunc BI (srl (and icc #x2) 1)) 3424) 3425 3426(define-pmacro (cbit icc) 3427 (trunc BI (and icc #x1)) 3428) 3429 3430(define-pmacro (ebit icc) 3431 (trunc BI (srl (and icc #x8) 3)) 3432) 3433 3434(define-pmacro (lbit icc) 3435 (trunc BI (srl (and icc #x4) 2)) 3436) 3437 3438(define-pmacro (gbit icc) 3439 (trunc BI (srl (and icc #x2) 1)) 3440) 3441 3442(define-pmacro (ubit icc) 3443 (trunc BI (and icc #x1)) 3444) 3445 3446; FRV insns 3447; 3448; 3449; Format: INT, Logic, Shift r-r 3450; 3451(define-pmacro (int-logic-r-r name operation op ope comment) 3452 (dni name 3453 (comment) 3454 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3455 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3456 (.str name "$pack $GRi,$GRj,$GRk") 3457 (+ pack GRk op GRi (ICCi_1-null) ope GRj) 3458 (set GRk (operation GRi GRj)) 3459 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3460 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3461 ) 3462) 3463 3464(int-logic-r-r add add OP_00 OPE2_00 "add reg/reg") 3465(int-logic-r-r sub sub OP_00 OPE2_04 "sub reg/reg") 3466(int-logic-r-r and and OP_01 OPE2_00 "and reg/reg") 3467(int-logic-r-r or or OP_01 OPE2_02 "or reg/reg") 3468(int-logic-r-r xor xor OP_01 OPE2_04 "xor reg/reg") 3469 3470(dni not 3471 ("not") 3472 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3473 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3474 ("not$pack $GRj,$GRk") 3475 (+ pack GRk OP_01 (rs-null) (ICCi_1-null) OPE2_06 GRj) 3476 (set GRk (inv GRj)) 3477 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3478 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3479) 3480 3481(dni sdiv 3482 "signed division" 3483 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 3484 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3485 "sdiv$pack $GRi,$GRj,$GRk" 3486 (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0E GRj) 3487 (sequence () 3488 (c-call VOID "@cpu@_signed_integer_divide" 3489 GRi GRj (index-of GRk) 0) 3490 (clobber GRk)) 3491 ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) 3492 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3493) 3494 3495(dni nsdiv 3496 "non excepting signed division" 3497 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING 3498 (MACH simple,tomcat,fr500,fr550,frv)) 3499 "nsdiv$pack $GRi,$GRj,$GRk" 3500 (+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0E GRj) 3501 (sequence () 3502 (c-call VOID "@cpu@_signed_integer_divide" 3503 GRi GRj (index-of GRk) 1) 3504 (clobber GRk)) 3505 ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3506) 3507 3508(dni udiv 3509 "unsigned division reg/reg" 3510 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 3511 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3512 "udiv$pack $GRi,$GRj,$GRk" 3513 (+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0F GRj) 3514 (sequence () 3515 (c-call VOID "@cpu@_unsigned_integer_divide" 3516 GRi GRj (index-of GRk) 0) 3517 (clobber GRk)) 3518 ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) 3519 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3520) 3521 3522(dni nudiv 3523 "non excepting unsigned division" 3524 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING 3525 (MACH simple,tomcat,fr500,fr550,frv)) 3526 "nudiv$pack $GRi,$GRj,$GRk" 3527 (+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0F GRj) 3528 (sequence () 3529 (c-call VOID "@cpu@_unsigned_integer_divide" 3530 GRi GRj (index-of GRk) 1) 3531 (clobber GRk)) 3532 ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3533) 3534 3535; Multiplication 3536; 3537(define-pmacro (multiply-r-r name signop op ope comment) 3538 (dni name 3539 (comment) 3540 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 3541 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3542 (.str name "$pack $GRi,$GRj,$GRdoublek") 3543 (+ pack GRdoublek op GRi (ICCi_1-null) ope GRj) 3544 (set GRdoublek (mul DI (signop DI GRi) (signop DI GRj))) 3545 ((fr400 (unit u-imul)) (fr450 (unit u-imul)) 3546 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 3547 ) 3548) 3549 3550(multiply-r-r smul ext OP_00 OPE2_08 "signed multiply reg/reg") 3551(multiply-r-r umul zext OP_00 OPE2_0A "unsigned multiply reg/reg") 3552 3553; Multiplication with integer accumulator IACC 3554; 3555 3556(define-pmacro (iacc-set value) 3557 (set (reg h-iacc0 0) value)) 3558 3559(define-pmacro (iacc-add value) 3560 (set (reg h-iacc0 0) 3561 (cond DI 3562 ((andif (andif (gt value 0) (gt (reg h-iacc0 0) 0)) 3563 (lt (sub DI #x7fffffffffffffff value) (reg h-iacc0 0))) 3564 ; Positive overflow 3565 (const DI #x7fffffffffffffff)) 3566 ((andif (andif (lt value 0) (lt (reg h-iacc0 0) 0)) 3567 (gt (sub DI #x8000000000000000 value) (reg h-iacc0 0))) 3568 ; Negative overflow 3569 (const DI #x8000000000000000)) 3570 (else 3571 (add DI (reg h-iacc0 0) value)))) 3572) 3573 3574(define-pmacro (iacc-sub value) 3575 (set (reg h-iacc0 0) 3576 (cond DI 3577 ((andif (andif (lt value 0) (gt (reg h-iacc0 0) 0)) 3578 (lt (add DI #x7fffffffffffffff value) (reg h-iacc0 0))) 3579 ; Positive overflow 3580 (const DI #x7fffffffffffffff)) 3581 ((andif (andif (gt value 0) (lt (reg h-iacc0 0) 0)) 3582 (gt (add DI #x8000000000000000 value) (reg h-iacc0 0))) 3583 ; Negative overflow 3584 (const DI #x8000000000000000)) 3585 (else 3586 (sub DI (reg h-iacc0 0) value)))) 3587) 3588 3589(define-pmacro (iacc-multiply-r-r name operation op ope comment) 3590 (dni name 3591 (comment) 3592 ((UNIT IACC) (MACH fr400,fr450) 3593 (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) 3594 (.str name "$pack $GRi,$GRj") 3595 (+ pack (rd-null) op GRi ope GRj) 3596 ((.sym iacc- operation) (mul DI (ext DI GRi) (ext DI GRj))) 3597 ((fr400 (unit u-integer)) (fr450 (unit u-integer))) 3598 ) 3599) 3600 3601(iacc-multiply-r-r smu set OP_46 OPE1_05 "Signed multiply reg/reg/iacc") 3602(iacc-multiply-r-r smass add OP_46 OPE1_06 "Signed multiply/add reg/reg/iacc") 3603(iacc-multiply-r-r smsss sub OP_46 OPE1_07 "Signed multiply/sub reg/reg/iacc") 3604 3605(define-pmacro (int-shift-r-r name op ope comment) 3606 (dni name 3607 (comment) 3608 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3609 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3610 (.str name "$pack $GRi,$GRj,$GRk") 3611 (+ pack GRk op GRi (ICCi_1-null) ope GRj) 3612 (set GRk (name GRi (and GRj #x1f))) 3613 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3614 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3615 ) 3616) 3617 3618(int-shift-r-r sll OP_01 OPE2_08 "shift left logical reg/reg") 3619(int-shift-r-r srl OP_01 OPE2_0A "shift right logical reg/reg") 3620(int-shift-r-r sra OP_01 OPE2_0C "shift right arith reg/reg") 3621 3622(dni slass 3623 "shift left arith reg/reg with saturation" 3624 ((UNIT IALL) (MACH fr400,fr450) 3625 (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) 3626 "slass$pack $GRi,$GRj,$GRk" 3627 (+ pack GRk OP_46 GRi OPE1_02 GRj) 3628 (set GRk (c-call SI "@cpu@_shift_left_arith_saturate" GRi GRj)) 3629 () 3630) 3631 3632(dni scutss 3633 "Integer accumulator cut with saturation" 3634 ((UNIT I0) (MACH fr400,fr450) 3635 (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) 3636 "scutss$pack $GRj,$GRk" 3637 (+ pack GRk OP_46 (rs-null) OPE1_04 GRj) 3638 (set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj)) 3639 () 3640) 3641 3642(define-pmacro (scan-semantics arg1 arg2 targ) 3643 (sequence ((WI tmp1) (WI tmp2)) 3644 (set tmp1 arg1) 3645 (set tmp2 (sra arg2 1)) 3646 (set targ (c-call WI "@cpu@_scan_result" (xor tmp1 tmp2)))) 3647) 3648 3649(dni scan 3650 "scan" 3651 ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3652 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3653 "scan$pack $GRi,$GRj,$GRk" 3654 (+ pack GRk OP_0B GRi (ICCi_1-null) OPE2_00 GRj) 3655 (scan-semantics GRi GRj GRk) 3656 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3657 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3658) 3659 3660; Format: conditional INT, Logic, Shift r-r 3661; 3662(define-pmacro (conditional-int-logic name operation op ope comment) 3663 (dni name 3664 (comment) 3665 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3666 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3667 (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") 3668 (+ pack GRk op GRi CCi cond ope GRj) 3669 (if (eq CCi (or cond 2)) 3670 (set GRk (operation GRi GRj))) 3671 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3672 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3673 ) 3674) 3675 3676(conditional-int-logic cadd add OP_58 OPE4_0 "conditional add") 3677(conditional-int-logic csub sub OP_58 OPE4_1 "conditional sub") 3678(conditional-int-logic cand and OP_5A OPE4_0 "conditional and") 3679(conditional-int-logic cor or OP_5A OPE4_1 "conditional or") 3680(conditional-int-logic cxor xor OP_5A OPE4_2 "conditional xor") 3681 3682(dni cnot 3683 "conditional not" 3684 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3685 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3686 "cnot$pack $GRj,$GRk,$CCi,$cond" 3687 (+ pack GRk OP_5A (rs-null) CCi cond OPE4_3 GRj) 3688 (if (eq CCi (or cond 2)) 3689 (set GRk (inv GRj))) 3690 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3691 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3692) 3693 3694(dni csmul 3695 "conditional signed multiply" 3696 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 3697 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3698 "csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond" 3699 (+ pack GRdoublek OP_58 GRi CCi cond OPE4_2 GRj) 3700 (if (eq CCi (or cond 2)) 3701 (set GRdoublek (mul DI (ext DI GRi) (ext DI GRj)))) 3702 ((fr400 (unit u-imul)) (fr450 (unit u-imul)) 3703 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 3704) 3705 3706(dni csdiv 3707 "conditional signed division" 3708 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 3709 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3710 "csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond" 3711 (+ pack GRk OP_58 GRi CCi cond OPE4_3 GRj) 3712 (if (eq CCi (or cond 2)) 3713 (sequence () 3714 (c-call VOID "@cpu@_signed_integer_divide" 3715 GRi GRj (index-of GRk) 0) 3716 (clobber GRk))) 3717 ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) 3718 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3719) 3720 3721(dni cudiv 3722 "conditional unsigned division" 3723 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 3724 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3725 "cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond" 3726 (+ pack GRk OP_59 GRi CCi cond OPE4_3 GRj) 3727 (if (eq CCi (or cond 2)) 3728 (sequence () 3729 (c-call VOID "@cpu@_unsigned_integer_divide" 3730 GRi GRj (index-of GRk) 0) 3731 (clobber GRk))) 3732 ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) 3733 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 3734) 3735 3736(define-pmacro (conditional-shift name operation op ope comment) 3737 (dni name 3738 (comment) 3739 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3740 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3741 (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") 3742 (+ pack GRk op GRi CCi cond ope GRj) 3743 (if (eq CCi (or cond 2)) 3744 (set GRk (operation GRi (and GRj #x1f)))) 3745 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3746 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3747 ) 3748) 3749 3750(conditional-shift csll sll OP_5C OPE4_0 "conditional shift left logical") 3751(conditional-shift csrl srl OP_5C OPE4_1 "conditional shift right logical") 3752(conditional-shift csra sra OP_5C OPE4_2 "conditional shift right arith") 3753 3754(dni cscan 3755 "conditional scan" 3756 ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3757 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3758 "cscan$pack $GRi,$GRj,$GRk,$CCi,$cond" 3759 (+ pack GRk OP_65 GRi CCi cond OPE4_3 GRj) 3760 (if (eq CCi (or cond 2)) 3761 (scan-semantics GRi GRj GRk)) 3762 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3763 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3764) 3765 3766; Format: INT, Logic, Shift, cc r-r 3767; 3768(define-pmacro (int-arith-cc-semantics operation icc) 3769 (sequence ((BI tmp) (QI cc) (SI result)) 3770 (set cc icc) 3771 (set tmp ((.sym operation -oflag) GRi GRj (const 0))) 3772 (set-v cc tmp) 3773 (set tmp ((.sym operation -cflag) GRi GRj (const 0))) 3774 (set-c cc tmp) 3775 (set result (operation GRi GRj)) 3776 (set-z-and-n cc result) 3777 (set GRk result) 3778 (set icc cc)) 3779) 3780 3781(define-pmacro (int-arith-cc-r-r name operation op ope comment) 3782 (dni name 3783 (comment) 3784 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3785 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3786 (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") 3787 (+ pack GRk op GRi ICCi_1 ope GRj) 3788 (int-arith-cc-semantics operation ICCi_1) 3789 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3790 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3791 ) 3792) 3793 3794(int-arith-cc-r-r addcc add OP_00 OPE2_01 "add reg/reg, set icc") 3795(int-arith-cc-r-r subcc sub OP_00 OPE2_05 "sub reg/reg, set icc") 3796 3797(define-pmacro (int-logic-cc-semantics op icc) 3798 (sequence ((SI tmp)) 3799 (set tmp (op GRi GRj)) 3800 (set GRk tmp) 3801 (set-z-and-n icc tmp)) 3802) 3803 3804(define-pmacro (int-logic-cc-r-r name op ope comment) 3805 (dni (.sym name cc) 3806 (comment) 3807 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3808 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3809 (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1") 3810 (+ pack GRk op GRi ICCi_1 ope GRj) 3811 (int-logic-cc-semantics name ICCi_1) 3812 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3813 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3814 ) 3815) 3816 3817(int-logic-cc-r-r and OP_01 OPE2_01 "and reg/reg, set icc") 3818(int-logic-cc-r-r or OP_01 OPE2_03 "or reg/reg, set icc") 3819(int-logic-cc-r-r xor OP_01 OPE2_05 "xor reg/reg, set icc") 3820 3821(define-pmacro (int-shift-cc-semantics op l-r icc) 3822 (sequence ((WI shift) (SI tmp) (QI cc)) 3823 (set shift (and GRj #x1f)) 3824 (set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r) 3825 GRi shift icc)) 3826 (set tmp (op GRi shift)) 3827 (set GRk tmp) 3828 (set-z-and-n cc tmp) 3829 (set icc cc)) 3830) 3831 3832(define-pmacro (int-shift-cc-r-r name l-r op ope comment) 3833 (dni (.sym name cc) 3834 (comment) 3835 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3836 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3837 (.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1") 3838 (+ pack GRk op GRi ICCi_1 ope GRj) 3839 (int-shift-cc-semantics name l-r ICCi_1) 3840 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3841 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3842 ) 3843) 3844 3845(int-shift-cc-r-r sll left OP_01 OPE2_09 "shift left logical reg/reg,set icc") 3846(int-shift-cc-r-r srl right OP_01 OPE2_0B "shift right logical reg/reg,set icc") 3847(int-shift-cc-r-r sra right OP_01 OPE2_0D "shift right arith reg/reg,set icc") 3848 3849(define-pmacro (multiply-cc-semantics signop arg1 arg2 targ icc) 3850 (sequence ((DI tmp) (QI cc)) 3851 (set cc icc) 3852 (set tmp (mul DI (signop DI arg1) (signop DI arg2))) 3853 (set-n cc (srl DI tmp 63)) 3854 (set-z cc (eq tmp 0)) 3855 (set targ tmp) 3856 (set icc cc)) 3857) 3858 3859(define-pmacro (multiply-cc-r-r name signop op ope comment) 3860 (dni name 3861 (comment) 3862 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 3863 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3864 (.str name "$pack $GRi,$GRj,$GRdoublek,$ICCi_1") 3865 (+ pack GRdoublek op GRi ICCi_1 ope GRj) 3866 (multiply-cc-semantics signop GRi GRj GRdoublek ICCi_1) 3867 ((fr400 (unit u-imul)) (fr450 (unit u-imul)) 3868 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 3869 ) 3870) 3871 3872(multiply-cc-r-r smulcc ext OP_00 OPE2_09 "signed multiply reg/reg") 3873(multiply-cc-r-r umulcc zext OP_00 OPE2_0B "unsigned multiply reg/reg") 3874 3875 3876; Format: conditional INT, Logic, Shift, cc r-r 3877; 3878(define-pmacro (conditional-int-arith-cc name operation op ope comment) 3879 (dni name 3880 (comment) 3881 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3882 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3883 (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") 3884 (+ pack GRk op GRi CCi cond ope GRj) 3885 (if (eq CCi (or cond 2)) 3886 (int-arith-cc-semantics operation 3887 (reg h-iccr (and (index-of CCi) 3)))) 3888 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3889 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3890 ) 3891) 3892 3893(conditional-int-arith-cc caddcc add OP_59 OPE4_0 "add, set icc") 3894(conditional-int-arith-cc csubcc sub OP_59 OPE4_1 "sub, set icc") 3895 3896(dni csmulcc 3897 "conditional signed multiply and set condition code" 3898 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 3899 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3900 "csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond" 3901 (+ pack GRdoublek OP_59 GRi CCi cond OPE4_2 GRj) 3902 (if (eq CCi (or cond 2)) 3903 (multiply-cc-semantics ext GRi GRj GRdoublek 3904 (reg h-iccr (and (index-of CCi) 3)))) 3905 ((fr400 (unit u-imul)) (fr450 (unit u-imul)) 3906 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 3907) 3908 3909(define-pmacro (conditional-int-logic-cc name operation op ope comment) 3910 (dni name 3911 (comment) 3912 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3913 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3914 (.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond") 3915 (+ pack GRk op GRi CCi cond ope GRj) 3916 (if (eq CCi (or cond 2)) 3917 (int-logic-cc-semantics operation 3918 (reg h-iccr (and (index-of CCi) 3)))) 3919 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3920 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3921 ) 3922) 3923 3924(conditional-int-logic-cc candcc and OP_5B OPE4_0 "conditional and, set icc") 3925(conditional-int-logic-cc corcc or OP_5B OPE4_1 "conditional or , set icc") 3926(conditional-int-logic-cc cxorcc xor OP_5B OPE4_2 "conditional xor, set icc") 3927 3928(define-pmacro (conditional-int-shift-cc name l-r op ope comment) 3929 (dni (.sym c name cc) 3930 (comment) 3931 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3932 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 3933 (.str (.sym c name cc) "$pack $GRi,$GRj,$GRk,$CCi,$cond") 3934 (+ pack GRk op GRi CCi cond ope GRj) 3935 (if (eq CCi (or cond 2)) 3936 (int-shift-cc-semantics name l-r 3937 (reg h-iccr (and (index-of CCi) 3)))) 3938 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3939 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3940 ) 3941) 3942 3943(conditional-int-shift-cc sll left OP_5D OPE4_0 "shift left logical, set icc") 3944(conditional-int-shift-cc srl right OP_5D OPE4_1 "shift right logical, set icc") 3945(conditional-int-shift-cc sra right OP_5D OPE4_2 "shift right arith , set icc") 3946 3947; Add and subtract with carry 3948; 3949(define-pmacro (int-arith-x-r-r name operation op ope comment) 3950 (dni name 3951 (comment) 3952 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3953 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3954 (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") 3955 (+ pack GRk op GRi ICCi_1 ope GRj) 3956 (set GRk ((.sym operation c) GRi GRj (cbit ICCi_1))) 3957 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3958 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3959 ) 3960) 3961 3962(int-arith-x-r-r addx add OP_00 OPE2_02 "Add reg/reg, with carry") 3963(int-arith-x-r-r subx sub OP_00 OPE2_06 "Sub reg/reg, with carry") 3964 3965(define-pmacro (int-arith-x-cc-r-r name operation op ope comment) 3966 (dni name 3967 (comment) 3968 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 3969 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 3970 (.str name "$pack $GRi,$GRj,$GRk,$ICCi_1") 3971 (+ pack GRk op GRi ICCi_1 ope GRj) 3972 (sequence ((WI tmp) (QI cc)) 3973 (set cc ICCi_1) 3974 (set tmp ((.sym operation c) GRi GRj (cbit cc))) 3975 (set-v cc ((.sym operation -oflag) GRi GRj (cbit cc))) 3976 (set-c cc ((.sym operation -cflag) GRi GRj (cbit cc))) 3977 (set-z-and-n cc tmp) 3978 (set GRk tmp) 3979 (set ICCi_1 cc)) 3980 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 3981 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 3982 ) 3983) 3984 3985(int-arith-x-cc-r-r addxcc add OP_00 OPE2_03 "Add reg/reg, use/set carry") 3986(int-arith-x-cc-r-r subxcc sub OP_00 OPE2_07 "Sub reg/reg, use/set carry") 3987; Add and subtract with saturation 3988; 3989(define-pmacro (int-arith-ss-r-r name operation op ope comment) 3990 (dni name 3991 (comment) 3992 ((UNIT IALL) (MACH fr400,fr450) 3993 (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO) 3994 (.str name "$pack $GRi,$GRj,$GRk") 3995 (+ pack GRk op GRi ope GRj) 3996 (sequence () 3997 (set GRk (operation GRi GRj)) 3998 (if ((.sym operation -oflag) GRi GRj (const 0)) 3999 ; Overflow, saturate. 4000 ; Sign of result will be 4001 ; same as sign of first operand. 4002 (set GRk 4003 (cond SI 4004 ((gt GRi 0) (const #x7fffffff)) 4005 ((lt GRi 0) (const #x80000000)) 4006 (else (const 0))))) 4007 ) 4008 ((fr400 (unit u-integer)) (fr450 (unit u-integer))) 4009 ) 4010) 4011 4012(int-arith-ss-r-r addss add OP_46 OPE1_00 "add reg/reg, with saturation") 4013(int-arith-ss-r-r subss sub OP_46 OPE1_01 "sub reg/reg, with saturation") 4014 4015; Format: INT, Logic, Shift r-simm 4016; 4017(define-pmacro (int-logic-r-simm name operation op comment) 4018 (dni name 4019 (comment) 4020 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4021 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4022 (.str name "$pack $GRi,$s12,$GRk") 4023 (+ pack GRk op GRi s12) 4024 (set GRk (operation GRi s12)) 4025 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4026 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 4027 ) 4028) 4029 4030(int-logic-r-simm addi add OP_10 "add reg/immed") 4031(int-logic-r-simm subi sub OP_14 "sub reg/immed") 4032(int-logic-r-simm andi and OP_20 "and reg/immed") 4033(int-logic-r-simm ori or OP_22 "or reg/immed") 4034(int-logic-r-simm xori xor OP_24 "xor reg/immed") 4035 4036(dni sdivi 4037 "signed division reg/immed" 4038 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 4039 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4040 "sdivi$pack $GRi,$s12,$GRk" 4041 (+ pack GRk OP_1E GRi s12) 4042 (sequence () 4043 (c-call VOID "@cpu@_signed_integer_divide" 4044 GRi s12 (index-of GRk) 0) 4045 (clobber GRk)) 4046 ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) 4047 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 4048) 4049 4050(dni nsdivi 4051 "non excepting signed division reg/immed" 4052 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING 4053 (MACH simple,tomcat,fr500,fr550,frv)) 4054 "nsdivi$pack $GRi,$s12,$GRk" 4055 (+ pack GRk OP_2E GRi s12) 4056 (sequence () 4057 (c-call VOID "@cpu@_signed_integer_divide" 4058 GRi s12 (index-of GRk) 1) 4059 (clobber GRk)) 4060 ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 4061) 4062 4063(dni udivi 4064 "unsigned division reg/immed" 4065 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 4066 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4067 "udivi$pack $GRi,$s12,$GRk" 4068 (+ pack GRk OP_1F GRi s12) 4069 (sequence () 4070 (c-call VOID "@cpu@_unsigned_integer_divide" 4071 GRi s12 (index-of GRk) 0) 4072 (clobber GRk)) 4073 ((fr400 (unit u-idiv)) (fr450 (unit u-idiv)) 4074 (fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 4075) 4076 4077(dni nudivi 4078 "non excepting unsigned division reg/immed" 4079 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING 4080 (MACH simple,tomcat,fr500,fr550,frv)) 4081 "nudivi$pack $GRi,$s12,$GRk" 4082 (+ pack GRk OP_2F GRi s12) 4083 (sequence () 4084 (c-call VOID "@cpu@_unsigned_integer_divide" 4085 GRi s12 (index-of GRk) 1) 4086 (clobber GRk)) 4087 ((fr500 (unit u-idiv)) (fr550 (unit u-idiv))) 4088) 4089 4090(define-pmacro (multiply-r-simm name signop op comment) 4091 (dni name 4092 (comment) 4093 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 4094 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4095 (.str name "$pack $GRi,$s12,$GRdoublek") 4096 (+ pack GRdoublek op GRi s12) 4097 (set GRdoublek (mul DI (signop DI GRi) (signop DI s12))) 4098 ((fr400 (unit u-imul)) (fr450 (unit u-imul)) 4099 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 4100 ) 4101) 4102 4103(multiply-r-simm smuli ext OP_18 "signed multiply reg/immed") 4104(multiply-r-simm umuli zext OP_1A "unsigned multiply reg/immed") 4105 4106(define-pmacro (int-shift-r-simm name op comment) 4107 (dni (.sym name i) 4108 (comment) 4109 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4110 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4111 (.str (.sym name i) "$pack $GRi,$s12,$GRk") 4112 (+ pack GRk op GRi s12) 4113 (set GRk (name GRi (and s12 #x1f))) 4114 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4115 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 4116 ) 4117) 4118 4119(int-shift-r-simm sll OP_28 "shift left logical reg/immed") 4120(int-shift-r-simm srl OP_2A "shift right logical reg/immed") 4121(int-shift-r-simm sra OP_2C "shift right arith reg/immed") 4122 4123(dni scani 4124 "scan immediate" 4125 ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4126 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4127 "scani$pack $GRi,$s12,$GRk" 4128 (+ pack GRk OP_47 GRi s12) 4129 (scan-semantics GRi s12 GRk) 4130 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4131 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 4132) 4133 4134; Format: INT, Logic, Shift cc r-simm 4135; 4136(define-pmacro (int-arith-cc-r-simm name operation op comment) 4137 (dni name 4138 (comment) 4139 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4140 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4141 (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") 4142 (+ pack GRk op GRi ICCi_1 s10) 4143 (sequence ((BI tmp) (QI cc) (SI result)) 4144 (set cc ICCi_1) 4145 (set tmp ((.sym operation -oflag) GRi s10 (const 0))) 4146 (set-v cc tmp) 4147 (set tmp ((.sym operation -cflag) GRi s10 (const 0))) 4148 (set-c cc tmp) 4149 (set result (operation GRi s10)) 4150 (set-z-and-n cc result) 4151 (set GRk result) 4152 (set ICCi_1 cc)) 4153 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4154 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 4155 ) 4156) 4157 4158(int-arith-cc-r-simm addicc add OP_11 "add reg/immed, set icc") 4159(int-arith-cc-r-simm subicc sub OP_15 "sub reg/immed, set icc") 4160 4161(define-pmacro (int-logic-cc-r-simm name op comment) 4162 (dni (.sym name icc) 4163 (comment) 4164 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4165 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4166 (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1") 4167 (+ pack GRk op GRi ICCi_1 s10) 4168 (sequence ((SI tmp)) 4169 (set tmp (name GRi s10)) 4170 (set GRk tmp) 4171 (set-z-and-n ICCi_1 tmp)) 4172 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4173 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 4174 ) 4175) 4176 4177(int-logic-cc-r-simm and OP_21 "and reg/immed, set icc") 4178(int-logic-cc-r-simm or OP_23 "or reg/immed, set icc") 4179(int-logic-cc-r-simm xor OP_25 "xor reg/immed, set icc") 4180 4181(define-pmacro (multiply-cc-r-simm name signop op comment) 4182 (dni name 4183 (comment) 4184 ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) 4185 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4186 (.str name "$pack $GRi,$s10,$GRdoublek,$ICCi_1") 4187 (+ pack GRdoublek op GRi ICCi_1 s10) 4188 (multiply-cc-semantics signop GRi s10 GRdoublek ICCi_1) 4189 ((fr400 (unit u-imul)) (fr450 (unit u-imul)) 4190 (fr500 (unit u-imul)) (fr550 (unit u-imul))) 4191 ) 4192) 4193 4194(multiply-cc-r-simm smulicc ext OP_19 "signed multiply reg/immed") 4195(multiply-cc-r-simm umulicc zext OP_1B "unsigned multiply reg/immed") 4196 4197(define-pmacro (int-shift-cc-r-simm name l-r op comment) 4198 (dni (.sym name icc) 4199 (comment) 4200 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4201 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4202 (.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1") 4203 (+ pack GRk op GRi ICCi_1 s10) 4204 (sequence ((WI shift) (SI tmp) (QI cc)) 4205 (set shift (and s10 #x1f)) 4206 (set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r) 4207 GRi shift ICCi_1)) 4208 (set tmp (name GRi shift)) 4209 (set GRk tmp) 4210 (set-z-and-n cc tmp) 4211 (set ICCi_1 cc)) 4212 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4213 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 4214 ) 4215) 4216 4217(int-shift-cc-r-simm sll left OP_29 "shift left logical reg/immed, set icc") 4218(int-shift-cc-r-simm srl right OP_2B "shift right logical reg/immed, set icc") 4219(int-shift-cc-r-simm sra right OP_2D "shift right arith reg/immed, set icc") 4220 4221(define-pmacro (int-arith-x-r-simm name operation op comment) 4222 (dni name 4223 (comment) 4224 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4225 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4226 (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") 4227 (+ pack GRk op GRi ICCi_1 s10) 4228 (set GRk ((.sym operation c) GRi s10 (cbit ICCi_1))) 4229 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4230 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 4231 ) 4232) 4233 4234(int-arith-x-r-simm addxi add OP_12 "Add reg/immed, with carry") 4235(int-arith-x-r-simm subxi sub OP_16 "Sub reg/immed, with carry") 4236 4237(define-pmacro (int-arith-x-cc-r-simm name operation op comment) 4238 (dni name 4239 (comment) 4240 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4241 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4242 (.str name "$pack $GRi,$s10,$GRk,$ICCi_1") 4243 (+ pack GRk op GRi ICCi_1 s10) 4244 (sequence ((WI tmp) (QI cc)) 4245 (set cc ICCi_1) 4246 (set tmp ((.sym operation c) GRi s10 (cbit cc))) 4247 (set-v cc ((.sym operation -oflag) GRi s10 (cbit cc))) 4248 (set-c cc ((.sym operation -cflag) GRi s10 (cbit cc))) 4249 (set-z-and-n cc tmp) 4250 (set GRk tmp) 4251 (set ICCi_1 cc)) 4252 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4253 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 4254 ) 4255) 4256 4257(int-arith-x-cc-r-simm addxicc add OP_13 "Add reg/immed, with carry") 4258(int-arith-x-cc-r-simm subxicc sub OP_17 "Sub reg/immed, with carry") 4259 4260; Byte compare insns 4261 4262(dni cmpb 4263 "Compare bytes" 4264 ((UNIT IALL) (MACH fr400,fr450,fr550) (FR550-MAJOR I-1) 4265 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4266 "cmpb$pack $GRi,$GRj,$ICCi_1" 4267 (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0C GRj) 4268 (sequence ((QI cc)) 4269 (set-n cc (eq (and GRi #xff000000) (and GRj #xff000000))) 4270 (set-z cc (eq (and GRi #x00ff0000) (and GRj #x00ff0000))) 4271 (set-v cc (eq (and GRi #x0000ff00) (and GRj #x0000ff00))) 4272 (set-c cc (eq (and GRi #x000000ff) (and GRj #x000000ff))) 4273 (set ICCi_1 cc)) 4274 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4275 (fr550 (unit u-integer))) 4276) 4277 4278(dni cmpba 4279 "OR of Compare bytes" 4280 ((UNIT IALL) (MACH fr400,fr450,fr550) (FR550-MAJOR I-1) 4281 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4282 "cmpba$pack $GRi,$GRj,$ICCi_1" 4283 (+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0D GRj) 4284 (sequence ((QI cc)) 4285 (set cc 0) 4286 (set-c cc 4287 (orif (eq (and GRi #xff000000) (and GRj #xff000000)) 4288 (orif (eq (and GRi #x00ff0000) (and GRj #x00ff0000)) 4289 (orif (eq (and GRi #x0000ff00) 4290 (and GRj #x0000ff00)) 4291 (eq (and GRi #x000000ff) 4292 (and GRj #x000000ff)))))) 4293 (set ICCi_1 cc)) 4294 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4295 (fr550 (unit u-integer))) 4296) 4297 4298; Format: Load immediate 4299; 4300(dni setlo 4301 "set low order bits" 4302 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4303 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4304 "setlo$pack $ulo16,$GRklo" 4305 (+ pack GRk OP_3D (misc-null-4) u16) 4306 (set GRklo u16) 4307 ((fr400 (unit u-set-hilo)) (fr450 (unit u-set-hilo)) 4308 (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo))) 4309) 4310 4311(dni sethi 4312 "set high order bits" 4313 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4314 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4315 "sethi$pack $uhi16,$GRkhi" 4316 (+ pack GRkhi OP_3E (misc-null-4) u16) 4317 (set GRkhi u16) 4318 ((fr400 (unit u-set-hilo)) (fr450 (unit u-set-hilo)) 4319 (fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo))) 4320) 4321 4322(dni setlos 4323 "set low order bits and extend sign" 4324 ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) 4325 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 4326 "setlos$pack $slo16,$GRk" 4327 (+ pack GRk OP_3F (misc-null-4) s16) 4328 (set GRk s16) 4329 ((fr400 (unit u-integer)) (fr450 (unit u-integer)) 4330 (fr500 (unit u-integer)) (fr550 (unit u-integer))) 4331) 4332 4333(define-pmacro (load-gr-r name mode op ope comment ann) 4334 (dni name 4335 (comment) 4336 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 4337 (FR400-MAJOR I-2) (FR450-MAJOR I-2)) 4338 (.str name "$pack " ann "($GRi,$GRj),$GRk") 4339 (+ pack GRk op GRi ope GRj) 4340 (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) 4341 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 4342 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4343 ) 4344) 4345 4346(dann ldann "ld annotation" SI "ld_annotation" "at") 4347 4348(load-gr-r ldsb QI OP_02 OPE1_00 "Load signed byte" "@") 4349(load-gr-r ldub UQI OP_02 OPE1_01 "Load unsigned byte" "@") 4350(load-gr-r ldsh HI OP_02 OPE1_02 "Load signed half" "@") 4351(load-gr-r lduh UHI OP_02 OPE1_03 "Load unsigned half" "@") 4352(load-gr-r ld SI OP_02 OPE1_04 "Load word" "$ldann") 4353 4354(define-pmacro (load-fr-r name mode op ope comment) 4355 (dni name 4356 (comment) 4357 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 4358 (FR400-MAJOR I-2) (FR450-MAJOR I-2) FR-ACCESS) 4359 (.str name "$pack @($GRi,$GRj),$FRintk") 4360 (+ pack FRintk op GRi ope GRj) 4361 (set FRintk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) 4362 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 4363 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4364 ) 4365) 4366 4367(load-fr-r ldbf UQI OP_02 OPE1_08 "Load byte float") 4368(load-fr-r ldhf UHI OP_02 OPE1_09 "Load half float") 4369(load-fr-r ldf SI OP_02 OPE1_0A "Load word float") 4370 4371(define-pmacro (load-cpr-r name mode op ope reg attr comment) 4372 (dni name 4373 (comment) 4374 ((UNIT LOAD) (FR500-MAJOR I-2) attr) 4375 (.str name "$pack @($GRi,$GRj),$" reg "k") 4376 (+ pack (.sym reg k) op GRi ope GRj) 4377 (set (.sym reg k) 4378 (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj))) 4379 () 4380 ) 4381) 4382 4383(load-cpr-r ldc SI OP_02 OPE1_0D CPR (MACH frv) "Load coprocessor word") 4384 4385; These correspond to enumerators in frv-sim.h 4386(define-pmacro (ne-UQI-size) 0) 4387(define-pmacro (ne-QI-size) 1) 4388(define-pmacro (ne-UHI-size) 2) 4389(define-pmacro (ne-HI-size) 3) 4390(define-pmacro (ne-SI-size) 4) 4391(define-pmacro (ne-DI-size) 5) 4392(define-pmacro (ne-XI-size) 6) 4393 4394(define-pmacro (ne-load-semantics base dispix targ idisp size is_float action) 4395 (sequence ((BI do_op)) 4396 (set do_op 4397 (c-call BI "@cpu@_check_non_excepting_load" 4398 (index-of base) dispix (index-of targ) 4399 idisp size is_float)) 4400 (if do_op action)) 4401) 4402 4403(define-pmacro (ne-load-gr-r name mode op ope size comment) 4404 (dni name 4405 (comment) 4406 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING 4407 (MACH simple,tomcat,fr500,fr550,frv)) 4408 (.str name "$pack @($GRi,$GRj),$GRk") 4409 (+ pack GRk op GRi ope GRj) 4410 (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 4411 (set GRk 4412 (c-call mode (.str "@cpu@_read_mem_" mode) 4413 pc (add GRi GRj)))) 4414 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4415 ) 4416) 4417 4418(ne-load-gr-r nldsb QI OP_02 OPE1_20 (ne-QI-size) "Load signed byte") 4419(ne-load-gr-r nldub UQI OP_02 OPE1_21 (ne-UQI-size) "Load unsigned byte") 4420(ne-load-gr-r nldsh HI OP_02 OPE1_22 (ne-HI-size) "Load signed half") 4421(ne-load-gr-r nlduh UHI OP_02 OPE1_23 (ne-UHI-size) "Load unsigned half") 4422(ne-load-gr-r nld SI OP_02 OPE1_24 (ne-SI-size) "Load word") 4423 4424(define-pmacro (ne-load-fr-r name mode op ope size comment) 4425 (dni name 4426 (comment) 4427 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS 4428 (MACH simple,tomcat,fr500,fr550,frv)) 4429 (.str name "$pack @($GRi,$GRj),$FRintk") 4430 (+ pack FRintk op GRi ope GRj) 4431 (ne-load-semantics GRi (index-of GRj) FRintk 0 size 1 4432 (set FRintk 4433 (c-call mode (.str "@cpu@_read_mem_" mode) 4434 pc (add GRi GRj)))) 4435 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4436 ) 4437) 4438 4439(ne-load-fr-r nldbf UQI OP_02 OPE1_28 (ne-UQI-size) "Load byte float") 4440(ne-load-fr-r nldhf UHI OP_02 OPE1_29 (ne-UHI-size) "Load half float") 4441(ne-load-fr-r nldf SI OP_02 OPE1_2A (ne-SI-size) "Load word float") 4442 4443; Semantics for a load-double insn 4444; 4445(define-pmacro (load-double-semantics not_gr mode regtype address arg) 4446 (if (orif not_gr (ne (index-of (.sym regtype doublek)) 0)) 4447 (sequence () 4448 (set address (add GRi arg)) 4449 (set (.sym regtype doublek) 4450 (c-call mode (.str "@cpu@_read_mem_" mode) pc address)))) 4451) 4452 4453(define-pmacro (load-double-r-r 4454 name not_gr mode op ope regtype attr profile comment ann) 4455 (dni name 4456 (comment) 4457 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 4458 (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) 4459 (.str name "$pack " ann "($GRi,$GRj),$" regtype "doublek") 4460 (+ pack (.sym regtype doublek) op GRi ope GRj) 4461 (sequence ((WI address)) 4462 (load-double-semantics not_gr mode regtype address GRj)) 4463 profile 4464 ) 4465) 4466 4467(dann lddann "ldd annotation" SI "ldd_annotation" "at") 4468 4469(load-double-r-r ldd 0 DI OP_02 OPE1_05 GR NA 4470 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 4471 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4472 "Load double word" "$lddann") 4473(load-double-r-r lddf 1 DF OP_02 OPE1_0B FR FR-ACCESS 4474 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 4475 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4476 "Load double float" "@") 4477(load-double-r-r lddc 1 DI OP_02 OPE1_0E CPR (MACH frv) () 4478 "Load coprocessor double" "@") 4479 4480(define-pmacro (ne-load-double-r-r 4481 name not_gr mode op ope regtype size is_float attr profile 4482 comment) 4483 (dni name 4484 (comment) 4485 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr 4486 (MACH simple,tomcat,fr500,fr550,frv)) 4487 (.str name "$pack @($GRi,$GRj),$" regtype "doublek") 4488 (+ pack (.sym regtype doublek) op GRi ope GRj) 4489 (sequence ((WI address)) 4490 (ne-load-semantics GRi (index-of GRj) (.sym regtype doublek) 4491 0 size is_float 4492 (load-double-semantics not_gr mode 4493 regtype 4494 address GRj))) 4495 profile 4496 ) 4497) 4498 4499(ne-load-double-r-r nldd 0 DI OP_02 OPE1_25 GR (ne-DI-size) 0 NA 4500 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") 4501(ne-load-double-r-r nlddf 1 DF OP_02 OPE1_2B FR (ne-DI-size) 1 FR-ACCESS 4502 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float") 4503 4504; Semantics for a load-quad insn 4505; 4506(define-pmacro (load-quad-semantics regtype address arg) 4507 (sequence () 4508 (set address (add GRi arg)) 4509 (c-call VOID (.str "@cpu@_load_quad_" regtype) 4510 pc address (index-of (.sym regtype k)))) 4511) 4512 4513(define-pmacro (load-quad-r-r name op ope regtype attr profile comment) 4514 (dni name 4515 (comment) 4516 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) 4517 (.str name "$pack @($GRi,$GRj),$" regtype "k") 4518 (+ pack (.sym regtype k) op GRi ope GRj) 4519 (sequence ((WI address)) 4520 (load-quad-semantics regtype address GRj)) 4521 ; TODO regtype-k not referenced for profiling 4522 profile 4523 ) 4524) 4525 4526(load-quad-r-r ldq OP_02 OPE1_06 GR NA ((fr500 (unit u-gr-load))) 4527 "Load quad word") 4528(load-quad-r-r ldqf OP_02 OPE1_0C FRint FR-ACCESS ((fr500 (unit u-fr-load))) 4529 "Load quad float") 4530(load-quad-r-r ldqc OP_02 OPE1_0F CPR NA () "Load coprocessor quad") 4531 4532(define-pmacro (ne-load-quad-r-r 4533 name op ope regtype size is_float attr profile comment) 4534 (dni name 4535 (comment) 4536 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING attr) 4537 (.str name "$pack @($GRi,$GRj),$" regtype "k") 4538 (+ pack (.sym regtype k) op GRi ope GRj) 4539 (sequence ((WI address)) 4540 (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 4541 0 size is_float 4542 (load-quad-semantics regtype address GRj))) 4543 ; TODO regtype-k not referenced for profiling 4544 profile 4545 ) 4546) 4547 4548(ne-load-quad-r-r nldq OP_02 OPE1_26 GR (ne-XI-size) 0 NA 4549 ((fr500 (unit u-gr-load))) "Load quad word") 4550(ne-load-quad-r-r nldqf OP_02 OPE1_2C FRint (ne-XI-size) 1 FR-ACCESS 4551 ((fr500 (unit u-fr-load))) "Load quad float") 4552 4553(define-pmacro (load-gr-u-semantics mode) 4554 (sequence ((UWI address)) 4555 (set address (add GRi GRj)) 4556 (set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc address)) 4557 (if (ne (index-of GRi) (index-of GRk)) 4558 (sequence () 4559 (set GRi address) 4560 (c-call VOID "@cpu@_force_update")))) 4561) 4562 4563(define-pmacro (load-gr-u name mode op ope comment) 4564 (dni name 4565 (comment) 4566 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 4567 (FR400-MAJOR I-2) (FR450-MAJOR I-2)) 4568 (.str name "$pack @($GRi,$GRj),$GRk") 4569 (+ pack GRk op GRi ope GRj) 4570 (load-gr-u-semantics mode) 4571 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 4572 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4573 ) 4574) 4575 4576(load-gr-u ldsbu QI OP_02 OPE1_10 "Load signed byte, update index") 4577(load-gr-u ldubu UQI OP_02 OPE1_11 "Load unsigned byte, update index") 4578(load-gr-u ldshu HI OP_02 OPE1_12 "Load signed half, update index") 4579(load-gr-u lduhu UHI OP_02 OPE1_13 "Load unsigned half, update index") 4580(load-gr-u ldu SI OP_02 OPE1_14 "Load word, update index") 4581 4582(define-pmacro (ne-load-gr-u name mode op ope size comment) 4583 (dni name 4584 (comment) 4585 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING 4586 (MACH simple,tomcat,fr500,fr550,frv)) 4587 (.str name "$pack @($GRi,$GRj),$GRk") 4588 (+ pack GRk op GRi ope GRj) 4589 (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 (load-gr-u-semantics mode)) 4590 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4591 ) 4592) 4593 4594(ne-load-gr-u nldsbu QI OP_02 OPE1_30 (ne-QI-size) "Load signed byte, update index") 4595(ne-load-gr-u nldubu UQI OP_02 OPE1_31 (ne-UQI-size) "Load unsigned byte, update index") 4596(ne-load-gr-u nldshu HI OP_02 OPE1_32 (ne-HI-size) "Load signed half, update index") 4597(ne-load-gr-u nlduhu UHI OP_02 OPE1_33 (ne-UHI-size) "Load unsigned half, update index") 4598(ne-load-gr-u nldu SI OP_02 OPE1_34 (ne-SI-size) "Load word, update index") 4599 4600(define-pmacro (load-non-gr-u-semantics mode regtype) 4601 (sequence ((UWI address)) 4602 (set address (add GRi GRj)) 4603 (set (.sym regtype k) 4604 (c-call mode (.str "@cpu@_read_mem_" mode) pc address)) 4605 (set GRi address) 4606 (c-call VOID "@cpu@_force_update")) 4607) 4608 4609(define-pmacro (load-fr-u name mode op ope comment) 4610 (dni name 4611 (comment) 4612 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 4613 (FR400-MAJOR I-2) (FR450-MAJOR I-2) FR-ACCESS) 4614 (.str name "$pack @($GRi,$GRj),$FRintk") 4615 (+ pack FRintk op GRi ope GRj) 4616 (load-non-gr-u-semantics mode FRint) 4617 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 4618 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4619 ) 4620) 4621 4622(load-fr-u ldbfu UQI OP_02 OPE1_18 "Load byte float, update index") 4623(load-fr-u ldhfu UHI OP_02 OPE1_19 "Load half float, update index") 4624(load-fr-u ldfu SI OP_02 OPE1_1A "Load word float, update index") 4625 4626(define-pmacro (load-cpr-u name mode op ope comment) 4627 (dni name 4628 (comment) 4629 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv)) 4630 (.str name "$pack @($GRi,$GRj),$CPRk") 4631 (+ pack CPRk op GRi ope GRj) 4632 (load-non-gr-u-semantics mode CPR) 4633 () 4634 ) 4635) 4636 4637(load-cpr-u ldcu SI OP_02 OPE1_1D "Load coprocessor word float,update index") 4638 4639(define-pmacro (ne-load-non-gr-u name mode op ope regtype size comment) 4640 (dni name 4641 (comment) 4642 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS 4643 (MACH simple,tomcat,fr500,fr550,frv)) 4644 (.str name "$pack @($GRi,$GRj),$" regtype "k") 4645 (+ pack (.sym regtype k) op GRi ope GRj) 4646 (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 0 size 1 4647 (load-non-gr-u-semantics mode regtype)) 4648 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4649 ) 4650) 4651 4652(ne-load-non-gr-u nldbfu UQI OP_02 OPE1_38 FRint (ne-UQI-size) "Load byte float, update index") 4653(ne-load-non-gr-u nldhfu UHI OP_02 OPE1_39 FRint (ne-UHI-size) "Load half float, update index") 4654(ne-load-non-gr-u nldfu SI OP_02 OPE1_3A FRint (ne-SI-size) "Load word float, update index") 4655 4656(define-pmacro (load-double-gr-u-semantics) 4657 (sequence ((WI address)) 4658 (load-double-semantics 0 DI GR address GRj) 4659 (if (ne (index-of GRi) (index-of GRdoublek)) 4660 (sequence () 4661 (set GRi address) 4662 (c-call VOID "@cpu@_force_update")))) 4663) 4664 4665(define-pmacro (load-double-gr-u name op ope comment) 4666 (dni name 4667 (comment) 4668 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 4669 (FR400-MAJOR I-2) (FR450-MAJOR I-2)) 4670 (.str name "$pack @($GRi,$GRj),$GRdoublek") 4671 (+ pack GRdoublek op GRi ope GRj) 4672 (load-double-gr-u-semantics) 4673 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 4674 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4675 ) 4676) 4677 4678(load-double-gr-u lddu OP_02 OPE1_15 "Load double word, update index") 4679 4680(define-pmacro (ne-load-double-gr-u name op ope size comment) 4681 (dni name 4682 (comment) 4683 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING 4684 (MACH simple,tomcat,fr500,fr550,frv)) 4685 (.str name "$pack @($GRi,$GRj),$GRdoublek") 4686 (+ pack GRdoublek op GRi ope GRj) 4687 (ne-load-semantics GRi (index-of GRj) GRdoublek 0 size 0 4688 (load-double-gr-u-semantics)) 4689 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4690 4691 ) 4692) 4693 4694(ne-load-double-gr-u nlddu OP_02 OPE1_35 (ne-DI-size) "Load double word, update index") 4695 4696(define-pmacro (load-double-non-gr-u-semantics mode regtype) 4697 (sequence ((WI address)) 4698 (load-double-semantics 1 mode regtype address GRj) 4699 (set GRi address) 4700 (c-call VOID "@cpu@_force_update")) 4701) 4702 4703(define-pmacro (load-double-non-gr-u 4704 name mode op ope regtype attr profile comment) 4705 (dni name 4706 (comment) 4707 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 4708 (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) 4709 (.str name "$pack @($GRi,$GRj),$" regtype "doublek") 4710 (+ pack (.sym regtype doublek) op GRi ope GRj) 4711 (load-double-non-gr-u-semantics mode regtype) 4712 profile 4713 ) 4714) 4715 4716(load-double-non-gr-u lddfu DF OP_02 OPE1_1B FR FR-ACCESS 4717 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 4718 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4719 "Load double float, update index") 4720(load-double-non-gr-u lddcu DI OP_02 OPE1_1E CPR (MACH frv) 4721 () "Load coprocessor double float, update index") 4722 4723(define-pmacro (ne-load-double-non-gr-u name mode op ope regtype size comment) 4724 (dni name 4725 (comment) 4726 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING FR-ACCESS 4727 (MACH simple,tomcat,fr500,fr550,frv)) 4728 (.str name "$pack @($GRi,$GRj),$" regtype "doublek") 4729 (+ pack (.sym regtype doublek) op GRi ope GRj) 4730 (ne-load-semantics GRi (index-of GRj) (.sym regtype doublek) 0 size 1 4731 (load-double-non-gr-u-semantics mode regtype)) 4732 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4733 ) 4734) 4735 4736(ne-load-double-non-gr-u nlddfu DF OP_02 OPE1_3B FR (ne-DI-size) "Load double float, update index") 4737 4738(define-pmacro (load-quad-gr-u-semantics) 4739 (sequence ((WI address)) 4740 (load-quad-semantics GR address GRj) 4741 (if (ne (index-of GRi) (index-of GRk)) 4742 (sequence () 4743 (set GRi address) 4744 (c-call VOID "@cpu@_force_update")))) 4745) 4746 4747(define-pmacro (load-quad-gr-u name op ope comment) 4748 (dni name 4749 (comment) 4750 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv)) 4751 (.str name "$pack @($GRi,$GRj),$GRk") 4752 (+ pack GRk op GRi ope GRj) 4753 (load-quad-gr-u-semantics) 4754 ; TODO - GRk not referenced here for profiling 4755 ((fr500 (unit u-gr-load))) 4756 ) 4757) 4758 4759(load-quad-gr-u ldqu OP_02 OPE1_16 "Load quad word, update index") 4760 4761(define-pmacro (ne-load-quad-gr-u name op ope size comment) 4762 (dni name 4763 (comment) 4764 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING) 4765 (.str name "$pack @($GRi,$GRj),$GRk") 4766 (+ pack GRk op GRi ope GRj) 4767 (ne-load-semantics GRi (index-of GRj) GRk 0 size 0 4768 (load-quad-gr-u-semantics)) 4769 ; TODO - GRk not referenced here for profiling 4770 ((fr500 (unit u-gr-load))) 4771 ) 4772) 4773 4774(ne-load-quad-gr-u nldqu OP_02 OPE1_36 (ne-XI-size) "Load quad word, update index") 4775 4776(define-pmacro (load-quad-non-gr-u-semantics regtype) 4777 (sequence ((WI address)) 4778 (load-quad-semantics regtype address GRj) 4779 (set GRi address) 4780 (c-call VOID "@cpu@_force_update")) 4781) 4782 4783(define-pmacro (load-quad-non-gr-u name op ope regtype attr profile comment) 4784 (dni name 4785 (comment) 4786 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) 4787 (.str name "$pack @($GRi,$GRj),$" regtype "k") 4788 (+ pack (.sym regtype k) op GRi ope GRj) 4789 (load-quad-non-gr-u-semantics regtype) 4790 profile 4791 ) 4792) 4793 4794(load-quad-non-gr-u ldqfu OP_02 OPE1_1C FRint FR-ACCESS 4795 ((fr500 (unit u-fr-load))) "Load quad float, update index") 4796(load-quad-non-gr-u ldqcu OP_02 OPE1_1F CPR NA 4797 () "Load coprocessor quad word, update index") 4798 4799(define-pmacro (ne-load-quad-non-gr-u name op ope regtype size comment) 4800 (dni name 4801 (comment) 4802 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING FR-ACCESS) 4803 (.str name "$pack @($GRi,$GRj),$" regtype "k") 4804 (+ pack (.sym regtype k) op GRi ope GRj) 4805 (ne-load-semantics GRi (index-of GRj) (.sym regtype k) 0 size 1 4806 (load-quad-non-gr-u-semantics regtype)) 4807 ((fr500 (unit u-fr-load))) 4808 ) 4809) 4810 4811(ne-load-quad-non-gr-u nldqfu OP_02 OPE1_3C FRint (ne-XI-size) "Load quad float,update index") 4812 4813(define-pmacro (load-r-simm name mode op regtype attr profile comment) 4814 (dni name 4815 (comment) 4816 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 4817 (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) 4818 (.str name "$pack @($GRi,$d12),$" regtype "k") 4819 (+ pack (.sym regtype k) op GRi d12) 4820 (set (.sym regtype k) 4821 (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi d12))) 4822 profile 4823 ) 4824) 4825 4826(load-r-simm ldsbi QI OP_30 GR NA 4827 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 4828 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4829 "Load signed byte") 4830(load-r-simm ldshi HI OP_31 GR NA 4831 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 4832 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4833 "Load signed half") 4834(load-r-simm ldi SI OP_32 GR NA 4835 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 4836 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4837 "Load word") 4838(load-r-simm ldubi UQI OP_35 GR NA 4839 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 4840 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4841 "Load unsigned byte") 4842(load-r-simm lduhi UHI OP_36 GR NA 4843 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 4844 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4845 "Load unsigned half") 4846 4847(load-r-simm ldbfi UQI OP_38 FRint FR-ACCESS 4848 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 4849 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4850 "Load byte float") 4851(load-r-simm ldhfi UHI OP_39 FRint FR-ACCESS 4852 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 4853 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4854 "Load half float") 4855(load-r-simm ldfi SI OP_3A FRint FR-ACCESS 4856 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 4857 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4858 "Load word float") 4859 4860(define-pmacro (ne-load-r-simm 4861 name mode op regtype size is_float attr profile comment) 4862 (dni name 4863 (comment) 4864 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr 4865 (MACH simple,tomcat,fr500,fr550,frv)) 4866 (.str name "$pack @($GRi,$d12),$" regtype "k") 4867 (+ pack (.sym regtype k) op GRi d12) 4868 (ne-load-semantics GRi -1 (.sym regtype k) d12 size is_float 4869 (set (.sym regtype k) 4870 (c-call mode (.str "@cpu@_read_mem_" mode) 4871 pc (add GRi d12)))) 4872 profile 4873 ) 4874) 4875 4876(ne-load-r-simm nldsbi QI OP_40 GR (ne-QI-size) 0 NA 4877 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed byte") 4878(ne-load-r-simm nldubi UQI OP_41 GR (ne-UQI-size) 0 NA 4879 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned byte") 4880(ne-load-r-simm nldshi HI OP_42 GR (ne-HI-size) 0 NA 4881 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load signed half") 4882(ne-load-r-simm nlduhi UHI OP_43 GR (ne-UHI-size) 0 NA 4883 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load unsigned half") 4884(ne-load-r-simm nldi SI OP_44 GR (ne-SI-size) 0 NA 4885 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load word") 4886 4887(ne-load-r-simm nldbfi UQI OP_48 FRint (ne-UQI-size) 1 FR-ACCESS 4888 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load byte float") 4889(ne-load-r-simm nldhfi UHI OP_49 FRint (ne-UHI-size) 1 FR-ACCESS 4890 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load half float") 4891(ne-load-r-simm nldfi SI OP_4A FRint (ne-SI-size) 1 FR-ACCESS 4892 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load word float") 4893 4894(define-pmacro (load-double-r-simm 4895 name not_gr mode op regtype attr profile comment) 4896 (dni name 4897 (comment) 4898 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 4899 (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr) 4900 (.str name "$pack @($GRi,$d12),$" regtype "doublek") 4901 (+ pack (.sym regtype doublek) op GRi d12) 4902 (sequence ((WI address)) 4903 (load-double-semantics not_gr mode regtype address d12)) 4904 profile 4905 ) 4906) 4907 4908(load-double-r-simm lddi 0 DI OP_33 GR NA 4909 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 4910 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 4911 "Load double word") 4912(load-double-r-simm lddfi 1 DF OP_3B FR FR-ACCESS 4913 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 4914 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 4915 "Load double float") 4916 4917(define-pmacro (ne-load-double-r-simm 4918 name not_gr mode op regtype size is_float attr profile comment) 4919 (dni name 4920 (comment) 4921 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) NON-EXCEPTING attr 4922 (MACH simple,tomcat,fr500,fr550,frv)) 4923 (.str name "$pack @($GRi,$d12),$" regtype "doublek") 4924 (+ pack (.sym regtype doublek) op GRi d12) 4925 (sequence ((WI address)) 4926 (ne-load-semantics GRi -1 (.sym regtype doublek) 4927 d12 size is_float 4928 (load-double-semantics not_gr mode 4929 regtype 4930 address d12))) 4931 profile 4932 ) 4933) 4934 4935(ne-load-double-r-simm nlddi 0 DI OP_45 GR (ne-DI-size) 0 NA 4936 ((fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) "Load double word") 4937(ne-load-double-r-simm nlddfi 1 DF OP_4B FR (ne-DI-size) 1 FR-ACCESS 4938 ((fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) "Load double float") 4939 4940(define-pmacro (load-quad-r-simm name op regtype attr profile comment) 4941 (dni name 4942 (comment) 4943 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) attr) 4944 (.str name "$pack @($GRi,$d12),$" regtype "k") 4945 (+ pack (.sym regtype k) op GRi d12) 4946 (sequence ((WI address)) 4947 (load-quad-semantics regtype address d12)) 4948 profile 4949 ) 4950) 4951 4952(load-quad-r-simm ldqi OP_34 GR NA 4953 ((fr500 (unit u-gr-load))) "Load quad word") 4954(load-quad-r-simm ldqfi OP_3C FRint FR-ACCESS 4955 ((fr500 (unit u-fr-load))) "Load quad float") 4956 4957(define-pmacro (ne-load-quad-r-simm 4958 name op regtype size is_float attr profile comment) 4959 (dni name 4960 (comment) 4961 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) NON-EXCEPTING attr) 4962 (.str name "$pack @($GRi,$d12),$" regtype "k") 4963 (+ pack (.sym regtype k) op GRi d12) 4964 (sequence ((WI address)) 4965 (ne-load-semantics GRi -1 (.sym regtype k) d12 size is_float 4966 (load-quad-semantics regtype address d12))) 4967 profile 4968 ) 4969) 4970 4971(ne-load-quad-r-simm nldqfi OP_4C FRint (ne-XI-size) 1 FR-ACCESS 4972 ((fr500 (unit u-fr-load))) "Load quad float") 4973 4974(define-pmacro (store-r-r name mode op ope reg attr profile comment) 4975 (dni name 4976 (comment) 4977 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) 4978 (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) 4979 (.str name "$pack $" reg "k,@($GRi,$GRj)") 4980 (+ pack (.sym reg k) op GRi ope GRj) 4981 (c-call VOID (.str "@cpu@_write_mem_" mode) 4982 pc (add GRi GRj) (.sym reg k)) 4983 profile 4984 ) 4985) 4986 4987(store-r-r stb QI OP_03 OPE1_00 GR NA 4988 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 4989 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4990 "Store unsigned byte") 4991(store-r-r sth HI OP_03 OPE1_01 GR NA 4992 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 4993 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4994 "Store unsigned half") 4995(store-r-r st SI OP_03 OPE1_02 GR NA 4996 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 4997 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 4998 "Store word") 4999 5000(store-r-r stbf QI OP_03 OPE1_08 FRint FR-ACCESS 5001 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5002 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5003 "Store byte float") 5004(store-r-r sthf HI OP_03 OPE1_09 FRint FR-ACCESS 5005 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5006 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5007 "Store half float") 5008(store-r-r stf SI OP_03 OPE1_0A FRint FR-ACCESS 5009 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5010 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5011 "Store word float") 5012 5013(store-r-r stc SI OP_03 OPE1_25 CPR (MACH frv) () "Store coprocessor word") 5014 5015; Semantics for a store-double insn 5016; 5017(define-pmacro (store-double-semantics mode regtype address arg) 5018 (sequence () 5019 (set address (add GRi arg)) 5020 (c-call VOID (.str "@cpu@_write_mem_" mode) 5021 pc address (.sym regtype doublek))) 5022) 5023 5024(define-pmacro (store-double-r-r name mode op ope regtype attr profile comment) 5025 (dni name 5026 (comment) 5027 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) 5028 (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) 5029 (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") 5030 (+ pack (.sym regtype doublek) op GRi ope GRj) 5031 (sequence ((WI address)) 5032 (store-double-semantics mode regtype address GRj)) 5033 profile 5034 ) 5035) 5036 5037(store-double-r-r std DI OP_03 OPE1_03 GR NA 5038 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5039 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5040 "Store double word") 5041(store-double-r-r stdf DF OP_03 OPE1_0B FR FR-ACCESS 5042 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5043 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5044 "Store double float") 5045 5046(store-double-r-r stdc DI OP_03 OPE1_26 CPR (MACH frv) 5047 () "Store coprocessor double word") 5048 5049; Semantics for a store-quad insn 5050; 5051(define-pmacro (store-quad-semantics regtype address arg) 5052 (sequence () 5053 (set address (add GRi arg)) 5054 (c-call VOID (.str "@cpu@_store_quad_" regtype) 5055 pc address (index-of (.sym regtype k)))) 5056) 5057 5058(define-pmacro (store-quad-r-r name op ope regtype attr profile comment) 5059 (dni name 5060 (comment) 5061 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) 5062 (.str name "$pack $" regtype "k,@($GRi,$GRj)") 5063 (+ pack (.sym regtype k) op GRi ope GRj) 5064 (sequence ((WI address)) 5065 (store-quad-semantics regtype address GRj)) 5066 profile 5067 ) 5068) 5069 5070(store-quad-r-r stq OP_03 OPE1_04 GR NA 5071 ((fr500 (unit u-gr-store))) "Store quad word") 5072(store-quad-r-r stqf OP_03 OPE1_0C FRint FR-ACCESS 5073 ((fr500 (unit u-fr-store))) 5074 "Store quad float") 5075(store-quad-r-r stqc OP_03 OPE1_27 CPR NA 5076 () "Store coprocessor quad word") 5077 5078(define-pmacro (store-r-r-u name mode op ope regtype attr profile comment) 5079 (dni name 5080 (comment) 5081 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) 5082 (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) 5083 (.str name "$pack $" regtype "k,@($GRi,$GRj)") 5084 (+ pack (.sym regtype k) op GRi ope GRj) 5085 (sequence ((UWI address)) 5086 (set address (add GRi GRj)) 5087 (c-call VOID (.str "@cpu@_write_mem_" mode) 5088 pc address (.sym regtype k)) 5089 (set GRi address)) 5090 profile 5091 ) 5092) 5093 5094(store-r-r-u stbu QI OP_03 OPE1_10 GR NA 5095 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5096 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5097 "Store unsigned byte, update index") 5098(store-r-r-u sthu HI OP_03 OPE1_11 GR NA 5099 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5100 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5101 "Store unsigned half, update index") 5102(store-r-r-u stu WI OP_03 OPE1_12 GR NA 5103 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5104 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5105 "Store word, update index") 5106 5107(store-r-r-u stbfu QI OP_03 OPE1_18 FRint FR-ACCESS 5108 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5109 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5110 "Store byte float, update index") 5111(store-r-r-u sthfu HI OP_03 OPE1_19 FRint FR-ACCESS 5112 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5113 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5114 "Store half float, update index") 5115(store-r-r-u stfu SI OP_03 OPE1_1A FRint FR-ACCESS 5116 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5117 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5118 "Store word float, update index") 5119 5120(store-r-r-u stcu SI OP_03 OPE1_2D CPR (MACH frv) () 5121 "Store coprocessor word, update index") 5122 5123(define-pmacro (store-double-r-r-u 5124 name mode op ope regtype attr profile comment) 5125 (dni name 5126 (comment) 5127 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) 5128 (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) 5129 (.str name "$pack $" regtype "doublek,@($GRi,$GRj)") 5130 (+ pack (.sym regtype doublek) op GRi ope GRj) 5131 (sequence ((WI address)) 5132 (store-double-semantics mode regtype address GRj) 5133 (set GRi address)) 5134 profile 5135 ) 5136) 5137 5138(store-double-r-r-u stdu DI OP_03 OPE1_13 GR NA 5139 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5140 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5141 "Store double word, update index") 5142(store-double-r-r-u stdfu DF OP_03 OPE1_1B FR FR-ACCESS 5143 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5144 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5145 "Store double float,update index") 5146(store-double-r-r-u stdcu DI OP_03 OPE1_2E CPR (MACH frv) () 5147 "Store coprocessor double word, update index") 5148 5149(define-pmacro (store-quad-r-r-u name op ope regtype attr profile comment) 5150 (dni name 5151 (comment) 5152 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) 5153 (.str name "$pack $" regtype "k,@($GRi,$GRj)") 5154 (+ pack (.sym regtype k) op GRi ope GRj) 5155 (sequence ((WI address)) 5156 (store-quad-semantics regtype address GRj) 5157 (set GRi address)) 5158 profile 5159 ) 5160) 5161 5162(store-quad-r-r-u stqu OP_03 OPE1_14 GR NA 5163 ((fr500 (unit u-gr-store))) 5164 "Store quad word, update index") 5165(store-quad-r-r-u stqfu OP_03 OPE1_1C FRint FR-ACCESS 5166 ((fr500 (unit u-fr-store))) 5167 "Store quad float, update index") 5168(store-quad-r-r-u stqcu OP_03 OPE1_2F CPR NA () 5169 "Store coprocessor quad word, update index") 5170 5171(define-pmacro (conditional-load name mode op ope regtype profile comment) 5172 (dni name 5173 (comment) 5174 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 5175 (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL) 5176 (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond") 5177 (+ pack (.sym regtype k) op GRi CCi cond ope GRj) 5178 (if (eq CCi (or cond 2)) 5179 (set (.sym regtype k) 5180 (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj)))) 5181 profile 5182 ) 5183) 5184 5185(conditional-load cldsb QI OP_5E OPE4_0 GR 5186 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 5187 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 5188 "Load signed byte") 5189(conditional-load cldub UQI OP_5E OPE4_1 GR 5190 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 5191 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 5192 "Load unsigned byte") 5193(conditional-load cldsh HI OP_5E OPE4_2 GR 5194 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 5195 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 5196 "Load signed half") 5197(conditional-load clduh UHI OP_5E OPE4_3 GR 5198 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 5199 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 5200 "Load unsigned half") 5201(conditional-load cld SI OP_5F OPE4_0 GR 5202 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 5203 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 5204 "Load word") 5205 5206(conditional-load cldbf UQI OP_60 OPE4_0 FRint 5207 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 5208 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 5209 "Load byte float") 5210(conditional-load cldhf UHI OP_60 OPE4_1 FRint 5211 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 5212 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 5213 "Load half float") 5214(conditional-load cldf SI OP_60 OPE4_2 FRint 5215 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 5216 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 5217 "Load word float") 5218 5219(define-pmacro (conditional-load-double 5220 name not_gr mode op ope regtype attr profile comment) 5221 (dni name 5222 (comment) 5223 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 5224 (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL attr) 5225 (.str name "$pack @($GRi,$GRj),$" regtype "doublek,$CCi,$cond") 5226 (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) 5227 (if (eq CCi (or cond 2)) 5228 (sequence ((WI address)) 5229 (load-double-semantics not_gr mode regtype address GRj))) 5230 profile 5231 ) 5232) 5233 5234(conditional-load-double cldd 0 DI OP_5F OPE4_1 GR NA 5235 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 5236 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 5237 "Load double word") 5238(conditional-load-double clddf 1 DF OP_60 OPE4_3 FR FR-ACCESS 5239 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 5240 (fr500 (unit u-gr-load)) (fr550 (unit u-fr-load))) 5241 "Load double float") 5242 5243(dni cldq 5244 "conditional load quad integer" 5245 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) CONDITIONAL) 5246 "cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond" 5247 (+ pack GRk OP_5F GRi CCi cond OPE4_2 GRj) 5248 (if (eq CCi (or cond 2)) 5249 (sequence ((WI address)) 5250 (load-quad-semantics GR address GRj))) 5251 ((fr500 (unit u-gr-load))) 5252) 5253 5254(define-pmacro (conditional-load-gr-u name mode op ope comment) 5255 (dni name 5256 (comment) 5257 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 5258 (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL) 5259 (.str name "$pack @($GRi,$GRj),$GRk,$CCi,$cond") 5260 (+ pack GRk op GRi CCi cond ope GRj) 5261 (if (eq CCi (or cond 2)) 5262 (sequence ((WI address)) 5263 (set address (add GRi GRj)) 5264 (set GRk 5265 (c-call mode (.str "@cpu@_read_mem_" mode) 5266 pc address)) 5267 (if (ne (index-of GRi) (index-of GRk)) 5268 (set GRi address)))) 5269 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 5270 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 5271 ) 5272) 5273 5274(conditional-load-gr-u cldsbu QI OP_61 OPE4_0 "Load signed byte, update") 5275(conditional-load-gr-u cldubu UQI OP_61 OPE4_1 "Load unsigned byte, update") 5276(conditional-load-gr-u cldshu HI OP_61 OPE4_2 "Load signed half, update") 5277(conditional-load-gr-u clduhu UHI OP_61 OPE4_3 "Load unsigned half, update") 5278(conditional-load-gr-u cldu SI OP_62 OPE4_0 "Load word, update") 5279 5280(define-pmacro (conditional-load-non-gr-u name mode op ope regtype comment) 5281 (dni name 5282 (comment) 5283 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 5284 (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL FR-ACCESS) 5285 (.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond") 5286 (+ pack (.sym regtype k) op GRi CCi cond ope GRj) 5287 (if (eq CCi (or cond 2)) 5288 (sequence ((WI address)) 5289 (set address (add GRi GRj)) 5290 (set (.sym regtype k) 5291 (c-call mode (.str "@cpu@_read_mem_" mode) 5292 pc address)) 5293 (set GRi address))) 5294 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 5295 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 5296 ) 5297) 5298 5299(conditional-load-non-gr-u cldbfu UQI OP_63 OPE4_0 FRint "Load byte float, update") 5300(conditional-load-non-gr-u cldhfu UHI OP_63 OPE4_1 FRint "Load half float, update") 5301(conditional-load-non-gr-u cldfu SI OP_63 OPE4_2 FRint "Load word float, update") 5302 5303 5304(dni clddu 5305 "Load double word, update" 5306 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 5307 (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL) 5308 "clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond" 5309 (+ pack GRdoublek OP_62 GRi CCi cond OPE4_1 GRj) 5310 (if (eq CCi (or cond 2)) 5311 (sequence ((WI address)) 5312 (load-double-semantics 0 DI GR address GRj) 5313 (if (ne (index-of GRi) (index-of GRdoublek)) 5314 (set GRi address)))) 5315 ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load)) 5316 (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load))) 5317) 5318 5319(dni clddfu 5320 "Load double float, update" 5321 ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) 5322 (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL FR-ACCESS) 5323 "clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond" 5324 (+ pack FRdoublek OP_63 GRi CCi cond OPE4_3 GRj) 5325 (if (eq CCi (or cond 2)) 5326 (sequence ((WI address)) 5327 (load-double-semantics 1 DF FR address GRj) 5328 (set GRi address))) 5329 ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load)) 5330 (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load))) 5331) 5332 5333(dni cldqu 5334 "conditional load quad integer and update index" 5335 ((UNIT LOAD) (FR500-MAJOR I-2) (MACH frv) CONDITIONAL) 5336 "cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond" 5337 (+ pack GRk OP_62 GRi CCi cond OPE4_2 GRj) 5338 (if (eq CCi (or cond 2)) 5339 (sequence ((WI address)) 5340 (load-quad-semantics GR address GRj) 5341 (if (ne (index-of GRi) (index-of GRk)) 5342 (set GRi address)))) 5343 ((fr500 (unit u-gr-load))) 5344) 5345 5346(define-pmacro (conditional-store name mode op ope regtype profile comment) 5347 (dni name 5348 (comment) 5349 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) 5350 (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL) 5351 (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond") 5352 (+ pack (.sym regtype k) op GRi CCi cond ope GRj) 5353 (if (eq CCi (or cond 2)) 5354 (c-call VOID (.str "@cpu@_write_mem_" mode) 5355 pc (add GRi GRj) (.sym regtype k))) 5356 profile 5357 ) 5358) 5359 5360(conditional-store cstb QI OP_64 OPE4_0 GR 5361 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5362 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5363 "Store unsigned byte") 5364(conditional-store csth HI OP_64 OPE4_1 GR 5365 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5366 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5367 "Store unsigned half") 5368(conditional-store cst SI OP_64 OPE4_2 GR 5369 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5370 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5371 "Store word") 5372 5373(conditional-store cstbf QI OP_66 OPE4_0 FRint 5374 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5375 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5376 "Store byte float") 5377(conditional-store csthf HI OP_66 OPE4_1 FRint 5378 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5379 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5380 "Store half float") 5381(conditional-store cstf SI OP_66 OPE4_2 FRint 5382 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5383 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5384 "Store word float") 5385 5386(define-pmacro (conditional-store-double 5387 name mode op ope regtype attr profile comment) 5388 (dni name 5389 (comment) 5390 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) 5391 (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr) 5392 (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond") 5393 (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) 5394 (if (eq CCi (or cond 2)) 5395 (sequence ((WI address)) 5396 (store-double-semantics mode regtype address GRj))) 5397 profile 5398 ) 5399) 5400 5401(conditional-store-double cstd DI OP_64 OPE4_3 GR NA 5402 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5403 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5404 "Store double word") 5405(conditional-store-double cstdf DF OP_66 OPE4_3 FR FR-ACCESS 5406 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5407 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5408 "Store double float") 5409 5410(dni cstq 5411 "conditionally store quad word" 5412 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) CONDITIONAL) 5413 "cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond" 5414 (+ pack GRk OP_65 GRi CCi cond OPE4_0 GRj) 5415 (if (eq CCi (or cond 2)) 5416 (sequence ((WI address)) 5417 (store-quad-semantics GR address GRj))) 5418 ((fr500 (unit u-gr-store))) 5419) 5420 5421(define-pmacro (conditional-store-u 5422 name mode op ope regtype attr profile comment) 5423 (dni name 5424 (comment) 5425 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) 5426 (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr) 5427 (.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond") 5428 (+ pack (.sym regtype k) op GRi CCi cond ope GRj) 5429 (if (eq CCi (or cond 2)) 5430 (sequence ((WI address)) 5431 (set address (add GRi GRj)) 5432 (c-call VOID (.str "@cpu@_write_mem_" mode) 5433 pc address (.sym regtype k)) 5434 (set GRi address))) 5435 profile 5436 ) 5437) 5438 5439(conditional-store-u cstbu QI OP_67 OPE4_0 GR NA 5440 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5441 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5442 "Store unsigned byte, update index") 5443(conditional-store-u csthu HI OP_67 OPE4_1 GR NA 5444 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5445 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5446 "Store unsigned half, update index") 5447(conditional-store-u cstu SI OP_67 OPE4_2 GR NA 5448 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5449 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5450 "Store word, update index") 5451 5452(conditional-store-u cstbfu QI OP_68 OPE4_0 FRint FR-ACCESS 5453 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5454 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5455 "Store byte float, update index") 5456(conditional-store-u csthfu HI OP_68 OPE4_1 FRint FR-ACCESS 5457 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5458 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5459 "Store half float, update index") 5460(conditional-store-u cstfu SI OP_68 OPE4_2 FRint FR-ACCESS 5461 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5462 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5463 "Store word float, update index") 5464 5465(define-pmacro (conditional-store-double-u 5466 name mode op ope regtype attr profile comment) 5467 (dni name 5468 (comment) 5469 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) 5470 (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr) 5471 (.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond") 5472 (+ pack (.sym regtype doublek) op GRi CCi cond ope GRj) 5473 (if (eq CCi (or cond 2)) 5474 (sequence ((WI address)) 5475 (store-double-semantics mode regtype address GRj) 5476 (set GRi address))) 5477 profile 5478 ) 5479) 5480 5481(conditional-store-double-u cstdu DI OP_67 OPE4_3 GR NA 5482 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5483 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5484 "Store double word, update index") 5485(conditional-store-double-u cstdfu DF OP_68 OPE4_3 FR FR-ACCESS 5486 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5487 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5488 "Store double float, update index") 5489 5490(define-pmacro (store-r-simm name mode op regtype attr profile comment) 5491 (dni name 5492 (comment) 5493 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) 5494 (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) 5495 (.str name "$pack $" regtype "k,@($GRi,$d12)") 5496 (+ pack (.sym regtype k) op GRi d12) 5497 (c-call VOID (.str "@cpu@_write_mem_" mode) 5498 pc (add GRi d12) (.sym regtype k)) 5499 profile 5500 ) 5501) 5502 5503(store-r-simm stbi QI OP_50 GR NA 5504 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5505 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5506 "Store unsigned byte") 5507(store-r-simm sthi HI OP_51 GR NA 5508 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5509 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5510 "Store unsigned half") 5511(store-r-simm sti SI OP_52 GR NA 5512 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5513 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5514 "Store word") 5515 5516(store-r-simm stbfi QI OP_4E FRint FR-ACCESS 5517 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5518 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5519 "Store byte float") 5520(store-r-simm sthfi HI OP_4F FRint FR-ACCESS 5521 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5522 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5523 "Store half float") 5524(store-r-simm stfi SI OP_55 FRint FR-ACCESS 5525 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5526 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5527 "Store word float") 5528 5529(define-pmacro (store-double-r-simm name mode op regtype attr profile comment) 5530 (dni name 5531 (comment) 5532 ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) 5533 (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr) 5534 (.str name "$pack $" regtype "doublek,@($GRi,$d12)") 5535 (+ pack (.sym regtype doublek) op GRi d12) 5536 (sequence ((WI address)) 5537 (store-double-semantics mode regtype address d12)) 5538 profile 5539 ) 5540) 5541 5542(store-double-r-simm stdi DI OP_53 GR NA 5543 ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store)) 5544 (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store))) 5545 "Store double word") 5546(store-double-r-simm stdfi DF OP_56 FR FR-ACCESS 5547 ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store)) 5548 (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store))) 5549 "Store double float") 5550 5551(define-pmacro (store-quad-r-simm name op regtype attr profile comment) 5552 (dni name 5553 (comment) 5554 ((UNIT STORE) (FR500-MAJOR I-3) (MACH frv) attr) 5555 (.str name "$pack $" regtype "k,@($GRi,$d12)") 5556 (+ pack (.sym regtype k) op GRi d12) 5557 (sequence ((WI address)) 5558 (store-quad-semantics regtype address d12)) 5559 profile 5560 ) 5561) 5562 5563(store-quad-r-simm stqi OP_54 GR NA ((fr500 (unit u-gr-store))) 5564 "Store quad word") 5565(store-quad-r-simm stqfi OP_57 FRint FR-ACCESS () 5566 "Store quad float") 5567 5568(define-pmacro (swap-semantics base offset arg) 5569 (sequence ((WI tmp) (WI address)) 5570 (set tmp arg) 5571 (set address (add base offset)) 5572 (c-call VOID "@cpu@_check_swap_address" address) 5573 (set arg (c-call WI "@cpu@_read_mem_WI" pc address)) 5574 (c-call VOID "@cpu@_write_mem_WI" pc address tmp)) 5575) 5576 5577(dni swap 5578 "Swap contents of memory with GR" 5579 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) 5580 (FR400-MAJOR C-2) (FR450-MAJOR C-2)) 5581 "swap$pack @($GRi,$GRj),$GRk" 5582 (+ pack GRk OP_03 GRi OPE1_05 GRj) 5583 (swap-semantics GRi GRj GRk) 5584 ((fr400 (unit u-swap)) (fr450 (unit u-swap)) 5585 (fr500 (unit u-swap)) (fr550 (unit u-swap))) 5586) 5587 5588(dni "swapi" 5589 "Swap contents of memory with GR" 5590 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) 5591 (FR400-MAJOR C-2) (FR450-MAJOR C-2)) 5592 ("swapi$pack @($GRi,$d12),$GRk") 5593 (+ pack GRk OP_4D GRi d12) 5594 (swap-semantics GRi d12 GRk) 5595 ((fr400 (unit u-swap)) (fr450 (unit u-swap)) 5596 (fr500 (unit u-swap)) (fr550 (unit u-swap))) 5597) 5598 5599(dni cswap 5600 "Conditionally swap contents of memory with GR" 5601 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) 5602 (FR400-MAJOR C-2) (FR450-MAJOR C-2) CONDITIONAL) 5603 "cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond" 5604 (+ pack GRk OP_65 GRi CCi cond OPE4_2 GRj) 5605 (if (eq CCi (or cond 2)) 5606 (swap-semantics GRi GRj GRk)) 5607 ((fr400 (unit u-swap)) (fr450 (unit u-swap)) 5608 (fr500 (unit u-swap)) (fr550 (unit u-swap))) 5609) 5610 5611(define-pmacro (register-transfer 5612 name op ope reg_src reg_targ pipe attrs profile comment) 5613 (dni name 5614 (comment) 5615 (.splice (UNIT pipe) (.unsplice attrs)) 5616 (.str name "$pack $" reg_src ",$" reg_targ) 5617 (+ pack reg_targ op (rs-null) ope reg_src) 5618 (set reg_targ reg_src) 5619 profile 5620 ) 5621) 5622 5623(register-transfer movgf OP_03 OPE1_15 5624 GRj FRintk I0 5625 ((FR500-MAJOR I-4) (FR550-MAJOR I-5) 5626 (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) 5627 ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) 5628 (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) 5629 "transfer gr to fr") 5630(register-transfer movfg OP_03 OPE1_0D 5631 FRintk GRj I0 5632 ((FR500-MAJOR I-4) (FR550-MAJOR I-5) 5633 (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) 5634 ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) 5635 (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) 5636 "transfer fr to gr") 5637 5638(define-pmacro (nextreg hw r offset) (reg hw (add (index-of r) offset))) 5639 5640(define-pmacro (register-transfer-double-from-gr-semantics cond) 5641 (if cond 5642 (if (eq (index-of GRj) 0) 5643 (sequence () 5644 (set FRintk 0) 5645 (set (nextreg h-fr_int FRintk 1) 0)) 5646 (sequence () 5647 (set FRintk GRj) 5648 (set (nextreg h-fr_int FRintk 1) (nextreg h-gr GRj 1))))) 5649) 5650 5651(dni movgfd 5652 "move GR for FR double" 5653 ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) 5654 (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) 5655 "movgfd$pack $GRj,$FRintk" 5656 (+ pack FRintk OP_03 (rs-null) OPE1_16 GRj) 5657 (register-transfer-double-from-gr-semantics 1) 5658 ; TODO -- doesn't handle second register in the pair 5659 ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) 5660 (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) 5661) 5662 5663(define-pmacro (register-transfer-double-to-gr-semantics cond) 5664 (if (andif (ne (index-of GRj) 0) cond) 5665 (sequence () 5666 (set GRj FRintk) 5667 (set (nextreg h-gr GRj 1) (nextreg h-fr_int FRintk 1)))) 5668) 5669 5670(dni movfgd 5671 "move FR for GR double" 5672 ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) 5673 (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS) 5674 "movfgd$pack $FRintk,$GRj" 5675 (+ pack FRintk OP_03 (rs-null) OPE1_0E GRj) 5676 (register-transfer-double-to-gr-semantics 1) 5677 ; TODO -- doesn't handle second register in the pair 5678 ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) 5679 (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) 5680) 5681 5682(dni movgfq 5683 "move GR for FR quad" 5684 ((UNIT I0) (FR500-MAJOR I-4) (MACH frv) FR-ACCESS) 5685 "movgfq$pack $GRj,$FRintk" 5686 (+ pack FRintk OP_03 (rs-null) OPE1_17 GRj) 5687 (if (eq (index-of GRj) 0) 5688 (sequence () 5689 (set FRintk 0) 5690 (set (reg h-fr_int (add (index-of FRintk) 1)) 0) 5691 (set (reg h-fr_int (add (index-of FRintk) 2)) 0) 5692 (set (reg h-fr_int (add (index-of FRintk) 3)) 0)) 5693 (sequence () 5694 (set FRintk GRj) 5695 (set (reg h-fr_int (add (index-of FRintk) 1)) 5696 (reg h-gr (add (index-of GRj) 1))) 5697 (set (reg h-fr_int (add (index-of FRintk) 2)) 5698 (reg h-gr (add (index-of GRj) 2))) 5699 (set (reg h-fr_int (add (index-of FRintk) 3)) 5700 (reg h-gr (add (index-of GRj) 3))))) 5701 () 5702) 5703 5704(dni movfgq 5705 "move FR for GR quad" 5706 ((UNIT I0) (FR500-MAJOR I-4) (MACH frv) FR-ACCESS) 5707 "movfgq$pack $FRintk,$GRj" 5708 (+ pack FRintk OP_03 (rs-null) OPE1_0F GRj) 5709 (if (ne (index-of GRj) 0) 5710 (sequence () 5711 (set GRj FRintk) 5712 (set (reg h-gr (add (index-of GRj) 1)) 5713 (reg h-fr_int (add (index-of FRintk) 1))) 5714 (set (reg h-gr (add (index-of GRj) 2)) 5715 (reg h-fr_int (add (index-of FRintk) 2))) 5716 (set (reg h-gr (add (index-of GRj) 3)) 5717 (reg h-fr_int (add (index-of FRintk) 3))))) 5718 () 5719) 5720 5721(define-pmacro (conditional-register-transfer 5722 name op ope reg_src reg_targ pipe attrs profile comment) 5723 (dni name 5724 (comment) 5725 (.splice (UNIT pipe) CONDITIONAL FR-ACCESS (.unsplice attrs)) 5726 (.str name "$pack $" reg_src ",$" reg_targ ",$CCi,$cond") 5727 (+ pack reg_targ op (rs-null) CCi cond ope reg_src) 5728 (if (eq CCi (or cond 2)) 5729 (set reg_targ reg_src)) 5730 profile 5731 ) 5732) 5733 5734(conditional-register-transfer cmovgf OP_69 OPE4_0 GRj FRintk I0 5735 ((FR500-MAJOR I-4) (FR550-MAJOR I-5) 5736 (FR400-MAJOR I-4) (FR450-MAJOR I-4)) 5737 ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) 5738 (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) 5739 "transfer gr to fr") 5740(conditional-register-transfer cmovfg OP_69 OPE4_2 FRintk GRj I0 5741 ((FR500-MAJOR I-4) (FR550-MAJOR I-5) 5742 (FR400-MAJOR I-4) (FR450-MAJOR I-4)) 5743 ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) 5744 (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) 5745 "transfer fr to gr") 5746 5747 5748(dni cmovgfd 5749 "Conditional move GR to FR double" 5750 ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) 5751 (FR400-MAJOR I-4) (FR450-MAJOR I-4) CONDITIONAL FR-ACCESS) 5752 "cmovgfd$pack $GRj,$FRintk,$CCi,$cond" 5753 (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_1 GRj) 5754 (register-transfer-double-from-gr-semantics (eq CCi (or cond 2))) 5755 ; TODO -- doesn't handle extra registers in double 5756 ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr)) 5757 (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr))) 5758) 5759 5760(dni cmovfgd 5761 "Conditional move FR to GR double" 5762 ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) 5763 (FR400-MAJOR I-4) (FR450-MAJOR I-4) CONDITIONAL FR-ACCESS) 5764 "cmovfgd$pack $FRintk,$GRj,$CCi,$cond" 5765 (+ pack FRintk OP_69 (rs-null) CCi cond OPE4_3 GRj) 5766 (register-transfer-double-to-gr-semantics (eq CCi (or cond 2))) 5767 ; TODO -- doesn't handle second register in the pair 5768 ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr)) 5769 (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr))) 5770) 5771 5772(define-pmacro (register-transfer-spr 5773 name op ope reg_src reg_targ unitname comment) 5774 (dni name 5775 (comment) 5776 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) 5777 (FR400-MAJOR C-2) (FR450-MAJOR C-2)) 5778 (.str name "$pack $" reg_src ",$" reg_targ) 5779 (+ pack reg_targ op ope reg_src) 5780 (set reg_targ reg_src) 5781 ((fr400 (unit unitname)) (fr450 (unit unitname)) 5782 (fr500 (unit unitname)) (fr550 (unit unitname))) 5783 ) 5784) 5785 5786(register-transfer-spr movgs OP_03 OPE1_06 GRj spr u-gr2spr "transfer gr->spr") 5787(register-transfer-spr movsg OP_03 OPE1_07 spr GRj u-spr2gr "transfer spr->gr") 5788 5789; Integer Branch Conditions 5790(define-pmacro (Inev cc) (const BI 0)) 5791(define-pmacro (Ira cc) (const BI 1)) 5792(define-pmacro (Ieq cc) ( zbit cc)) 5793(define-pmacro (Ine cc) (not (zbit cc))) 5794(define-pmacro (Ile cc) ( orif (zbit cc) (xor (nbit cc) (vbit cc)))) 5795(define-pmacro (Igt cc) (not (orif (zbit cc) (xor (nbit cc) (vbit cc))))) 5796(define-pmacro (Ilt cc) ( xor (nbit cc) (vbit cc))) 5797(define-pmacro (Ige cc) (not (xor (nbit cc) (vbit cc)))) 5798(define-pmacro (Ils cc) ( orif (cbit cc) (zbit cc))) 5799(define-pmacro (Ihi cc) (not (orif (cbit cc) (zbit cc)))) 5800(define-pmacro (Ic cc) ( cbit cc)) 5801(define-pmacro (Inc cc) (not (cbit cc))) 5802(define-pmacro (In cc) ( nbit cc)) 5803(define-pmacro (Ip cc) (not (nbit cc))) 5804(define-pmacro (Iv cc) ( vbit cc)) 5805(define-pmacro (Inv cc) (not (vbit cc))) 5806 5807; Float Branch Conditions 5808(define-pmacro (Fnev cc) (const BI 0)) 5809(define-pmacro (Fra cc) (const BI 1)) 5810(define-pmacro (Fne cc) (orif (lbit cc) (orif (gbit cc) (ubit cc)))) 5811(define-pmacro (Feq cc) (ebit cc)) 5812(define-pmacro (Flg cc) (orif (lbit cc) (gbit cc))) 5813(define-pmacro (Fue cc) (orif (ebit cc) (ubit cc))) 5814(define-pmacro (Ful cc) (orif (lbit cc) (ubit cc))) 5815(define-pmacro (Fge cc) (orif (ebit cc) (gbit cc))) 5816(define-pmacro (Flt cc) (lbit cc)) 5817(define-pmacro (Fuge cc) (orif (ebit cc) (orif (gbit cc) (ubit cc)))) 5818(define-pmacro (Fug cc) (orif (gbit cc) (ubit cc))) 5819(define-pmacro (Fle cc) (orif (ebit cc) (lbit cc))) 5820(define-pmacro (Fgt cc) (gbit cc)) 5821(define-pmacro (Fule cc) (orif (ebit cc) (orif (lbit cc) (ubit cc)))) 5822(define-pmacro (Fu cc) (ubit cc)) 5823(define-pmacro (Fo cc) (orif (ebit cc) (orif (lbit cc) (gbit cc)))) 5824 5825(define-pmacro (conditional-branch-i prefix cc op cond comment) 5826 (dni (.sym prefix cc) 5827 (comment) 5828 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) 5829 (FR400-MAJOR B-1) (FR450-MAJOR B-1)) 5830 (.str (.sym prefix cc) "$pack $ICCi_2,$hint,$label16") 5831 (+ pack (.sym ICC_ cc) ICCi_2 op hint label16) 5832 (sequence () 5833 (c-call VOID "@cpu@_model_branch" label16 hint) 5834 (if (cond ICCi_2) 5835 (set pc label16))) 5836 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 5837 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5838 ) 5839) 5840 5841(dni bra 5842 "integer branch equal" 5843 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) 5844 (FR400-MAJOR B-1) (FR450-MAJOR B-1)) 5845 "bra$pack $hint_taken$label16" 5846 (+ pack ICC_ra (ICCi_2-null) OP_06 hint_taken label16) 5847 (sequence () 5848 (c-call VOID "@cpu@_model_branch" label16 hint_taken) 5849 (set pc label16)) 5850 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 5851 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5852) 5853 5854(dni bno 5855 "integer branch never" 5856 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) 5857 (FR400-MAJOR B-1) (FR450-MAJOR B-1)) 5858 "bno$pack$hint_not_taken" 5859 (+ pack ICC_nev (ICCi_2-null) OP_06 hint_not_taken (label16-null)) 5860 (c-call VOID "@cpu@_model_branch" label16 hint_not_taken) 5861 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 5862 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5863) 5864 5865(conditional-branch-i b eq OP_06 Ieq "integer branch equal") 5866(conditional-branch-i b ne OP_06 Ine "integer branch not equal") 5867(conditional-branch-i b le OP_06 Ile "integer branch less or equal") 5868(conditional-branch-i b gt OP_06 Igt "integer branch greater") 5869(conditional-branch-i b lt OP_06 Ilt "integer branch less") 5870(conditional-branch-i b ge OP_06 Ige "integer branch greater or equal") 5871(conditional-branch-i b ls OP_06 Ils "integer branch less or equal unsigned") 5872(conditional-branch-i b hi OP_06 Ihi "integer branch greater unsigned") 5873(conditional-branch-i b c OP_06 Ic "integer branch carry set") 5874(conditional-branch-i b nc OP_06 Inc "integer branch carry clear") 5875(conditional-branch-i b n OP_06 In "integer branch negative") 5876(conditional-branch-i b p OP_06 Ip "integer branch positive") 5877(conditional-branch-i b v OP_06 Iv "integer branch overflow set") 5878(conditional-branch-i b nv OP_06 Inv "integer branch overflow clear") 5879 5880(define-pmacro (conditional-branch-f prefix cc op cond comment) 5881 (dni (.sym prefix cc) 5882 (comment) 5883 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) 5884 (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS) 5885 (.str (.sym prefix cc) "$pack $FCCi_2,$hint,$label16") 5886 (+ pack (.sym FCC_ cc) FCCi_2 op hint label16) 5887 (sequence () 5888 (c-call VOID "@cpu@_model_branch" label16 hint) 5889 (if (cond FCCi_2) (set pc label16))) 5890 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 5891 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5892 ) 5893) 5894 5895(dni fbra 5896 "float branch equal" 5897 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) 5898 (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS) 5899 "fbra$pack $hint_taken$label16" 5900 (+ pack FCC_ra (FCCi_2-null) OP_07 hint_taken label16) 5901 (sequence () 5902 (c-call VOID "@cpu@_model_branch" label16 hint_taken) 5903 (set pc label16)) 5904 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 5905 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5906) 5907 5908(dni fbno 5909 "float branch never" 5910 ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) 5911 (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS) 5912 "fbno$pack$hint_not_taken" 5913 (+ pack FCC_nev (FCCi_2-null) OP_07 hint_not_taken (label16-null)) 5914 (c-call VOID "@cpu@_model_branch" label16 hint_not_taken) 5915 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 5916 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5917) 5918 5919(conditional-branch-f fb ne OP_07 Fne "float branch not equal") 5920(conditional-branch-f fb eq OP_07 Feq "float branch equal") 5921(conditional-branch-f fb lg OP_07 Flg "float branch less or greater") 5922(conditional-branch-f fb ue OP_07 Fue "float branch unordered or equal") 5923(conditional-branch-f fb ul OP_07 Ful "float branch unordered or less") 5924(conditional-branch-f fb ge OP_07 Fge "float branch greater or equal") 5925(conditional-branch-f fb lt OP_07 Flt "float branch less") 5926(conditional-branch-f fb uge OP_07 Fuge "float branch unordered, greater,equal") 5927(conditional-branch-f fb ug OP_07 Fug "float branch unordered or greater") 5928(conditional-branch-f fb le OP_07 Fle "float branch less or equal") 5929(conditional-branch-f fb gt OP_07 Fgt "float branch greater") 5930(conditional-branch-f fb ule OP_07 Fule "float branch unordered, less or equal") 5931(conditional-branch-f fb u OP_07 Fu "float branch unordered") 5932(conditional-branch-f fb o OP_07 Fo "float branch ordered") 5933 5934(define-pmacro (ctrlr-branch-semantics cond ccond) 5935 (sequence ((SI tmp)) 5936 (set tmp (sub (spr-lcr) 1)) 5937 (set (spr-lcr) tmp) 5938 (if cond 5939 (if (eq ccond 0) 5940 (if (ne tmp 0) 5941 (set pc (spr-lr))) 5942 (if (eq tmp 0) 5943 (set pc (spr-lr)))))) 5944) 5945 5946(dni bctrlr 5947 "LCR conditional branch to lr" 5948 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) 5949 (FR400-MAJOR B-2) (FR450-MAJOR B-2)) 5950 ("bctrlr$pack $ccond,$hint") 5951 (+ pack (cond-null) (ICCi_2-null) OP_0E hint OPE3_01 ccond (s12-null)) 5952 (sequence () 5953 (c-call VOID "@cpu@_model_branch" (spr-lr) hint) 5954 (ctrlr-branch-semantics (const BI 1) ccond)) 5955 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 5956 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5957) 5958 5959(define-pmacro (conditional-branch-cclr prefix cc i-f op ope cond attr comment) 5960 (dni (.sym prefix cc lr) 5961 (comment) 5962 ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) 5963 (FR400-MAJOR B-3) (FR450-MAJOR B-3) attr) 5964 (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$hint") 5965 (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope 5966 (ccond-null) (s12-null)) 5967 (sequence () 5968 (c-call VOID "@cpu@_model_branch" (spr-lr) hint) 5969 (if (cond (.sym i-f CCi_2)) (set pc (spr-lr)))) 5970 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 5971 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5972 ) 5973) 5974 5975(dni bralr 5976 "integer cclr branch always" 5977 ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) 5978 (FR400-MAJOR B-3) (FR450-MAJOR B-3)) 5979 "bralr$pack$hint_taken" 5980 (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_02 (ccond-null) (s12-null)) 5981 (sequence () 5982 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) 5983 (set pc (spr-lr))) 5984 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 5985 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5986) 5987 5988(dni bnolr 5989 "integer cclr branch never" 5990 ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) 5991 (FR400-MAJOR B-3) (FR450-MAJOR B-3)) 5992 "bnolr$pack$hint_not_taken" 5993 (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_02 (ccond-null) (s12-null)) 5994 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) 5995 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 5996 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 5997) 5998 5999(conditional-branch-cclr b eq I OP_0E OPE3_02 Ieq NA "integer cclr branch equal") 6000(conditional-branch-cclr b ne I OP_0E OPE3_02 Ine NA "integer cclr branch not equal") 6001(conditional-branch-cclr b le I OP_0E OPE3_02 Ile NA "integer cclr branch less or equal") 6002(conditional-branch-cclr b gt I OP_0E OPE3_02 Igt NA "integer cclr branch greater") 6003(conditional-branch-cclr b lt I OP_0E OPE3_02 Ilt NA "integer cclr branch less") 6004(conditional-branch-cclr b ge I OP_0E OPE3_02 Ige NA "integer cclr branch greater or equal") 6005(conditional-branch-cclr b ls I OP_0E OPE3_02 Ils NA "integer cclr branch less or equal unsigned") 6006(conditional-branch-cclr b hi I OP_0E OPE3_02 Ihi NA "integer cclr branch greater unsigned") 6007(conditional-branch-cclr b c I OP_0E OPE3_02 Ic NA "integer cclr branch carry set") 6008(conditional-branch-cclr b nc I OP_0E OPE3_02 Inc NA "integer cclr branch carry clear") 6009(conditional-branch-cclr b n I OP_0E OPE3_02 In NA "integer cclr branch negative") 6010(conditional-branch-cclr b p I OP_0E OPE3_02 Ip NA "integer cclr branch positive") 6011(conditional-branch-cclr b v I OP_0E OPE3_02 Iv NA "integer cclr branch overflow set") 6012(conditional-branch-cclr b nv I OP_0E OPE3_02 Inv NA "integer cclr branch overflow clear") 6013 6014(dni fbralr 6015 "float cclr branch always" 6016 ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) 6017 (FR400-MAJOR B-3) (FR450-MAJOR B-3) FR-ACCESS) 6018 "fbralr$pack$hint_taken" 6019 (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_06 (ccond-null) (s12-null)) 6020 (sequence () 6021 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) 6022 (set pc (spr-lr))) 6023 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6024 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6025) 6026 6027(dni fbnolr 6028 "float cclr branch never" 6029 ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) 6030 (FR400-MAJOR B-3) (FR450-MAJOR B-3) FR-ACCESS) 6031 "fbnolr$pack$hint_not_taken" 6032 (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_06 (ccond-null) (s12-null)) 6033 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) 6034 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6035 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6036) 6037 6038(conditional-branch-cclr fb eq F OP_0E OPE3_06 Feq FR-ACCESS "float cclr branch equal") 6039(conditional-branch-cclr fb ne F OP_0E OPE3_06 Fne FR-ACCESS "float cclr branch not equal") 6040(conditional-branch-cclr fb lg F OP_0E OPE3_06 Flg FR-ACCESS "float branch less or greater") 6041(conditional-branch-cclr fb ue F OP_0E OPE3_06 Fue FR-ACCESS "float branch unordered or equal") 6042(conditional-branch-cclr fb ul F OP_0E OPE3_06 Ful FR-ACCESS "float branch unordered or less") 6043(conditional-branch-cclr fb ge F OP_0E OPE3_06 Fge FR-ACCESS "float branch greater or equal") 6044(conditional-branch-cclr fb lt F OP_0E OPE3_06 Flt FR-ACCESS "float branch less") 6045(conditional-branch-cclr fb uge F OP_0E OPE3_06 Fuge FR-ACCESS "float branch unordered, greater, equal") 6046(conditional-branch-cclr fb ug F OP_0E OPE3_06 Fug FR-ACCESS "float branch unordered or greater") 6047(conditional-branch-cclr fb le F OP_0E OPE3_06 Fle FR-ACCESS "float branch less or equal") 6048(conditional-branch-cclr fb gt F OP_0E OPE3_06 Fgt FR-ACCESS "float branch greater") 6049(conditional-branch-cclr fb ule F OP_0E OPE3_06 Fule FR-ACCESS "float branch unordered, less or equal") 6050(conditional-branch-cclr fb u F OP_0E OPE3_06 Fu FR-ACCESS "float branch unordered") 6051(conditional-branch-cclr fb o F OP_0E OPE3_06 Fo FR-ACCESS "float branch ordered") 6052 6053(define-pmacro (conditional-branch-ctrlr prefix cc i-f op ope cond attr comment) 6054 (dni (.sym prefix cc lr) 6055 (comment) 6056 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) 6057 (FR400-MAJOR B-2) (FR450-MAJOR B-2) attr) 6058 (.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$ccond,$hint") 6059 (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope ccond (s12-null)) 6060 (sequence () 6061 (c-call VOID "@cpu@_model_branch" (spr-lr) hint) 6062 (ctrlr-branch-semantics (cond (.sym i-f CCi_2)) ccond)) 6063 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6064 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6065 ) 6066) 6067 6068(dni bcralr 6069 "integer ctrlr branch always" 6070 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) 6071 (FR400-MAJOR B-2) (FR450-MAJOR B-2)) 6072 "bcralr$pack $ccond$hint_taken" 6073 (+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_03 ccond (s12-null)) 6074 (sequence () 6075 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) 6076 (ctrlr-branch-semantics (const BI 1) ccond)) 6077 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6078 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6079) 6080 6081(dni bcnolr 6082 "integer ctrlr branch never" 6083 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) 6084 (FR400-MAJOR B-2) (FR450-MAJOR B-2)) 6085 "bcnolr$pack$hint_not_taken" 6086 (+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_03 (ccond-null) (s12-null)) 6087 (sequence () 6088 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) 6089 (ctrlr-branch-semantics (const BI 0) ccond)) 6090 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6091 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6092) 6093 6094(conditional-branch-ctrlr bc eq I OP_0E OPE3_03 Ieq NA "integer ctrlr branch equal") 6095(conditional-branch-ctrlr bc ne I OP_0E OPE3_03 Ine NA "integer ctrlr branch not equal") 6096(conditional-branch-ctrlr bc le I OP_0E OPE3_03 Ile NA "integer ctrlr branch less equal") 6097(conditional-branch-ctrlr bc gt I OP_0E OPE3_03 Igt NA "integer ctrlr branch greater") 6098(conditional-branch-ctrlr bc lt I OP_0E OPE3_03 Ilt NA "integer ctrlr branch less") 6099(conditional-branch-ctrlr bc ge I OP_0E OPE3_03 Ige NA "integer ctrlr branch greater equal") 6100(conditional-branch-ctrlr bc ls I OP_0E OPE3_03 Ils NA "integer ctrlr branch less equal unsigned") 6101(conditional-branch-ctrlr bc hi I OP_0E OPE3_03 Ihi NA "integer ctrlr branch greater unsigned") 6102(conditional-branch-ctrlr bc c I OP_0E OPE3_03 Ic NA "integer ctrlr branch carry set") 6103(conditional-branch-ctrlr bc nc I OP_0E OPE3_03 Inc NA "integer ctrlr branch carry clear") 6104(conditional-branch-ctrlr bc n I OP_0E OPE3_03 In NA "integer ctrlr branch negative") 6105(conditional-branch-ctrlr bc p I OP_0E OPE3_03 Ip NA "integer ctrlr branch positive") 6106(conditional-branch-ctrlr bc v I OP_0E OPE3_03 Iv NA "integer ctrlr branch overflow set") 6107(conditional-branch-ctrlr bc nv I OP_0E OPE3_03 Inv NA "integer ctrlr branch overflow clear") 6108 6109(dni fcbralr 6110 "float ctrlr branch always" 6111 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) 6112 (FR400-MAJOR B-2) (FR450-MAJOR B-2) FR-ACCESS) 6113 "fcbralr$pack $ccond$hint_taken" 6114 (+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_07 ccond (s12-null)) 6115 (sequence () 6116 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken) 6117 (ctrlr-branch-semantics (const BI 1) ccond)) 6118 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6119 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6120) 6121 6122(dni fcbnolr 6123 "float ctrlr branch never" 6124 ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) 6125 (FR400-MAJOR B-2) (FR450-MAJOR B-2) FR-ACCESS) 6126 "fcbnolr$pack$hint_not_taken" 6127 (+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_07 (ccond-null) (s12-null)) 6128 (sequence () 6129 (c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken) 6130 (ctrlr-branch-semantics (const BI 0) ccond)) 6131 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6132 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6133) 6134 6135(conditional-branch-ctrlr fcb eq F OP_0E OPE3_07 Feq FR-ACCESS "float cclr branch equal") 6136(conditional-branch-ctrlr fcb ne F OP_0E OPE3_07 Fne FR-ACCESS "float cclr branch not equal") 6137(conditional-branch-ctrlr fcb lg F OP_0E OPE3_07 Flg FR-ACCESS "float branch less or greater") 6138(conditional-branch-ctrlr fcb ue F OP_0E OPE3_07 Fue FR-ACCESS "float branch unordered or equal") 6139(conditional-branch-ctrlr fcb ul F OP_0E OPE3_07 Ful FR-ACCESS "float branch unordered or less") 6140(conditional-branch-ctrlr fcb ge F OP_0E OPE3_07 Fge FR-ACCESS "float branch greater or equal") 6141(conditional-branch-ctrlr fcb lt F OP_0E OPE3_07 Flt FR-ACCESS "float branch less") 6142(conditional-branch-ctrlr fcb uge F OP_0E OPE3_07 Fuge FR-ACCESS "float branch unordered, greater, equal") 6143(conditional-branch-ctrlr fcb ug F OP_0E OPE3_07 Fug FR-ACCESS "float branch unordered or greater") 6144(conditional-branch-ctrlr fcb le F OP_0E OPE3_07 Fle FR-ACCESS "float branch less or equal") 6145(conditional-branch-ctrlr fcb gt F OP_0E OPE3_07 Fgt FR-ACCESS "float branch greater") 6146(conditional-branch-ctrlr fcb ule F OP_0E OPE3_07 Fule FR-ACCESS "float branch unordered, less or equal") 6147(conditional-branch-ctrlr fcb u F OP_0E OPE3_07 Fu FR-ACCESS "float branch unordered") 6148(conditional-branch-ctrlr fcb o F OP_0E OPE3_07 Fo FR-ACCESS "float branch ordered") 6149 6150(define-pmacro (jump-and-link-semantics base offset LI) 6151 (sequence () 6152 (if (eq LI 1) 6153 (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1)) 6154 ; Target address gets aligned here 6155 (set pc (and (add base offset) #xfffffffc)) 6156 (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken 6157) 6158 6159(dni jmpl 6160 "jump and link" 6161 ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) 6162 (FR400-MAJOR I-5) (FR450-MAJOR I-5)) 6163 "jmpl$pack @($GRi,$GRj)" 6164 (+ pack (misc-null-1) (LI-off) OP_0C GRi (misc-null-2) GRj) 6165 (jump-and-link-semantics GRi GRj LI) 6166 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6167 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6168) 6169 6170(dann callann "call annotation" SI "call_annotation" "at") 6171 6172(dni calll 6173 "call and link" 6174 ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) 6175 (FR400-MAJOR I-5) (FR450-MAJOR I-5)) 6176 "calll$pack $callann($GRi,$GRj)" 6177 (+ pack (misc-null-1) (LI-on) OP_0C GRi (misc-null-2) GRj) 6178 (jump-and-link-semantics GRi GRj LI) 6179 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6180 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6181) 6182 6183(dni jmpil 6184 "jump immediate and link" 6185 ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) 6186 (FR400-MAJOR I-5) (FR450-MAJOR I-5)) 6187 "jmpil$pack @($GRi,$s12)" 6188 (+ pack (misc-null-1) (LI-off) OP_0D GRi s12) 6189 (jump-and-link-semantics GRi s12 LI) 6190 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6191 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6192) 6193 6194(dni callil 6195 "call immediate and link" 6196 ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) 6197 (FR400-MAJOR I-5) (FR450-MAJOR I-5)) 6198 "callil$pack @($GRi,$s12)" 6199 (+ pack (misc-null-1) (LI-on) OP_0D GRi s12) 6200 (jump-and-link-semantics GRi s12 LI) 6201 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6202 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6203) 6204 6205(dni call 6206 "call and link" 6207 ((UNIT B0) (FR500-MAJOR B-4) (FR550-MAJOR B-4) 6208 (FR400-MAJOR B-4) (FR450-MAJOR B-4)) 6209 "call$pack $label24" 6210 (+ pack OP_0F label24) 6211 (sequence () 6212 (c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1) 6213 (set pc label24) 6214 (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken 6215 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6216 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6217) 6218 6219(dni rett 6220 "return from trap" 6221 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) 6222 (FR400-MAJOR C-2) (FR450-MAJOR C-2) PRIVILEGED) 6223 "rett$pack $debug" 6224 (+ pack (misc-null-1) debug OP_05 (rs-null) (s12-null)) 6225 ; frv_rett handles operating vs user mode 6226 (sequence () 6227 (set pc (c-call UWI "frv_rett" pc debug)) 6228 (c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken 6229 () 6230) 6231 6232(dni rei 6233 "run exception instruction" 6234 ((UNIT C) (FR500-MAJOR C-1) (MACH frv) PRIVILEGED) 6235 "rei$pack $eir" 6236 (+ pack (rd-null) OP_37 eir (s12-null)) 6237 (nop) ; for now 6238 () 6239) 6240 6241(define-pmacro (trap-semantics cond base offset) 6242 (if cond 6243 (sequence () 6244 ; This is defered to frv_itrap because for the breakpoint 6245 ; case we want to change as little of the machine state as 6246 ; possible. 6247 ; 6248 ; PCSR=PC 6249 ; PSR.PS=PSR.S 6250 ; PSR.ET=0 6251 ; if PSR.ESR==1 6252 ; SR0 through SR3=GR4 through GR7 6253 ; TBR.TT=0x80 + ((GRi + s12) & 0x7f) 6254 ; PC=TBR 6255 ; We still should indicate what is modified by this insn. 6256 (clobber (spr-pcsr)) 6257 (clobber psr_ps) 6258 (clobber psr_et) 6259 (clobber tbr_tt) 6260 (if (ne psr_esr (const 0)) 6261 (sequence () 6262 (clobber (spr-sr0)) 6263 (clobber (spr-sr1)) 6264 (clobber (spr-sr2)) 6265 (clobber (spr-sr3)))) 6266 ; frv_itrap handles operating vs user mode 6267 (c-call VOID "frv_itrap" pc base offset))) 6268) 6269 6270(define-pmacro (trap-r prefix cc i-f op ope cond attr comment) 6271 (dni (.sym prefix cc) 6272 (comment) 6273 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6274 (FR400-MAJOR C-1) (FR450-MAJOR C-1) attr) 6275 (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$GRj") 6276 (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi (misc-null-3) ope GRj) 6277 (trap-semantics (cond (.sym i-f CCi_2)) GRi GRj) 6278 ((fr400 (unit u-trap)) (fr450 (unit u-trap)) 6279 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 6280 ) 6281) 6282 6283(dni tra 6284 "integer trap always" 6285 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6286 (FR400-MAJOR C-1) (FR450-MAJOR C-1)) 6287 "tra$pack $GRi,$GRj" 6288 (+ pack ICC_ra (ICCi_2-null) OP_04 GRi (misc-null-3) OPE4_0 GRj) 6289 (trap-semantics (const BI 1) GRi GRj) 6290 ((fr400 (unit u-trap)) (fr450 (unit u-trap)) 6291 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 6292) 6293 6294(dni tno 6295 "integer trap never" 6296 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6297 (FR400-MAJOR C-1) (FR450-MAJOR C-1)) 6298 "tno$pack" 6299 (+ pack ICC_nev (ICCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_0 (GRj-null)) 6300 (trap-semantics (const BI 0) GRi GRj) 6301 ((fr400 (unit u-trap)) (fr450 (unit u-trap)) 6302 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 6303) 6304 6305(trap-r t eq I OP_04 OPE4_0 Ieq NA "integer trap equal") 6306(trap-r t ne I OP_04 OPE4_0 Ine NA "integer trap not equal") 6307(trap-r t le I OP_04 OPE4_0 Ile NA "integer trap less or equal") 6308(trap-r t gt I OP_04 OPE4_0 Igt NA "integer trap greater") 6309(trap-r t lt I OP_04 OPE4_0 Ilt NA "integer trap less") 6310(trap-r t ge I OP_04 OPE4_0 Ige NA "integer trap greater or equal") 6311(trap-r t ls I OP_04 OPE4_0 Ils NA "integer trap less or equal unsigned") 6312(trap-r t hi I OP_04 OPE4_0 Ihi NA "integer trap greater unsigned") 6313(trap-r t c I OP_04 OPE4_0 Ic NA "integer trap carry set") 6314(trap-r t nc I OP_04 OPE4_0 Inc NA "integer trap carry clear") 6315(trap-r t n I OP_04 OPE4_0 In NA "integer trap negative") 6316(trap-r t p I OP_04 OPE4_0 Ip NA "integer trap positive") 6317(trap-r t v I OP_04 OPE4_0 Iv NA "integer trap overflow set") 6318(trap-r t nv I OP_04 OPE4_0 Inv NA "integer trap overflow clear") 6319 6320(dni ftra 6321 "float trap always" 6322 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6323 (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) 6324 "ftra$pack $GRi,$GRj" 6325 (+ pack FCC_ra (FCCi_2-null) OP_04 GRi (misc-null-3) OPE4_1 GRj) 6326 (trap-semantics (const BI 1) GRi GRj) 6327 ((fr400 (unit u-trap)) (fr450 (unit u-trap)) 6328 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 6329) 6330 6331(dni ftno 6332 "flost trap never" 6333 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6334 (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) 6335 "ftno$pack" 6336 (+ pack FCC_nev (FCCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_1 (GRj-null)) 6337 (trap-semantics (const BI 0) GRi GRj) 6338 ((fr400 (unit u-trap)) (fr450 (unit u-trap)) 6339 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 6340) 6341 6342(trap-r ft ne F OP_04 OPE4_1 Fne FR-ACCESS "float trap not equal") 6343(trap-r ft eq F OP_04 OPE4_1 Feq FR-ACCESS "float trap equal") 6344(trap-r ft lg F OP_04 OPE4_1 Flg FR-ACCESS "float trap greater or less") 6345(trap-r ft ue F OP_04 OPE4_1 Fue FR-ACCESS "float trap unordered or equal") 6346(trap-r ft ul F OP_04 OPE4_1 Ful FR-ACCESS "float trap unordered or less") 6347(trap-r ft ge F OP_04 OPE4_1 Fge FR-ACCESS "float trap greater or equal") 6348(trap-r ft lt F OP_04 OPE4_1 Flt FR-ACCESS "float trap less") 6349(trap-r ft uge F OP_04 OPE4_1 Fuge FR-ACCESS "float trap unordered greater or equal") 6350(trap-r ft ug F OP_04 OPE4_1 Fug FR-ACCESS "float trap unordered or greater") 6351(trap-r ft le F OP_04 OPE4_1 Fle FR-ACCESS "float trap less or equal") 6352(trap-r ft gt F OP_04 OPE4_1 Fgt FR-ACCESS "float trap greater") 6353(trap-r ft ule F OP_04 OPE4_1 Fule FR-ACCESS "float trap unordered less or equal") 6354(trap-r ft u F OP_04 OPE4_1 Fu FR-ACCESS "float trap unordered") 6355(trap-r ft o F OP_04 OPE4_1 Fo FR-ACCESS "float trap ordered") 6356 6357(define-pmacro (trap-immed prefix cc i-f op cond attr comment) 6358 (dni (.sym prefix cc) 6359 (comment) 6360 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6361 (FR400-MAJOR C-1) (FR450-MAJOR C-1) attr) 6362 (.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$s12") 6363 (+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi s12) 6364 (trap-semantics (cond (.sym i-f CCi_2)) GRi s12) 6365 ((fr400 (unit u-trap)) (fr450 (unit u-trap)) 6366 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 6367 ) 6368) 6369 6370(dni tira 6371 "integer trap always" 6372 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6373 (FR400-MAJOR C-1) (FR450-MAJOR C-1)) 6374 "tira$pack $GRi,$s12" 6375 (+ pack ICC_ra (ICCi_2-null) OP_1C GRi s12) 6376 (trap-semantics (const BI 1) GRi s12) 6377 ((fr400 (unit u-trap)) (fr450 (unit u-trap)) 6378 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 6379) 6380 6381(dni tino 6382 "integer trap never" 6383 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6384 (FR400-MAJOR C-1) (FR450-MAJOR C-1)) 6385 "tino$pack" 6386 (+ pack ICC_nev (ICCi_2-null) OP_1C (GRi-null) (s12-null)) 6387 (trap-semantics (const BI 0) GRi s12) 6388 ((fr400 (unit u-trap)) (fr450 (unit u-trap)) 6389 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 6390) 6391 6392(trap-immed ti eq I OP_1C Ieq NA "integer trap equal") 6393(trap-immed ti ne I OP_1C Ine NA "integer trap not equal") 6394(trap-immed ti le I OP_1C Ile NA "integer trap less or equal") 6395(trap-immed ti gt I OP_1C Igt NA "integer trap greater") 6396(trap-immed ti lt I OP_1C Ilt NA "integer trap less") 6397(trap-immed ti ge I OP_1C Ige NA "integer trap greater or equal") 6398(trap-immed ti ls I OP_1C Ils NA "integer trap less or equal unsigned") 6399(trap-immed ti hi I OP_1C Ihi NA "integer trap greater unsigned") 6400(trap-immed ti c I OP_1C Ic NA "integer trap carry set") 6401(trap-immed ti nc I OP_1C Inc NA "integer trap carry clear") 6402(trap-immed ti n I OP_1C In NA "integer trap negative") 6403(trap-immed ti p I OP_1C Ip NA "integer trap positive") 6404(trap-immed ti v I OP_1C Iv NA "integer trap overflow set") 6405(trap-immed ti nv I OP_1C Inv NA "integer trap overflow clear") 6406 6407(dni ftira 6408 "float trap always" 6409 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6410 (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) 6411 "ftira$pack $GRi,$s12" 6412 (+ pack FCC_ra (ICCi_2-null) OP_1D GRi s12) 6413 (trap-semantics (const BI 1) GRi s12) 6414 ((fr400 (unit u-trap)) 6415 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 6416) 6417 6418(dni ftino 6419 "float trap never" 6420 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6421 (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) 6422 "ftino$pack" 6423 (+ pack FCC_nev (FCCi_2-null) OP_1D (GRi-null) (s12-null)) 6424 (trap-semantics (const BI 0) GRi s12) 6425 ((fr400 (unit u-trap)) (fr450 (unit u-trap)) 6426 (fr500 (unit u-trap)) (fr550 (unit u-trap))) 6427) 6428 6429(trap-immed fti ne F OP_1D Fne FR-ACCESS "float trap not equal") 6430(trap-immed fti eq F OP_1D Feq FR-ACCESS "float trap equal") 6431(trap-immed fti lg F OP_1D Flg FR-ACCESS "float trap greater or less") 6432(trap-immed fti ue F OP_1D Fue FR-ACCESS "float trap unordered or equal") 6433(trap-immed fti ul F OP_1D Ful FR-ACCESS "float trap unordered or less") 6434(trap-immed fti ge F OP_1D Fge FR-ACCESS "float trap greater or equal") 6435(trap-immed fti lt F OP_1D Flt FR-ACCESS "float trap less") 6436(trap-immed fti uge F OP_1D Fuge FR-ACCESS "float trap unordered greater or equal") 6437(trap-immed fti ug F OP_1D Fug FR-ACCESS "float trap unordered or greater") 6438(trap-immed fti le F OP_1D Fle FR-ACCESS "float trap less or equal") 6439(trap-immed fti gt F OP_1D Fgt FR-ACCESS "float trap greater") 6440(trap-immed fti ule F OP_1D Fule FR-ACCESS "float trap unordered less or equal") 6441(trap-immed fti u F OP_1D Fu FR-ACCESS "float trap unordered") 6442(trap-immed fti o F OP_1D Fo FR-ACCESS "float trap ordered") 6443 6444(dni break 6445 "break trap" 6446 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6447 (FR400-MAJOR C-1) (FR450-MAJOR C-1)) 6448 "break$pack" 6449 (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_3 (GRj-null)) 6450 (sequence () 6451 ; This is defered to frv_break because for the breakpoint 6452 ; case we want to change as little of the machine state as 6453 ; possible. 6454 ; 6455 ; BPCSR=PC 6456 ; BPSR.BS=PSR.S 6457 ; BPSR.BET=PSR.ET 6458 ; PSR.S=1 6459 ; PSR.ET=0 6460 ; TBR.TT=0xff 6461 ; PC=TBR 6462 ; We still should indicate what is modified by this insn. 6463 (clobber (spr-bpcsr)) 6464 (clobber bpsr_bs) 6465 (clobber bpsr_bet) 6466 (clobber psr_s) 6467 (clobber psr_et) 6468 (clobber tbr_tt) 6469 (c-call VOID "frv_break")) 6470 () 6471) 6472 6473(dni mtrap 6474 "media trap" 6475 ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) 6476 (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS) 6477 "mtrap$pack" 6478 (+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_2 (GRj-null)) 6479 (c-call VOID "frv_mtrap") 6480 () 6481) 6482 6483(define-pmacro (condition-code-logic name operation ope comment) 6484 (dni name 6485 (comment) 6486 ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) 6487 (FR400-MAJOR B-6) (FR450-MAJOR B-6)) 6488 (.str name "$pack $CRi,$CRj,$CRk") 6489 (+ pack (misc-null-6) CRk OP_0A (misc-null-7) CRi ope (misc-null-8) CRj) 6490 (set CRk (c-call UQI "@cpu@_cr_logic" operation CRi CRj)) 6491 () 6492 ) 6493) 6494(define-pmacro (op-andcr) 0) 6495(define-pmacro (op-orcr) 1) 6496(define-pmacro (op-xorcr) 2) 6497(define-pmacro (op-nandcr) 3) 6498(define-pmacro (op-norcr) 4) 6499(define-pmacro (op-andncr) 5) 6500(define-pmacro (op-orncr) 6) 6501(define-pmacro (op-nandncr) 7) 6502(define-pmacro (op-norncr) 8) 6503 6504(define-pmacro (cr-true) 3) 6505(define-pmacro (cr-false) 2) 6506(define-pmacro (cr-undefined) 0) 6507 6508(condition-code-logic andcr (op-andcr) OPE1_08 "and condition code regs") 6509(condition-code-logic orcr (op-orcr) OPE1_09 "or condition code regs") 6510(condition-code-logic xorcr (op-xorcr) OPE1_0A "xor condition code regs") 6511(condition-code-logic nandcr (op-nandcr) OPE1_0C "nand condition code regs") 6512(condition-code-logic norcr (op-norcr) OPE1_0D "nor condition code regs") 6513(condition-code-logic andncr (op-andncr) OPE1_10 "andn condition code regs") 6514(condition-code-logic orncr (op-orncr) OPE1_11 "orn condition code regs") 6515(condition-code-logic nandncr (op-nandncr) OPE1_14 "nandn condition code regs") 6516(condition-code-logic norncr (op-norncr) OPE1_15 "norn condition code regs") 6517 6518(dni notcr 6519 ("not cccr register") 6520 ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) 6521 (FR400-MAJOR B-6) (FR450-MAJOR B-6)) 6522 (.str notcr "$pack $CRj,$CRk") 6523 (+ pack (misc-null-6) CRk OP_0A (rs-null) OPE1_0B (misc-null-8) CRj) 6524 (set CRk (xor CRj 1)) 6525 () 6526) 6527 6528(define-pmacro (check-semantics cond cr) 6529 (if cond (set cr (cr-true)) (set cr (cr-false))) 6530) 6531 6532(define-pmacro (check-int-condition-code prefix cc op cond comment) 6533 (dni (.sym prefix cc) 6534 (comment) 6535 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6536 (FR400-MAJOR B-5) (FR450-MAJOR B-5)) 6537 (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int") 6538 (+ pack (.sym ICC_ cc) CRj_int op (misc-null-5) ICCi_3) 6539 (check-semantics (cond ICCi_3) CRj_int) 6540 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6541 (fr500 (unit u-check)) (fr550 (unit u-check))) 6542 ) 6543) 6544 6545(dni ckra 6546 "check integer cc always" 6547 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6548 (FR400-MAJOR B-5) (FR450-MAJOR B-5)) 6549 "ckra$pack $CRj_int" 6550 (+ pack ICC_ra CRj_int OP_08 (misc-null-5) (ICCi_3-null)) 6551 (check-semantics (const BI 1) CRj_int) 6552 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6553 (fr500 (unit u-check)) (fr550 (unit u-check))) 6554) 6555 6556(dni ckno 6557 "check integer cc never" 6558 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6559 (FR400-MAJOR B-5) (FR450-MAJOR B-5)) 6560 "ckno$pack $CRj_int" 6561 (+ pack ICC_nev CRj_int OP_08 (misc-null-5) (ICCi_3-null)) 6562 (check-semantics (const BI 0) CRj_int) 6563 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6564 (fr500 (unit u-check)) (fr550 (unit u-check))) 6565) 6566 6567(check-int-condition-code ck eq OP_08 Ieq "check integer cc equal") 6568(check-int-condition-code ck ne OP_08 Ine "check integer cc not equal") 6569(check-int-condition-code ck le OP_08 Ile "check integer cc less or equal") 6570(check-int-condition-code ck gt OP_08 Igt "check integer cc greater") 6571(check-int-condition-code ck lt OP_08 Ilt "check integer cc less") 6572(check-int-condition-code ck ge OP_08 Ige "check integer cc greater or equal") 6573(check-int-condition-code ck ls OP_08 Ils "check integer cc less or equal unsigned") 6574(check-int-condition-code ck hi OP_08 Ihi "check integer cc greater unsigned") 6575(check-int-condition-code ck c OP_08 Ic "check integer cc carry set") 6576(check-int-condition-code ck nc OP_08 Inc "check integer cc carry clear") 6577(check-int-condition-code ck n OP_08 In "check integer cc negative") 6578(check-int-condition-code ck p OP_08 Ip "check integer cc positive") 6579(check-int-condition-code ck v OP_08 Iv "check integer cc overflow set") 6580(check-int-condition-code ck nv OP_08 Inv "check integer cc overflow clear") 6581 6582(define-pmacro (check-float-condition-code prefix cc op cond comment) 6583 (dni (.sym prefix cc) 6584 (comment) 6585 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6586 (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS) 6587 (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float") 6588 (+ pack (.sym FCC_ cc) CRj_float op (misc-null-5) FCCi_3) 6589 (check-semantics (cond FCCi_3) CRj_float) 6590 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6591 (fr500 (unit u-check)) (fr550 (unit u-check))) 6592 ) 6593) 6594 6595(dni fckra 6596 "check float cc always" 6597 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6598 (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS) 6599 "fckra$pack $CRj_float" 6600 (+ pack FCC_ra CRj_float OP_09 (misc-null-5) FCCi_3) 6601 (check-semantics (const BI 1) CRj_float) 6602 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6603 (fr500 (unit u-check)) (fr550 (unit u-check))) 6604) 6605 6606(dni fckno 6607 "check float cc never" 6608 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6609 (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS) 6610 "fckno$pack $CRj_float" 6611 (+ pack FCC_nev CRj_float OP_09 (misc-null-5) FCCi_3) 6612 (check-semantics (const BI 0) CRj_float) 6613 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6614 (fr500 (unit u-check)) (fr550 (unit u-check))) 6615) 6616 6617(check-float-condition-code fck ne OP_09 Fne "check float cc not equal") 6618(check-float-condition-code fck eq OP_09 Feq "check float cc equal") 6619(check-float-condition-code fck lg OP_09 Flg "check float cc greater or less") 6620(check-float-condition-code fck ue OP_09 Fue "check float cc unordered or equal") 6621(check-float-condition-code fck ul OP_09 Ful "check float cc unordered or less") 6622(check-float-condition-code fck ge OP_09 Fge "check float cc greater or equal") 6623(check-float-condition-code fck lt OP_09 Flt "check float cc less") 6624(check-float-condition-code fck uge OP_09 Fuge "check float cc unordered greater or equal") 6625(check-float-condition-code fck ug OP_09 Fug "check float cc unordered or greater") 6626(check-float-condition-code fck le OP_09 Fle "check float cc less or equal") 6627(check-float-condition-code fck gt OP_09 Fgt "check float cc greater") 6628(check-float-condition-code fck ule OP_09 Fule "check float cc unordered less or equal") 6629(check-float-condition-code fck u OP_09 Fu "check float cc unordered") 6630(check-float-condition-code fck o OP_09 Fo "check float cc ordered") 6631 6632(define-pmacro (conditional-check-int-condition-code prefix cc op ope test comment) 6633 (dni (.sym prefix cc) 6634 (comment) 6635 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6636 (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL) 6637 (.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int,$CCi,$cond") 6638 (+ pack (.sym ICC_ cc) CRj_int op (rs-null) CCi cond ope 6639 (misc-null-9) ICCi_3) 6640 (if (eq CCi (or cond 2)) 6641 (check-semantics (test ICCi_3) CRj_int) 6642 (set CRj_int (cr-undefined))) 6643 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6644 (fr500 (unit u-check)) (fr550 (unit u-check))) 6645 ) 6646) 6647 6648(dni cckra 6649 "conditional check integer cc always" 6650 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6651 (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL) 6652 "cckra$pack $CRj_int,$CCi,$cond" 6653 (+ pack ICC_ra CRj_int OP_6A (rs-null) CCi cond OPE4_0 6654 (misc-null-9) (ICCi_3-null)) 6655 (if (eq CCi (or cond 2)) 6656 (check-semantics (const BI 1) CRj_int) 6657 (set CRj_int (cr-undefined))) 6658 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6659 (fr500 (unit u-check)) (fr550 (unit u-check))) 6660) 6661 6662(dni cckno 6663 "conditional check integer cc never" 6664 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6665 (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL) 6666 "cckno$pack $CRj_int,$CCi,$cond" 6667 (+ pack ICC_nev CRj_int OP_6A (rs-null) CCi cond OPE4_0 6668 (misc-null-9) (ICCi_3-null)) 6669 (if (eq CCi (or cond 2)) 6670 (check-semantics (const BI 0) CRj_int) 6671 (set CRj_int (cr-undefined))) 6672 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6673 (fr500 (unit u-check)) (fr550 (unit u-check))) 6674) 6675 6676(conditional-check-int-condition-code cck eq OP_6A OPE4_0 Ieq "check integer cc equal") 6677(conditional-check-int-condition-code cck ne OP_6A OPE4_0 Ine "check integer cc not equal") 6678(conditional-check-int-condition-code cck le OP_6A OPE4_0 Ile "check integer cc less or equal") 6679(conditional-check-int-condition-code cck gt OP_6A OPE4_0 Igt "check integer cc greater") 6680(conditional-check-int-condition-code cck lt OP_6A OPE4_0 Ilt "check integer cc less") 6681(conditional-check-int-condition-code cck ge OP_6A OPE4_0 Ige "check integer cc greater or equal") 6682(conditional-check-int-condition-code cck ls OP_6A OPE4_0 Ils "check integer cc less or equal unsigned") 6683(conditional-check-int-condition-code cck hi OP_6A OPE4_0 Ihi "check integer cc greater unsigned") 6684(conditional-check-int-condition-code cck c OP_6A OPE4_0 Ic "check integer cc carry set") 6685(conditional-check-int-condition-code cck nc OP_6A OPE4_0 Inc "check integer cc carry clear") 6686(conditional-check-int-condition-code cck n OP_6A OPE4_0 In "check integer cc negative") 6687(conditional-check-int-condition-code cck p OP_6A OPE4_0 Ip "check integer cc positive") 6688(conditional-check-int-condition-code cck v OP_6A OPE4_0 Iv "check integer cc overflow set") 6689(conditional-check-int-condition-code cck nv OP_6A OPE4_0 Inv "check integer cc overflow clear") 6690 6691(define-pmacro (conditional-check-float-condition-code prefix cc op ope test comment) 6692 (dni (.sym prefix cc) 6693 (comment) 6694 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6695 (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS) 6696 (.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float,$CCi,$cond") 6697 (+ pack (.sym FCC_ cc) CRj_float op (rs-null) CCi cond ope 6698 (misc-null-9) FCCi_3) 6699 (if (eq CCi (or cond 2)) 6700 (check-semantics (test FCCi_3) CRj_float) 6701 (set CRj_float (cr-undefined))) 6702 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6703 (fr500 (unit u-check)) (fr550 (unit u-check))) 6704 ) 6705) 6706 6707(dni cfckra 6708 "conditional check float cc always" 6709 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6710 (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS) 6711 "cfckra$pack $CRj_float,$CCi,$cond" 6712 (+ pack FCC_ra CRj_float OP_6A (rs-null) CCi cond OPE4_1 6713 (misc-null-9) (FCCi_3-null)) 6714 (if (eq CCi (or cond 2)) 6715 (check-semantics (const BI 1) CRj_float) 6716 (set CRj_float (cr-undefined))) 6717 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6718 (fr500 (unit u-check)) (fr550 (unit u-check))) 6719) 6720 6721(dni cfckno 6722 "conditional check float cc never" 6723 ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) 6724 (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS) 6725 "cfckno$pack $CRj_float,$CCi,$cond" 6726 (+ pack FCC_nev CRj_float OP_6A (rs-null) CCi cond OPE4_1 6727 (misc-null-9) (FCCi_3-null)) 6728 (if (eq CCi (or cond 2)) 6729 (check-semantics (const BI 0) CRj_float) 6730 (set CRj_float (cr-undefined))) 6731 ((fr400 (unit u-check)) (fr450 (unit u-check)) 6732 (fr500 (unit u-check)) (fr550 (unit u-check))) 6733) 6734 6735(conditional-check-float-condition-code cfck ne OP_6A OPE4_1 Fne "check float cc not equal") 6736(conditional-check-float-condition-code cfck eq OP_6A OPE4_1 Feq "check float cc equal") 6737(conditional-check-float-condition-code cfck lg OP_6A OPE4_1 Flg "check float cc greater or less") 6738(conditional-check-float-condition-code cfck ue OP_6A OPE4_1 Fue "check float cc unordered or equal") 6739(conditional-check-float-condition-code cfck ul OP_6A OPE4_1 Ful "check float cc unordered or less") 6740(conditional-check-float-condition-code cfck ge OP_6A OPE4_1 Fge "check float cc greater or equal") 6741(conditional-check-float-condition-code cfck lt OP_6A OPE4_1 Flt "check float cc less") 6742(conditional-check-float-condition-code cfck uge OP_6A OPE4_1 Fuge "check float cc unordered greater or equal") 6743(conditional-check-float-condition-code cfck ug OP_6A OPE4_1 Fug "check float cc unordered or greater") 6744(conditional-check-float-condition-code cfck le OP_6A OPE4_1 Fle "check float cc less or equal") 6745(conditional-check-float-condition-code cfck gt OP_6A OPE4_1 Fgt "check float cc greater") 6746(conditional-check-float-condition-code cfck ule OP_6A OPE4_1 Fule "check float cc unordered less or equal") 6747(conditional-check-float-condition-code cfck u OP_6A OPE4_1 Fu "check float cc unordered") 6748(conditional-check-float-condition-code cfck o OP_6A OPE4_1 Fo "check float cc ordered") 6749 6750(dni cjmpl 6751 "conditional jump and link" 6752 ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) 6753 (FR400-MAJOR I-5) (FR450-MAJOR I-5) CONDITIONAL) 6754 "cjmpl$pack @($GRi,$GRj),$CCi,$cond" 6755 (+ pack (misc-null-1) (LI-off) OP_6A GRi CCi cond OPE4_2 GRj) 6756 (if (eq CCi (or cond 2)) 6757 (jump-and-link-semantics GRi GRj LI)) 6758 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6759 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6760) 6761 6762(dni ccalll 6763 "conditional call and link" 6764 ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) 6765 (FR400-MAJOR I-5) (FR450-MAJOR I-5) CONDITIONAL) 6766 "ccalll$pack @($GRi,$GRj),$CCi,$cond" 6767 (+ pack (misc-null-1) (LI-on) OP_6A GRi CCi cond OPE4_2 GRj) 6768 (if (eq CCi (or cond 2)) 6769 (jump-and-link-semantics GRi GRj LI)) 6770 ((fr400 (unit u-branch)) (fr450 (unit u-branch)) 6771 (fr500 (unit u-branch)) (fr550 (unit u-branch))) 6772) 6773 6774(define-pmacro (cache-invalidate name cache all op ope profile comment) 6775 (dni name 6776 (comment) 6777 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) 6778 (FR400-MAJOR C-2) (FR450-MAJOR C-2)) 6779 (.str name "$pack @($GRi,$GRj)") 6780 (+ pack (rd-null) op GRi ope GRj) 6781 (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) all) 6782 profile 6783 ) 6784) 6785 6786(cache-invalidate ici insn 0 OP_03 OPE1_38 6787 ((fr400 (unit u-ici)) (fr450 (unit u-ici)) 6788 (fr500 (unit u-ici)) (fr550 (unit u-ici))) 6789 "invalidate insn cache") 6790(cache-invalidate dci data 0 OP_03 OPE1_3C 6791 ((fr400 (unit u-dci)) (fr450 (unit u-dci)) 6792 (fr500 (unit u-dci)) (fr550 (unit u-dci))) 6793 "invalidate data cache") 6794 6795(define-pmacro (cache-invalidate-entry name cache op ope profile comment) 6796 (dni name 6797 (comment) 6798 ((UNIT C) (MACH fr400,fr450,fr550) (FR550-MAJOR C-2) 6799 (FR400-MAJOR C-2) (FR450-MAJOR C-2)) 6800 (.str name "$pack @($GRi,$GRj),$ae") 6801 (+ pack (misc-null-1) ae op GRi ope GRj) 6802 (if (eq ae 0) 6803 (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) -1) ; Invalid ae setting for this insn 6804 (c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) ae)) 6805 profile 6806 ) 6807) 6808 6809(cache-invalidate-entry icei insn OP_03 OPE1_39 6810 ((fr400 (unit u-ici)) (fr450 (unit u-ici)) 6811 (fr550 (unit u-ici))) 6812 "invalidate insn cache entry") 6813(cache-invalidate-entry dcei data OP_03 OPE1_3A 6814 ((fr400 (unit u-dci)) (fr450 (unit u-dci)) 6815 (fr550 (unit u-dci))) 6816 "invalidate data cache entry") 6817 6818(dni dcf 6819 "Data cache flush" 6820 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) 6821 (FR400-MAJOR C-2) (FR450-MAJOR C-2)) 6822 "dcf$pack @($GRi,$GRj)" 6823 (+ pack (rd-null) OP_03 GRi OPE1_3D GRj) 6824 (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) 0) 6825 ((fr400 (unit u-dcf)) (fr450 (unit u-dcf)) 6826 (fr500 (unit u-dcf)) (fr550 (unit u-dcf))) 6827) 6828 6829(dni dcef 6830 "Data cache entry flush" 6831 ((UNIT C) (MACH fr400,fr450,fr550) (FR550-MAJOR C-2) 6832 (FR400-MAJOR C-2) (FR450-MAJOR C-2)) 6833 "dcef$pack @($GRi,$GRj),$ae" 6834 (+ pack (misc-null-1) ae OP_03 GRi OPE1_3B GRj) 6835 (if (eq ae 0) 6836 (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) -1) 6837 (c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) ae)) 6838 ((fr400 (unit u-dcf)) (fr450 (unit u-dcf)) (fr550 (unit u-dcf))) 6839) 6840 6841(define-pmacro (write-TLB name insn op ope comment) 6842 (dni name 6843 (comment) 6844 ((UNIT C) (FR500-MAJOR C-2) (MACH frv) PRIVILEGED) 6845 (.str insn "$pack $GRk,@($GRi,$GRj)") 6846 (+ pack GRk op GRi ope GRj) 6847 (nop) ; for now 6848 () 6849 ) 6850) 6851 6852(write-TLB witlb witlb OP_03 OPE1_32 "write for insn TLB") 6853(write-TLB wdtlb wdtlb OP_03 OPE1_36 "write for data TLB") 6854 6855(define-pmacro (invalidate-TLB name insn op ope comment) 6856 (dni name 6857 (comment) 6858 ((UNIT C) (FR500-MAJOR C-2) (MACH frv) PRIVILEGED) 6859 (.str insn "$pack @($GRi,$GRj)") 6860 (+ pack (rd-null) op GRi ope GRj) 6861 (nop) ; for now 6862 () 6863 ) 6864) 6865 6866(invalidate-TLB itlbi itlbi OP_03 OPE1_33 "invalidate insn TLB") 6867(invalidate-TLB dtlbi dtlbi OP_03 OPE1_37 "invalidate data TLB") 6868 6869(define-pmacro (cache-preload name cache pipe attrs op ope profile comment) 6870 (dni name 6871 (comment) 6872 (.splice (UNIT pipe) (FR500-MAJOR C-2) 6873 (FR400-MAJOR C-2) (.unsplice attrs)) 6874 (.str name "$pack $GRi,$GRj,$lock") 6875 (+ pack (misc-null-1) lock op GRi ope GRj) 6876 (c-call VOID (.str "@cpu@_" cache "_cache_preload") GRi GRj lock) 6877 profile 6878 ) 6879) 6880 6881(cache-preload icpl insn C ((FR550-MAJOR C-2) (FR450-MAJOR C-2)) OP_03 OPE1_30 6882 ((fr400 (unit u-icpl)) (fr450 (unit u-icpl)) 6883 (fr500 (unit u-icpl)) (fr550 (unit u-icpl))) 6884 "preload insn cache") 6885(cache-preload dcpl data DCPL ((FR550-MAJOR I-8) (FR450-MAJOR I-2)) OP_03 OPE1_34 6886 ((fr400 (unit u-dcpl)) (fr450 (unit u-dcpl)) 6887 (fr500 (unit u-dcpl)) (fr550 (unit u-dcpl))) 6888 "preload data cache") 6889 6890(define-pmacro (cache-unlock name cache op ope profile comment) 6891 (dni name 6892 (comment) 6893 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) 6894 (FR400-MAJOR C-2) (FR450-MAJOR C-2)) 6895 (.str name "$pack $GRi") 6896 (+ pack (rd-null) op GRi ope (GRj-null)) 6897 (c-call VOID (.str "@cpu@_" cache "_cache_unlock") GRi) 6898 profile 6899 ) 6900) 6901 6902(cache-unlock icul insn OP_03 OPE1_31 6903 ((fr400 (unit u-icul)) (fr450 (unit u-icul)) 6904 (fr500 (unit u-icul)) (fr550 (unit u-icul))) 6905 "unlock insn cache") 6906(cache-unlock dcul data OP_03 OPE1_35 6907 ((fr400 (unit u-dcul)) (fr450 (unit u-dcul)) 6908 (fr500 (unit u-dcul)) (fr550 (unit u-dcul))) 6909 "unlock data cache") 6910 6911(define-pmacro (barrier name insn op ope profile comment) 6912 (dni name 6913 (comment) 6914 ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) 6915 (FR400-MAJOR C-2) (FR450-MAJOR C-2)) 6916 (.str insn "$pack") 6917 (+ pack (rd-null) op (rs-null) ope (GRj-null)) 6918 (nop) ; sufficient implementation 6919 profile 6920 ) 6921) 6922 6923(barrier bar bar OP_03 OPE1_3E 6924 ((fr400 (unit u-barrier)) (fr450 (unit u-barrier)) 6925 (fr500 (unit u-barrier))) 6926 "barrier") 6927(barrier membar membar OP_03 OPE1_3F 6928 ((fr400 (unit u-membar)) (fr450 (unit u-membar)) 6929 (fr500 (unit u-membar))) 6930 "memory barrier") 6931 6932; Load real address instructions 6933(define-pmacro (load-real-address name insn what op ope) 6934 (dni name 6935 (.str "Load real address of " what) 6936 ((UNIT C) (FR450-MAJOR C-2) (MACH fr450)) 6937 (.str insn "$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS") 6938 (+ pack GRk op GRi ope LRAE LRAD LRAS (LRA-null)) 6939 (nop) ; not simulated 6940 () 6941 ) 6942) 6943 6944(load-real-address lrai "lrai" "instruction" OP_03 OPE1_20) 6945(load-real-address lrad "lrad" "data" OP_03 OPE1_21) 6946 6947(dni tlbpr 6948 "TLB Probe" 6949 ((UNIT C) (FR450-MAJOR C-2) (MACH fr450)) 6950 "tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL" 6951 (+ pack (TLBPR-null) TLBPRopx TLBPRL OP_03 GRi OPE1_24 GRj) 6952 (nop) ; not simulated 6953 () 6954) 6955 6956; Coprocessor operations 6957(define-pmacro (cop-op num op) 6958 (dni (.sym cop num) 6959 "Coprocessor operation" 6960 ((UNIT C) (FR500-MAJOR C-2) (MACH frv)) 6961 (.str "cop" num "$pack $s6_1,$CPRi,$CPRj,$CPRk") 6962 (+ pack CPRk op CPRi s6_1 CPRj) 6963 (nop) ; sufficient implementation 6964 () 6965 ) 6966) 6967 6968(cop-op 1 OP_7E) 6969(cop-op 2 OP_7F) 6970 6971(define-pmacro (clear-ne-flag-semantics target_index is_float) 6972 (c-call VOID "@cpu@_clear_ne_flags" target_index is_float) 6973) 6974 6975(define-pmacro (clear-ne-flag-r name op ope reg is_float attr profile comment) 6976 (dni name 6977 (comment) 6978 ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH simple,tomcat,fr500,fr550,frv) attr) 6979 (.str name "$pack $" reg "k") 6980 (+ pack (.sym reg k) op (rs-null) ope (GRj-null)) 6981 (sequence () 6982 ; hack to get this referenced for profiling 6983 (c-raw-call VOID "frv_ref_SI" (.sym reg k)) 6984 (clear-ne-flag-semantics (index-of (.sym reg k)) is_float)) 6985 profile 6986 ) 6987) 6988 6989(clear-ne-flag-r clrgr OP_0A OPE1_00 GR 0 NA 6990 ((fr500 (unit u-clrgr)) (fr550 (unit u-clrgr))) 6991 "Clear GR NE flag") 6992(clear-ne-flag-r clrfr OP_0A OPE1_02 FR 1 FR-ACCESS 6993 ((fr500 (unit u-clrfr)) (fr550 (unit u-clrfr))) 6994 "Clear FR NE flag") 6995 6996(define-pmacro (clear-ne-flag-all name op ope is_float attr profile comment) 6997 (dni name 6998 (comment) 6999 ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH simple,tomcat,fr500,fr550,frv) attr) 7000 (.str name "$pack") 7001 (+ pack (rd-null) op (rs-null) ope (GRj-null)) 7002 (clear-ne-flag-semantics -1 is_float) 7003 profile 7004 ) 7005) 7006 7007(clear-ne-flag-all clrga OP_0A OPE1_01 0 NA 7008 ((fr500 (unit u-clrgr)) (fr550 (unit u-clrgr))) 7009 "Clear GR NE flag ALL") 7010(clear-ne-flag-all clrfa OP_0A OPE1_03 1 FR-ACCESS 7011 ((fr500 (unit u-clrfr)) (fr550 (unit u-clrfr))) 7012 "Clear FR NE flag ALL") 7013 7014(define-pmacro (commit-semantics target_index is_float) 7015 (c-call VOID "@cpu@_commit" target_index is_float) 7016) 7017 7018(define-pmacro (commit-r name op ope reg is_float attr comment) 7019 (dni name 7020 (comment) 7021 ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH frv,fr500,fr550) attr) 7022 (.str name "$pack $" reg "k") 7023 (+ pack (.sym reg k) op (rs-null) ope (GRj-null)) 7024 (commit-semantics (index-of (.sym reg k)) is_float) 7025 ((fr500 (unit u-commit)) (fr550 (unit u-commit))) 7026 ) 7027) 7028 7029(commit-r commitgr OP_0A OPE1_04 GR 0 NA "commit exceptions, specific GR") 7030(commit-r commitfr OP_0A OPE1_06 FR 1 FR-ACCESS "commit exceptions, specific FR") 7031 7032(define-pmacro (commit name op ope is_float attr comment) 7033 (dni name 7034 (comment) 7035 ((UNIT I01) (FR500-MAJOR I-6) (FR550-MAJOR I-7) (MACH frv,fr500,fr550) attr) 7036 (.str name "$pack") 7037 (+ pack (rd-null) op (rs-null) ope (GRj-null)) 7038 (commit-semantics -1 is_float) 7039 ((fr500 (unit u-commit)) (fr550 (unit u-commit))) 7040 ) 7041) 7042 7043(commit commitga OP_0A OPE1_05 0 NA "commit exceptions, any GR") 7044(commit commitfa OP_0A OPE1_07 1 FR-ACCESS "commit exceptions, any FR") 7045 7046(define-pmacro (floating-point-conversion 7047 name op ope conv mode src targ attr comment) 7048 (dni name 7049 (comment) 7050 (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) 7051 (.str name "$pack $" src ",$" targ) 7052 (+ pack targ op (rs-null) ope src) 7053 (set targ (conv mode FPCONV-DEFAULT src)) 7054 ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) 7055 ) 7056) 7057 7058(floating-point-conversion fitos OP_79 OPE1_00 float SF FRintj FRk 7059 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 7060 "Convert Integer to Single") 7061(floating-point-conversion fstoi OP_79 OPE1_01 fix SI FRj FRintk 7062 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 7063 "Convert Single to Integer") 7064(floating-point-conversion fitod OP_7A OPE1_00 float DF FRintj FRdoublek 7065 ((MACH frv)) 7066 "Convert Integer to Double") 7067(floating-point-conversion fdtoi OP_7A OPE1_01 fix SI FRdoublej FRintk 7068 ((MACH frv)) 7069 "Convert Double to Integer") 7070 7071(define-pmacro (floating-point-dual-conversion 7072 name op ope conv mode src src_hw targ targ_hw attr comment) 7073 (dni name 7074 (comment) 7075 ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1) attr) 7076 (.str name "$pack $" src ",$" targ) 7077 (+ pack targ op (rs-null) ope src) 7078 (sequence () 7079 (set targ (conv mode FPCONV-DEFAULT src)) 7080 (set (nextreg targ_hw targ 1) 7081 (conv mode FPCONV-DEFAULT (nextreg src_hw src 1)))) 7082 ((fr500 (unit u-float-dual-convert))) 7083 ) 7084) 7085 7086(floating-point-dual-conversion fditos OP_79 OPE1_10 float SF FRintj h-fr_int FRk h-fr NA "Dual Convert Integer to Single") 7087(floating-point-dual-conversion fdstoi OP_79 OPE1_11 fix SI FRj h-fr FRintk h-fr_int NA "Dual Convert Single to Integer") 7088 7089(define-pmacro (ne-floating-point-dual-conversion 7090 name op ope conv mode src src_hw targ targ_hw attr comment) 7091 (dni name 7092 (comment) 7093 ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1) NON-EXCEPTING attr) 7094 (.str name "$pack $" src ",$" targ) 7095 (+ pack targ op (rs-null) ope src) 7096 (sequence () 7097 (c-call VOID "@cpu@_set_ne_index" (index-of targ)) 7098 (set targ (conv mode FPCONV-DEFAULT src)) 7099 (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1)) 7100 (set (nextreg targ_hw targ 1) 7101 (conv mode FPCONV-DEFAULT (nextreg src_hw src 1)))) 7102 ((fr500 (unit u-float-dual-convert))) 7103 ) 7104) 7105 7106(ne-floating-point-dual-conversion nfditos OP_79 OPE1_30 float SF FRintj h-fr_int FRk h-fr NA "Non excepting dual Convert Integer to Single") 7107(ne-floating-point-dual-conversion nfdstoi OP_79 OPE1_31 fix SI FRj h-fr FRintk h-fr_int NA "Non excepting dual Convert Single to Integer") 7108 7109(define-pmacro (conditional-floating-point-conversion 7110 name op ope conv mode src targ comment) 7111 (dni name 7112 (comment) 7113 ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 7114 (.str name "$pack $" src ",$" targ ",$CCi,$cond") 7115 (+ pack targ op (rs-null) CCi cond ope src) 7116 (if (eq CCi (or cond 2)) 7117 (set targ (conv mode FPCONV-DEFAULT src))) 7118 ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) 7119 ) 7120) 7121 7122(conditional-floating-point-conversion cfitos OP_6B OPE4_0 float SF FRintj FRk "Conditional convert Integer to Single") 7123(conditional-floating-point-conversion cfstoi OP_6B OPE4_1 fix SI FRj FRintk "Conditional convert Single to Integer") 7124 7125(define-pmacro (ne-floating-point-conversion 7126 name op ope conv mode src targ comment) 7127 (dni name 7128 (comment) 7129 ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 7130 (.str name "$pack $" src ",$" targ) 7131 (+ pack targ op (rs-null) ope src) 7132 (sequence () 7133 (c-call VOID "@cpu@_set_ne_index" (index-of targ)) 7134 (set targ (conv mode FPCONV-DEFAULT src))) 7135 ((fr500 (unit u-float-convert)) (fr550 (unit u-float-convert))) 7136 ) 7137) 7138 7139(ne-floating-point-conversion nfitos OP_79 OPE1_20 float SF FRintj FRk "NE convert Integer to Single") 7140(ne-floating-point-conversion nfstoi OP_79 OPE1_21 fix SI FRj FRintk "NE convert Single to Integer") 7141 7142(register-transfer fmovs OP_79 OPE1_02 7143 FRj FRk FMALL 7144 ((FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 7145 ((fr500 (unit u-fr2fr))) 7146 "Move Single Float") 7147(register-transfer fmovd OP_7A OPE1_02 7148 ; TODO -- unit doesn't handle extra register 7149 FRdoublej FRdoublek FM01 7150 ((FR500-MAJOR F-1) (MACH frv)) 7151 ((fr500 (unit u-fr2fr)) (fr550 (unit u-fr2fr))) 7152 "Move Double Float") 7153 7154(dni fdmovs 7155 "Dual move single float" 7156 ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) 7157 "fdmovs$pack $FRj,$FRk" 7158 (+ pack FRk OP_79 (rs-null) OPE1_12 FRj) 7159 (sequence () 7160 (set FRk FRj) 7161 (set (nextreg h-fr FRk 1) (nextreg h-fr FRj 1))) 7162 ; TODO -- unit doesn't handle extra register 7163 ((fr500 (unit u-fr2fr))) 7164) 7165 7166(conditional-register-transfer cfmovs OP_6C OPE4_0 FRj FRk FMALL 7167 ((FR500-MAJOR F-1) (FR550-MAJOR F-2) 7168 (MACH simple,tomcat,fr500,fr550,frv)) 7169 ((fr500 (unit u-fr2fr)) (fr550 (unit u-fr2fr))) 7170 "Conditional move Single Float") 7171 7172(define-pmacro (floating-point-neg name src targ op ope attr comment) 7173 (dni name 7174 (comment) 7175 (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) 7176 (.str name "$pack $" src ",$" targ) 7177 (+ pack src op (rs-null) ope targ) 7178 (set targ (neg src)) 7179 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7180 ) 7181) 7182 7183(floating-point-neg fnegs FRj FRk OP_79 OPE1_03 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) "Floating point negate, single") 7184(floating-point-neg fnegd FRdoublej FRdoublek OP_7A OPE1_03 ((MACH frv)) "Floating point negate, double") 7185 7186(dni fdnegs 7187 "Floating point dual negate, single" 7188 ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) 7189 "fdnegs$pack $FRj,$FRk" 7190 (+ pack FRk OP_79 (rs-null) OPE1_13 FRj) 7191 (sequence () 7192 (set FRk (neg FRj)) 7193 (set (nextreg h-fr FRk 1) (neg (nextreg h-fr FRj 1)))) 7194 ((fr500 (unit u-float-dual-arith))) 7195) 7196 7197(dni cfnegs 7198 "Conditional floating point negate, single" 7199 ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 7200 "cfnegs$pack $FRj,$FRk,$CCi,$cond" 7201 (+ pack FRj OP_6C (rs-null) CCi cond OPE4_1 FRk) 7202 (if (eq CCi (or cond 2)) 7203 (set FRk (neg FRj))) 7204 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7205) 7206 7207(define-pmacro (float-abs name src targ op ope attr comment) 7208 (dni name 7209 (comment) 7210 (.splice (UNIT FMALL) (FR500-MAJOR F-1) (.unsplice attr)) 7211 (.str name "$pack $" src ",$" targ ) 7212 (+ pack targ op (rs-null) ope src) 7213 (set targ (abs src)) 7214 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7215 ) 7216) 7217 7218(float-abs fabss FRj FRk OP_79 OPE1_04 ((FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) "Float absolute value, single") 7219(float-abs fabsd FRdoublej FRdoublek OP_7A OPE1_04 ((MACH frv)) "Float absolute value, double") 7220 7221(dni fdabss 7222 "Floating point dual absolute value, single" 7223 ((MACH frv) (UNIT FMALL) (FR500-MAJOR F-1)) 7224 "fdabss$pack $FRj,$FRk" 7225 (+ pack FRk OP_79 (rs-null) OPE1_14 FRj) 7226 (sequence () 7227 (set FRk (abs FRj)) 7228 (set (nextreg h-fr FRk 1) (abs (nextreg h-fr FRj 1)))) 7229 ((fr500 (unit u-float-dual-arith))) 7230) 7231 7232(dni cfabss 7233 "Conditional floating point absolute value, single" 7234 ((UNIT FMALL) (FR500-MAJOR F-1) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 7235 "cfabss$pack $FRj,$FRk,$CCi,$cond" 7236 (+ pack FRj OP_6C (rs-null) CCi cond OPE4_2 FRk) 7237 (if (eq CCi (or cond 2)) 7238 (set FRk (abs FRj))) 7239 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7240) 7241 7242(dni fsqrts 7243 "Square root single" 7244 ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) 7245 "fsqrts$pack $FRj,$FRk" 7246 (+ pack FRk OP_79 (rs-null) OPE1_05 FRj) 7247 (set FRk (sqrt SF FRj)) 7248 ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) 7249) 7250 7251(dni fdsqrts 7252 "Dual square root single" 7253 ((MACH frv) (UNIT FM01) (FR500-MAJOR F-4)) 7254 "fdsqrts$pack $FRj,$FRk" 7255 (+ pack FRk OP_79 (rs-null) OPE1_15 FRj) 7256 (sequence () 7257 (set FRk (sqrt SF FRj)) 7258 (set (nextreg h-fr FRk 1) (sqrt (nextreg h-fr FRj 1)))) 7259 ((fr500 (unit u-float-dual-sqrt))) 7260) 7261 7262(dni nfdsqrts 7263 "Non excepting Dual square root single" 7264 ((MACH frv) (UNIT FM01) (FR500-MAJOR F-4) NON-EXCEPTING) 7265 "nfdsqrts$pack $FRj,$FRk" 7266 (+ pack FRk OP_79 (rs-null) OPE1_35 FRj) 7267 (sequence () 7268 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7269 (set FRk (sqrt SF FRj)) 7270 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 7271 (set (nextreg h-fr FRk 1) (sqrt (nextreg h-fr FRj 1)))) 7272 ((fr500 (unit u-float-dual-sqrt))) 7273) 7274 7275(dni fsqrtd 7276 "Square root double" 7277 ((UNIT FM01) (FR500-MAJOR F-4) (MACH frv)) 7278 "fsqrtd$pack $FRdoublej,$FRdoublek" 7279 (+ pack FRdoublek OP_7A (rs-null) OPE1_05 FRdoublej) 7280 (set FRdoublek (sqrt DF FRdoublej)) 7281 ((fr500 (unit u-float-sqrt))) 7282) 7283 7284(dni cfsqrts 7285 "Conditional square root single" 7286 ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) 7287 "cfsqrts$pack $FRj,$FRk,$CCi,$cond" 7288 (+ pack FRk OP_6E (rs-null) CCi cond OPE4_2 FRj) 7289 (if (eq CCi (or cond 2)) 7290 (set FRk (sqrt SF FRj))) 7291 ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) 7292) 7293 7294(dni nfsqrts 7295 "Non exception square root, single" 7296 ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) 7297 "nfsqrts$pack $FRj,$FRk" 7298 (+ pack FRk OP_79 (rs-null) OPE1_25 FRj) 7299 (sequence () 7300 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7301 (set FRk (sqrt SF FRj))) 7302 ((fr500 (unit u-float-sqrt)) (fr550 (unit u-float-sqrt))) 7303) 7304 7305(define-pmacro (float-binary-op-s name pipe attr operation op ope comment) 7306 (dni name 7307 (comment) 7308 (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) (.unsplice attr)) 7309 (.str name "$pack $FRi,$FRj,$FRk") 7310 (+ pack FRk op FRi ope FRj) 7311 (set FRk (operation FRi FRj)) 7312 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7313 ) 7314) 7315 7316(float-binary-op-s fadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_79 OPE1_06 "add single float") 7317(float-binary-op-s fsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_79 OPE1_07 "sub single float") 7318(float-binary-op-s fmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_79 OPE1_08 "mul single float") 7319 7320(dni fdivs 7321 "div single float" 7322 ((UNIT FM01) (FR500-MAJOR F-4) (FR550-MAJOR F-3) (MACH simple,tomcat,fr500,fr550,frv)) 7323 "fdivs$pack $FRi,$FRj,$FRk" 7324 (+ pack FRk OP_79 FRi OPE1_09 FRj) 7325 (set FRk (div FRi FRj)) 7326 ((fr500 (unit u-float-div)) 7327 (fr550 (unit u-float-div))) 7328) 7329 7330(define-pmacro (float-binary-op-d name operation op ope major comment) 7331 (dni name 7332 (comment) 7333 ((UNIT FMALL) (FR500-MAJOR major) (MACH frv)) 7334 (.str name "$pack $FRdoublei,$FRdoublej,$FRdoublek") 7335 (+ pack FRdoublek op FRdoublei ope FRdoublej) 7336 (set FRdoublek (operation FRdoublei FRdoublej)) 7337 ((fr500 (unit u-float-arith))) 7338 ) 7339) 7340 7341(float-binary-op-d faddd add OP_7A OPE1_06 F-2 "add double float") 7342(float-binary-op-d fsubd sub OP_7A OPE1_07 F-2 "sub double float") 7343(float-binary-op-d fmuld mul OP_7A OPE1_08 F-3 "mul double float") 7344(float-binary-op-d fdivd div OP_7A OPE1_09 F-4 "div double float") 7345 7346(define-pmacro (conditional-float-binary-op name pipe attr operation op ope profile comment) 7347 (dni name 7348 (comment) 7349 (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) 7350 (.unsplice attr)) 7351 (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") 7352 (+ pack FRk op FRi CCi cond ope FRj) 7353 (if (eq CCi (or cond 2)) 7354 (set FRk (operation FRi FRj))) 7355 profile 7356 ) 7357) 7358 7359(conditional-float-binary-op cfadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_6D OPE4_0 7360 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7361 "cond add single") 7362(conditional-float-binary-op cfsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_6D OPE4_1 7363 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7364 "cond sub single") 7365(conditional-float-binary-op cfmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_6E OPE4_0 7366 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7367 "cond mul single") 7368(conditional-float-binary-op cfdivs FM01 ((FR500-MAJOR F-4) (FR550-MAJOR F-3)) div OP_6E OPE4_1 7369 ((fr500 (unit u-float-div)) (fr550 (unit u-float-div))) 7370 "cond div single") 7371 7372(define-pmacro (ne-float-binary-op name pipe attr operation op ope profile comment) 7373 (dni name 7374 (comment) 7375 (.splice (UNIT pipe) (MACH simple,tomcat,fr500,fr550,frv) 7376 (.unsplice attr)) 7377 (.str name "$pack $FRi,$FRj,$FRk") 7378 (+ pack FRk op FRi ope FRj) 7379 (sequence () 7380 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7381 (set FRk (operation FRi FRj))) 7382 profile 7383 ) 7384) 7385 7386(ne-float-binary-op nfadds FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) add OP_79 OPE1_26 7387 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7388 "ne add single") 7389(ne-float-binary-op nfsubs FMALL ((FR500-MAJOR F-2) (FR550-MAJOR F-2)) sub OP_79 OPE1_27 7390 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7391 "ne sub single") 7392(ne-float-binary-op nfmuls FM01 ((FR500-MAJOR F-3) (FR550-MAJOR F-3)) mul OP_79 OPE1_28 7393 ((fr500 (unit u-float-arith)) (fr550 (unit u-float-arith))) 7394 "ne mul single") 7395(ne-float-binary-op nfdivs FM01 ((FR500-MAJOR F-4) (FR550-MAJOR F-3)) div OP_79 OPE1_29 7396 ((fr500 (unit u-float-div)) (fr550 (unit u-float-div))) 7397 "ne div single") 7398 7399(define-pmacro (fcc-eq) 8) 7400(define-pmacro (fcc-lt) 4) 7401(define-pmacro (fcc-gt) 2) 7402(define-pmacro (fcc-uo) 1) 7403 7404(define-pmacro (compare-and-set-fcc arg1 arg2 fcc) 7405 (if (gt arg1 arg2) 7406 (set fcc (fcc-gt)) 7407 (if (eq arg1 arg2) 7408 (set fcc (fcc-eq)) 7409 (if (lt arg1 arg2) 7410 (set fcc (fcc-lt)) 7411 (set fcc (fcc-uo))))) 7412) 7413 7414(dni fcmps 7415 "compare single float" 7416 ((UNIT FMALL) (FR500-MAJOR F-2) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 7417 "fcmps$pack $FRi,$FRj,$FCCi_2" 7418 (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_0A FRj) 7419 (compare-and-set-fcc FRi FRj FCCi_2) 7420 ((fr500 (unit u-float-compare)) (fr550 (unit u-float-compare))) 7421) 7422 7423(dni fcmpd 7424 "compare double float" 7425 ((UNIT FMALL) (FR500-MAJOR F-2) (MACH frv)) 7426 "fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2" 7427 (+ pack (cond-null) FCCi_2 OP_7A FRdoublei OPE1_0A FRdoublej) 7428 (compare-and-set-fcc FRdoublei FRdoublej FCCi_2) 7429 ((fr500 (unit u-float-compare))) 7430) 7431 7432(dni cfcmps 7433 "Conditional compare single, float" 7434 ((UNIT FMALL) (FR500-MAJOR F-2) (FR550-MAJOR F-2) (MACH simple,tomcat,fr500,fr550,frv)) 7435 "cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond" 7436 (+ pack (cond-null) FCCi_2 OP_6D FRi CCi cond OPE4_2 FRj) 7437 (if (eq CCi (or cond 2)) 7438 (compare-and-set-fcc FRi FRj FCCi_2)) 7439 ((fr500 (unit u-float-compare)) (fr550 (unit u-float-compare))) 7440) 7441 7442(dni fdcmps 7443 "float dual compare single" 7444 ((UNIT FMALL) (FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) 7445 "fdcmps$pack $FRi,$FRj,$FCCi_2" 7446 (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_1A FRj) 7447 (sequence () 7448 (compare-and-set-fcc FRi FRj FCCi_2) 7449 (compare-and-set-fcc (nextreg h-fr FRi 1) (nextreg h-fr FRj 1) 7450 (nextreg h-fccr FCCi_2 1))) 7451 ((fr500 (unit u-float-dual-compare)) (fr550 (unit u-float-dual-compare))) 7452) 7453 7454(define-pmacro (float-mul-with-add name add_sub arg1 arg2 targ op ope comment) 7455 (dni name 7456 (comment) 7457 ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) 7458 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 7459 (+ pack targ op arg1 ope arg2) 7460 (set targ (add_sub (mul arg1 arg2) targ)) 7461 ((fr500 (unit u-float-dual-arith))) 7462 ) 7463) 7464 7465(float-mul-with-add fmadds add FRi FRj FRk OP_79 OPE1_0B "mul with add, single") 7466(float-mul-with-add fmsubs sub FRi FRj FRk OP_79 OPE1_0C "mul with sub, single") 7467 7468(float-mul-with-add fmaddd add FRdoublei FRdoublej FRdoublek OP_7A OPE1_0B "mul with add, double") 7469(float-mul-with-add fmsubd sub FRdoublei FRdoublej FRdoublek OP_7A OPE1_0C "mul with sub, double") 7470 7471(dni fdmadds 7472 "Float dual multiply with add" 7473 ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) 7474 "fdmadds$pack $FRi,$FRj,$FRk" 7475 (+ pack FRk OP_79 FRi OPE1_1B FRj) 7476 (sequence () 7477 (set FRk (add (mul FRi FRj) FRk)) 7478 (set (nextreg h-fr FRk 1) 7479 (add (mul (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)) 7480 (nextreg h-fr FRk 1)))) 7481 ; TODO dual registers not referenced for profiling 7482 ((fr500 (unit u-float-dual-arith))) 7483) 7484 7485(dni nfdmadds 7486 "Non excepting float dual multiply with add" 7487 ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv)) 7488 "nfdmadds$pack $FRi,$FRj,$FRk" 7489 (+ pack FRk OP_79 FRi OPE1_3B FRj) 7490 (sequence () 7491 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7492 (set FRk (add (mul FRi FRj) FRk)) 7493 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 7494 (set (nextreg h-fr FRk 1) 7495 (add (mul (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)) 7496 (nextreg h-fr FRk 1)))) 7497 ; TODO dual registers not referenced for profiling 7498 ((fr500 (unit u-float-dual-arith))) 7499) 7500 7501(define-pmacro (conditional-float-mul-with-add 7502 name add_sub arg1 arg2 targ op ope comment) 7503 (dni name 7504 (comment) 7505 ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv) CONDITIONAL) 7506 (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") 7507 (+ pack FRk op FRi CCi cond ope FRj) 7508 (if (eq CCi (or cond 2)) 7509 (set targ (add_sub (mul arg1 arg2) targ))) 7510 ((fr500 (unit u-float-dual-arith))) 7511 ) 7512) 7513 7514(conditional-float-mul-with-add cfmadds add FRi FRj FRk OP_6F OPE4_0 "conditional mul with add, single") 7515(conditional-float-mul-with-add cfmsubs sub FRi FRj FRk OP_6F OPE4_1 "conditional mul with sub, single") 7516 7517(define-pmacro (ne-float-mul-with-add name add_sub arg1 arg2 targ op ope comment) 7518 (dni name 7519 (comment) 7520 ((UNIT FMALL) (FR500-MAJOR F-5) (MACH frv) NON-EXCEPTING) 7521 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 7522 (+ pack targ op arg1 ope arg2) 7523 (sequence () 7524 (c-call VOID "@cpu@_set_ne_index" (index-of targ)) 7525 (set targ (add_sub (mul arg1 arg2) targ))) 7526 ((fr500 (unit u-float-dual-arith))) 7527 ) 7528) 7529 7530(ne-float-mul-with-add nfmadds add FRi FRj FRk OP_79 OPE1_2B "non excepting mul with add, single") 7531(ne-float-mul-with-add nfmsubs sub FRi FRj FRk OP_79 OPE1_2C "non excepting mul with sub, single") 7532 7533(define-pmacro (float-parallel-mul-add-semantics cond add_sub arg1 arg2 targ) 7534 (if cond 7535 (sequence () 7536 (set targ (mul arg1 arg2)) 7537 (set (nextreg h-fr targ 1) 7538 (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))))) 7539) 7540 7541(define-pmacro (float-parallel-mul-add 7542 name add_sub arg1 arg2 targ op ope comment) 7543 (dni name 7544 (comment) 7545 ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) 7546 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 7547 (+ pack targ op arg1 ope arg2) 7548 (float-parallel-mul-add-semantics 1 add_sub arg1 arg2 targ) 7549 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7550 ) 7551) 7552 7553(float-parallel-mul-add fmas add FRi FRj FRk OP_79 OPE1_0E "parallel mul/add, single") 7554(float-parallel-mul-add fmss sub FRi FRj FRk OP_79 OPE1_0F "parallel mul/sub, single") 7555 7556(define-pmacro (float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) 7557 (sequence () 7558 (set targ (mul arg1 arg2)) 7559 (set (nextreg h-fr targ 1) 7560 (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))) 7561 (set (nextreg h-fr targ 2) 7562 (mul (nextreg h-fr arg1 2) (nextreg h-fr arg2 2))) 7563 (set (nextreg h-fr targ 3) 7564 (add_sub (nextreg h-fr arg1 3) (nextreg h-fr arg2 3)))) 7565) 7566 7567(define-pmacro (float-dual-parallel-mul-add 7568 name add_sub arg1 arg2 targ op ope comment) 7569 (dni name 7570 (comment) 7571 ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) 7572 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 7573 (+ pack targ op arg1 ope arg2) 7574 (float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) 7575 () 7576 ) 7577) 7578 7579(float-dual-parallel-mul-add fdmas add FRi FRj FRk OP_79 OPE1_1C "dual parallel mul/add, single") 7580(float-dual-parallel-mul-add fdmss sub FRi FRj FRk OP_79 OPE1_1D "dual parallel mul/sub, single") 7581 7582(define-pmacro (ne-float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) 7583 (sequence () 7584 (c-call VOID "@cpu@_set_ne_index" (index-of targ)) 7585 (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 1)) 7586 (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 2)) 7587 (c-call VOID "@cpu@_set_ne_index" (add (index-of targ) 3)) 7588 (set targ (mul arg1 arg2)) 7589 (set (nextreg h-fr targ 1) 7590 (add_sub (nextreg h-fr arg1 1) (nextreg h-fr arg2 1))) 7591 (set (nextreg h-fr targ 2) 7592 (mul (nextreg h-fr arg1 2) (nextreg h-fr arg2 2))) 7593 (set (nextreg h-fr targ 3) 7594 (add_sub (nextreg h-fr arg1 3) (nextreg h-fr arg2 3)))) 7595) 7596 7597(define-pmacro (ne-float-dual-parallel-mul-add 7598 name add_sub arg1 arg2 targ op ope comment) 7599 (dni name 7600 (comment) 7601 ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) 7602 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 7603 (+ pack targ op arg1 ope arg2) 7604 (ne-float-dual-parallel-mul-add-semantics add_sub arg1 arg2 targ) 7605 () 7606 ) 7607) 7608 7609(ne-float-dual-parallel-mul-add nfdmas add FRi FRj FRk OP_79 OPE1_3C "non excepting dual parallel mul/add, single") 7610(ne-float-dual-parallel-mul-add nfdmss sub FRi FRj FRk OP_79 OPE1_3D "non excepting dual parallel mul/sub, single") 7611 7612(define-pmacro (conditional-float-parallel-mul-add name add_sub op ope comment) 7613 (dni name 7614 (comment) 7615 ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) CONDITIONAL (MACH simple,tomcat,fr500,fr550,frv)) 7616 (.str name "$pack $FRi,$FRj,$FRk,$CCi,$cond") 7617 (+ pack FRk op FRi CCi cond ope FRj) 7618 (float-parallel-mul-add-semantics (eq CCi (or cond 2)) 7619 add_sub FRi FRj FRk) 7620 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7621 ) 7622) 7623 7624(conditional-float-parallel-mul-add cfmas add OP_6F OPE4_2 "conditional parallel mul/add, single") 7625(conditional-float-parallel-mul-add cfmss sub OP_6F OPE4_3 "conditional parallel mul/sub, single") 7626 7627(define-pmacro (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ) 7628 (sequence () 7629 (set targ (ftrunc SF FPCONV-DEFAULT 7630 (mul DF 7631 (fext DF FPCONV-DEFAULT arg1) 7632 (fext DF FPCONV-DEFAULT arg2)))) 7633 (set (nextreg h-fr targ 1) 7634 (ftrunc SF FPCONV-DEFAULT 7635 (add_sub DF 7636 (fext DF FPCONV-DEFAULT (nextreg h-fr arg1 1)) 7637 (fext DF FPCONV-DEFAULT (nextreg h-fr arg2 1)))))) 7638) 7639 7640(define-pmacro (float-parallel-mul-add-double 7641 name add_sub arg1 arg2 targ op ope comment) 7642 (dni name 7643 (comment) 7644 ((UNIT FM01) (FR500-MAJOR F-5) (MACH frv)) 7645 (.str name "$pack $" arg1 ",$" arg2 ",$" targ) 7646 (+ pack targ op arg1 ope arg2) 7647 (float-parallel-mul-add-double-semantics add_sub arg1 arg2 targ) 7648 () 7649 ) 7650) 7651 7652(float-parallel-mul-add-double fmad add FRi FRj FRk OP_7A OPE1_0E "parallel mul/add, double") 7653(float-parallel-mul-add-double fmsd sub FRi FRj FRk OP_7A OPE1_0F "parallel mul/sub, double") 7654 7655(define-pmacro (ne-float-parallel-mul-add name add_sub op ope comment) 7656 (dni name 7657 (comment) 7658 ((UNIT FM01) (FR500-MAJOR F-5) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) 7659 (.str name "$pack $FRi,$FRj,$FRk") 7660 (+ pack FRk op FRi ope FRj) 7661 (sequence () 7662 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7663 (set FRk (mul FRi FRj)) 7664 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 7665 (set (nextreg h-fr FRk 1) 7666 (add_sub (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) 7667 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7668 ) 7669) 7670 7671(ne-float-parallel-mul-add nfmas add OP_79 OPE1_2E "ne parallel mul/add,single") 7672(ne-float-parallel-mul-add nfmss sub OP_79 OPE1_2F "ne parallel mul/sub,single") 7673 7674(define-pmacro (float-dual-arith name attr oper1 oper2 op ope comment) 7675 (dni name 7676 (comment) 7677 (.splice (UNIT FM01) (.unsplice attr)) 7678 (.str name "$pack $FRi,$FRj,$FRk") 7679 (+ pack FRk op FRi ope FRj) 7680 (sequence () 7681 (set FRk (oper1 FRi FRj)) 7682 (set (nextreg h-fr FRk 1) 7683 (oper2 (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) 7684 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7685 ) 7686) 7687 7688(float-dual-arith fdadds ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add add OP_79 OPE1_16 "dual add, single") 7689(float-dual-arith fdsubs ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) sub sub OP_79 OPE1_17 "dual sub, single") 7690(float-dual-arith fdmuls ((FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) mul mul OP_79 OPE1_18 "dual mul, single") 7691(float-dual-arith fddivs ((FR500-MAJOR F-7) (MACH frv)) div div OP_79 OPE1_19 "dual div,single") 7692(float-dual-arith fdsads ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add sub OP_79 OPE1_1E "dual add/sub, single") 7693 7694(dni fdmulcs 7695 "Float dual cross multiply single" 7696 ((UNIT FM01) (FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) 7697 "fdmulcs$pack $FRi,$FRj,$FRk" 7698 (+ pack FRk OP_79 FRi OPE1_1F FRj) 7699 (sequence () 7700 (set FRk (mul FRi (nextreg h-fr FRj 1))) 7701 (set (nextreg h-fr FRk 1) (mul (nextreg h-fr FRi 1) FRj))) 7702 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7703) 7704 7705(dni nfdmulcs 7706 "NE float dual cross multiply single" 7707 ((UNIT FM01) (FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) 7708 "nfdmulcs$pack $FRi,$FRj,$FRk" 7709 (+ pack FRk OP_79 FRi OPE1_3F FRj) 7710 (sequence () 7711 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7712 (set FRk (mul FRi (nextreg h-fr FRj 1))) 7713 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 7714 (set (nextreg h-fr FRk 1) (mul (nextreg h-fr FRi 1) FRj))) 7715 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7716) 7717 7718(define-pmacro (ne-float-dual-arith name attr oper1 oper2 op ope comment) 7719 (dni name 7720 (comment) 7721 (.splice (UNIT FM01) (.unsplice attr)) 7722 (.str name "$pack $FRi,$FRj,$FRk") 7723 (+ pack FRk op FRi ope FRj) 7724 (sequence () 7725 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7726 (set FRk (oper1 FRi FRj)) 7727 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 7728 (set (nextreg h-fr FRk 1) 7729 (oper2 (nextreg h-fr FRi 1) (nextreg h-fr FRj 1)))) 7730 ((fr500 (unit u-float-dual-arith)) (fr550 (unit u-float-dual-arith))) 7731 ) 7732) 7733 7734(ne-float-dual-arith nfdadds ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add add OP_79 OPE1_36 "ne dual add, single") 7735(ne-float-dual-arith nfdsubs ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) sub sub OP_79 OPE1_37 "ne dual sub, single") 7736(ne-float-dual-arith nfdmuls ((FR500-MAJOR F-7) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) mul mul OP_79 OPE1_38 "ne dual mul, single") 7737(ne-float-dual-arith nfddivs ((FR500-MAJOR F-7) (MACH frv)) div div OP_79 OPE1_39 "ne dual div,single") 7738(ne-float-dual-arith nfdsads ((FR500-MAJOR F-6) (FR550-MAJOR F-4) (MACH simple,tomcat,fr500,fr550,frv)) add sub OP_79 OPE1_3E "ne dual add/sub, single") 7739 7740(dni nfdcmps 7741 "non-excepting dual float compare" 7742 ((UNIT FM01) (FR500-MAJOR F-6) (MACH simple,tomcat,frv)) 7743 "nfdcmps$pack $FRi,$FRj,$FCCi_2" 7744 (+ pack (cond-null) FCCi_2 OP_79 FRi OPE1_3A FRj) 7745 (sequence () 7746 (c-call VOID "@cpu@_set_ne_index" (index-of FRk)) 7747 (compare-and-set-fcc FRi FRj FCCi_2) 7748 (c-call VOID "@cpu@_set_ne_index" (add (index-of FRk) 1)) 7749 (compare-and-set-fcc (nextreg h-fr FRi 1) (nextreg h-fr FRj 1) 7750 (nextreg h-fccr FCCi_2 1))) 7751 ((fr500 (unit u-float-dual-compare))) 7752) 7753 7754; Media Instructions 7755; 7756(define-pmacro (halfword hilo arg offset) 7757 (reg (.sym h-fr_ hilo) (add (index-of arg) offset))) 7758 7759(dni mhsetlos 7760 "Media set lower signed 12 bits" 7761 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) 7762 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 7763 "mhsetlos$pack $u12,$FRklo" 7764 (+ pack FRklo OP_78 OPE1_20 u12) 7765 (set FRklo u12) 7766 ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo)) 7767 (fr550 (unit u-media-set (out FRintk FRklo)))) 7768) 7769 7770(dni mhsethis 7771 "Media set upper signed 12 bits" 7772 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) 7773 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 7774 "mhsethis$pack $u12,$FRkhi" 7775 (+ pack FRkhi OP_78 OPE1_22 u12) 7776 (set FRkhi u12) 7777 ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo)) 7778 (fr550 (unit u-media-set (out FRintk FRkhi)))) 7779) 7780 7781(dni mhdsets 7782 "Media dual set halfword signed 12 bits" 7783 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) 7784 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 7785 "mhdsets$pack $u12,$FRintk" 7786 (+ pack FRintk OP_78 OPE1_24 u12) 7787 (sequence () 7788 ; hack to get FRintk passed to modelling functions 7789 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 7790 (set (halfword hi FRintk 0) u12) 7791 (set (halfword lo FRintk 0) u12)) 7792 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 7793 (fr550 (unit u-media-set))) 7794) 7795 7796(define-pmacro (set-5-semantics target value) 7797 (sequence ((HI tmp)) 7798 (set tmp target) 7799 (set tmp (and tmp #x07ff)) 7800 (set tmp (or tmp (sll (and s5 #x1f) 11))) 7801 (set target tmp)) 7802) 7803 7804(define-pmacro (media-set-5 name hilo op ope comment) 7805 (dni name 7806 (comment) 7807 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) 7808 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 7809 (.str name "$pack $s5,$FRk" hilo) 7810 (+ pack (.sym FRk hilo) op (FRi-null) ope (misc-null-11) s5) 7811 (set-5-semantics (.sym FRk hilo) s5) 7812 ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo)) 7813 (fr550 (unit u-media-set (out FRintk (.sym FRk hilo))))) 7814 ) 7815) 7816 7817(media-set-5 mhsetloh lo OP_78 OPE1_21 "Media set upper 5 bits lo") 7818(media-set-5 mhsethih hi OP_78 OPE1_23 "Media set upper 5 bits hi") 7819 7820(dni mhdseth 7821 "Media dual set halfword upper 5 bits" 7822 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5) 7823 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 7824 "mhdseth$pack $s5,$FRintk" 7825 (+ pack FRintk OP_78 (FRi-null) OPE1_25 (misc-null-11) s5) 7826 (sequence () 7827 ; hack to get FRintk passed to modelling functions 7828 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 7829 (set-5-semantics (halfword hi FRintk 0) s5) 7830 (set-5-semantics (halfword lo FRintk 0) s5)) 7831 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 7832 (fr550 (unit u-media-set))) 7833) 7834 7835(define-pmacro (media-logic-r-r name operation op ope comment) 7836 (dni name 7837 (comment) 7838 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 7839 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 7840 (.str name "$pack $FRinti,$FRintj,$FRintk") 7841 (+ pack FRintk op FRinti ope FRintj) 7842 (set FRintk (operation FRinti FRintj)) 7843 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 7844 (fr500 (unit u-media)) (fr550 (unit u-media))) 7845 ) 7846) 7847 7848(media-logic-r-r mand and OP_7B OPE1_00 "and reg/reg") 7849(media-logic-r-r mor or OP_7B OPE1_01 "or reg/reg") 7850(media-logic-r-r mxor xor OP_7B OPE1_02 "xor reg/reg") 7851 7852(define-pmacro (conditional-media-logic name operation op ope comment) 7853 (dni name 7854 (comment) 7855 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 7856 (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) 7857 (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond") 7858 (+ pack FRintk op FRinti CCi cond ope FRintj) 7859 (if (eq CCi (or cond 2)) 7860 (set FRintk (operation FRinti FRintj))) 7861 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 7862 (fr500 (unit u-media)) (fr550 (unit u-media))) 7863 ) 7864) 7865 7866(conditional-media-logic cmand and OP_70 OPE4_0 "conditional and reg/reg") 7867(conditional-media-logic cmor or OP_70 OPE4_1 "conditional or reg/reg") 7868(conditional-media-logic cmxor xor OP_70 OPE4_2 "conditional xor reg/reg") 7869 7870(dni mnot 7871 ("mnot") 7872 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 7873 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 7874 ("mnot$pack $FRintj,$FRintk") 7875 (+ pack FRintk OP_7B (rs-null) OPE1_03 FRintj) 7876 (set FRintk (inv FRintj)) 7877 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 7878 (fr500 (unit u-media)) (fr550 (unit u-media))) 7879) 7880 7881(dni cmnot 7882 ("cmnot") 7883 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 7884 (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) 7885 ("cmnot$pack $FRintj,$FRintk,$CCi,$cond") 7886 (+ pack FRintk OP_70 (rs-null) CCi cond OPE4_3 FRintj) 7887 (if (eq CCi (or cond 2)) 7888 (set FRintk (inv FRintj))) 7889 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 7890 (fr500 (unit u-media)) (fr550 (unit u-media))) 7891) 7892 7893(define-pmacro (media-rotate-r-r name operation op ope comment) 7894 (dni name 7895 (comment) 7896 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 7897 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 7898 (.str name "$pack $FRinti,$u6,$FRintk") 7899 (+ pack FRintk op FRinti ope u6) 7900 (set FRintk (operation FRinti (and u6 #x1f))) 7901 ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) 7902 (fr500 (unit u-media)) (fr550 (unit u-media))) 7903 ) 7904) 7905 7906(media-rotate-r-r mrotli rol OP_7B OPE1_04 "rotate left reg/reg") 7907(media-rotate-r-r mrotri ror OP_7B OPE1_05 "rotate right reg/reg") 7908 7909(define-pmacro (media-cut-r-r name arg op ope comment) 7910 (dni name 7911 (comment) 7912 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 7913 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 7914 (.str name "$pack $FRinti,$" arg ",$FRintk") 7915 (+ pack FRintk op FRinti ope arg) 7916 (set FRintk (c-call SI "@cpu@_cut" FRinti (nextreg h-fr_int FRinti 1) arg)) 7917 ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) 7918 (fr500 (unit u-media)) (fr550 (unit u-media))) 7919 ) 7920) 7921 7922(media-cut-r-r mwcut FRintj OP_7B OPE1_06 "media cut") 7923(media-cut-r-r mwcuti u6 OP_7B OPE1_07 "media cut") 7924 7925(define-pmacro (media-cut-acc name arg op ope fr450-major comment) 7926 (dni name 7927 (comment) 7928 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 7929 (FR400-MAJOR M-1) (FR450-MAJOR fr450-major)) 7930 (.str name "$pack $ACC40Si,$" arg ",$FRintk") 7931 (+ pack FRintk op ACC40Si ope arg) 7932 (set FRintk (c-call SI "@cpu@_media_cut" ACC40Si arg)) 7933 ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) 7934 (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) 7935 ) 7936) 7937 7938(media-cut-acc mcut FRintj OP_7B OPE1_2C M-1 "media accumulator cut reg") 7939(media-cut-acc mcuti s6 OP_7B OPE1_2E M-5 "media accumulator cut immed") 7940 7941(define-pmacro (media-cut-acc-ss name arg op ope fr450-major comment) 7942 (dni name 7943 (comment) 7944 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 7945 (FR400-MAJOR M-1) (FR450-MAJOR fr450-major)) 7946 (.str name "$pack $ACC40Si,$" arg ",$FRintk") 7947 (+ pack FRintk op ACC40Si ope arg) 7948 (set FRintk (c-call SI "@cpu@_media_cut_ss" ACC40Si arg)) 7949 ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) 7950 (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) 7951 ) 7952) 7953 7954(media-cut-acc-ss mcutss FRintj OP_7B OPE1_2D M-1 "media accumulator cut reg with saturation") 7955(media-cut-acc-ss mcutssi s6 OP_7B OPE1_2F M-5 "media accumulator cut immed with saturation") 7956 7957; Dual Media Instructions 7958; 7959(define-pmacro (register-unaligned register alignment) 7960 (and (index-of register) (sub alignment 1)) 7961) 7962 7963(dni mdcutssi 7964 "Media dual cut with signed saturation" 7965 ((UNIT MDCUTSSI) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) 7966 (FR400-MAJOR M-2) (FR450-MAJOR M-6)) 7967 "mdcutssi$pack $ACC40Si,$s6,$FRintkeven" 7968 (+ pack FRintkeven OP_78 ACC40Si OPE1_0E s6) 7969 (if (register-unaligned ACC40Si 2) 7970 (c-call VOID "@cpu@_media_acc_not_aligned") 7971 (if (register-unaligned FRintkeven 2) 7972 (c-call VOID "@cpu@_media_register_not_aligned") 7973 (sequence () 7974 (set FRintkeven (c-call SI "@cpu@_media_cut_ss" ACC40Si s6)) 7975 (set (nextreg h-fr_int FRintkeven 1) 7976 (c-call SI "@cpu@_media_cut_ss" 7977 (nextreg h-acc40S ACC40Si 1) s6))))) 7978 ((fr400 (unit u-media-4-acc-dual 7979 (out FRintk FRintkeven))) 7980 (fr450 (unit u-media-4-acc-dual 7981 (out FRintk FRintkeven))) 7982 (fr550 (unit u-media-3-acc-dual))) 7983) 7984 7985; The (add (xxxx) (mul arg 0)) is a hack to get a reference to arg generated 7986; so it will be passed to the unit modelers. YUCK!!!!! 7987(define-pmacro (extract-hilo reg1 off1 reg2 off2 arg1hi arg1lo arg2hi arg2lo) 7988 (sequence () 7989 (set arg1hi (add (halfword hi reg1 off1) (mul reg1 0))) 7990 (set arg1lo (add (halfword lo reg1 off1) (mul reg1 0))) 7991 (set arg2hi (add (halfword hi reg2 off2) (mul reg2 0))) 7992 (set arg2lo (add (halfword lo reg2 off2) (mul reg2 0)))) 7993) 7994 7995(dni maveh 7996 "Media dual average" 7997 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 7998 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 7999 "maveh$pack $FRinti,$FRintj,$FRintk" 8000 (+ pack FRintk OP_7B FRinti OPE1_08 FRintj) 8001 (set FRintk (c-call SI "@cpu@_media_average" FRinti FRintj)) 8002 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 8003 (fr500 (unit u-media)) (fr550 (unit u-media))) 8004) 8005 8006(define-pmacro (media-dual-shift name operation op ope profile comment) 8007 (dni name 8008 (comment) 8009 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 8010 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 8011 (.str name "$pack $FRinti,$u6,$FRintk") 8012 (+ pack FRintk op FRinti ope u6) 8013 (sequence () 8014 ; hack to get these referenced for profiling 8015 (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) 8016 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 8017 (set (halfword hi FRintk 0) 8018 (operation (halfword hi FRinti 0) (and u6 #xf))) 8019 (set (halfword lo FRintk 0) 8020 (operation (halfword lo FRinti 0) (and u6 #xf)))) 8021 profile 8022 ) 8023) 8024 8025(media-dual-shift msllhi sll OP_7B OPE1_09 8026 ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) 8027 (fr500 (unit u-media)) (fr550 (unit u-media))) 8028 "Media dual shift left logical") 8029(media-dual-shift msrlhi srl OP_7B OPE1_0A 8030 ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) 8031 (fr500 (unit u-media)) (fr550 (unit u-media))) 8032 "Media dual shift right logical") 8033(media-dual-shift msrahi sra OP_7B OPE1_0B 8034 ((fr400 (unit u-media-6)) (fr450 (unit u-media-6)) 8035 (fr500 (unit u-media)) (fr550 (unit u-media))) 8036 "Media dual shift right arithmetic") 8037 8038(define-pmacro (media-dual-word-rotate-r-r name operation op ope comment) 8039 (dni name 8040 (comment) 8041 ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) 8042 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 8043 (.str name "$pack $FRintieven,$s6,$FRintkeven") 8044 (+ pack FRintkeven op FRintieven ope s6) 8045 (if (orif (register-unaligned FRintieven 2) 8046 (register-unaligned FRintkeven 2)) 8047 (c-call VOID "@cpu@_media_register_not_aligned") 8048 (sequence () 8049 (set FRintkeven (operation FRintieven (and s6 #x1f))) 8050 (set (nextreg h-fr_int FRintkeven 1) 8051 (operation (nextreg h-fr_int FRintieven 1) 8052 (and s6 #x1f))))) 8053 ((fr400 (unit u-media-3-quad 8054 (in FRinti FRintieven) 8055 (out FRintk FRintkeven))) 8056 (fr450 (unit u-media-3-quad 8057 (in FRinti FRintieven) 8058 (out FRintk FRintkeven))) 8059 (fr550 (unit u-media-quad))) 8060 ) 8061) 8062 8063(media-dual-word-rotate-r-r mdrotli rol OP_78 OPE1_0B "rotate left reg/reg") 8064 8065(dni mcplhi 8066 "Media bit concatenate, halfword" 8067 ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) 8068 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 8069 "mcplhi$pack $FRinti,$u6,$FRintk" 8070 (+ pack FRintk OP_78 FRinti OPE1_0C u6) 8071 (sequence ((HI arg1) (HI arg2) (HI shift)) 8072 (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) 8073 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 8074 (set shift (and u6 #xf)) 8075 (set arg1 (sll (halfword hi FRinti 0) shift)) 8076 (if (ne shift 0) 8077 (sequence () 8078 (set arg2 (halfword hi FRinti 1)) 8079 (set arg2 (srl HI (sll HI arg2 (sub 15 shift)) 8080 (sub 15 shift))) 8081 (set arg1 (or HI arg1 arg2)))) 8082 (set (halfword hi FRintk 0) arg1)) 8083 ((fr400 (unit u-media-3-dual)) (fr450 (unit u-media-3-dual)) 8084 (fr550 (unit u-media-3-dual))) 8085) 8086 8087(dni mcpli 8088 "Media bit concatenate, word" 8089 ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3) 8090 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 8091 "mcpli$pack $FRinti,$u6,$FRintk" 8092 (+ pack FRintk OP_78 FRinti OPE1_0D u6) 8093 (sequence ((SI tmp) (SI shift)) 8094 (set shift (and u6 #x1f)) 8095 (set tmp (sll FRinti shift)) 8096 (if (ne shift 0) 8097 (sequence ((SI tmp1)) 8098 (set tmp1 (srl (sll (nextreg h-fr_int FRinti 1) 8099 (sub 31 shift)) 8100 (sub 31 shift))) 8101 (set tmp (or tmp tmp1)))) 8102 (set FRintk tmp)) 8103 ((fr400 (unit u-media-3-dual)) (fr450 (unit u-media-3-dual)) 8104 (fr550 (unit u-media-3-dual))) 8105) 8106 8107(define-pmacro (saturate arg max min result) 8108 (if (gt arg max) 8109 (set result max) 8110 (if (lt arg min) 8111 (set result min) 8112 (set result arg))) 8113) 8114 8115(dni msaths 8116 "Media dual saturation signed" 8117 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 8118 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 8119 "msaths$pack $FRinti,$FRintj,$FRintk" 8120 (+ pack FRintk OP_7B FRinti OPE1_0C FRintj) 8121 (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo)) 8122 (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) 8123 (saturate argihi argjhi (inv argjhi) (halfword hi FRintk 0)) 8124 (saturate argilo argjlo (inv argjlo) (halfword lo FRintk 0))) 8125 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 8126 (fr500 (unit u-media)) (fr550 (unit u-media))) 8127) 8128 8129(dni mqsaths 8130 "Media quad saturation signed" 8131 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-2) 8132 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 8133 "mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven" 8134 (+ pack FRintkeven OP_78 FRintieven OPE1_0F FRintjeven) 8135 (if (orif (register-unaligned FRintieven 2) 8136 (orif (register-unaligned FRintjeven 2) 8137 (register-unaligned FRintkeven 2))) 8138 (c-call VOID "@cpu@_media_register_not_aligned") 8139 (sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo)) 8140 ; hack to get FRintkeven referenced as a target for profiling 8141 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 8142 (extract-hilo FRintieven 0 FRintjeven 0 argihi argilo argjhi argjlo) 8143 (saturate argihi argjhi (inv argjhi) (halfword hi FRintkeven 0)) 8144 (saturate argilo argjlo (inv argjlo) (halfword lo FRintkeven 0)) 8145 (extract-hilo FRintieven 1 FRintjeven 1 argihi argilo argjhi argjlo) 8146 (saturate argihi argjhi (inv argjhi) (halfword hi FRintkeven 1)) 8147 (saturate argilo argjlo (inv argjlo) (halfword lo FRintkeven 1)))) 8148 ((fr400 (unit u-media-1-quad 8149 (in FRinti FRintieven) 8150 (in FRintj FRintjeven) 8151 (out FRintk FRintkeven))) 8152 (fr450 (unit u-media-1-quad 8153 (in FRinti FRintieven) 8154 (in FRintj FRintjeven) 8155 (out FRintk FRintkeven))) 8156 (fr550 (unit u-media-quad))) 8157) 8158 8159(define-pmacro (saturate-unsigned arg max result) 8160 (if (gt arg max) 8161 (set result max) 8162 (set result arg)) 8163) 8164 8165(dni msathu 8166 "Media dual saturation unsigned" 8167 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 8168 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 8169 "msathu$pack $FRinti,$FRintj,$FRintk" 8170 (+ pack FRintk OP_7B FRinti OPE1_0D FRintj) 8171 (sequence ((UHI argihi) (UHI argilo) (UHI argjhi) (UHI argjlo)) 8172 (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) 8173 (saturate-unsigned argihi argjhi (halfword hi FRintk 0)) 8174 (saturate-unsigned argilo argjlo (halfword lo FRintk 0))) 8175 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 8176 (fr500 (unit u-media)) (fr550 (unit u-media))) 8177) 8178 8179(define-pmacro (media-dual-compare name mode op ope comment) 8180 (dni name 8181 (comment) 8182 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 8183 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 8184 (.str name "$pack $FRinti,$FRintj,$FCCk") 8185 (+ pack (cond-null) FCCk op FRinti ope FRintj) 8186 (if (register-unaligned FCCk 2) 8187 (c-call VOID "@cpu@_media_cr_not_aligned") 8188 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 8189 (extract-hilo FRinti 0 FRintj 0 8190 argihi argilo argjhi argjlo) 8191 (compare-and-set-fcc argihi argjhi FCCk) 8192 (compare-and-set-fcc argilo argjlo (nextreg h-fccr FCCk 1)))) 8193 ; TODO - doesn't handle second FCC 8194 ((fr400 (unit u-media-7)) (fr450 (unit u-media-7)) 8195 (fr500 (unit u-media)) (fr550 (unit u-media))) 8196 ) 8197) 8198 8199(media-dual-compare mcmpsh HI OP_7B OPE1_0E "Media dual compare signed") 8200(media-dual-compare mcmpuh UHI OP_7B OPE1_0F "Media dual compare unsigned") 8201 8202; Bits for the MSR.SIE field 8203(define-pmacro (msr-sie-nil) 0) 8204(define-pmacro (msr-sie-fri-hi) 8) 8205(define-pmacro (msr-sie-fri-lo) 4) 8206(define-pmacro (msr-sie-fri-1-hi) 2) 8207(define-pmacro (msr-sie-fri-1-lo) 1) 8208(define-pmacro (msr-sie-acci) 8) 8209(define-pmacro (msr-sie-acci-1) 4) 8210(define-pmacro (msr-sie-acci-2) 2) 8211(define-pmacro (msr-sie-acci-3) 1) 8212 8213(define-pmacro (saturate-v arg max min sie result) 8214 (if (gt DI arg max) 8215 (sequence () 8216 (set result max) 8217 (c-call VOID "@cpu@_media_overflow" sie)) 8218 (if (lt DI arg min) 8219 (sequence () 8220 (set result min) 8221 (c-call VOID "@cpu@_media_overflow" sie)) 8222 (set result arg))) 8223) 8224 8225(dni mabshs 8226 "Media dual absolute value, halfword" 8227 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-2) 8228 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 8229 "mabshs$pack $FRintj,$FRintk" 8230 (+ pack FRintk OP_78 (FRi-null) OPE1_0A FRintj) 8231 (sequence ((HI arghi) (HI arglo)) 8232 (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) 8233 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 8234 (set arghi (halfword hi FRintj 0)) 8235 (set arglo (halfword lo FRintj 0)) 8236 ; We extend the argument before the abs operation so we can 8237 ; notice -32768 overflowing as 32768. 8238 (saturate-v (abs (ext DI arghi)) 32767 -32768 (msr-sie-fri-hi) 8239 (halfword hi FRintk 0)) 8240 (saturate-v (abs (ext DI arglo)) 32767 -32768 (msr-sie-fri-lo) 8241 (halfword lo FRintk 0))) 8242 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 8243 (fr550 (unit u-media))) 8244) 8245 8246; How to extend from a mode to get the intended signedness. 8247(define-pmacro (DI-ext-HI x) (ext DI x)) 8248(define-pmacro (DI-ext-UHI x) (zext DI x)) 8249(define-pmacro (DI-ext-DI x) x) 8250 8251(define-pmacro (media-arith-sat-semantics 8252 operation arg1 arg2 res mode max min sie) 8253 (sequence ((DI tmp)) 8254 ; Make sure we saturate at max/min against a value that is 8255 ; sign- or zero-extended appropriately from "mode". 8256 (set tmp (operation DI 8257 ((.sym DI-ext- mode) arg1) ((.sym DI-ext- mode) arg2))) 8258 (saturate-v tmp max min sie res)) 8259) 8260 8261(define-pmacro (media-dual-arith-sat-semantics operation mode max min) 8262 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 8263 (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) 8264 (media-arith-sat-semantics operation argihi argjhi 8265 (halfword hi FRintk 0) mode max min 8266 (msr-sie-fri-hi)) 8267 (media-arith-sat-semantics operation argilo argjlo 8268 (halfword lo FRintk 0) mode max min 8269 (msr-sie-fri-lo))) 8270) 8271 8272(define-pmacro (media-dual-arith-sat name operation mode max min op ope comment) 8273 (dni name 8274 (comment) 8275 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 8276 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 8277 (.str name "$pack $FRinti,$FRintj,$FRintk") 8278 (+ pack FRintk op FRinti ope FRintj) 8279 (media-dual-arith-sat-semantics operation mode max min) 8280 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 8281 (fr500 (unit u-media)) (fr550 (unit u-media))) 8282 ) 8283) 8284 8285(media-dual-arith-sat maddhss add HI 32767 -32768 OP_7B OPE1_10 "Media dual add signed with saturation") 8286(media-dual-arith-sat maddhus add UHI 65535 0 OP_7B OPE1_11 "Media dual add unsigned with saturation") 8287 8288(media-dual-arith-sat msubhss sub HI 32767 -32768 OP_7B OPE1_12 "Media dual sub signed with saturation") 8289(media-dual-arith-sat msubhus sub UHI 65535 0 OP_7B OPE1_13 "Media dual sub unsigned with saturation") 8290 8291(define-pmacro (conditional-media-dual-arith-sat 8292 name operation mode max min op ope comment) 8293 (dni name 8294 (comment) 8295 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 8296 (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) 8297 (.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond") 8298 (+ pack FRintk op FRinti CCi cond ope FRintj) 8299 (if (eq CCi (or cond 2)) 8300 (media-dual-arith-sat-semantics operation mode max min)) 8301 ((fr400 (unit u-media-1)) (fr450 (unit u-media-1)) 8302 (fr500 (unit u-media)) (fr550 (unit u-media))) 8303 ) 8304) 8305 8306(conditional-media-dual-arith-sat cmaddhss add HI 32767 -32768 OP_71 OPE4_0 "Conditional Media dual add signed with saturation") 8307(conditional-media-dual-arith-sat cmaddhus add UHI 65535 0 OP_71 OPE4_1 "Conditional Media dual add unsigned with saturation") 8308 8309(conditional-media-dual-arith-sat cmsubhss sub HI 32767 -32768 OP_71 OPE4_2 "Conditional Media dual sub signed with saturation") 8310(conditional-media-dual-arith-sat cmsubhus sub UHI 65535 0 OP_71 OPE4_3 "Conditional Media dual sub unsigned with saturation") 8311 8312(define-pmacro (media-quad-arith-sat-semantics cond operation mode max min) 8313 (if (orif (register-unaligned FRintieven 2) 8314 (orif (register-unaligned FRintjeven 2) 8315 (register-unaligned FRintkeven 2))) 8316 (c-call VOID "@cpu@_media_register_not_aligned") 8317 (if cond 8318 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 8319 ; hack to get FRintkeven referenced as a target for profiling 8320 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 8321 (extract-hilo FRintieven 0 FRintjeven 0 8322 argihi argilo argjhi argjlo) 8323 (media-arith-sat-semantics operation argihi argjhi 8324 (halfword hi FRintkeven 0) mode 8325 max min (msr-sie-fri-hi)) 8326 (media-arith-sat-semantics operation argilo argjlo 8327 (halfword lo FRintkeven 0) mode 8328 max min (msr-sie-fri-lo)) 8329 (extract-hilo FRintieven 1 FRintjeven 1 8330 argihi argilo argjhi argjlo) 8331 (media-arith-sat-semantics operation argihi argjhi 8332 (halfword hi FRintkeven 1) mode 8333 max min (msr-sie-fri-1-hi)) 8334 (media-arith-sat-semantics operation argilo argjlo 8335 (halfword lo FRintkeven 1) mode 8336 max min (msr-sie-fri-1-lo))))) 8337) 8338 8339(define-pmacro (media-quad-arith-sat name operation mode max min op ope comment) 8340 (dni name 8341 (comment) 8342 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 8343 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 8344 (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven") 8345 (+ pack FRintkeven op FRintieven ope FRintjeven) 8346 (media-quad-arith-sat-semantics 1 operation mode max min) 8347 ((fr400 (unit u-media-1-quad 8348 (in FRinti FRintieven) 8349 (in FRintj FRintjeven) 8350 (out FRintk FRintkeven))) 8351 (fr450 (unit u-media-1-quad 8352 (in FRinti FRintieven) 8353 (in FRintj FRintjeven) 8354 (out FRintk FRintkeven))) 8355 (fr500 (unit u-media-quad-arith 8356 (in FRinti FRintieven) 8357 (in FRintj FRintjeven) 8358 (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) 8359 ) 8360) 8361 8362(media-quad-arith-sat mqaddhss add HI 32767 -32768 OP_7B OPE1_18 "Media quad add signed with saturation") 8363(media-quad-arith-sat mqaddhus add UHI 65535 0 OP_7B OPE1_19 "Media quad add unsigned with saturation") 8364 8365(media-quad-arith-sat mqsubhss sub HI 32767 -32768 OP_7B OPE1_1A "Media quad sub signed with saturation") 8366(media-quad-arith-sat mqsubhus sub UHI 65535 0 OP_7B OPE1_1B "Media quad sub unsigned with saturation") 8367 8368(define-pmacro (conditional-media-quad-arith-sat 8369 name operation mode max min op ope comment) 8370 (dni name 8371 (comment) 8372 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) 8373 (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) 8374 (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond") 8375 (+ pack FRintkeven op FRintieven CCi cond ope FRintjeven) 8376 (media-quad-arith-sat-semantics (eq CCi (or cond 2)) 8377 operation mode max min) 8378 ((fr400 (unit u-media-1-quad 8379 (in FRinti FRintieven) 8380 (in FRintj FRintjeven) 8381 (out FRintk FRintkeven))) 8382 (fr450 (unit u-media-1-quad 8383 (in FRinti FRintieven) 8384 (in FRintj FRintjeven) 8385 (out FRintk FRintkeven))) 8386 (fr500 (unit u-media-quad-arith 8387 (in FRinti FRintieven) 8388 (in FRintj FRintjeven) 8389 (out FRintk FRintkeven))) (fr550 (unit u-media-quad))) 8390 ) 8391) 8392 8393(conditional-media-quad-arith-sat cmqaddhss add HI 32767 -32768 OP_73 OPE4_0 "Conditional Media quad add signed with saturation") 8394(conditional-media-quad-arith-sat cmqaddhus add UHI 65535 0 OP_73 OPE4_1 "Conditional Media quad add unsigned with saturation") 8395 8396(conditional-media-quad-arith-sat cmqsubhss sub HI 32767 -32768 OP_73 OPE4_2 "Conditional Media quad sub signed with saturation") 8397(conditional-media-quad-arith-sat cmqsubhus sub UHI 65535 0 OP_73 OPE4_3 "Conditional Media quad sub unsigned with saturation") 8398 8399;; Return A if |A| > |B| and B is positive. Return -A if |A| > |B| and 8400;; B is negative, saturating 0x8000 as 0x7fff. Return 0 otherwise. 8401(define-pmacro (media-low-clear-semantics a b) 8402 (cond HI 8403 ((le UHI (abs a) (abs b)) 0) 8404 ((le HI 0 b) a) 8405 ((eq HI a -32768) 32767) 8406 (else (neg a)))) 8407 8408;; Return A if -|B| < A < |B|. Return -B if A <= -|B|, saturating 0x8000 8409;; as 0x7fff. Return B if A >= |B|. 8410(define-pmacro (media-scope-limit-semantics a b) 8411 (cond HI 8412 ((andif (gt HI b -32768) 8413 (ge HI a (abs b))) b) 8414 ((gt HI a (neg (abs b))) a) 8415 ((eq HI b -32768) 32767) 8416 (else (neg b)))) 8417 8418(define-pmacro (media-quad-limit name operation op ope comment) 8419 (dni name 8420 comment 8421 ((UNIT FM0) (MACH fr450) (FR450-MAJOR M-2)) 8422 (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven") 8423 (+ pack FRintkeven op FRintieven ope FRintjeven) 8424 (if (orif (register-unaligned FRintieven 2) 8425 (orif (register-unaligned FRintjeven 2) 8426 (register-unaligned FRintkeven 2))) 8427 (c-call VOID "@cpu@_media_register_not_aligned") 8428 (sequence ((HI a1) (HI a2) (HI a3) (HI a4) 8429 (HI b1) (HI b2) (HI b3) (HI b4)) 8430 ; hack to get FRintkeven referenced as a target 8431 ; for profiling 8432 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 8433 (extract-hilo FRintieven 0 FRintjeven 0 a1 a2 b1 b2) 8434 (extract-hilo FRintieven 1 FRintjeven 1 a3 a4 b3 b4) 8435 (set (halfword hi FRintkeven 0) (operation a1 b1)) 8436 (set (halfword lo FRintkeven 0) (operation a2 b2)) 8437 (set (halfword hi FRintkeven 1) (operation a3 b3)) 8438 (set (halfword lo FRintkeven 1) (operation a4 b4)))) 8439 ((fr450 (unit u-media-1-quad 8440 (in FRinti FRintieven) 8441 (in FRintj FRintjeven) 8442 (out FRintk FRintkeven)))) 8443 ) 8444) 8445 8446(media-quad-limit mqlclrhs media-low-clear-semantics OP_78 OPE1_10 8447 "Media quad low clear") 8448(media-quad-limit mqlmths media-scope-limit-semantics OP_78 OPE1_14 8449 "Media quad scope limitation") 8450 8451(define-pmacro (media-quad-shift name operation op ope comment) 8452 (dni name 8453 (comment) 8454 ((UNIT FM0) (MACH fr450) (FR450-MAJOR M-2)) 8455 (.str name "$pack $FRintieven,$u6,$FRintkeven") 8456 (+ pack FRintkeven op FRintieven ope u6) 8457 (if (orif (register-unaligned FRintieven 2) 8458 (register-unaligned FRintkeven 2)) 8459 (c-call VOID "@cpu@_media_register_not_aligned") 8460 (sequence () 8461 ; hack to get these referenced for profiling 8462 (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) 8463 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 8464 (set (halfword hi FRintkeven 0) 8465 (operation HI (halfword hi FRintieven 0) 8466 (and u6 #xf))) 8467 (set (halfword lo FRintkeven 0) 8468 (operation HI (halfword lo FRintieven 0) 8469 (and u6 #xf))) 8470 (set (halfword hi FRintkeven 1) 8471 (operation HI (halfword hi FRintieven 1) 8472 (and u6 #xf))) 8473 (set (halfword lo FRintkeven 1) 8474 (operation HI (halfword lo FRintieven 1) 8475 (and u6 #xf))))) 8476 ((fr450 (unit u-media-3-quad 8477 (in FRinti FRintieven) 8478 (in FRintj FRintieven) 8479 (out FRintk FRintkeven)))) 8480 ) 8481) 8482 8483(media-quad-shift mqsllhi sll OP_78 OPE1_11 "Media quad left shift") 8484(media-quad-shift mqsrahi sra OP_78 OPE1_13 "Media quad right shift") 8485 8486(define-pmacro (media-acc-arith-sat name operation mode max min op ope comment) 8487 (dni name 8488 (comment) 8489 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) 8490 (FR400-MAJOR M-1) (FR450-MAJOR M-3)) 8491 (.str name "$pack $ACC40Si,$ACC40Sk") 8492 (+ pack ACC40Sk op ACC40Si ope (ACCj-null)) 8493 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) 8494 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 8495 (if (register-unaligned ACC40Si 2) 8496 (c-call VOID "@cpu@_media_acc_not_aligned") 8497 (media-arith-sat-semantics operation ACC40Si 8498 (nextreg h-acc40S ACC40Si 1) 8499 ACC40Sk mode max min (msr-sie-acci))))) 8500 ((fr400 (unit u-media-2-acc)) (fr450 (unit u-media-2-acc)) 8501 (fr550 (unit u-media-4-acc))) 8502 ) 8503) 8504 8505(media-acc-arith-sat maddaccs add DI #x7fffffffff (inv DI #x7fffffffff) 8506 OP_78 OPE1_04 "Media accumulator addition") 8507(media-acc-arith-sat msubaccs sub DI #x7fffffffff (inv DI #x7fffffffff) 8508 OP_78 OPE1_05 "Media accumulator subtraction") 8509 8510(define-pmacro (media-dual-acc-arith-sat name operation mode max min op ope 8511 comment) 8512 (dni name 8513 (comment) 8514 ((UNIT MDUALACC) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) 8515 (FR400-MAJOR M-2) (FR450-MAJOR M-4)) 8516 (.str name "$pack $ACC40Si,$ACC40Sk") 8517 (+ pack ACC40Sk op ACC40Si ope (ACCj-null)) 8518 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) 8519 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 8520 (if (register-unaligned ACC40Si 4) 8521 (c-call VOID "@cpu@_media_acc_not_aligned") 8522 (if (register-unaligned ACC40Sk 2) 8523 (c-call VOID "@cpu@_media_acc_not_aligned") 8524 (sequence () 8525 (media-arith-sat-semantics operation ACC40Si 8526 (nextreg h-acc40S ACC40Si 1) 8527 ACC40Sk mode max min 8528 (msr-sie-acci)) 8529 (media-arith-sat-semantics operation 8530 (nextreg h-acc40S ACC40Si 2) 8531 (nextreg h-acc40S ACC40Si 3) 8532 (nextreg h-acc40S ACC40Sk 1) 8533 mode max min 8534 (msr-sie-acci-1))))))) 8535 ((fr400 (unit u-media-2-acc-dual)) (fr450 (unit u-media-2-acc-dual)) 8536 (fr550 (unit u-media-4-acc-dual))) 8537 ) 8538) 8539 8540(media-dual-acc-arith-sat mdaddaccs add DI #x7fffffffff (inv DI #x7fffffffff) 8541 OP_78 OPE1_06 "Media accumulator addition") 8542(media-dual-acc-arith-sat mdsubaccs sub DI #x7fffffffff (inv DI #x7fffffffff) 8543 OP_78 OPE1_07 "Media accumulator subtraction") 8544 8545(dni masaccs 8546 "Media add and subtract signed accumulator with saturation" 8547 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) 8548 (FR400-MAJOR M-1) (FR450-MAJOR M-3)) 8549 "masaccs$pack $ACC40Si,$ACC40Sk" 8550 (+ pack ACC40Sk OP_78 ACC40Si OPE1_08 (ACCj-null)) 8551 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) 8552 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 8553 (if (register-unaligned ACC40Si 2) 8554 (c-call VOID "@cpu@_media_acc_not_aligned") 8555 (if (register-unaligned ACC40Sk 2) 8556 (c-call VOID "@cpu@_media_acc_not_aligned") 8557 (sequence () 8558 (media-arith-sat-semantics add ACC40Si 8559 (nextreg h-acc40S ACC40Si 1) 8560 ACC40Sk DI 8561 #x7fffffffff 8562 (inv DI #x7fffffffff) 8563 (msr-sie-acci)) 8564 (media-arith-sat-semantics sub ACC40Si 8565 (nextreg h-acc40S ACC40Si 1) 8566 (nextreg h-acc40S ACC40Sk 1) 8567 DI 8568 #x7fffffffff 8569 (inv DI #x7fffffffff) 8570 (msr-sie-acci-1))))))) 8571 ((fr400 (unit u-media-2-add-sub)) (fr450 (unit u-media-2-add-sub)) 8572 (fr550 (unit u-media-4-add-sub))) 8573 ) 8574 8575(dni mdasaccs 8576 "Media add and subtract signed accumulator with saturation" 8577 ((UNIT MDUALACC) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) 8578 (FR400-MAJOR M-2) (FR450-MAJOR M-4)) 8579 "mdasaccs$pack $ACC40Si,$ACC40Sk" 8580 (+ pack ACC40Sk OP_78 ACC40Si OPE1_09 (ACCj-null)) 8581 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si)) 8582 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 8583 (if (register-unaligned ACC40Si 4) 8584 (c-call VOID "@cpu@_media_acc_not_aligned") 8585 (if (register-unaligned ACC40Sk 4) 8586 (c-call VOID "@cpu@_media_acc_not_aligned") 8587 (sequence () 8588 (media-arith-sat-semantics add ACC40Si 8589 (nextreg h-acc40S ACC40Si 1) 8590 ACC40Sk DI 8591 #x7fffffffff 8592 (inv DI #x7fffffffff) 8593 (msr-sie-acci)) 8594 (media-arith-sat-semantics sub ACC40Si 8595 (nextreg h-acc40S ACC40Si 1) 8596 (nextreg h-acc40S ACC40Sk 1) 8597 DI 8598 #x7fffffffff 8599 (inv DI #x7fffffffff) 8600 (msr-sie-acci-1)) 8601 (media-arith-sat-semantics add 8602 (nextreg h-acc40S ACC40Si 2) 8603 (nextreg h-acc40S ACC40Si 3) 8604 (nextreg h-acc40S ACC40Sk 2) 8605 DI 8606 #x7fffffffff 8607 (inv DI #x7fffffffff) 8608 (msr-sie-acci-2)) 8609 (media-arith-sat-semantics sub 8610 (nextreg h-acc40S ACC40Si 2) 8611 (nextreg h-acc40S ACC40Si 3) 8612 (nextreg h-acc40S ACC40Sk 3) 8613 DI 8614 #x7fffffffff 8615 (inv DI #x7fffffffff) 8616 (msr-sie-acci-3))))))) 8617 ((fr400 (unit u-media-2-add-sub-dual)) 8618 (fr450 (unit u-media-2-add-sub-dual)) 8619 (fr550 (unit u-media-4-add-sub-dual))) 8620 ) 8621 8622(define-pmacro (media-multiply-semantics conv arg1 arg2 res) 8623 (set res (mul DI (conv DI arg1) (conv DI arg2))) 8624) 8625 8626(define-pmacro (media-dual-multiply-semantics cond mode conv rhs1 rhs2) 8627 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 8628 (if (register-unaligned ACC40Sk 2) 8629 (c-call VOID "@cpu@_media_acc_not_aligned") 8630 (if cond 8631 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 8632 (extract-hilo FRinti 0 FRintj 0 8633 argihi argilo argjhi argjlo) 8634 (media-multiply-semantics conv argihi rhs1 ACC40Sk) 8635 (media-multiply-semantics conv argilo rhs2 8636 (nextreg h-acc40S ACC40Sk 1)))))) 8637) 8638 8639(define-pmacro (media-dual-multiply name mode conv rhs1 rhs2 op ope comment) 8640 (dni name 8641 (comment) 8642 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 8643 (FR400-MAJOR M-1) (FR450-MAJOR M-3) PRESERVE-OVF) 8644 (.str name "$pack $FRinti,$FRintj,$ACC40Sk") 8645 (+ pack ACC40Sk op FRinti ope FRintj) 8646 (media-dual-multiply-semantics 1 mode conv rhs1 rhs2) 8647 ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) 8648 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 8649 ) 8650) 8651 8652(media-dual-multiply mmulhs HI ext argjhi argjlo OP_7B OPE1_14 "Media dual multiply signed") 8653(media-dual-multiply mmulhu UHI zext argjhi argjlo OP_7B OPE1_15 "Media dual multiply unsigned") 8654 8655(media-dual-multiply mmulxhs HI ext argjlo argjhi OP_7B OPE1_28 "Media dual cross multiply signed") 8656(media-dual-multiply mmulxhu UHI zext argjlo argjhi OP_7B OPE1_29 "Media dual cross multiply unsigned") 8657 8658(define-pmacro (conditional-media-dual-multiply 8659 name mode conv rhs1 rhs2 op ope comment) 8660 (dni name 8661 (comment) 8662 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 8663 (FR400-MAJOR M-1) (FR450-MAJOR M-3) 8664 PRESERVE-OVF CONDITIONAL) 8665 (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") 8666 (+ pack ACC40Sk op FRinti CCi cond ope FRintj) 8667 (media-dual-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2) 8668 ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) 8669 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 8670 ) 8671) 8672 8673(conditional-media-dual-multiply cmmulhs HI ext argjhi argjlo OP_72 OPE4_0 "Conditional Media dual multiply signed") 8674(conditional-media-dual-multiply cmmulhu UHI zext argjhi argjlo OP_72 OPE4_1 "Conditional Media dual multiply unsigned") 8675 8676(define-pmacro (media-quad-multiply-semantics cond mode conv rhs1 rhs2) 8677 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 8678 (if (register-unaligned ACC40Sk 4) 8679 (c-call VOID "@cpu@_media_acc_not_aligned") 8680 (if (orif (register-unaligned FRintieven 2) 8681 (register-unaligned FRintjeven 2)) 8682 (c-call VOID "@cpu@_media_register_not_aligned") 8683 (if cond 8684 (sequence ((mode argihi) (mode argilo) 8685 (mode argjhi) (mode argjlo)) 8686 (extract-hilo FRintieven 0 FRintjeven 0 8687 argihi argilo argjhi argjlo) 8688 (media-multiply-semantics conv argihi rhs1 ACC40Sk) 8689 (media-multiply-semantics conv argilo rhs2 8690 (nextreg h-acc40S ACC40Sk 1)) 8691 (extract-hilo FRintieven 1 FRintjeven 1 8692 argihi argilo argjhi argjlo) 8693 (media-multiply-semantics conv argihi rhs1 8694 (nextreg h-acc40S ACC40Sk 2)) 8695 (media-multiply-semantics conv argilo rhs2 8696 (nextreg h-acc40S ACC40Sk 3))))))) 8697) 8698 8699(define-pmacro (media-quad-multiply name mode conv rhs1 rhs2 op ope comment) 8700 (dni name 8701 (comment) 8702 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 8703 (FR400-MAJOR M-2) (FR450-MAJOR M-4) PRESERVE-OVF) 8704 (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") 8705 (+ pack ACC40Sk op FRintieven ope FRintjeven) 8706 (media-quad-multiply-semantics 1 mode conv rhs1 rhs2) 8707 ((fr400 (unit u-media-2-quad 8708 (in FRinti FRintieven) 8709 (in FRintj FRintjeven))) 8710 (fr450 (unit u-media-2-quad 8711 (in FRinti FRintieven) 8712 (in FRintj FRintjeven))) 8713 (fr500 (unit u-media-quad-mul 8714 (in FRinti FRintieven) 8715 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8716 ) 8717) 8718 8719(media-quad-multiply mqmulhs HI ext argjhi argjlo OP_7B OPE1_1C "Media quad multiply signed") 8720(media-quad-multiply mqmulhu UHI zext argjhi argjlo OP_7B OPE1_1D "Media quad multiply unsigned") 8721 8722(media-quad-multiply mqmulxhs HI ext argjlo argjhi OP_7B OPE1_2A "Media quad cross multiply signed") 8723(media-quad-multiply mqmulxhu UHI zext argjlo argjhi OP_7B OPE1_2B "Media quad cross multiply unsigned") 8724 8725(define-pmacro (conditional-media-quad-multiply 8726 name mode conv rhs1 rhs2 op ope comment) 8727 (dni name 8728 (comment) 8729 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 8730 (FR400-MAJOR M-2) (FR450-MAJOR M-4) 8731 PRESERVE-OVF CONDITIONAL) 8732 (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond") 8733 (+ pack ACC40Sk op FRintieven CCi cond ope FRintjeven) 8734 (media-quad-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2) 8735 ((fr400 (unit u-media-2-quad 8736 (in FRinti FRintieven) 8737 (in FRintj FRintjeven))) 8738 (fr450 (unit u-media-2-quad 8739 (in FRinti FRintieven) 8740 (in FRintj FRintjeven))) 8741 (fr500 (unit u-media-quad-mul 8742 (in FRinti FRintieven) 8743 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8744 ) 8745) 8746 8747(conditional-media-quad-multiply cmqmulhs HI ext argjhi argjlo OP_74 OPE4_0 "Conditional Media quad multiply signed") 8748(conditional-media-quad-multiply cmqmulhu UHI zext argjhi argjlo OP_74 OPE4_1 "Conditional Media quad multiply unsigned") 8749 8750(define-pmacro (media-multiply-acc-semantics 8751 conv arg1 addop arg2 res max min sie) 8752 (sequence ((DI tmp)) 8753 (set tmp (addop res (mul DI (conv DI arg1) (conv DI arg2)))) 8754 (saturate-v tmp max min sie res)) 8755) 8756 8757(define-pmacro (media-dual-multiply-acc-semantics 8758 cond mode conv addop rhw res max min) 8759 (if (c-call SI "@cpu@_check_acc_range" (index-of res)) 8760 (if (register-unaligned res 2) 8761 (c-call VOID "@cpu@_media_acc_not_aligned") 8762 (if cond 8763 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 8764 (extract-hilo FRinti 0 FRintj 0 8765 argihi argilo argjhi argjlo) 8766 (media-multiply-acc-semantics conv argihi addop argjhi 8767 res 8768 max min (msr-sie-acci)) 8769 (media-multiply-acc-semantics conv argilo addop argjlo 8770 (nextreg rhw res 1) 8771 max min (msr-sie-acci-1)))))) 8772) 8773 8774(define-pmacro (media-dual-multiply-acc 8775 name mode conv addop rhw res max min op ope comment) 8776 (dni name 8777 (comment) 8778 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 8779 (FR400-MAJOR M-1) (FR450-MAJOR M-3)) 8780 (.str name "$pack $FRinti,$FRintj,$" res) 8781 (+ pack res op FRinti ope FRintj) 8782 (media-dual-multiply-acc-semantics 1 mode conv addop rhw res max min) 8783 ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) 8784 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 8785 ) 8786) 8787 8788(media-dual-multiply-acc mmachs HI ext add h-acc40S ACC40Sk 8789 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8790 OP_7B OPE1_16 8791 "Media dual multiply and accumulate signed") 8792 8793(media-dual-multiply-acc mmachu UHI zext add h-acc40U ACC40Uk 8794 (const DI #xffffffffff) (const DI 0) 8795 OP_7B OPE1_17 8796 "Media dual multiply and accumulate unsigned") 8797 8798(media-dual-multiply-acc mmrdhs HI ext sub h-acc40S ACC40Sk 8799 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8800 OP_7B OPE1_30 8801 "Media dual multiply and reduce signed") 8802 8803(media-dual-multiply-acc mmrdhu UHI zext sub h-acc40U ACC40Uk 8804 (const DI #xffffffffff) (const DI 0) 8805 OP_7B OPE1_31 8806 "Media dual multiply and reduce unsigned") 8807 8808(define-pmacro (conditional-media-dual-multiply-acc 8809 name mode conv addop rhw res max min op ope comment) 8810 (dni name 8811 (comment) 8812 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 8813 (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL) 8814 (.str name "$pack $FRinti,$FRintj,$" res ",$CCi,$cond") 8815 (+ pack res op FRinti CCi cond ope FRintj) 8816 (media-dual-multiply-acc-semantics (eq CCi (or cond 2)) 8817 mode conv addop rhw res max min) 8818 ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) 8819 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 8820 ) 8821) 8822 8823(conditional-media-dual-multiply-acc cmmachs HI ext add h-acc40S ACC40Sk 8824 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8825 OP_72 OPE4_2 8826 "Conditional Media dual multiply and accumulate signed") 8827 8828(conditional-media-dual-multiply-acc cmmachu UHI zext add h-acc40U ACC40Uk 8829 (const DI #xffffffffff) (const DI 0) 8830 OP_72 OPE4_3 8831 "Conditional Media dual multiply and accumulate unsigned") 8832 8833(define-pmacro (media-quad-multiply-acc-semantics 8834 cond mode conv addop rhw res max min) 8835 (if (c-call SI "@cpu@_check_acc_range" (index-of res)) 8836 (if (register-unaligned res 4) 8837 (c-call VOID "@cpu@_media_acc_not_aligned") 8838 (if (orif (register-unaligned FRintieven 2) 8839 (register-unaligned FRintjeven 2)) 8840 (c-call VOID "@cpu@_media_register_not_aligned") 8841 (if cond 8842 (sequence ((mode argihi) (mode argilo) 8843 (mode argjhi) (mode argjlo)) 8844 (extract-hilo FRintieven 0 FRintjeven 0 8845 argihi argilo argjhi argjlo) 8846 (media-multiply-acc-semantics conv argihi addop argjhi 8847 res 8848 max min (msr-sie-acci)) 8849 (media-multiply-acc-semantics conv argilo addop argjlo 8850 (nextreg rhw res 1) 8851 max min (msr-sie-acci-1)) 8852 (extract-hilo FRintieven 1 FRintjeven 1 8853 argihi argilo argjhi argjlo) 8854 (media-multiply-acc-semantics conv argihi addop argjhi 8855 (nextreg rhw res 2) 8856 max min (msr-sie-acci-2)) 8857 (media-multiply-acc-semantics conv argilo addop argjlo 8858 (nextreg rhw res 3) 8859 max min 8860 (msr-sie-acci-3))))))) 8861) 8862 8863(define-pmacro (media-quad-multiply-acc 8864 name mode conv addop rhw res max min op ope comment) 8865 (dni name 8866 (comment) 8867 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 8868 (FR400-MAJOR M-2) (FR450-MAJOR M-4)) 8869 (.str name "$pack $FRintieven,$FRintjeven,$" res) 8870 (+ pack res op FRintieven ope FRintjeven) 8871 (media-quad-multiply-acc-semantics 1 mode conv addop rhw res max min) 8872 ((fr400 (unit u-media-2-quad 8873 (in FRinti FRintieven) 8874 (in FRintj FRintjeven))) 8875 (fr450 (unit u-media-2-quad 8876 (in FRinti FRintieven) 8877 (in FRintj FRintjeven))) 8878 (fr500 (unit u-media-quad-mul 8879 (in FRinti FRintieven) 8880 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8881 ) 8882) 8883 8884(media-quad-multiply-acc mqmachs HI ext add h-acc40S ACC40Sk 8885 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8886 OP_7B OPE1_1E 8887 "Media quad multiply and accumulate signed") 8888 8889(media-quad-multiply-acc mqmachu UHI zext add h-acc40U ACC40Uk 8890 (const DI #xffffffffff) (const DI 0) 8891 OP_7B OPE1_1F 8892 "Media quad multiply and accumulate unsigned") 8893 8894(define-pmacro (conditional-media-quad-multiply-acc 8895 name mode conv addop rhw res max min op ope comment) 8896 (dni name 8897 (comment) 8898 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 8899 (FR400-MAJOR M-2) (FR450-MAJOR M-4) CONDITIONAL) 8900 (.str name "$pack $FRintieven,$FRintjeven,$" res ",$CCi,$cond") 8901 (+ pack res op FRintieven CCi cond ope FRintjeven) 8902 (media-quad-multiply-acc-semantics (eq CCi (or cond 2)) 8903 mode conv addop rhw res max min) 8904 ((fr400 (unit u-media-2-quad 8905 (in FRinti FRintieven) 8906 (in FRintj FRintjeven))) 8907 (fr450 (unit u-media-2-quad 8908 (in FRinti FRintieven) 8909 (in FRintj FRintjeven))) 8910 (fr500 (unit u-media-quad-mul 8911 (in FRinti FRintieven) 8912 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 8913 ) 8914) 8915 8916(conditional-media-quad-multiply-acc cmqmachs HI ext add h-acc40S ACC40Sk 8917 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8918 OP_74 OPE4_2 8919 "Conditional Media quad multiply and accumulate signed") 8920 8921(conditional-media-quad-multiply-acc cmqmachu UHI zext add h-acc40U ACC40Uk 8922 (const DI #xffffffffff) (const DI 0) 8923 OP_74 OPE4_3 8924 "Conditional media quad multiply and accumulate unsigned") 8925 8926(define-pmacro (media-quad-multiply-cross-acc-semantics 8927 cond mode conv addop rhw res max min) 8928 (if (c-call SI "@cpu@_check_acc_range" (index-of res)) 8929 (if (register-unaligned res 4) 8930 (c-call VOID "@cpu@_media_acc_not_aligned") 8931 (if (orif (register-unaligned FRintieven 2) 8932 (register-unaligned FRintjeven 2)) 8933 (c-call VOID "@cpu@_media_register_not_aligned") 8934 (if cond 8935 (sequence ((mode argihi) (mode argilo) 8936 (mode argjhi) (mode argjlo)) 8937 (extract-hilo FRintieven 0 FRintjeven 0 8938 argihi argilo argjhi argjlo) 8939 (media-multiply-acc-semantics conv argihi addop argjhi 8940 (nextreg rhw res 2) 8941 max min (msr-sie-acci-2)) 8942 (media-multiply-acc-semantics conv argilo addop argjlo 8943 (nextreg rhw res 3) 8944 max min (msr-sie-acci-3)) 8945 (extract-hilo FRintieven 1 FRintjeven 1 8946 argihi argilo argjhi argjlo) 8947 (media-multiply-acc-semantics conv argihi addop argjhi 8948 res 8949 max min (msr-sie-acci)) 8950 (media-multiply-acc-semantics conv argilo addop argjlo 8951 (nextreg rhw res 1) 8952 max min 8953 (msr-sie-acci-1))))))) 8954) 8955 8956(define-pmacro (media-quad-multiply-cross-acc 8957 name mode conv addop rhw res max min op ope comment) 8958 (dni name 8959 (comment) 8960 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) 8961 (FR400-MAJOR M-2) (FR450-MAJOR M-4)) 8962 (.str name "$pack $FRintieven,$FRintjeven,$" res) 8963 (+ pack res op FRintieven ope FRintjeven) 8964 (media-quad-multiply-cross-acc-semantics 1 mode conv addop rhw res 8965 max min) 8966 ((fr400 (unit u-media-2-quad 8967 (in FRinti FRintieven) 8968 (in FRintj FRintjeven))) 8969 (fr450 (unit u-media-2-quad 8970 (in FRinti FRintieven) 8971 (in FRintj FRintjeven))) 8972 (fr550 (unit u-media-4-quad))) 8973 ) 8974) 8975 8976(media-quad-multiply-cross-acc mqxmachs HI ext add h-acc40S ACC40Sk 8977 (const DI #x7fffffffff) (const DI #xffffff8000000000) 8978 OP_78 OPE1_00 8979 "Media quad multiply and cross accumulate signed") 8980 8981(define-pmacro (media-quad-cross-multiply-cross-acc-semantics 8982 cond mode conv addop rhw res max min) 8983 (if (c-call SI "@cpu@_check_acc_range" (index-of res)) 8984 (if (register-unaligned res 4) 8985 (c-call VOID "@cpu@_media_acc_not_aligned") 8986 (if (orif (register-unaligned FRintieven 2) 8987 (register-unaligned FRintjeven 2)) 8988 (c-call VOID "@cpu@_media_register_not_aligned") 8989 (if cond 8990 (sequence ((mode argihi) (mode argilo) 8991 (mode argjhi) (mode argjlo)) 8992 (extract-hilo FRintieven 0 FRintjeven 0 8993 argihi argilo argjhi argjlo) 8994 (media-multiply-acc-semantics conv argihi addop argjlo 8995 (nextreg rhw res 2) 8996 max min (msr-sie-acci-2)) 8997 (media-multiply-acc-semantics conv argilo addop argjhi 8998 (nextreg rhw res 3) 8999 max min (msr-sie-acci-3)) 9000 (extract-hilo FRintieven 1 FRintjeven 1 9001 argihi argilo argjhi argjlo) 9002 (media-multiply-acc-semantics conv argihi addop argjlo 9003 res 9004 max min (msr-sie-acci)) 9005 (media-multiply-acc-semantics conv argilo addop argjhi 9006 (nextreg rhw res 1) 9007 max min 9008 (msr-sie-acci-1))))))) 9009) 9010 9011(define-pmacro (media-quad-cross-multiply-cross-acc 9012 name mode conv addop rhw res max min op ope comment) 9013 (dni name 9014 (comment) 9015 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) 9016 (FR400-MAJOR M-2) (FR450-MAJOR M-4)) 9017 (.str name "$pack $FRintieven,$FRintjeven,$" res) 9018 (+ pack res op FRintieven ope FRintjeven) 9019 (media-quad-cross-multiply-cross-acc-semantics 1 mode conv addop rhw res 9020 max min) 9021 ((fr400 (unit u-media-2-quad 9022 (in FRinti FRintieven) 9023 (in FRintj FRintjeven))) 9024 (fr450 (unit u-media-2-quad 9025 (in FRinti FRintieven) 9026 (in FRintj FRintjeven))) 9027 (fr550 (unit u-media-4-quad))) 9028 ) 9029) 9030 9031(media-quad-cross-multiply-cross-acc mqxmacxhs HI ext add h-acc40S ACC40Sk 9032 (const DI #x7fffffffff) (const DI #xffffff8000000000) 9033 OP_78 OPE1_01 9034 "Media quad cross multiply and cross accumulate signed") 9035 9036(define-pmacro (media-quad-cross-multiply-acc-semantics 9037 cond mode conv addop rhw res max min) 9038 (if (c-call SI "@cpu@_check_acc_range" (index-of res)) 9039 (if (register-unaligned res 4) 9040 (c-call VOID "@cpu@_media_acc_not_aligned") 9041 (if (orif (register-unaligned FRintieven 2) 9042 (register-unaligned FRintjeven 2)) 9043 (c-call VOID "@cpu@_media_register_not_aligned") 9044 (if cond 9045 (sequence ((mode argihi) (mode argilo) 9046 (mode argjhi) (mode argjlo)) 9047 (extract-hilo FRintieven 0 FRintjeven 0 9048 argihi argilo argjhi argjlo) 9049 (media-multiply-acc-semantics conv argihi addop argjlo 9050 res 9051 max min (msr-sie-acci)) 9052 (media-multiply-acc-semantics conv argilo addop argjhi 9053 (nextreg rhw res 1) 9054 max min (msr-sie-acci-1)) 9055 (extract-hilo FRintieven 1 FRintjeven 1 9056 argihi argilo argjhi argjlo) 9057 (media-multiply-acc-semantics conv argihi addop argjlo 9058 (nextreg rhw res 2) 9059 max min (msr-sie-acci-2)) 9060 (media-multiply-acc-semantics conv argilo addop argjhi 9061 (nextreg rhw res 3) 9062 max min 9063 (msr-sie-acci-3))))))) 9064) 9065 9066(define-pmacro (media-quad-cross-multiply-acc 9067 name mode conv addop rhw res max min op ope comment) 9068 (dni name 9069 (comment) 9070 ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4) 9071 (FR400-MAJOR M-2) (FR450-MAJOR M-4)) 9072 (.str name "$pack $FRintieven,$FRintjeven,$" res) 9073 (+ pack res op FRintieven ope FRintjeven) 9074 (media-quad-cross-multiply-acc-semantics 1 mode conv addop rhw res 9075 max min) 9076 ((fr400 (unit u-media-2-quad 9077 (in FRinti FRintieven) 9078 (in FRintj FRintjeven))) 9079 (fr450 (unit u-media-2-quad 9080 (in FRinti FRintieven) 9081 (in FRintj FRintjeven))) 9082 (fr550 (unit u-media-4-quad))) 9083 ) 9084) 9085 9086(media-quad-cross-multiply-acc mqmacxhs HI ext add h-acc40S ACC40Sk 9087 (const DI #x7fffffffff) (const DI #xffffff8000000000) 9088 OP_78 OPE1_02 9089 "Media quad cross multiply and accumulate signed") 9090 9091(define-pmacro (media-complex-semantics 9092 conv lhs1 rhs1 lhs2 rhs2 res max min sie) 9093 (sequence ((DI tmp1) (DI tmp2)) 9094 (media-multiply-semantics conv lhs1 rhs1 tmp1) 9095 (media-multiply-semantics conv lhs2 rhs2 tmp2) 9096 (set tmp1 (sub tmp1 tmp2)) 9097 (saturate-v tmp1 max min sie res)) 9098) 9099 9100(define-pmacro (media-complex-semantics-i 9101 conv lhs1 rhs1 lhs2 rhs2 res max min sie) 9102 (sequence ((DI tmp1) (DI tmp2)) 9103 (media-multiply-semantics conv lhs1 rhs1 tmp1) 9104 (media-multiply-semantics conv lhs2 rhs2 tmp2) 9105 (set tmp1 (add tmp1 tmp2)) 9106 (saturate-v tmp1 max min sie res)) 9107) 9108 9109(define-pmacro (media-dual-complex-semantics mode conv rhs1 rhs2 max min) 9110 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 9111 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 9112 (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) 9113 (media-complex-semantics conv argihi rhs1 argilo rhs2 ACC40Sk 9114 max min (msr-sie-acci)))) 9115) 9116 9117(define-pmacro (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min) 9118 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 9119 (sequence ((mode argihi) (mode argilo) (mode argjhi) (mode argjlo)) 9120 (extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo) 9121 (media-complex-semantics-i conv argihi rhs1 argilo rhs2 ACC40Sk 9122 max min (msr-sie-acci)))) 9123) 9124 9125(define-pmacro (media-dual-complex 9126 name mode conv rhs1 rhs2 max min op ope comment) 9127 (dni name 9128 (comment) 9129 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 9130 (FR400-MAJOR M-1) (FR450-MAJOR M-3)) 9131 (.str name "$pack $FRinti,$FRintj,$ACC40Sk") 9132 (+ pack ACC40Sk op FRinti ope FRintj) 9133 (media-dual-complex-semantics mode conv rhs1 rhs2 max min) 9134 ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) 9135 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 9136 ) 9137) 9138 9139(define-pmacro (media-dual-complex-i 9140 name mode conv rhs1 rhs2 max min op ope comment) 9141 (dni name 9142 (comment) 9143 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 9144 (FR400-MAJOR M-1) (FR450-MAJOR M-3)) 9145 (.str name "$pack $FRinti,$FRintj,$ACC40Sk") 9146 (+ pack ACC40Sk op FRinti ope FRintj) 9147 (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min) 9148 ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) 9149 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 9150 ) 9151) 9152 9153(media-dual-complex mcpxrs HI ext argjhi argjlo 9154 (const DI #x7fffffffff) (const DI #xffffff8000000000) 9155 OP_7B OPE1_20 9156 "Media dual complex real signed with saturation") 9157 9158(media-dual-complex mcpxru UHI zext argjhi argjlo 9159 (const DI #xffffffffff) (const DI 0) 9160 OP_7B OPE1_21 9161 "Media dual complex real unsigned with saturation") 9162 9163(media-dual-complex-i mcpxis HI ext argjlo argjhi 9164 (const DI #x7fffffffff) (const DI #xffffff8000000000) 9165 OP_7B OPE1_22 9166 "Media dual complex imaginary signed with saturation") 9167 9168(media-dual-complex-i mcpxiu UHI zext argjlo argjhi 9169 (const DI #xffffffffff) (const DI 0) 9170 OP_7B OPE1_23 9171 "Media dual complex imaginary unsigned with saturation") 9172 9173(define-pmacro (conditional-media-dual-complex 9174 name mode conv rhs1 rhs2 max min op ope comment) 9175 (dni name 9176 (comment) 9177 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 9178 (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL) 9179 (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") 9180 (+ pack ACC40Sk op FRinti CCi cond ope FRintj) 9181 (if (eq CCi (or cond 2)) 9182 (media-dual-complex-semantics mode conv rhs1 rhs2 max min)) 9183 ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) 9184 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 9185 ) 9186) 9187 9188(define-pmacro (conditional-media-dual-complex-i 9189 name mode conv rhs1 rhs2 max min op ope comment) 9190 (dni name 9191 (comment) 9192 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 9193 (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL) 9194 (.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond") 9195 (+ pack ACC40Sk op FRinti CCi cond ope FRintj) 9196 (if (eq CCi (or cond 2)) 9197 (media-dual-complex-semantics-i mode conv rhs1 rhs2 max min)) 9198 ((fr400 (unit u-media-2)) (fr450 (unit u-media-2)) 9199 (fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4))) 9200 ) 9201) 9202 9203(conditional-media-dual-complex cmcpxrs HI ext argjhi argjlo 9204 (const DI #x7fffffffff) (const DI #xffffff8000000000) 9205 OP_75 OPE4_0 9206 "Conditional Media dual complex real signed with saturation") 9207 9208(conditional-media-dual-complex cmcpxru UHI zext argjhi argjlo 9209 (const DI #xffffffffff) (const DI 0) 9210 OP_75 OPE4_1 9211 "Conditional Media dual complex real unsigned with saturation") 9212 9213(conditional-media-dual-complex-i cmcpxis HI ext argjlo argjhi 9214 (const DI #x7fffffffff) (const DI #xffffff8000000000) 9215 OP_75 OPE4_2 9216 "Conditional Media dual complex imaginary signed with saturation") 9217 9218(conditional-media-dual-complex-i cmcpxiu UHI zext argjlo argjhi 9219 (const DI #xffffffffff) (const DI 0) 9220 OP_75 OPE4_3 9221 "Conditional Media dual complex imaginary unsigned with saturation") 9222 9223(define-pmacro (media-quad-complex 9224 name mode conv rhs1 rhs2 max min op ope comment) 9225 (dni name 9226 (comment) 9227 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 9228 (FR400-MAJOR M-2) (FR450-MAJOR M-4)) 9229 (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") 9230 (+ pack ACC40Sk op FRintieven ope FRintjeven) 9231 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 9232 (if (register-unaligned ACC40Sk 2) 9233 (c-call VOID "@cpu@_media_acc_not_aligned") 9234 (if (orif (register-unaligned FRintieven 2) 9235 (register-unaligned FRintjeven 2)) 9236 (c-call VOID "@cpu@_media_register_not_aligned") 9237 (sequence ((mode argihi) (mode argilo) 9238 (mode argjhi) (mode argjlo)) 9239 (extract-hilo FRintieven 0 FRintjeven 0 9240 argihi argilo argjhi argjlo) 9241 (media-complex-semantics conv argihi rhs1 argilo rhs2 9242 ACC40Sk 9243 max min (msr-sie-acci)) 9244 (extract-hilo FRintieven 1 FRintjeven 1 9245 argihi argilo argjhi argjlo) 9246 (media-complex-semantics conv argihi rhs1 argilo rhs2 9247 (nextreg h-acc40S ACC40Sk 1) 9248 max min (msr-sie-acci-1)))))) 9249 ((fr400 (unit u-media-2-quad 9250 (in FRinti FRintieven) 9251 (in FRintj FRintjeven))) 9252 (fr450 (unit u-media-2-quad 9253 (in FRinti FRintieven) 9254 (in FRintj FRintjeven))) 9255 (fr500 (unit u-media-quad-complex 9256 (in FRinti FRintieven) 9257 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 9258 ) 9259) 9260 9261(define-pmacro (media-quad-complex-i 9262 name mode conv rhs1 rhs2 max min op ope comment) 9263 (dni name 9264 (comment) 9265 ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) 9266 (FR400-MAJOR M-2) (FR450-MAJOR M-4)) 9267 (.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk") 9268 (+ pack ACC40Sk op FRintieven ope FRintjeven) 9269 (if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk)) 9270 (if (register-unaligned ACC40Sk 2) 9271 (c-call VOID "@cpu@_media_acc_not_aligned") 9272 (if (orif (register-unaligned FRintieven 2) 9273 (register-unaligned FRintjeven 2)) 9274 (c-call VOID "@cpu@_media_register_not_aligned") 9275 (sequence ((mode argihi) (mode argilo) 9276 (mode argjhi) (mode argjlo)) 9277 (extract-hilo FRintieven 0 FRintjeven 0 9278 argihi argilo argjhi argjlo) 9279 (media-complex-semantics-i conv argihi rhs1 argilo rhs2 9280 ACC40Sk 9281 max min (msr-sie-acci)) 9282 (extract-hilo FRintieven 1 FRintjeven 1 9283 argihi argilo argjhi argjlo) 9284 (media-complex-semantics-i conv argihi rhs1 argilo rhs2 9285 (nextreg h-acc40S ACC40Sk 1) 9286 max min (msr-sie-acci-1)))))) 9287 ((fr400 (unit u-media-2-quad 9288 (in FRinti FRintieven) 9289 (in FRintj FRintjeven))) 9290 (fr450 (unit u-media-2-quad 9291 (in FRinti FRintieven) 9292 (in FRintj FRintjeven))) 9293 (fr500 (unit u-media-quad-complex 9294 (in FRinti FRintieven) 9295 (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad))) 9296 ) 9297) 9298 9299(media-quad-complex mqcpxrs HI ext argjhi argjlo 9300 (const DI #x7fffffffff) (const DI #xffffff8000000000) 9301 OP_7B OPE1_24 9302 "Media quad complex real signed with saturation") 9303 9304(media-quad-complex mqcpxru UHI zext argjhi argjlo 9305 (const DI #xffffffffff) (const DI 0) 9306 OP_7B OPE1_25 9307 "Media quad complex real unsigned with saturation") 9308 9309(media-quad-complex-i mqcpxis HI ext argjlo argjhi 9310 (const DI #x7fffffffff) (const DI #xffffff8000000000) 9311 OP_7B OPE1_26 9312 "Media quad complex imaginary signed with saturation") 9313 9314(media-quad-complex-i mqcpxiu UHI zext argjlo argjhi 9315 (const DI #xffffffffff) (const DI 0) 9316 OP_7B OPE1_27 9317 "Media quad complex imaginary unsigned with saturation") 9318 9319(define-pmacro (media-pack src1 src2 targ offset) 9320 (sequence () 9321 (set (halfword hi targ offset) (halfword lo src1 offset)) 9322 (set (halfword lo targ offset) (halfword lo src2 offset))) 9323) 9324 9325(define-pmacro (media-expand-halfword-to-word-semantics cond) 9326 (if cond 9327 (sequence ((UHI tmp)) 9328 (if (and u6 1) 9329 (set tmp (halfword lo FRinti 0)) 9330 (set tmp (halfword hi FRinti 0))) 9331 (set (halfword hi FRintk 0) tmp) 9332 (set (halfword lo FRintk 0) tmp))) 9333) 9334 9335(dni mexpdhw 9336 "Media expand halfword to word" 9337 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9338 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 9339 "mexpdhw$pack $FRinti,$u6,$FRintk" 9340 (+ pack FRintk OP_7B FRinti OPE1_32 u6) 9341 (media-expand-halfword-to-word-semantics 1) 9342 ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) 9343 (fr500 (unit u-media)) (fr550 (unit u-media))) 9344) 9345 9346(dni cmexpdhw 9347 "Conditional media expand halfword to word" 9348 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9349 (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL) 9350 "cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond" 9351 (+ pack FRintk OP_76 FRinti CCi cond OPE4_2 u6) 9352 (media-expand-halfword-to-word-semantics (eq CCi (or cond 2))) 9353 ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) 9354 (fr500 (unit u-media)) (fr550 (unit u-media))) 9355) 9356 9357(define-pmacro (media-expand-halfword-to-double-semantics cond) 9358 (if (register-unaligned FRintkeven 2) 9359 (c-call VOID "@cpu@_media_register_not_aligned") 9360 (if cond 9361 (sequence ((UHI tmp)) 9362 ; a hack to get FRintkeven referenced for profiling 9363 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 9364 (if (and u6 1) 9365 (set tmp (halfword lo FRinti 0)) 9366 (set tmp (halfword hi FRinti 0))) 9367 (set (halfword hi FRintkeven 0) tmp) 9368 (set (halfword lo FRintkeven 0) tmp) 9369 (set (halfword hi FRintkeven 1) tmp) 9370 (set (halfword lo FRintkeven 1) tmp)))) 9371) 9372 9373(dni mexpdhd 9374 "Media expand halfword to double" 9375 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9376 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 9377 "mexpdhd$pack $FRinti,$u6,$FRintkeven" 9378 (+ pack FRintkeven OP_7B FRinti OPE1_33 u6) 9379 (media-expand-halfword-to-double-semantics 1) 9380 ((fr400 (unit u-media-dual-expand 9381 (out FRintk FRintkeven))) 9382 (fr450 (unit u-media-dual-expand 9383 (out FRintk FRintkeven))) 9384 (fr500 (unit u-media-dual-expand 9385 (out FRintk FRintkeven))) 9386 (fr550 (unit u-media-dual-expand))) 9387) 9388 9389(dni cmexpdhd 9390 "Conditional media expand halfword to double" 9391 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9392 (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) 9393 "cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond" 9394 (+ pack FRintkeven OP_76 FRinti CCi cond OPE4_3 u6) 9395 (media-expand-halfword-to-double-semantics (eq CCi (or cond 2))) 9396 ((fr400 (unit u-media-dual-expand 9397 (out FRintk FRintkeven))) 9398 (fr450 (unit u-media-dual-expand 9399 (out FRintk FRintkeven))) 9400 (fr500 (unit u-media-dual-expand 9401 (out FRintk FRintkeven))) 9402 (fr550 (unit u-media-dual-expand))) 9403) 9404 9405(dni mpackh 9406 "Media halfword pack" 9407 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9408 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 9409 "mpackh$pack $FRinti,$FRintj,$FRintk" 9410 (+ pack FRintk OP_7B FRinti OPE1_34 FRintj) 9411 (media-pack FRinti FRintj FRintk 0) 9412 ((fr400 (unit u-media-3)) (fr450 (unit u-media-3)) 9413 (fr500 (unit u-media)) (fr550 (unit u-media))) 9414) 9415 9416(dni mdpackh 9417 "Media dual pack" 9418 ((UNIT FM01) (FR500-MAJOR M-5) (FR550-MAJOR M-3) 9419 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 9420 "mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven" 9421 (+ pack FRintkeven OP_7B FRintieven OPE1_36 FRintjeven) 9422 (if (orif (register-unaligned FRintieven 2) 9423 (orif (register-unaligned FRintjeven 2) 9424 (register-unaligned FRintkeven 2))) 9425 (c-call VOID "@cpu@_media_register_not_aligned") 9426 (sequence () 9427 ; hack to get these referenced for profiling 9428 (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) 9429 (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) 9430 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 9431 (media-pack FRintieven FRintjeven FRintkeven 0) 9432 (media-pack FRintieven FRintjeven FRintkeven 1))) 9433 ((fr400 (unit u-media-3-quad 9434 (in FRinti FRintieven) 9435 (in FRintj FRintjeven) 9436 (out FRintk FRintkeven))) 9437 (fr450 (unit u-media-3-quad 9438 (in FRinti FRintieven) 9439 (in FRintj FRintjeven) 9440 (out FRintk FRintkeven))) 9441 (fr500 (unit u-media-quad-arith 9442 (in FRinti FRintieven) 9443 (in FRintj FRintjeven) 9444 (out FRintk FRintkeven))) 9445 (fr550 (unit u-media-quad))) 9446) 9447 9448(define-pmacro (media-unpack src soff targ toff) 9449 (sequence () 9450 (set (halfword hi targ toff) (halfword hi src soff)) 9451 (set (halfword lo targ toff) (halfword hi src soff)) 9452 (set (halfword hi targ (add toff 1)) (halfword lo src soff)) 9453 (set (halfword lo targ (add toff 1)) (halfword lo src soff))) 9454) 9455 9456(dni munpackh 9457 "Media halfword unpack" 9458 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9459 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 9460 "munpackh$pack $FRinti,$FRintkeven" 9461 (+ pack FRintkeven OP_7B FRinti OPE1_35 (FRj-null)) 9462 (if (register-unaligned FRintkeven 2) 9463 (c-call VOID "@cpu@_media_register_not_aligned") 9464 (sequence () 9465 ; hack to get these referenced for profiling 9466 (set FRinti (c-raw-call SI "frv_ref_SI" FRinti)) 9467 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 9468 (media-unpack FRinti 0 FRintkeven 0))) 9469 ((fr400 (unit u-media-dual-expand 9470 (out FRintk FRintkeven))) 9471 (fr450 (unit u-media-dual-expand 9472 (out FRintk FRintkeven))) 9473 (fr500 (unit u-media-dual-expand 9474 (out FRintk FRintkeven))) 9475 (fr550 (unit u-media-dual-expand))) 9476) 9477 9478(dni mdunpackh 9479 "Media dual unpack" 9480 ((UNIT FM01) (FR500-MAJOR M-7) (MACH simple,tomcat,frv)) 9481 "mdunpackh$pack $FRintieven,$FRintk" 9482 (+ pack FRintk OP_7B FRintieven OPE1_37 (FRj-null)) 9483 (if (orif (register-unaligned FRintieven 2) (register-unaligned FRintk 4)) 9484 (c-call VOID "@cpu@_media_register_not_aligned") 9485 (sequence () 9486 ; hack to get these referenced for profiling 9487 (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven)) 9488 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 9489 (media-unpack FRintieven 0 FRintk 0) 9490 (media-unpack FRintieven 1 FRintk 2))) 9491 ((fr500 (unit u-media-dual-unpack 9492 (in FRinti FRintieven)))) 9493) 9494 9495(define-pmacro (ubyte num arg offset) 9496 (reg (.sym h-fr_ num) (add (index-of arg) offset))) 9497 9498(define-pmacro (mbtoh-semantics cond) 9499 (if (register-unaligned FRintkeven 2) 9500 (c-call VOID "@cpu@_media_register_not_aligned") 9501 (if cond 9502 (sequence () 9503 (set (halfword hi FRintkeven 0) (ubyte 3 FRintj 0)) 9504 (set (halfword lo FRintkeven 0) (ubyte 2 FRintj 0)) 9505 (set (halfword hi FRintkeven 1) (ubyte 1 FRintj 0)) 9506 (set (halfword lo FRintkeven 1) (ubyte 0 FRintj 0))))) 9507) 9508 9509(dni mbtoh 9510 "Media convert byte to halfword" 9511 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9512 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 9513 "mbtoh$pack $FRintj,$FRintkeven" 9514 (+ pack FRintkeven OP_7B (FRi-null) OPE1_38 FRintj) 9515 (sequence () 9516 ; hack to get these referenced for profiling 9517 (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) 9518 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 9519 (mbtoh-semantics 1)) 9520 ((fr400 (unit u-media-dual-expand 9521 (out FRintk FRintkeven))) 9522 (fr450 (unit u-media-dual-expand 9523 (out FRintk FRintkeven))) 9524 (fr500 (unit u-media-dual-btoh 9525 (out FRintk FRintkeven))) 9526 (fr550 (unit u-media-dual-expand))) 9527) 9528 9529(dni cmbtoh 9530 "Conditional media convert byte to halfword" 9531 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9532 (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) 9533 "cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond" 9534 (+ pack FRintkeven OP_77 (FRi-null) CCi cond OPE4_0 FRintj) 9535 (sequence () 9536 ; hack to get these referenced for profiling 9537 (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) 9538 (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven)) 9539 (mbtoh-semantics (eq CCi (or cond 2)))) 9540 ((fr400 (unit u-media-dual-expand 9541 (out FRintk FRintkeven))) 9542 (fr450 (unit u-media-dual-expand 9543 (out FRintk FRintkeven))) 9544 (fr500 (unit u-media-dual-btoh 9545 (out FRintk FRintkeven))) 9546 (fr550 (unit u-media-dual-expand 9547 (in FRinti FRintj)))) 9548) 9549 9550(define-pmacro (mhtob-semantics cond) 9551 (if (register-unaligned FRintjeven 2) 9552 (c-call VOID "@cpu@_media_register_not_aligned") 9553 (if cond 9554 (sequence () 9555 (set (ubyte 3 FRintk 0) (halfword hi FRintjeven 0)) 9556 (set (ubyte 2 FRintk 0) (halfword lo FRintjeven 0)) 9557 (set (ubyte 1 FRintk 0) (halfword hi FRintjeven 1)) 9558 (set (ubyte 0 FRintk 0) (halfword lo FRintjeven 1))))) 9559) 9560 9561(dni mhtob 9562 "Media convert halfword to byte" 9563 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9564 (FR400-MAJOR M-2) (FR450-MAJOR M-2)) 9565 "mhtob$pack $FRintjeven,$FRintk" 9566 (+ pack FRintk OP_7B (FRi-null) OPE1_39 FRintjeven) 9567 (sequence () 9568 ; hack to get these referenced for profiling 9569 (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) 9570 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 9571 (mhtob-semantics 1)) 9572 ((fr400 (unit u-media-dual-htob 9573 (in FRintj FRintjeven))) 9574 (fr450 (unit u-media-dual-htob 9575 (in FRintj FRintjeven))) 9576 (fr500 (unit u-media-dual-htob 9577 (in FRintj FRintjeven))) 9578 (fr550 (unit u-media-3-dual 9579 (in FRinti FRintjeven)))) 9580) 9581 9582(dni cmhtob 9583 "Conditional media convert halfword to byte" 9584 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9585 (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL) 9586 "cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond" 9587 (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_1 FRintjeven) 9588 (sequence () 9589 ; hack to get these referenced for profiling 9590 (set FRintjeven (c-raw-call SI "frv_ref_SI" FRintjeven)) 9591 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 9592 (mhtob-semantics (eq CCi (or cond 2)))) 9593 ((fr400 (unit u-media-dual-htob 9594 (in FRintj FRintjeven))) 9595 (fr450 (unit u-media-dual-htob 9596 (in FRintj FRintjeven))) 9597 (fr500 (unit u-media-dual-htob 9598 (in FRintj FRintjeven))) 9599 (fr550 (unit u-media-3-dual 9600 (in FRinti FRintjeven)))) 9601) 9602 9603(define-pmacro (mbtohe-semantics cond) 9604 (if (register-unaligned FRintk 4) 9605 (c-call VOID "@cpu@_media_register_not_aligned") 9606 (if cond 9607 (sequence () 9608 (set (halfword hi FRintk 0) (ubyte 3 FRintj 0)) 9609 (set (halfword lo FRintk 0) (ubyte 3 FRintj 0)) 9610 (set (halfword hi FRintk 1) (ubyte 2 FRintj 0)) 9611 (set (halfword lo FRintk 1) (ubyte 2 FRintj 0)) 9612 (set (halfword hi FRintk 2) (ubyte 1 FRintj 0)) 9613 (set (halfword lo FRintk 2) (ubyte 1 FRintj 0)) 9614 (set (halfword hi FRintk 3) (ubyte 0 FRintj 0)) 9615 (set (halfword lo FRintk 3) (ubyte 0 FRintj 0))))) 9616) 9617 9618(dni mbtohe 9619 "Media convert byte to halfword extended" 9620 ((UNIT FM01) (FR500-MAJOR M-7) (MACH simple,tomcat,frv)) 9621 "mbtohe$pack $FRintj,$FRintk" 9622 (+ pack FRintk OP_7B (FRi-null) OPE1_3A FRintj) 9623 (sequence () 9624 ; hack to get these referenced for profiling 9625 (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) 9626 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 9627 (mbtohe-semantics 1)) 9628 ((fr500 (unit u-media-dual-btohe))) 9629) 9630 9631(dni cmbtohe 9632 "Conditional media convert byte to halfword extended" 9633 ((UNIT FM01) (FR500-MAJOR M-7) CONDITIONAL (MACH simple,tomcat,frv)) 9634 "cmbtohe$pack $FRintj,$FRintk,$CCi,$cond" 9635 (+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_2 FRintj) 9636 (sequence () 9637 ; hack to get these referenced for profiling 9638 (set FRintj (c-raw-call SI "frv_ref_SI" FRintj)) 9639 (set FRintk (c-raw-call SI "frv_ref_SI" FRintk)) 9640 (mbtohe-semantics (eq CCi (or cond 2)))) 9641 ((fr500 (unit u-media-dual-btohe))) 9642) 9643 9644; Media NOP 9645; A special case of mclracc 9646(dni mnop "Media nop" 9647 ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-1) 9648 (FR400-MAJOR M-1) (FR450-MAJOR M-1)) 9649 "mnop$pack" 9650 (+ pack (f-ACC40Sk 63) OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null)) 9651 (nop) 9652 () 9653) 9654 9655; mclracc with #A==0 9656(dni mclracc-0 9657 "Media clear accumulator(s)" 9658 ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) 9659 (FR400-MAJOR M-1) (FR450-MAJOR M-3)) 9660 "mclracc$pack $ACC40Sk,$A0" 9661 (+ pack ACC40Sk OP_7B (f-A 0) (misc-null-10) OPE1_3B (FRj-null)) 9662 (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 0) 9663 ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) 9664 (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc))) 9665) 9666 9667; mclracc with #A==1 9668(dni mclracc-1 9669 "Media clear accumulator(s)" 9670 ((UNIT MCLRACC-1) (FR500-MAJOR M-6) (FR550-MAJOR M-3) 9671 (FR400-MAJOR M-2) (FR450-MAJOR M-4)) 9672 "mclracc$pack $ACC40Sk,$A1" 9673 (+ pack ACC40Sk OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null)) 9674 (c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 1) 9675 ((fr400 (unit u-media-4)) (fr450 (unit u-media-4-mclracca)) 9676 (fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc))) 9677) 9678 9679(dni mrdacc 9680 "Media read accumulator" 9681 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9682 (FR400-MAJOR M-1) (FR450-MAJOR M-5)) 9683 "mrdacc$pack $ACC40Si,$FRintk" 9684 (+ pack FRintk OP_7B ACC40Si OPE1_3C (FRj-null)) 9685 (set FRintk ACC40Si) 9686 ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) 9687 (fr500 (unit u-media)) (fr550 (unit u-media-3-acc))) 9688) 9689 9690(dni mrdaccg 9691 "Media read accumulator guard" 9692 ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) 9693 (FR400-MAJOR M-1) (FR450-MAJOR M-5)) 9694 "mrdaccg$pack $ACCGi,$FRintk" 9695 (+ pack FRintk OP_7B ACCGi OPE1_3E (FRj-null)) 9696 (set FRintk ACCGi) 9697 ((fr400 (unit u-media-4-accg)) (fr450 (unit u-media-4-accg)) 9698 (fr500 (unit u-media)) (fr550 (unit u-media-3-acc (in ACC40Si ACCGi)))) 9699) 9700 9701(dni mwtacc 9702 "Media write accumulator" 9703 ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) 9704 (FR400-MAJOR M-1) (FR450-MAJOR M-3)) 9705 "mwtacc$pack $FRinti,$ACC40Sk" 9706 (+ pack ACC40Sk OP_7B FRinti OPE1_3D (FRj-null)) 9707 (set ACC40Sk (or (and ACC40Sk (const DI #xffffffff00000000)) 9708 FRinti)) 9709 ((fr400 (unit u-media-4)) (fr450 (unit u-media-4)) 9710 (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc))) 9711) 9712 9713(dni mwtaccg 9714 "Media write accumulator guard" 9715 ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) 9716 (FR400-MAJOR M-1) (FR450-MAJOR M-3)) 9717 "mwtaccg$pack $FRinti,$ACCGk" 9718 (+ pack ACCGk OP_7B FRinti OPE1_3F (FRj-null)) 9719 (sequence () 9720 ; hack to get these referenced for profiling 9721 (c-raw-call VOID "frv_ref_SI" ACCGk) 9722 (set ACCGk FRinti)) 9723 ((fr400 (unit u-media-4-accg)) (fr450 (unit u-media-4-accg)) 9724 (fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc (in ACC40Sk ACCGk)))) 9725) 9726 9727(define-pmacro (media-cop num op) 9728 (dni (.sym mcop num) 9729 "Media custom instruction" 9730 ((UNIT FM01) (FR500-MAJOR M-1) (MACH frv)) 9731 (.str "mcop" num "$pack $FRi,$FRj,$FRk") 9732 (+ pack FRk op FRi OPE1_00 FRj) 9733 (c-call VOID "@cpu@_media_cop" num) 9734 () 9735 ) 9736) 9737 9738(media-cop 1 OP_7C) 9739(media-cop 2 OP_7D) 9740 9741; nop 9742; A nop is defined to be a "ori gr0,0,gr0" 9743; This needn't be a macro-insn, but making it one greatly simplifies decode.c 9744; On the other hand spending a little time in the decoder is often worth it. 9745; 9746(dnmi nop "nop" 9747 ((UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 9748 "nop$pack" 9749 (emit ori pack (GRi 0) (s12 0) (GRk 0)) 9750) 9751 9752; Floating point NOP 9753(dni fnop 9754 "Floating point nop" 9755 ((UNIT FMALL) (FR500-MAJOR F-8) (FR550-MAJOR F-1) (MACH simple,tomcat,fr500,fr550,frv)) 9756 "fnop$pack" 9757 (+ pack (rd-null) OP_79 (FRi-null) OPE1_0D (FRj-null)) 9758 (nop) 9759 () 9760) 9761 9762; A return instruction 9763(dnmi ret "return" 9764 (NO-DIS (UNIT B01) (FR500-MAJOR B-3) 9765 (FR400-MAJOR B-3) (FR450-MAJOR B-3)) 9766 "ret$pack" 9767 (emit bralr pack (hint_taken 2)) 9768) 9769 9770(dnmi cmp "compare" 9771 (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) 9772 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 9773 "cmp$pack $GRi,$GRj,$ICCi_1" 9774 (emit subcc pack GRi GRj (GRk 0) ICCi_1) 9775) 9776 9777(dnmi cmpi "compare immediate" 9778 (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) 9779 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 9780 "cmpi$pack $GRi,$s10,$ICCi_1" 9781 (emit subicc pack GRi s10 (GRk 0) ICCi_1) 9782) 9783 9784(dnmi ccmp "conditional compare" 9785 (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) 9786 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 9787 "ccmp$pack $GRi,$GRj,$CCi,$cond" 9788 (emit csubcc pack GRi GRj (GRk 0) CCi cond) 9789) 9790 9791(dnmi mov "move" 9792 (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) 9793 (FR400-MAJOR I-1) (FR450-MAJOR I-1)) 9794 "mov$pack $GRi,$GRk" 9795 (emit ori pack GRi (s12 0) GRk) 9796) 9797 9798(dnmi cmov "conditional move" 9799 (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) 9800 (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL) 9801 "cmov$pack $GRi,$GRk,$CCi,$cond" 9802 (emit cor pack GRi (GRj 0) GRk CCi cond) 9803) 9804