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Searched refs:SI (Results 1 – 25 of 54) sorted by relevance

123

/toolchain/binutils/binutils-2.25/cpu/
Dlm32.cpu77 (register SI (32))
95 (register SI (32))
130 ((value pc) (sra SI (sub SI value pc) 2))
131 ((value pc) (add SI pc (sra SI (sll SI value 16) 14)))
134 ((value pc) (sra SI (sub SI value pc) 2))
135 ((value pc) (add SI pc (sra SI (sll SI value 6) 4)))
289 (set r1 (add r0 (ext SI (trunc HI imm))))
303 (set r1 (and r0 (zext SI uimm)))
310 (set r1 (and r0 (sll SI hi16 16)))
324 (set pc (ext SI call))
[all …]
Dmep-avc.cpu55 (type register SI (32))
57 (get (index) (trunc SI (c-call DI "h_cr64_get" index)))
69 (type register SI (64))
71 (get (index) (c-call SI "h_ccr_get" index))
203 (set avcc3CRq (ext SI avcc3Imm16s4x24e32))
238 (set avcc3CRq (add avcc3CRq (ext SI avcc3Imm6s24)))
259 (set avcc3CRq (ext SI (and QI (srl avcc3CRq 0) #xff)))
266 (set avcc3CRq (ext SI (and HI (srl avcc3CRq 0) #xffff)))
273 (set avcc3CRq (zext SI (and QI (srl avcc3CRq 0) #xff)))
280 (set avcc3CRq (zext SI (and HI (srl avcc3CRq 0) #xffff)))
[all …]
Dmep-avc2.cpu55 (type register SI (32))
57 (get (index) (trunc SI (c-call DI "h_cr64_get" index)))
69 (type register SI (64))
71 (get (index) (c-call SI "h_ccr_get" index))
207 (set avc2c3CRq (ext SI avc2c3Imm16s4x24e32))
242 (set avc2c3CRq (add avc2c3CRq (ext SI avc2c3Imm6s24)))
263 (set avc2c3CRq (ext SI (and QI (srl avc2c3CRq 0) #xff)))
270 (set avc2c3CRq (ext SI (and HI (srl avc2c3CRq 0) #xffff)))
277 (set avc2c3CRq (zext SI (and QI (srl avc2c3CRq 0) #xff)))
284 (set avc2c3CRq (zext SI (and HI (srl avc2c3CRq 0) #xffff)))
[all …]
Dcris.cpu30 (define-pmacro (SI-ext x) "How to sign-extend a dword to dword (a nop)" x)
31 (define-pmacro (HI-ext x) "How to sign-extend a word to dword" (ext SI x))
32 (define-pmacro (QI-ext x) "How to sign-extend a byte to dword" (ext SI x))
33 (define-pmacro (SI-zext x) "How to zero-extend a dword to dword (a nop)" x)
34 (define-pmacro (HI-zext x) "How to zero-extend a word to dword" (zext SI x))
35 (define-pmacro (QI-zext x) "How to zero-extend a byte to dword" (zext SI x))
199 ((simplecris-const-timing-SI)
327 ((crisv32-timing-c-SI) ((crisv32 (unit u-const32) (unit u-exec))))
328 ((crisv32-timing-c-sr-SI) ((crisv32 (unit u-const32) (unit u-exec-to-sr))))
359 ((cris-timing-const-SI) (.splice
[all …]
Dsh64-compact.cpu136 (type register SI)
137 (get () (or (or (or (raw-reg h-fpscr) (sll SI prbit 19)) (sll SI szbit 20)) (sll SI frbit 21)))
149 (type register SI)
150 (get () (subword SI (raw-reg h-gr 16) 1))
158 (type register SI)
159 (get () (subword SI (raw-reg h-gr 18) 1))
167 (type register SI)
168 (get () (subword SI (raw-reg h-gr 17) 1))
169 (set (newval) (set (raw-reg h-gr 17) (-join-si (subword SI (raw-reg h-gr 17) 0) newval)))
176 (type register SI)
[all …]
Dmep-c5.cpu47 (set rn (c-call SI "do_ldcb" (and rma #xffff)))
67 (c-call VOID "do_cache_prefetch" cimm4 (add INT rma (ext SI sdisp16)) pc))
111 (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
112 (set (mem QI (add rma (ext SI cdisp12))) (and crn #xff)))
121 (set crn (ext SI (mem QI (add rma (ext SI cdisp12))))))
130 (set crn (zext SI (mem QI (add rma (ext SI cdisp12))))))
140 (c-call VOID "check_write_to_text" (add rma (ext SI cdisp12)))
141 (set (mem HI (add rma (ext SI cdisp12))) (and crn #xffff)))
150 (set crn (ext SI (mem HI (add rma (ext SI cdisp12))))))
159 (set crn (zext SI (mem HI (add rma (ext SI cdisp12))))))
[all …]
Dsh64-media.cpu113 ((value pc) (sra SI value 5))
114 ((value pc) (sll SI value 5)))
119 ((value pc) (sra SI value 3))
120 ((value pc) (sll SI value 3)))
123 ((value pc) (sra SI value 2))
124 ((value pc) (sll SI value 2)))
127 ((value pc) (sra SI value 1))
128 ((value pc) (sll SI value 1)))
197 (set rd (add (subword SI rm 1) (subword SI rn 1))))
209 (set rd (ext DI (add (ext SI disp10) (subword SI rm 1)))))
[all …]
Dmep-core.cpu242 (type register SI (16))
256 (type register SI (32))
266 (get (index) (c-call SI "cgen_get_csr_value" index))
292 (type register SI (32))
295 (get (index) (trunc SI (c-call DI "h_cr64_get" index)))
306 (type register SI (64))
314 (type register SI (64))
432 ((value pc) (sra SI (sub SI value pc) 1))
433 ((value pc) (add SI (sll SI value 1) pc)))
436 ((value pc) (sra SI (sub SI value pc) 1))
[all …]
Dxstormy16.cpu127 (type register SI(8))
137 (type register SI(2))
156 (type register SI)
359 (encode (value pc) (sub SI value (add SI pc 2)))
360 (decode (value pc) (add SI value (add SI pc 2)))
371 (encode (value pc) (sub SI value (add SI pc 4)))
372 (decode (value pc) (add SI value (add SI pc 4)))
383 (encode (value pc) (sub SI value (add SI pc 4)))
384 (decode (value pc) (add SI value (add SI pc 4)))
395 (encode (value pc) (sra SI (sub SI value (add SI pc 2)) 1))
[all …]
Diq2000.cpu128 (type register SI (32))
131 (cond SI
204 ((value pc) (srl SI (and SI value #x7FFFFF) 2))
205 ((value pc) (or SI (and SI pc #xF0000000) (sll SI value 2))))
209 ((value pc) (sra SI (sub SI value pc) 2))
210 ((value pc) (add SI (sll SI value 2) (add pc 4))))
466 (set rt-rs (add rt-rs (ext SI (trunc HI lo16))))
472 (set rt (add rs (ext SI (trunc HI lo16))))
478 (set rt-rs (add rt-rs (ext SI (trunc HI lo16))))
484 (set rt (add rs (ext SI (trunc HI lo16))))
[all …]
Depiphany.cpu151 ((value pc) (sra SI (sub SI value pc) 1))
152 ((value pc) (add SI (sll SI value 1) pc)))
155 ((value pc) (sra SI (sub SI value pc) 1))
156 ((value pc) (add SI (sll SI value 1) pc)))
227 (set (ifield f-disp8) (and #xff (srl SI (ifield f-sdisp11) 3)))
228 (set (ifield f-disp3) (and SI (ifield f-sdisp11) 7)))
231 (sra SI (sll SI (or SI (sll (ifield f-disp8) 3)
384 (type register SI (64))
399 (set (index newval) (set (reg h-registers index) (subword SI newval 0)))
664 (dnh h-memaddr "memory effective address" (PROFILE) (register SI) () () ())
[all …]
Dm32c.cpu284 ; SI mode gr encoding for m32c is as follows:
289 (df f-src32-rn-unprefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 10 2 UINT
293 (df f-src32-rn-prefixed-SI "source Rn SI for m32c" (MACH32 m32c-isa) 18 2 UINT
342 ; SI mode gr encoding for m32c is as follows:
347 (df f-dst32-rn-unprefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 8 2 UINT
351 (df f-dst32-rn-prefixed-SI "destination Rn SI for m32c" (MACH32 m32c-isa) 16 2 UINT
574 ((value pc) (or SI
577 ((value pc) (or SI
583 ((value pc) (or SI
586 ((value pc) (or SI
[all …]
Dsh.cpu141 (type register SI (16))
171 (type register SI)
178 (type register SI)
187 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 14))) (sll SI newvalue 14))))
196 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 13))) (sll SI newvalue 13))))
205 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 12))) (sll SI newvalue 12))))
214 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv 2)) (sll SI newvalue 1))))
223 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 9))) (sll SI newvalue 9))))
232 (set (newvalue) (set (reg h-sr) (or (and (reg h-sr) (inv (sll 1 8))) (sll SI newvalue 8))))
291 (sll DI (zext DI (subword SI (reg h-fr index) 0)) 32)
[all …]
Dmep-rhcop.cpu43 (type register SI (32))
45 (get (index) (trunc SI (c-call DI "h_cr64_get" index)))
53 (type register SI (64))
197 (set cprm (subword SI cpcrn 1))
282 (sequence ((SI dummy))
293 (sequence ((SI dummy))
295 (set cpcrm64 (subword SI cpcrn64 1)))
304 (sequence ((SI dummy))
306 (set cpcrn64 (or (sll (zext DI cpcrm64) 32) (zext DI (subword SI cpcrn64 1)))))
315 (sequence ((SI dummy))
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Dmt.cpu247 ((value pc) (srl SI value 2))
248 ((value pc) (add SI (sll value 2) 8))
281 EI DI SI RETI BREAK IFLUSH - -
389 (type register SI (16))
592 (set frdrrr (add SI frsr1 frsr2))
610 (set frdr (add SI frsr1 (ext SI tmp)))
627 (set frdrrr (sub SI frsr1 frsr2))
645 (set frdr (sub SI frsr1 (ext SI tmp)))
647 ;(set frdr (sub SI frsr1 (ext SI imm16)))
672 (set frdrrr (mul SI (ext SI op1) (ext SI op2)))
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Dor1korbis.cpu29 (dsh h-atomic-address "atomic reserve address" () (register SI))
77 ((value pc) (sra SI (sub IAI value pc) (const 2)))
589 (c-call AI "@cpu@_make_load_store_addr" base (ext SI offset) size))
604 (set WI rD (ext WI (mem SI (load-store-addr rA simm16 4))))
662 (sequence ((SI addr))
682 (sequence ((SI addr) (BI flag))
997 (extw-insn extws ext WI SI)
1090 (set DI result (add (join DI SI mac-machi mac-maclo) (ext DI prod)))
1091 (set SI mac-machi (subword SI result 0))
1092 (set SI mac-maclo (subword SI result 1))
[all …]
Dmep-fmax.cpu146 (get (index) (c-call SI "h_ccr_get" index))
166 (define-full-operand fmax-FRd-int "FRd as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fm…
167 (define-full-operand fmax-FRn-int "FRn as an integer" (all-fmax-isas (CDATA FMAX_INT)) h-cr SI f-fm…
239 (fmax-conv froundws #xC #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_froundws" …
240 (fmax-conv ftruncws #xD #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ftruncws" …
241 (fmax-conv fceilws #xE #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fceilws" f…
242 (fmax-conv ffloorws #xF #x0 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_ffloorws" …
243 (fmax-conv fcvtws #x4 #x1 fmax-FRd-int fmax-FRn (set fmax-FRd-int (c-call SI "fmax_fcvtws" fm…
Diq2000m.cpu83 (sequence ((SI temp))
102 (sequence ((SI temp))
564 (sequence ((SI addr))
566 (set (reg h-gr (add (ifield f-rt) 1)) (mem SI addr))
567 (set rt (mem SI (add addr 4))))
573 (sequence ((SI addr))
575 (set (mem SI (add addr 4)) rt)
576 (set (mem SI addr) (reg h-gr (add (ifield f-rt) 1))))
Dfrv.cpu105 (cur-ccr-complex SI) ; Current use of CCR register has variable latency
1752 ; (define-extract (const SI 0))
1757 ; (define-execute (const SI 0))
1983 (set (ifield f-u12-h) (sra SI (ifield f-u12) 6))
2976 (set (spr-iacc0h) (trunc SI (srl newval 32)))
2977 (set (spr-iacc0l) (trunc SI newval))))
3119 (dnmop GRi "source register 1" () h-gr f-GRi SI)
3120 (dnmop GRj "source register 2" () h-gr f-GRj SI)
3121 (dnmop GRk "destination register" () h-gr f-GRk SI)
3132 (dnmop CPRi "source register" ((MACH frv)) h-cpr f-CPRi SI)
[all …]
/toolchain/binutils/binutils-2.25/include/cgen/
Dbasic-ops.h119 #define DIVSI(x, y) ((SI) (x) / (SI) (y))
121 #define MODSI(x, y) ((SI) (x) % (SI) (y))
123 #define SRASI(x, y) ((SI) (x) >> (y))
126 extern SI RORSI (SI, int);
127 extern SI ROLSI (SI, int);
132 #define NOTSI(x) (! (SI) (x))
135 #define EQSI(x, y) ((SI) (x) == (SI) (y))
136 #define NESI(x, y) ((SI) (x) != (SI) (y))
137 #define LTSI(x, y) ((SI) (x) < (SI) (y))
138 #define LESI(x, y) ((SI) (x) <= (SI) (y))
[all …]
Dbasic-modes.h40 typedef int32_t SI; typedef
50 #define MAKEDI(hi, lo) ((((DI) (SI) (hi)) << 32) | ((UDI) (USI) (lo)))
/toolchain/binutils/binutils-2.25/opcodes/
Di370-opc.c385 #define SI(op, i2, b1, d1) \ macro
390 #define SI_MASK SI (0xff, 0x0, 0x0, 0x0)
798 { "cli", 4, {{SI(0x95,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
799 { "mc", 4, {{SI(0xaf,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
800 { "mvi", 4, {{SI(0x92,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
801 { "ni", 4, {{SI(0x94,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
802 { "oi", 4, {{SI(0x96,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
803 { "stnsm", 4, {{SI(0xac,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} },
804 { "stosm", 4, {{SI(0xad,0,0,0), 0}}, {{SI_MASK, 0}}, IXA, {SI_D1, SI_B1, SI_I2} },
805 { "tm", 4, {{SI(0x91,0,0,0), 0}}, {{SI_MASK, 0}}, I370, {SI_D1, SI_B1, SI_I2} },
[all …]
Dppc-opc.c593 #define SI SHO + 1 macro
598 #define SISIGNOPT SI + 1
2782 {"tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2783 {"tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2784 {"tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2785 {"tdlgei", OPTO(2,TOLGE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2786 {"tdlnli", OPTO(2,TOLNL), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2787 {"tdllei", OPTO(2,TOLLE), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2788 {"tdlngi", OPTO(2,TOLNG), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
2789 {"tdgti", OPTO(2,TOGT), OPTO_MASK, PPC64, PPCNONE, {RA, SI}},
[all …]
Dlm32-ibld.c571 value = ((SI) (((value) - (pc))) >> (2)); in lm32_cgen_insert_operand()
578 value = ((SI) (((value) - (pc))) >> (2)); in lm32_cgen_insert_operand()
674 value = ((pc) + (((SI) (((value) << (16))) >> (14)))); in lm32_cgen_extract_operand()
682 value = ((pc) + (((SI) (((value) << (6))) >> (4)))); in lm32_cgen_extract_operand()
Dfr30-ibld.c624 value = ((SI) (value) >> (2)); in fr30_cgen_insert_operand()
634 value = ((SI) (value) >> (1)); in fr30_cgen_insert_operand()
661 value = ((SI) (((value) - (((pc) + (2))))) >> (1)); in fr30_cgen_insert_operand()
668 value = ((SI) (((value) - (((pc) + (2))))) >> (1)); in fr30_cgen_insert_operand()
696 value = ((SI) (value) >> (2)); in fr30_cgen_insert_operand()

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