| /toolchain/binutils/binutils-2.25/bfd/ |
| D | xtensa-modules.c | 303 Field_t_Slot_inst_get (const xtensa_insnbuf insn) in Field_t_Slot_inst_get() argument
306 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); in Field_t_Slot_inst_get()
311 Field_t_Slot_inst_set (xtensa_insnbuf insn, uint32 val) in Field_t_Slot_inst_set() argument
315 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); in Field_t_Slot_inst_set()
319 Field_t_Slot_inst16a_get (const xtensa_insnbuf insn) in Field_t_Slot_inst16a_get() argument
322 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); in Field_t_Slot_inst16a_get()
327 Field_t_Slot_inst16a_set (xtensa_insnbuf insn, uint32 val) in Field_t_Slot_inst16a_set() argument
331 insn[0] = (insn[0] & ~0xf0) | (tie_t << 4); in Field_t_Slot_inst16a_set()
335 Field_t_Slot_inst16b_get (const xtensa_insnbuf insn) in Field_t_Slot_inst16b_get() argument
338 tie_t = (tie_t << 4) | ((insn[0] << 24) >> 28); in Field_t_Slot_inst16b_get()
[all …]
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| D | hppa-dis.c | 164 #define GET_COMPL(insn) (GET_FIELD (insn, 26, 26) | \ argument
165 GET_FIELD (insn, 18, 18) << 1)
167 #define GET_COND(insn) (GET_FIELD ((insn), 16, 18) + \ argument
168 (GET_FIELD ((insn), 19, 19) ? 8 : 0))
361 unsigned int insn, i; in print_insn_hppa() local
373 insn = bfd_getb32 (buffer); in print_insn_hppa()
379 if ((insn & opcode->mask) == opcode->match) in print_insn_hppa()
395 fput_reg (GET_FIELD (insn, 11, 15), info); in print_insn_hppa()
399 fput_reg (GET_FIELD (insn, 6, 10), info); in print_insn_hppa()
402 fput_creg (GET_FIELD (insn, 6, 10), info); in print_insn_hppa()
[all …]
|
| D | nds32-dis.c | 36 #define MASK_OP(insn, mask) ((insn) & (0x3f << 25 | (mask))) argument
50 uint32_t insn, uint32_t parse_mode);
51 static void print_insn32 (bfd_vma pc, disassemble_info *info, uint32_t insn,
80 uint32_t insn; in nds32_ex9_info() local
114 insn = bfd_getb32 (buffer); in nds32_ex9_info()
116 if (insn & 0x80000000) in nds32_ex9_info()
117 print_insn16 (pc, info, (insn & 0x0000FFFF), in nds32_ex9_info()
121 print_insn32 (pc, info, insn, NDS32_PARSE_INSN32 | NDS32_PARSE_EX9IT); in nds32_ex9_info()
143 disassemble_info *info, uint32_t insn) in nds32_parse_audio_ext() argument
154 N32_IMMS ((insn >> pfd->bitpos), pfd->bitsize) << pfd->shift; in nds32_parse_audio_ext()
[all …]
|
| D | m10200-dis.c | 30 unsigned long insn, in disassemble() argument
67 if ((op->mask & insn) == op->opcode in disassemble()
88 value = (insn & 0xffff) << 8; in disassemble()
93 value = ((insn >> (operand->shift)) in disassemble()
110 value = ((insn >> (operand->shift + extra_shift)) in disassemble()
117 value = ((insn >> (operand->shift + extra_shift)) in disassemble()
157 (*info->fprintf_func) (info->stream, _("unknown\t0x%04lx"), insn); in disassemble()
165 unsigned long insn; in print_insn_mn10200() local
177 insn = *(unsigned char *) buffer; in print_insn_mn10200()
180 if ((insn & 0xf0) == 0x00 in print_insn_mn10200()
[all …]
|
| D | m10300-dis.c | 34 unsigned long insn, in disassemble() argument
75 if ((op->mask & insn) == op->opcode in disassemble()
114 insn &= 0xff0000; in disassemble()
122 insn |= bfd_getl16 (buffer); in disassemble()
138 insn &= 0xffff0000; in disassemble()
146 insn |= bfd_getl16 (buffer); in disassemble()
161 insn &= 0xff000000; in disassemble()
162 insn |= (temp & 0xffffff00) >> 8; in disassemble()
173 insn &= 0xffff0000; in disassemble()
174 insn |= bfd_getl16 (buffer); in disassemble()
[all …]
|
| D | avr-dis.c | 51 avr_operand (unsigned int insn, unsigned int insn2, unsigned int pc, int constraint, in avr_operand() argument
62 insn = (insn & 0xf) | ((insn & 0x0200) >> 5); /* Source register. */ in avr_operand()
64 insn = (insn & 0x01f0) >> 4; /* Destination register. */ in avr_operand()
66 sprintf (buf, "r%d", insn); in avr_operand()
71 sprintf (buf, "r%d", 16 + (insn & 0xf)); in avr_operand()
73 sprintf (buf, "r%d", 16 + ((insn & 0xf0) >> 4)); in avr_operand()
77 sprintf (buf, "r%d", 24 + ((insn & 0x30) >> 3)); in avr_operand()
82 sprintf (buf, "r%d", 16 + (insn & 7)); in avr_operand()
84 sprintf (buf, "r%d", 16 + ((insn >> 4) & 7)); in avr_operand()
89 sprintf (buf, "r%d", (insn & 0xf) * 2); in avr_operand()
[all …]
|
| D | i860-dis.c | 97 unsigned int insn, i; in print_insn_i860() local
110 insn = bfd_getl32 (buff); in print_insn_i860()
117 if ((insn & opcode->match) == opcode->match in print_insn_i860()
118 && (insn & opcode->lose) == 0) in print_insn_i860()
129 (*info->fprintf_func) (info->stream, ".long %#08x", insn); in print_insn_i860()
138 if (((insn & 0xfc000000) == 0x48000000 in print_insn_i860()
139 || (insn & 0xfc000000) == 0xb0000000) in print_insn_i860()
140 && (insn & 0x200)) in print_insn_i860()
152 grnames[(insn >> 11) & 0x1f]); in print_insn_i860()
158 grnames[(insn >> 21) & 0x1f]); in print_insn_i860()
[all …]
|
| D | sparc-dis.c | 33 #define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9)) argument
35 #define V9_P(insn) (((insn)->architecture & MASK_V9) != 0) argument
194 is_delayed_branch (unsigned long insn) in is_delayed_branch() argument
198 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) in is_delayed_branch()
202 if ((opcode->match & insn) == opcode->match in is_delayed_branch()
203 && (opcode->lose & insn) == 0) in is_delayed_branch()
468 unsigned long insn; in print_insn_sparc() local
515 insn = getword (buffer); in print_insn_sparc()
522 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) in print_insn_sparc()
530 if ((opcode->match & insn) == opcode->match in print_insn_sparc()
[all …]
|
| D | arc-opc.c | 331 insert_reg (arc_insn insn, in insert_reg() argument
372 insn |= marker << operand->shift; in insert_reg()
381 insn |= ARC_REG_LIMM << operand->shift; in insert_reg()
397 if ((insn & I(-1)) == I(2)) /* Check for use validity. */ in insert_reg()
407 insn |= ARC_REG_SHIMM << operand->shift; in insert_reg()
408 insn |= reg->value << arc_operands[reg->type].shift; in insert_reg()
414 if ('a' == operand->fmt || ((insn & I(-1)) < I(2))) in insert_reg()
430 insn |= reg->value << operand->shift; in insert_reg()
444 if ((insn & I(-1)) == I(2)) in insert_reg()
454 return insn; in insert_reg()
[all …]
|
| D | cris-dis.c | 170 get_opcode_entry (unsigned int insn, in get_opcode_entry() argument
286 && prefix_opc_table[insn] != NULL) in get_opcode_entry()
287 max_matchedp = prefix_opc_table[insn]; in get_opcode_entry()
288 else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL) in get_opcode_entry()
289 max_matchedp = opc_table[insn]; in get_opcode_entry()
361 if ((opcodep->match & insn) == opcodep->match in get_opcode_entry()
362 && (opcodep->lose & insn) == 0 in get_opcode_entry()
365 insn, in get_opcode_entry()
391 opc_table[insn] = max_matchedp; in get_opcode_entry()
393 prefix_opc_table[insn] = max_matchedp; in get_opcode_entry()
[all …]
|
| D | tic30-dis.c | 33 #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000) argument
72 get_tic30_instruction (unsigned long insn_word, struct instruction *insn) in get_tic30_instruction() argument
79 insn->type = NORMAL_INSN; in get_tic30_instruction()
91 insn->tm = current_optab; in get_tic30_instruction()
97 insn->tm = current_optab; in get_tic30_instruction()
106 insn->type = PARALLEL_INSN; in get_tic30_instruction()
117 insn->ptm = current_optab; in get_tic30_instruction()
126 insn->type = PARALLEL_INSN; in get_tic30_instruction()
137 insn->ptm = current_optab; in get_tic30_instruction()
146 insn->type = NORMAL_INSN; in get_tic30_instruction()
[all …]
|
| /toolchain/binutils/binutils-2.25/gas/config/ |
| D | tc-mt.c | 36 const CGEN_INSN * insn; member
197 mt_insn insn; in md_assemble() local
203 insn.insn = mt_cgen_assemble_insn in md_assemble()
204 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); in md_assemble()
206 if (!insn.insn) in md_assemble()
213 gas_cgen_finish_insn (insn.insn, insn.buffer, in md_assemble()
214 CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); in md_assemble()
222 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_MEMORY_ACCESS) in md_assemble()
225 CGEN_INSN_NAME (insn.insn)); in md_assemble()
229 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_IO_INSN)) in md_assemble()
[all …]
|
| D | tc-tic30.c | 271 struct tic30_insn insn; variable
748 ordinal_names[insn.operands]); in tic30_parallel_insn()
766 ordinal_names[insn.operands]); in tic30_parallel_insn()
783 ordinal_names[insn.operands]); in tic30_parallel_insn()
1423 memset (&insn, '\0', sizeof (insn)); in md_assemble()
1468 insn.tm = op; in md_assemble()
1495 ordinal_names[insn.operands]); in md_assemble()
1509 ordinal_names[insn.operands]); in md_assemble()
1520 ordinal_names[insn.operands]); in md_assemble()
1532 this_operand = insn.operands++; in md_assemble()
[all …]
|
| D | tc-mep.c | 38 const CGEN_INSN * insn; member
368 mep_check_for_disabled_registers (mep_insn *insn) in mep_check_for_disabled_registers() argument
381 b = insn->buffer[0] * 256 + insn->buffer[1]; in mep_check_for_disabled_registers()
383 b = insn->buffer[1] * 256 + insn->buffer[0]; in mep_check_for_disabled_registers()
385 b = insn->buffer[0]; in mep_check_for_disabled_registers()
532 const CGEN_INSN *insn = ilist->insn; in mep_cgen_assemble_cop_insn() local
533 if (strcmp (CGEN_INSN_MNEMONIC (ilist->insn), in mep_cgen_assemble_cop_insn()
535 && MEP_INSN_COP_P (ilist->insn) in mep_cgen_assemble_cop_insn()
536 && mep_cgen_insn_supported (cd, insn)) in mep_cgen_assemble_cop_insn()
541 if (CGEN_INSN_RX (insn) != NULL && in mep_cgen_assemble_cop_insn()
[all …]
|
| D | tc-epiphany.c | 37 const CGEN_INSN * insn; member
279 unsigned char *insn = (unsigned char *)where; in epiphany_apply_fix() local
314 value = (((value & 0xff) << 5) | insn[0]) in epiphany_apply_fix()
315 | (insn[1] << 8) in epiphany_apply_fix()
317 | (insn[2] << 16); in epiphany_apply_fix()
411 epiphany_insn insn; in md_assemble() local
416 memset (&insn, 0, sizeof (insn)); in md_assemble()
477 insn.insn = epiphany_cgen_assemble_insn in md_assemble()
478 (gas_cgen_cpu_desc, str, &insn.fields, insn.buffer, & errmsg); in md_assemble()
480 if (!insn.insn) in md_assemble()
[all …]
|
| D | tc-metag.c | 211 parse_none (const char *line, metag_insn *insn, in parse_none() argument
214 insn->bits = template->meta_opcode; in parse_none()
215 insn->len = 4; in parse_none()
445 parse_mov_u2u (const char *line, metag_insn *insn, in parse_mov_u2u() argument
461 insn->bits = (template->meta_opcode | in parse_mov_u2u()
466 insn->len = 4; in parse_mov_u2u()
472 parse_mov_port (const char *line, metag_insn *insn, in parse_mov_port() argument
511 insn->bits = (template->meta_opcode | in parse_mov_port()
517 insn->bits = (template->meta_opcode | in parse_mov_port()
521 insn->len = 4; in parse_mov_port()
[all …]
|
| D | tc-nios2.c | 168 const char *insn; member
1394 nios2_insn_infoS *insn, in nios2_assemble_expression() argument
1404 gas_assert (insn != NULL); in nios2_assemble_expression()
1430 reloc->reloc_next = insn->insn_reloc; in nios2_assemble_expression()
1431 insn->insn_reloc = reloc; in nios2_assemble_expression()
1453 nios2_assemble_arg_c (const char *token, nios2_insn_infoS *insn) in nios2_assemble_arg_c() argument
1456 const struct nios2_opcode *op = insn->insn_nios2_opcode; in nios2_assemble_arg_c()
1464 insn->insn_code |= SET_IW_R_IMM5 (reg->index); in nios2_assemble_arg_c()
1472 nios2_assemble_arg_d (const char *token, nios2_insn_infoS *insn) in nios2_assemble_arg_d() argument
1474 const struct nios2_opcode *op = insn->insn_nios2_opcode; in nios2_assemble_arg_d()
[all …]
|
| D | tc-fr30.c | 33 const CGEN_INSN * insn; member
112 fr30_insn insn; in md_assemble() local
118 insn.insn = fr30_cgen_assemble_insn in md_assemble()
119 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); in md_assemble()
121 if (!insn.insn) in md_assemble()
128 gas_cgen_finish_insn (insn.insn, insn.buffer, in md_assemble()
129 CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); in md_assemble()
133 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_NOT_IN_DELAY_SLOT)) in md_assemble()
135 CGEN_INSN_NAME (insn.insn)); in md_assemble()
138 = CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_DELAY_SLOT); in md_assemble()
[all …]
|
| D | tc-tic54x.c | 3392 operands_match (tic54x_insn *insn, in operands_match() argument
3436 insn->using_default_dst = 1; in operands_match()
3460 encode_dmad (tic54x_insn *insn, struct opstruct *operand, int xpc_code) in encode_dmad() argument
3462 int op = 1 + insn->is_lkaddr; in encode_dmad()
3471 insn->opcode[op].addr_expr = operand->exp; in encode_dmad()
3473 if (insn->opcode[op].addr_expr.X_op == O_constant) in encode_dmad()
3475 valueT value = insn->opcode[op].addr_expr.X_add_number; in encode_dmad()
3479 insn->opcode[0].word &= 0xFF80; in encode_dmad()
3480 insn->opcode[0].word |= (value >> 16) & 0x7F; in encode_dmad()
3481 insn->opcode[1].word = value & 0xFFFF; in encode_dmad()
[all …]
|
| D | tc-m32r.c | 44 const CGEN_INSN *insn; member
555 prev_insn.insn = NULL; in fill_insn()
754 const CGEN_OPINST *a_operands = CGEN_INSN_OPERANDS (a->insn); in first_writes_to_seconds_operands()
755 const CGEN_OPINST *b_ops = CGEN_INSN_OPERANDS (b->insn); in first_writes_to_seconds_operands()
828 if (CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_UNCOND_CTI) in writes_to_pc()
829 || CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_COND_CTI)) in writes_to_pc()
851 a_pipe = CGEN_INSN_ATTR_VALUE (a->insn, CGEN_INSN_PIPE); in can_make_parallel()
852 b_pipe = CGEN_INSN_ATTR_VALUE (b->insn, CGEN_INSN_PIPE); in can_make_parallel()
919 if (! (first.insn = m32r_cgen_assemble_insn in assemble_two_insns()
936 && ((CGEN_INSN_ATTR_VALUE (first.insn, CGEN_INSN_MACH) in assemble_two_insns()
[all …]
|
| D | tc-iq2000.c | 38 const CGEN_INSN * insn; member
340 iq2000_insn insn; in md_assemble() local
346 insn.insn = iq2000_cgen_assemble_insn in md_assemble()
347 (gas_cgen_cpu_desc, str, & insn.fields, insn.buffer, & errmsg); in md_assemble()
349 if (!insn.insn) in md_assemble()
356 gas_cgen_finish_insn (insn.insn, insn.buffer, in md_assemble()
357 CGEN_FIELDS_BITSIZE (& insn.fields), 1, NULL); in md_assemble()
362 CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_YIELD_INSN)) in md_assemble()
364 CGEN_INSN_NAME (insn.insn)); in md_assemble()
369 && CGEN_INSN_ATTR_VALUE (insn.insn, CGEN_INSN_EVEN_REG_NUM) in md_assemble()
[all …]
|
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| D | spu.h | 90 #define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size)) argument
91 #define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1)) argument
93 #define DECODE_INSN_RT(insn) (insn & 0x7f) argument
94 #define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f) argument
95 #define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f) argument
96 #define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f) argument
98 #define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14) argument
99 #define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14) argument
102 #define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7) argument
103 #define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7) argument
[all …]
|
| D | nds32.h | 135 #define N32_OP6(insn) (((insn) >> 25) & 0x3f) argument
136 #define N32_RT5(insn) (((insn) >> 20) & 0x1f) argument
137 #define N32_RT53(insn) (N32_RT5 (insn) & 0x7) argument
138 #define N32_RT54(insn) nds32_r54map[N32_RT5 (insn)] argument
139 #define N32_RA5(insn) (((insn) >> 15) & 0x1f) argument
140 #define N32_RA53(insn) (N32_RA5 (insn) & 0x7) argument
141 #define N32_RA54(insn) nds32_r54map[N32_RA5 (insn)] argument
142 #define N32_RB5(insn) (((insn) >> 10) & 0x1f) argument
143 #define N32_UB5(insn) (((insn) >> 10) & 0x1f) argument
144 #define N32_RB53(insn) (N32_RB5 (insn) & 0x7) argument
[all …]
|
| D | cgen.h | 994 #define CGEN_INSN_NUM(insn) ((insn)->base->num) argument
999 #define CGEN_INSN_NAME(insn) ((insn)->base->name) argument
1007 #define CGEN_INSN_MNEMONIC(insn) ((insn)->base->mnemonic) argument
1011 #define CGEN_INSN_BITSIZE(insn) ((insn)->base->bitsize) argument
1021 #define CGEN_INSN_RTX(insn) ((insn)->base->rtx)
1032 #define CGEN_INSN_ATTRS(insn) (&(insn)->base->attrs) argument
1034 #define CGEN_INSN_ATTR_VALUE(insn, attr) \ argument
1035 CGEN_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
1036 #define CGEN_INSN_BITSET_ATTR_VALUE(insn, attr) \ argument
1037 CGEN_BITSET_ATTR_VALUE ((insn), CGEN_INSN_ATTRS (insn), (attr))
[all …]
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| D | mxu.s | 7 .macro test1 insn argument
8 \insn xr1, xr2, xr3, xr4,AA,WW
9 \insn xr1, xr2, xr3, xr4,AA,LW
10 \insn xr1, xr2, xr3, xr4,AA,HW
11 \insn xr1, xr2, xr3, xr4,AA,XW
13 \insn xr1, xr2, xr3, xr4,AA,0
14 \insn xr1, xr2, xr3, xr4,AA,1
15 \insn xr1, xr2, xr3, xr4,AA,2
16 \insn xr1, xr2, xr3, xr4,AA,3
18 \insn xr1, xr2, xr3, xr4,AS,WW
[all …]
|