1 /* Copyright (C) 1995-1998 Eric Young (eay@cryptsoft.com)
2 * All rights reserved.
3 *
4 * This package is an SSL implementation written
5 * by Eric Young (eay@cryptsoft.com).
6 * The implementation was written so as to conform with Netscapes SSL.
7 *
8 * This library is free for commercial and non-commercial use as long as
9 * the following conditions are aheared to. The following conditions
10 * apply to all code found in this distribution, be it the RC4, RSA,
11 * lhash, DES, etc., code; not just the SSL code. The SSL documentation
12 * included with this distribution is covered by the same copyright terms
13 * except that the holder is Tim Hudson (tjh@cryptsoft.com).
14 *
15 * Copyright remains Eric Young's, and as such any Copyright notices in
16 * the code are not to be removed.
17 * If this package is used in a product, Eric Young should be given attribution
18 * as the author of the parts of the library used.
19 * This can be in the form of a textual message at program startup or
20 * in documentation (online or textual) provided with the package.
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 * 1. Redistributions of source code must retain the copyright
26 * notice, this list of conditions and the following disclaimer.
27 * 2. Redistributions in binary form must reproduce the above copyright
28 * notice, this list of conditions and the following disclaimer in the
29 * documentation and/or other materials provided with the distribution.
30 * 3. All advertising materials mentioning features or use of this software
31 * must display the following acknowledgement:
32 * "This product includes cryptographic software written by
33 * Eric Young (eay@cryptsoft.com)"
34 * The word 'cryptographic' can be left out if the rouines from the library
35 * being used are not cryptographic related :-).
36 * 4. If you include any Windows specific code (or a derivative thereof) from
37 * the apps directory (application code) you must include an acknowledgement:
38 * "This product includes software written by Tim Hudson (tjh@cryptsoft.com)"
39 *
40 * THIS SOFTWARE IS PROVIDED BY ERIC YOUNG ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
44 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 * SUCH DAMAGE.
51 *
52 * The licence and distribution terms for any publically available version or
53 * derivative of this code cannot be changed. i.e. this code cannot simply be
54 * copied and put under another distribution licence
55 * [including the GNU Public Licence.] */
56
57 #if !defined(__STDC_FORMAT_MACROS)
58 #define __STDC_FORMAT_MACROS
59 #endif
60
61 #include <openssl/cpu.h>
62
63
64 #if !defined(OPENSSL_NO_ASM) && (defined(OPENSSL_X86) || defined(OPENSSL_X86_64))
65
66 #include <inttypes.h>
67 #include <stdlib.h>
68 #include <stdio.h>
69 #include <string.h>
70
71 #if defined(OPENSSL_WINDOWS)
72 #pragma warning(push, 3)
73 #include <immintrin.h>
74 #include <intrin.h>
75 #pragma warning(pop)
76 #endif
77
78
79 /* OPENSSL_cpuid runs the cpuid instruction. |leaf| is passed in as EAX and ECX
80 * is set to zero. It writes EAX, EBX, ECX, and EDX to |*out_eax| through
81 * |*out_edx|. */
OPENSSL_cpuid(uint32_t * out_eax,uint32_t * out_ebx,uint32_t * out_ecx,uint32_t * out_edx,uint32_t leaf)82 static void OPENSSL_cpuid(uint32_t *out_eax, uint32_t *out_ebx,
83 uint32_t *out_ecx, uint32_t *out_edx, uint32_t leaf) {
84 #if defined(OPENSSL_WINDOWS)
85 int tmp[4];
86 __cpuid(tmp, (int)leaf);
87 *out_eax = (uint32_t)tmp[0];
88 *out_ebx = (uint32_t)tmp[1];
89 *out_ecx = (uint32_t)tmp[2];
90 *out_edx = (uint32_t)tmp[3];
91 #elif defined(__pic__) && defined(OPENSSL_32_BIT)
92 /* Inline assembly may not clobber the PIC register. For 32-bit, this is EBX.
93 * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=47602. */
94 __asm__ volatile (
95 "xor %%ecx, %%ecx\n"
96 "mov %%ebx, %%edi\n"
97 "cpuid\n"
98 "xchg %%edi, %%ebx\n"
99 : "=a"(*out_eax), "=D"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
100 : "a"(leaf)
101 );
102 #else
103 __asm__ volatile (
104 "xor %%ecx, %%ecx\n"
105 "cpuid\n"
106 : "=a"(*out_eax), "=b"(*out_ebx), "=c"(*out_ecx), "=d"(*out_edx)
107 : "a"(leaf)
108 );
109 #endif
110 }
111
112 /* OPENSSL_xgetbv returns the value of an Intel Extended Control Register (XCR).
113 * Currently only XCR0 is defined by Intel so |xcr| should always be zero. */
OPENSSL_xgetbv(uint32_t xcr)114 static uint64_t OPENSSL_xgetbv(uint32_t xcr) {
115 #if defined(OPENSSL_WINDOWS)
116 return (uint64_t)_xgetbv(xcr);
117 #else
118 uint32_t eax, edx;
119 __asm__ volatile ("xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
120 return (((uint64_t)edx) << 32) | eax;
121 #endif
122 }
123
124 /* handle_cpu_env applies the value from |in| to the CPUID values in |out[0]|
125 * and |out[1]|. See the comment in |OPENSSL_cpuid_setup| about this. */
handle_cpu_env(uint32_t * out,const char * in)126 static void handle_cpu_env(uint32_t *out, const char *in) {
127 const int invert = in[0] == '~';
128 uint64_t v;
129
130 if (!sscanf(in + invert, "%" PRIi64, &v)) {
131 return;
132 }
133
134 if (invert) {
135 out[0] &= ~v;
136 out[1] &= ~(v >> 32);
137 } else {
138 out[0] = v;
139 out[1] = v >> 32;
140 }
141 }
142
OPENSSL_cpuid_setup(void)143 void OPENSSL_cpuid_setup(void) {
144 /* Determine the vendor and maximum input value. */
145 uint32_t eax, ebx, ecx, edx;
146 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0);
147
148 uint32_t num_ids = eax;
149
150 int is_intel = ebx == 0x756e6547 /* Genu */ &&
151 edx == 0x49656e69 /* ineI */ &&
152 ecx == 0x6c65746e /* ntel */;
153 int is_amd = ebx == 0x68747541 /* Auth */ &&
154 edx == 0x69746e65 /* enti */ &&
155 ecx == 0x444d4163 /* cAMD */;
156
157 int has_amd_xop = 0;
158 if (is_amd) {
159 /* AMD-specific logic.
160 * See http://developer.amd.com/wordpress/media/2012/10/254811.pdf */
161 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0x80000000);
162 uint32_t num_extended_ids = eax;
163 if (num_extended_ids >= 0x80000001) {
164 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 0x80000001);
165 if (ecx & (1 << 11)) {
166 has_amd_xop = 1;
167 }
168 }
169 }
170
171 uint32_t extended_features = 0;
172 if (num_ids >= 7) {
173 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 7);
174 extended_features = ebx;
175 }
176
177 /* Determine the number of cores sharing an L1 data cache to adjust the
178 * hyper-threading bit. */
179 uint32_t cores_per_cache = 0;
180 if (is_amd) {
181 /* AMD CPUs never share an L1 data cache between threads but do set the HTT
182 * bit on multi-core CPUs. */
183 cores_per_cache = 1;
184 } else if (num_ids >= 4) {
185 /* TODO(davidben): The Intel manual says this CPUID leaf enumerates all
186 * caches using ECX and doesn't say which is first. Does this matter? */
187 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 4);
188 cores_per_cache = 1 + ((eax >> 14) & 0xfff);
189 }
190
191 OPENSSL_cpuid(&eax, &ebx, &ecx, &edx, 1);
192
193 /* Adjust the hyper-threading bit. */
194 if (edx & (1 << 28)) {
195 uint32_t num_logical_cores = (ebx >> 16) & 0xff;
196 if (cores_per_cache == 1 || num_logical_cores <= 1) {
197 edx &= ~(1 << 28);
198 }
199 }
200
201 /* Reserved bit #20 was historically repurposed to control the in-memory
202 * representation of RC4 state. Always set it to zero. */
203 edx &= ~(1 << 20);
204
205 /* Reserved bit #30 is repurposed to signal an Intel CPU. */
206 if (is_intel) {
207 edx |= (1 << 30);
208 } else {
209 edx &= ~(1 << 30);
210 }
211
212 /* The SDBG bit is repurposed to denote AMD XOP support. */
213 if (has_amd_xop) {
214 ecx |= (1 << 11);
215 } else {
216 ecx &= ~(1 << 11);
217 }
218
219 uint64_t xcr0 = 0;
220 if (ecx & (1 << 27)) {
221 /* XCR0 may only be queried if the OSXSAVE bit is set. */
222 xcr0 = OPENSSL_xgetbv(0);
223 }
224 /* See Intel manual, section 14.3. */
225 if ((xcr0 & 6) != 6) {
226 /* YMM registers cannot be used. */
227 ecx &= ~(1 << 28); /* AVX */
228 ecx &= ~(1 << 12); /* FMA */
229 ecx &= ~(1 << 11); /* AMD XOP */
230 extended_features &= ~(1 << 5); /* AVX2 */
231 }
232
233 OPENSSL_ia32cap_P[0] = edx;
234 OPENSSL_ia32cap_P[1] = ecx;
235 OPENSSL_ia32cap_P[2] = extended_features;
236 OPENSSL_ia32cap_P[3] = 0;
237
238 const char *env1, *env2;
239 env1 = getenv("OPENSSL_ia32cap");
240 if (env1 == NULL) {
241 return;
242 }
243
244 /* OPENSSL_ia32cap can contain zero, one or two values, separated with a ':'.
245 * Each value is a 64-bit, unsigned value which may start with "0x" to
246 * indicate a hex value. Prior to the 64-bit value, a '~' may be given.
247 *
248 * If '~' isn't present, then the value is taken as the result of the CPUID.
249 * Otherwise the value is inverted and ANDed with the probed CPUID result.
250 *
251 * The first value determines OPENSSL_ia32cap_P[0] and [1]. The second [2]
252 * and [3]. */
253
254 handle_cpu_env(&OPENSSL_ia32cap_P[0], env1);
255 env2 = strchr(env1, ':');
256 if (env2 != NULL) {
257 handle_cpu_env(&OPENSSL_ia32cap_P[2], env2 + 1);
258 }
259 }
260
261 #endif /* !OPENSSL_NO_ASM && (OPENSSL_X86 || OPENSSL_X86_64) */
262