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1 //===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the PowerPC implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCREGISTERINFO_H
17 
18 #include "PPC.h"
19 #include "llvm/ADT/DenseMap.h"
20 
21 #define GET_REGINFO_HEADER
22 #include "PPCGenRegisterInfo.inc"
23 
24 namespace llvm {
25 
getCRFromCRBit(unsigned SrcReg)26 inline static unsigned getCRFromCRBit(unsigned SrcReg) {
27   unsigned Reg = 0;
28   if (SrcReg == PPC::CR0LT || SrcReg == PPC::CR0GT ||
29       SrcReg == PPC::CR0EQ || SrcReg == PPC::CR0UN)
30     Reg = PPC::CR0;
31   else if (SrcReg == PPC::CR1LT || SrcReg == PPC::CR1GT ||
32            SrcReg == PPC::CR1EQ || SrcReg == PPC::CR1UN)
33     Reg = PPC::CR1;
34   else if (SrcReg == PPC::CR2LT || SrcReg == PPC::CR2GT ||
35            SrcReg == PPC::CR2EQ || SrcReg == PPC::CR2UN)
36     Reg = PPC::CR2;
37   else if (SrcReg == PPC::CR3LT || SrcReg == PPC::CR3GT ||
38            SrcReg == PPC::CR3EQ || SrcReg == PPC::CR3UN)
39     Reg = PPC::CR3;
40   else if (SrcReg == PPC::CR4LT || SrcReg == PPC::CR4GT ||
41            SrcReg == PPC::CR4EQ || SrcReg == PPC::CR4UN)
42     Reg = PPC::CR4;
43   else if (SrcReg == PPC::CR5LT || SrcReg == PPC::CR5GT ||
44            SrcReg == PPC::CR5EQ || SrcReg == PPC::CR5UN)
45     Reg = PPC::CR5;
46   else if (SrcReg == PPC::CR6LT || SrcReg == PPC::CR6GT ||
47            SrcReg == PPC::CR6EQ || SrcReg == PPC::CR6UN)
48     Reg = PPC::CR6;
49   else if (SrcReg == PPC::CR7LT || SrcReg == PPC::CR7GT ||
50            SrcReg == PPC::CR7EQ || SrcReg == PPC::CR7UN)
51     Reg = PPC::CR7;
52 
53   assert(Reg != 0 && "Invalid CR bit register");
54   return Reg;
55 }
56 
57 class PPCRegisterInfo : public PPCGenRegisterInfo {
58   DenseMap<unsigned, unsigned> ImmToIdxMap;
59   const PPCTargetMachine &TM;
60 
61 public:
62   PPCRegisterInfo(const PPCTargetMachine &TM);
63 
64   /// getPointerRegClass - Return the register class to use to hold pointers.
65   /// This is used for addressing modes.
66   const TargetRegisterClass *
67   getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
68 
69   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
70                                MachineFunction &MF) const override;
71 
72   const TargetRegisterClass *
73   getLargestLegalSuperClass(const TargetRegisterClass *RC,
74                             const MachineFunction &MF) const override;
75 
76   /// Code Generation virtual methods...
77   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
78   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
79                                        CallingConv::ID CC) const override;
80   const uint32_t *getNoPreservedMask() const override;
81 
82   void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
83 
84   BitVector getReservedRegs(const MachineFunction &MF) const override;
85 
86   /// We require the register scavenger.
requiresRegisterScavenging(const MachineFunction & MF)87   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
88     return true;
89   }
90 
requiresFrameIndexScavenging(const MachineFunction & MF)91   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
92     return true;
93   }
94 
trackLivenessAfterRegAlloc(const MachineFunction & MF)95   bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
96     return true;
97   }
98 
requiresVirtualBaseRegisters(const MachineFunction & MF)99   bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override {
100     return true;
101   }
102 
103   void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
104   void lowerDynamicAreaOffset(MachineBasicBlock::iterator II) const;
105   void lowerCRSpilling(MachineBasicBlock::iterator II,
106                        unsigned FrameIndex) const;
107   void lowerCRRestore(MachineBasicBlock::iterator II,
108                       unsigned FrameIndex) const;
109   void lowerCRBitSpilling(MachineBasicBlock::iterator II,
110                           unsigned FrameIndex) const;
111   void lowerCRBitRestore(MachineBasicBlock::iterator II,
112                          unsigned FrameIndex) const;
113   void lowerVRSAVESpilling(MachineBasicBlock::iterator II,
114                            unsigned FrameIndex) const;
115   void lowerVRSAVERestore(MachineBasicBlock::iterator II,
116                           unsigned FrameIndex) const;
117 
118   bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
119                             int &FrameIdx) const override;
120   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
121                            unsigned FIOperandNum,
122                            RegScavenger *RS = nullptr) const override;
123 
124   // Support for virtual base registers.
125   bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
126   void materializeFrameBaseRegister(MachineBasicBlock *MBB,
127                                     unsigned BaseReg, int FrameIdx,
128                                     int64_t Offset) const override;
129   void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
130                          int64_t Offset) const override;
131   bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
132                           int64_t Offset) const override;
133 
134   // Debug information queries.
135   unsigned getFrameRegister(const MachineFunction &MF) const override;
136 
137   // Base pointer (stack realignment) support.
138   unsigned getBaseRegister(const MachineFunction &MF) const;
139   bool hasBasePointer(const MachineFunction &MF) const;
140 };
141 
142 } // end namespace llvm
143 
144 #endif
145