1; RUN: llc -mtriple=armv6t2-eabi %s -o - | FileCheck %s 2 3define i64 @f1(i64 %a, i64 %b) { 4; CHECK-LABEL: f1: 5; CHECK: subs r 6; CHECK: sbc r 7entry: 8 %tmp = sub i64 %a, %b 9 ret i64 %tmp 10} 11 12define i64 @f2(i64 %a, i64 %b) { 13; CHECK-LABEL: f2: 14; CHECK: adc r 15; CHECK: subs r 16; CHECK: sbc r 17entry: 18 %tmp1 = shl i64 %a, 1 19 %tmp2 = sub i64 %tmp1, %b 20 ret i64 %tmp2 21} 22 23; add with live carry 24define i64 @f3(i32 %al, i32 %bl) { 25; CHECK-LABEL: f3: 26; CHECK: adds r 27; CHECK: adc r 28entry: 29 ; unsigned wide add 30 %aw = zext i32 %al to i64 31 %bw = zext i32 %bl to i64 32 %cw = add i64 %aw, %bw 33 ; ch == carry bit 34 %ch = lshr i64 %cw, 32 35 %dw = add i64 %ch, %bw 36 ret i64 %dw 37} 38 39; rdar://10073745 40define i64 @f4(i64 %x) nounwind readnone { 41entry: 42; CHECK-LABEL: f4: 43; CHECK: rsbs r 44; CHECK: rsc r 45 %0 = sub nsw i64 0, %x 46 ret i64 %0 47} 48 49; rdar://12559385 50define i64 @f5(i32 %vi) { 51entry: 52; CHECK-LABEL: f5: 53; CHECK: movw [[REG:r[0-9]+]], #36102 54; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]] 55 %v0 = zext i32 %vi to i64 56 %v1 = xor i64 %v0, -155057456198619 57 %v4 = add i64 %v1, 155057456198619 58 %v5 = add i64 %v4, %v1 59 ret i64 %v5 60} 61