1; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=fast -optimize-regalloc=0 -verify-machineinstrs | FileCheck %s -check-prefix=A8 -check-prefix=CHECK 2; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-m3 -regalloc=fast -optimize-regalloc=0 | FileCheck %s -check-prefix=M3 -check-prefix=CHECK 3; rdar://6949835 4; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=basic | FileCheck %s -check-prefix=BASIC -check-prefix=CHECK 5; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 -regalloc=greedy | FileCheck %s -check-prefix=GREEDY -check-prefix=CHECK 6; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=swift | FileCheck %s -check-prefix=SWIFT -check-prefix=CHECK 7 8; Magic ARM pair hints works best with linearscan / fast. 9 10@b = external global i64* 11 12; We use the following two to force values into specific registers. 13declare i64* @get_ptr() 14declare void @use_i64(i64 %v) 15 16define void @test_ldrd(i64 %a) nounwind readonly { 17; CHECK-LABEL: test_ldrd: 18; CHECK: bl{{x?}} _get_ptr 19; A8: ldrd r0, r1, [r0] 20; Cortex-M3 errata 602117: LDRD with base in list may result in incorrect base 21; register when interrupted or faulted. 22; M3-NOT: ldrd r[[REGNUM:[0-9]+]], {{r[0-9]+}}, [r[[REGNUM]]] 23; CHECK: bl{{x?}} _use_i64 24 %ptr = call i64* @get_ptr() 25 %v = load i64, i64* %ptr, align 8 26 call void @use_i64(i64 %v) 27 ret void 28} 29 30; rdar://10435045 mixed LDRi8/LDRi12 31; 32; In this case, LSR generate a sequence of LDRi8/LDRi12. We should be 33; able to generate an LDRD pair here, but this is highly sensitive to 34; regalloc hinting. So, this doubles as a register allocation 35; test. RABasic currently does a better job within the inner loop 36; because of its *lack* of hinting ability. Whereas RAGreedy keeps 37; R0/R1/R2 live as the three arguments, forcing the LDRD's odd 38; destination into R3. We then sensibly split LDRD again rather then 39; evict another live range or use callee saved regs. Sorry if the test 40; is sensitive to Regalloc changes, but it is an interesting case. 41; 42; BASIC: @f 43; BASIC: %bb 44; BASIC: ldrd 45; BASIC: str 46; GREEDY: @f 47; GREEDY: %bb 48; GREEDY: ldrd 49; GREEDY: str 50define void @f(i32* nocapture %a, i32* nocapture %b, i32 %n) nounwind { 51entry: 52 %0 = add nsw i32 %n, -1 ; <i32> [#uses=2] 53 %1 = icmp sgt i32 %0, 0 ; <i1> [#uses=1] 54 br i1 %1, label %bb, label %return 55 56bb: ; preds = %bb, %entry 57 %i.03 = phi i32 [ %tmp, %bb ], [ 0, %entry ] ; <i32> [#uses=3] 58 %scevgep = getelementptr i32, i32* %a, i32 %i.03 ; <i32*> [#uses=1] 59 %scevgep4 = getelementptr i32, i32* %b, i32 %i.03 ; <i32*> [#uses=1] 60 %tmp = add i32 %i.03, 1 ; <i32> [#uses=3] 61 %scevgep5 = getelementptr i32, i32* %a, i32 %tmp ; <i32*> [#uses=1] 62 %2 = load i32, i32* %scevgep, align 4 ; <i32> [#uses=1] 63 %3 = load i32, i32* %scevgep5, align 4 ; <i32> [#uses=1] 64 %4 = add nsw i32 %3, %2 ; <i32> [#uses=1] 65 store i32 %4, i32* %scevgep4, align 4 66 %exitcond = icmp eq i32 %tmp, %0 ; <i1> [#uses=1] 67 br i1 %exitcond, label %return, label %bb 68 69return: ; preds = %bb, %entry 70 ret void 71} 72 73; rdar://13978317 74; Pair of loads not formed when lifetime markers are set. 75%struct.Test = type { i32, i32, i32 } 76 77@TestVar = external global %struct.Test 78 79define void @Func1() nounwind ssp { 80; CHECK: @Func1 81entry: 82; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}} 83; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}} 84; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4] 85; A8-NEXT: add [[FIELD1]], [[FIELD2]] 86; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}} 87 %orig_blocks = alloca [256 x i16], align 2 88 %0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start(i64 512, i8* %0) nounwind 89 %tmp1 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 1), align 4 90 %tmp2 = load i32, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 2), align 4 91 %add = add nsw i32 %tmp2, %tmp1 92 store i32 %add, i32* getelementptr inbounds (%struct.Test, %struct.Test* @TestVar, i32 0, i32 0), align 4 93 call void @llvm.lifetime.end(i64 512, i8* %0) nounwind 94 ret void 95} 96 97declare void @extfunc(i32, i32, i32, i32) 98 99; CHECK-LABEL: Func2: 100; A8: ldrd 101; A8: blx 102; A8: pop 103define void @Func2(i32* %p) { 104entry: 105 %addr0 = getelementptr i32, i32* %p, i32 0 106 %addr1 = getelementptr i32, i32* %p, i32 1 107 %v0 = load i32, i32* %addr0 108 %v1 = load i32, i32* %addr1 109 ; try to force %v0/%v1 into non-adjacent registers 110 call void @extfunc(i32 %v0, i32 0, i32 0, i32 %v1) 111 ret void 112} 113 114; CHECK-LABEL: strd_spill_ldrd_reload: 115; A8: strd r1, r0, [sp, #-8]! 116; M3: strd r1, r0, [sp, #-8]! 117; BASIC: strd r1, r0, [sp, #-8]! 118; GREEDY: strd r0, r1, [sp, #-8]! 119; CHECK: @ InlineAsm Start 120; CHECK: @ InlineAsm End 121; A8: ldrd r2, r1, [sp] 122; M3: ldrd r2, r1, [sp] 123; BASIC: ldrd r2, r1, [sp] 124; GREEDY: ldrd r1, r2, [sp] 125; CHECK: bl{{x?}} _extfunc 126define void @strd_spill_ldrd_reload(i32 %v0, i32 %v1) { 127 ; force %v0 and %v1 to be spilled 128 call void asm sideeffect "", "~{r0},~{r1},~{r2},~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12},~{lr}"() 129 ; force the reloaded %v0, %v1 into different registers 130 call void @extfunc(i32 0, i32 %v0, i32 %v1, i32 7) 131 ret void 132} 133 134declare void @extfunc2(i32*, i32, i32) 135 136; CHECK-LABEL: ldrd_postupdate_dec: 137; CHECK: ldrd r1, r2, [r0], #-8 138; CHECK-NEXT: bl{{x?}} _extfunc 139define void @ldrd_postupdate_dec(i32* %p0) { 140 %p0.1 = getelementptr i32, i32* %p0, i32 1 141 %v0 = load i32, i32* %p0 142 %v1 = load i32, i32* %p0.1 143 %p1 = getelementptr i32, i32* %p0, i32 -2 144 call void @extfunc2(i32* %p1, i32 %v0, i32 %v1) 145 ret void 146} 147 148; CHECK-LABEL: ldrd_postupdate_inc: 149; CHECK: ldrd r1, r2, [r0], #8 150; CHECK-NEXT: bl{{x?}} _extfunc 151define void @ldrd_postupdate_inc(i32* %p0) { 152 %p0.1 = getelementptr i32, i32* %p0, i32 1 153 %v0 = load i32, i32* %p0 154 %v1 = load i32, i32* %p0.1 155 %p1 = getelementptr i32, i32* %p0, i32 2 156 call void @extfunc2(i32* %p1, i32 %v0, i32 %v1) 157 ret void 158} 159 160; CHECK-LABEL: strd_postupdate_dec: 161; CHECK: strd r1, r2, [r0], #-8 162; CHECK-NEXT: bx lr 163define i32* @strd_postupdate_dec(i32* %p0, i32 %v0, i32 %v1) { 164 %p0.1 = getelementptr i32, i32* %p0, i32 1 165 store i32 %v0, i32* %p0 166 store i32 %v1, i32* %p0.1 167 %p1 = getelementptr i32, i32* %p0, i32 -2 168 ret i32* %p1 169} 170 171; CHECK-LABEL: strd_postupdate_inc: 172; CHECK: strd r1, r2, [r0], #8 173; CHECK-NEXT: bx lr 174define i32* @strd_postupdate_inc(i32* %p0, i32 %v0, i32 %v1) { 175 %p0.1 = getelementptr i32, i32* %p0, i32 1 176 store i32 %v0, i32* %p0 177 store i32 %v1, i32* %p0.1 178 %p1 = getelementptr i32, i32* %p0, i32 2 179 ret i32* %p1 180} 181 182declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind 183declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind 184