1; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s 2 3; Check that we avoid producing vldm instructions using d registers that 4; begin in the most-significant half of a q register. These require more 5; micro-ops on swift and so aren't worth combining. 6 7; CHECK-LABEL: test_vldm 8; CHECK: vldmia r{{[0-9]+}}, {d2, d3, d4} 9; CHECK-NOT: vldmia r{{[0-9]+}}, {d1, d2, d3, d4} 10 11declare fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4) 12 13define void @test_vldm(double* %x, double * %y) { 14entry: 15 %addr1 = getelementptr double, double * %x, i32 1 16 %addr2 = getelementptr double, double * %x, i32 2 17 %addr3 = getelementptr double, double * %x, i32 3 18 %d0 = load double , double * %y 19 %d1 = load double , double * %x 20 %d2 = load double , double * %addr1 21 %d3 = load double , double * %addr2 22 %d4 = load double , double * %addr3 23 ; We are trying to force x[0-3] in registers d1 to d4 so that we can test we 24 ; don't form a "vldmia rX, {d1, d2, d3, d4}". 25 ; We are relying on the calling convention and that register allocation 26 ; properly coalesces registers. 27 call fastcc void @force_register(double %d0, double %d1, double %d2, double %d3, double %d4) 28 ret void 29} 30