1; RUN: llc -enable-misched -misched=shuffle -enable-aa-sched-mi -use-tbaa-in-sched-mi=0 -post-RA-scheduler=0 -mcpu=ppc64 < %s | FileCheck %s 2 3; REQUIRES: asserts 4; -misched=shuffle is NDEBUG only! 5 6target datalayout = "E-m:e-i64:64-n32:64" 7target triple = "powerpc64-unknown-linux-gnu" 8 9%"class.llvm::MCOperand" = type { i8, %union.anon.110 } 10%union.anon.110 = type { i64 } 11 12define void @foo(i32 %v) { 13entry: 14 %MCOp = alloca %"class.llvm::MCOperand", align 8 15 br label %next 16 17; CHECK-LABEL: @foo 18 19next: 20 %sunkaddr18 = ptrtoint %"class.llvm::MCOperand"* %MCOp to i64 21 %sunkaddr19 = add i64 %sunkaddr18, 8 22 %sunkaddr20 = inttoptr i64 %sunkaddr19 to double* 23 store double 0.000000e+00, double* %sunkaddr20, align 8, !tbaa !1 24 %sunkaddr21 = ptrtoint %"class.llvm::MCOperand"* %MCOp to i64 25 %sunkaddr22 = add i64 %sunkaddr21, 8 26 %sunkaddr23 = inttoptr i64 %sunkaddr22 to i32* 27 store i32 %v, i32* %sunkaddr23, align 8, !tbaa !2 28 ret void 29 30; Make sure that the 64-bit store comes first, regardless of what TBAA says 31; about the two not aliasing! 32; CHECK: li [[REG:[0-9]+]], 0 33; CHECK: std [[REG]], -[[OFF:[0-9]+]](1) 34; CHECK: stw 3, -[[OFF]](1) 35; CHECK: blr 36} 37 38!0 = !{ !"root" } 39!1 = !{ !"set1", !0 } 40!2 = !{ !"set2", !0 } 41 42