1; RUN: llc < %s -march=ppc64 -mcpu=a2q | FileCheck %s 2target triple = "powerpc64-bgq-linux" 3 4@Q = constant <4 x i1> <i1 0, i1 undef, i1 1, i1 1>, align 16 5@R = global <4 x i1> <i1 0, i1 0, i1 0, i1 0>, align 16 6 7define <4 x double> @test1(<4 x double> %a, <4 x double> %b, <4 x i1> %c) nounwind readnone { 8entry: 9 %r = select <4 x i1> %c, <4 x double> %a, <4 x double> %b 10 ret <4 x double> %r 11 12; CHECK-LABEL: @test1 13; CHECK: qvfsel 1, 3, 1, 2 14; CHECK: blr 15} 16 17define <4 x double> @test2(<4 x double> %a, <4 x double> %b, i1 %c1, i1 %c2, i1 %c3, i1 %c4) nounwind readnone { 18entry: 19 %v = insertelement <4 x i1> undef, i1 %c1, i32 0 20 %v2 = insertelement <4 x i1> %v, i1 %c2, i32 1 21 %v3 = insertelement <4 x i1> %v2, i1 %c3, i32 2 22 %v4 = insertelement <4 x i1> %v3, i1 %c4, i32 3 23 %r = select <4 x i1> %v4, <4 x double> %a, <4 x double> %b 24 ret <4 x double> %r 25 26; CHECK-LABEL: @test2 27 28; FIXME: This load/store sequence is unnecessary. 29; CHECK-DAG: lbz 30; CHECK-DAG: stw 31 32; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], 33; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 34; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] 35; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] 36; CHECK: qvfsel 1, [[REG4]], 1, 2 37; CHECK: blr 38} 39 40define <4 x i1> @test3(<4 x i1> %a) nounwind readnone { 41entry: 42 %v = and <4 x i1> %a, <i1 0, i1 undef, i1 1, i1 1> 43 ret <4 x i1> %v 44 45; CHECK-LABEL: @test3 46; CHECK: qvlfsx [[REG:[0-9]+]], 47; qvflogical 1, 1, [[REG]], 1 48; blr 49} 50 51define <4 x i1> @test4(<4 x i1> %a) nounwind { 52entry: 53 %q = load <4 x i1>, <4 x i1>* @Q, align 16 54 %v = and <4 x i1> %a, %q 55 ret <4 x i1> %v 56 57; CHECK-LABEL: @test4 58; CHECK-DAG: lbz 59; CHECK-DAG: qvlfdx [[REG1:[0-9]+]], 60; CHECK-DAG: stw 61; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]], 62; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]] 63; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]] 64; CHECK: qvflogical 1, 1, [[REG4]], 1 65; CHECK: blr 66} 67 68define void @test5(<4 x i1> %a) nounwind { 69entry: 70 store <4 x i1> %a, <4 x i1>* @R 71 ret void 72 73; CHECK-LABEL: @test5 74; CHECK: qvlfdx [[REG1:[0-9]+]], 75; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 76; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 77; CHECK: qvstfiwx [[REG3]], 78; CHECK: lwz 79; CHECK: stb 80; CHECK: blr 81} 82 83define i1 @test6(<4 x i1> %a) nounwind { 84entry: 85 %r = extractelement <4 x i1> %a, i32 2 86 ret i1 %r 87 88; CHECK-LABEL: @test6 89; CHECK: qvlfdx [[REG1:[0-9]+]], 90; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 91; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 92; CHECK: qvstfiwx [[REG3]], 93; CHECK: lwz 94; CHECK: blr 95} 96 97define i1 @test7(<4 x i1> %a) nounwind { 98entry: 99 %r = extractelement <4 x i1> %a, i32 2 100 %s = extractelement <4 x i1> %a, i32 3 101 %q = and i1 %r, %s 102 ret i1 %q 103 104; CHECK-LABEL: @test7 105; CHECK: qvlfdx [[REG1:[0-9]+]], 106; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 107; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 108; CHECK: qvstfiwx [[REG3]], 109; CHECK-DAG: lwz [[REG4:[0-9]+]], 110; FIXME: We're storing the vector twice, and that's silly. 111; CHECK-DAG: qvstfiwx [[REG3]], 112; CHECK-DAG: lwz [[REG5:[0-9]+]], 113; CHECK: and 3, 114; CHECK: blr 115} 116 117define i1 @test8(<3 x i1> %a) nounwind { 118entry: 119 %r = extractelement <3 x i1> %a, i32 2 120 ret i1 %r 121 122; CHECK-LABEL: @test8 123; CHECK: qvlfdx [[REG1:[0-9]+]], 124; CHECK: qvfmadd [[REG2:[0-9]+]], 1, [[REG1]], [[REG1]] 125; CHECK: qvfctiwu [[REG3:[0-9]+]], [[REG2]] 126; CHECK: qvstfiwx [[REG3]], 127; CHECK: lwz 128; CHECK: blr 129} 130 131define <3 x double> @test9(<3 x double> %a, <3 x double> %b, i1 %c1, i1 %c2, i1 %c3) nounwind readnone { 132entry: 133 %v = insertelement <3 x i1> undef, i1 %c1, i32 0 134 %v2 = insertelement <3 x i1> %v, i1 %c2, i32 1 135 %v3 = insertelement <3 x i1> %v2, i1 %c3, i32 2 136 %r = select <3 x i1> %v3, <3 x double> %a, <3 x double> %b 137 ret <3 x double> %r 138 139; CHECK-LABEL: @test9 140 141; FIXME: This load/store sequence is unnecessary. 142; CHECK-DAG: lbz 143; CHECK-DAG: stw 144 145; CHECK-DAG: qvlfiwzx [[REG1:[0-9]+]], 146; CHECK-DAG: qvlfdx [[REG2:[0-9]+]], 147; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG1]] 148; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG2]] 149; CHECK: qvfsel 1, [[REG4]], 1, 2 150; CHECK: blr 151} 152 153