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1; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | FileCheck %s
2
3define i32 @test0(<1 x i64>* %v4) {
4; CHECK-LABEL: test0:
5; CHECK:       # BB#0:{{.*}} %entry
6; CHECK:    pshufw $238, (%[[REG:[a-z]+]]), %mm0
7; CHECK-NEXT:    movd %mm0, %eax
8; CHECK-NEXT:    addl $32, %eax
9; CHECK-NEXT:    retq
10entry:
11  %v5 = load <1 x i64>, <1 x i64>* %v4, align 8
12  %v12 = bitcast <1 x i64> %v5 to <4 x i16>
13  %v13 = bitcast <4 x i16> %v12 to x86_mmx
14  %v14 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %v13, i8 -18)
15  %v15 = bitcast x86_mmx %v14 to <4 x i16>
16  %v16 = bitcast <4 x i16> %v15 to <1 x i64>
17  %v17 = extractelement <1 x i64> %v16, i32 0
18  %v18 = bitcast i64 %v17 to <2 x i32>
19  %v19 = extractelement <2 x i32> %v18, i32 0
20  %v20 = add i32 %v19, 32
21  ret i32 %v20
22}
23
24define i32 @test1(i32* nocapture readonly %ptr) {
25; CHECK-LABEL: test1:
26; CHECK:       # BB#0:{{.*}} %entry
27; CHECK:    movd (%[[REG]]), %mm0
28; CHECK-NEXT:    pshufw $232, %mm0, %mm0
29; CHECK-NEXT:    movd %mm0, %eax
30; CHECK-NEXT:    emms
31; CHECK-NEXT:    retq
32entry:
33  %0 = load i32, i32* %ptr, align 4
34  %1 = insertelement <2 x i32> undef, i32 %0, i32 0
35  %2 = insertelement <2 x i32> %1, i32 0, i32 1
36  %3 = bitcast <2 x i32> %2 to x86_mmx
37  %4 = bitcast x86_mmx %3 to i64
38  %5 = bitcast i64 %4 to <4 x i16>
39  %6 = bitcast <4 x i16> %5 to x86_mmx
40  %7 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %6, i8 -24)
41  %8 = bitcast x86_mmx %7 to <4 x i16>
42  %9 = bitcast <4 x i16> %8 to <1 x i64>
43  %10 = extractelement <1 x i64> %9, i32 0
44  %11 = bitcast i64 %10 to <2 x i32>
45  %12 = extractelement <2 x i32> %11, i32 0
46  tail call void @llvm.x86.mmx.emms()
47  ret i32 %12
48}
49
50define i32 @test2(i32* nocapture readonly %ptr) {
51; CHECK-LABEL: test2:
52; CHECK:       # BB#0:{{.*}} %entry
53; CHECK:    pshufw $232, (%[[REG]]), %mm0
54; CHECK-NEXT:    movd %mm0, %eax
55; CHECK-NEXT:    emms
56; CHECK-NEXT:    retq
57entry:
58  %0 = bitcast i32* %ptr to x86_mmx*
59  %1 = load x86_mmx, x86_mmx* %0, align 8
60  %2 = tail call x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx %1, i8 -24)
61  %3 = bitcast x86_mmx %2 to <4 x i16>
62  %4 = bitcast <4 x i16> %3 to <1 x i64>
63  %5 = extractelement <1 x i64> %4, i32 0
64  %6 = bitcast i64 %5 to <2 x i32>
65  %7 = extractelement <2 x i32> %6, i32 0
66  tail call void @llvm.x86.mmx.emms()
67  ret i32 %7
68}
69
70declare x86_mmx @llvm.x86.sse.pshuf.w(x86_mmx, i8)
71declare void @llvm.x86.mmx.emms()
72