1 //===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Interface definition for R600InstrInfo 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef R600INSTRUCTIONINFO_H_ 15 #define R600INSTRUCTIONINFO_H_ 16 17 #include "AMDIL.h" 18 #include "AMDGPUInstrInfo.h" 19 #include "R600RegisterInfo.h" 20 21 #include <map> 22 23 namespace llvm { 24 25 class AMDGPUTargetMachine; 26 class DFAPacketizer; 27 class ScheduleDAG; 28 class MachineFunction; 29 class MachineInstr; 30 class MachineInstrBuilder; 31 32 class R600InstrInfo : public AMDGPUInstrInfo { 33 private: 34 const R600RegisterInfo RI; 35 AMDGPUTargetMachine &TM; 36 37 int getBranchInstr(const MachineOperand &op) const; 38 39 public: 40 explicit R600InstrInfo(AMDGPUTargetMachine &tm); 41 42 const R600RegisterInfo &getRegisterInfo() const; 43 virtual void copyPhysReg(MachineBasicBlock &MBB, 44 MachineBasicBlock::iterator MI, DebugLoc DL, 45 unsigned DestReg, unsigned SrcReg, 46 bool KillSrc) const; 47 48 bool isTrig(const MachineInstr &MI) const; 49 bool isPlaceHolderOpcode(unsigned opcode) const; 50 bool isReductionOp(unsigned opcode) const; 51 bool isCubeOp(unsigned opcode) const; 52 53 /// isVector - Vector instructions are instructions that must fill all 54 /// instruction slots within an instruction group. 55 bool isVector(const MachineInstr &MI) const; 56 57 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg, 58 int64_t Imm) const; 59 60 virtual unsigned getIEQOpcode() const; 61 virtual bool isMov(unsigned Opcode) const; 62 63 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM, 64 const ScheduleDAG *DAG) const; 65 66 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; 67 68 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 69 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const; 70 71 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const; 72 73 unsigned RemoveBranch(MachineBasicBlock &MBB) const; 74 75 bool isPredicated(const MachineInstr *MI) const; 76 77 bool isPredicable(MachineInstr *MI) const; 78 79 bool 80 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 81 const BranchProbability &Probability) const; 82 83 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles, 84 unsigned ExtraPredCycles, 85 const BranchProbability &Probability) const ; 86 87 bool 88 isProfitableToIfCvt(MachineBasicBlock &TMBB, 89 unsigned NumTCycles, unsigned ExtraTCycles, 90 MachineBasicBlock &FMBB, 91 unsigned NumFCycles, unsigned ExtraFCycles, 92 const BranchProbability &Probability) const; 93 94 bool DefinesPredicate(MachineInstr *MI, 95 std::vector<MachineOperand> &Pred) const; 96 97 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, 98 const SmallVectorImpl<MachineOperand> &Pred2) const; 99 100 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, 101 MachineBasicBlock &FMBB) const; 102 103 bool PredicateInstruction(MachineInstr *MI, 104 const SmallVectorImpl<MachineOperand> &Pred) const; 105 106 int getInstrLatency(const InstrItineraryData *ItinData, 107 const MachineInstr *MI, 108 unsigned *PredCost = 0) const; 109 getInstrLatency(const InstrItineraryData * ItinData,SDNode * Node)110 virtual int getInstrLatency(const InstrItineraryData *ItinData, 111 SDNode *Node) const { return 1;} 112 113 ///hasFlagOperand - Returns true if this instruction has an operand for 114 /// storing target flags. 115 bool hasFlagOperand(const MachineInstr &MI) const; 116 117 ///addFlag - Add one of the MO_FLAG* flags to the specified Operand. 118 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 119 120 ///isFlagSet - Determine if the specified flag is set on this Operand. 121 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const; 122 123 ///getFlagOp - Return the operand containing the flags for this instruction. 124 MachineOperand &getFlagOp(MachineInstr *MI) const; 125 126 ///clearFlag - Clear the specified flag on the instruction. 127 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const; 128 }; 129 130 } // End llvm namespace 131 132 namespace R600_InstFlag { 133 enum TIF { 134 TRANS_ONLY = (1 << 0), 135 TEX = (1 << 1), 136 REDUCTION = (1 << 2), 137 FC = (1 << 3), 138 TRIG = (1 << 4), 139 OP3 = (1 << 5), 140 VECTOR = (1 << 6) 141 //FlagOperand bits 7, 8 142 }; 143 } 144 145 #endif // R600INSTRINFO_H_ 146