1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * on the rights to use, copy, modify, merge, publish, distribute, sub 8 * license, and/or sell copies of the Software, and to permit persons to whom 9 * the Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, 19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 21 * USE OR OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: 24 * Christian König <christian.koenig@amd.com> 25 */ 26 27 #ifndef RADEONSI_PM4_H 28 #define RADEONSI_PM4_H 29 30 #include "../../winsys/radeon/drm/radeon_winsys.h" 31 32 #define SI_PM4_MAX_DW 128 33 #define SI_PM4_MAX_BO 32 34 #define SI_PM4_MAX_RELOCS 4 35 36 // forward defines 37 struct r600_context; 38 39 struct si_pm4_state 40 { 41 /* PKT3_SET_*_REG handling */ 42 unsigned last_opcode; 43 unsigned last_reg; 44 unsigned last_pm4; 45 46 /* flush flags for SURFACE_SYNC */ 47 uint32_t cp_coher_cntl; 48 49 /* commands for the DE */ 50 unsigned ndw; 51 uint32_t pm4[SI_PM4_MAX_DW]; 52 53 /* BO's referenced by this state */ 54 unsigned nbo; 55 struct si_resource *bo[SI_PM4_MAX_BO]; 56 enum radeon_bo_usage bo_usage[SI_PM4_MAX_BO]; 57 58 /* relocs for shader data */ 59 unsigned nrelocs; 60 unsigned relocs[SI_PM4_MAX_RELOCS]; 61 }; 62 63 void si_pm4_cmd_begin(struct si_pm4_state *state, unsigned opcode); 64 void si_pm4_cmd_add(struct si_pm4_state *state, uint32_t dw); 65 void si_pm4_cmd_end(struct si_pm4_state *state, bool predicate); 66 67 void si_pm4_set_reg(struct si_pm4_state *state, unsigned reg, uint32_t val); 68 void si_pm4_add_bo(struct si_pm4_state *state, 69 struct si_resource *bo, 70 enum radeon_bo_usage usage); 71 72 void si_pm4_sh_data_begin(struct si_pm4_state *state); 73 void si_pm4_sh_data_add(struct si_pm4_state *state, uint32_t dw); 74 void si_pm4_sh_data_end(struct si_pm4_state *state, unsigned reg); 75 76 void si_pm4_inval_shader_cache(struct si_pm4_state *state); 77 void si_pm4_inval_texture_cache(struct si_pm4_state *state); 78 void si_pm4_inval_vertex_cache(struct si_pm4_state *state); 79 void si_pm4_inval_fb_cache(struct si_pm4_state *state, unsigned nr_cbufs); 80 void si_pm4_inval_zsbuf_cache(struct si_pm4_state *state); 81 82 void si_pm4_free_state(struct r600_context *rctx, 83 struct si_pm4_state *state, 84 unsigned idx); 85 86 uint32_t si_pm4_sync_flags(struct r600_context *rctx); 87 unsigned si_pm4_dirty_dw(struct r600_context *rctx); 88 void si_pm4_emit(struct r600_context *rctx, struct si_pm4_state *state); 89 void si_pm4_emit_dirty(struct r600_context *rctx); 90 void si_pm4_reset_emitted(struct r600_context *rctx); 91 92 #endif 93