1/* 2 * This file was generated automatically by gen-mterp.py for 'arm'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: arm/header.S */ 8/* 9 * Copyright (C) 2016 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 Art assembly interpreter notes: 26 27 First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't 28 handle invoke, allows higher-level code to create frame & shadow frame. 29 30 Once that's working, support direct entry code & eliminate shadow frame (and 31 excess locals allocation. 32 33 Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the 34 base of the vreg array within the shadow frame. Access the other fields, 35 dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue 36 the shadow frame mechanism of double-storing object references - via rFP & 37 number_of_vregs_. 38 39 */ 40 41/* 42ARM EABI general notes: 43 44r0-r3 hold first 4 args to a method; they are not preserved across method calls 45r4-r8 are available for general use 46r9 is given special treatment in some situations, but not for us 47r10 (sl) seems to be generally available 48r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) 49r12 (ip) is scratch -- not preserved across method calls 50r13 (sp) should be managed carefully in case a signal arrives 51r14 (lr) must be preserved 52r15 (pc) can be tinkered with directly 53 54r0 holds returns of <= 4 bytes 55r0-r1 hold returns of 8 bytes, low word in r0 56 57Callee must save/restore r4+ (except r12) if it modifies them. If VFP 58is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, 59s0-s15 (d0-d7, q0-a3) do not need to be. 60 61Stack is "full descending". Only the arguments that don't fit in the first 4 62registers are placed on the stack. "sp" points at the first stacked argument 63(i.e. the 5th arg). 64 65VFP: single-precision results in s0, double-precision results in d0. 66 67In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 6864-bit quantities (long long, double) must be 64-bit aligned. 69*/ 70 71/* 72Mterp and ARM notes: 73 74The following registers have fixed assignments: 75 76 reg nick purpose 77 r4 rPC interpreted program counter, used for fetching instructions 78 r5 rFP interpreted frame pointer, used for accessing locals and args 79 r6 rSELF self (Thread) pointer 80 r7 rINST first 16-bit code unit of current instruction 81 r8 rIBASE interpreted instruction base pointer, used for computed goto 82 r10 rPROFILE branch profiling countdown 83 r11 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). 84 85Macros are provided for common operations. Each macro MUST emit only 86one instruction to make instruction-counting easier. They MUST NOT alter 87unspecified registers or condition codes. 88*/ 89 90/* 91 * This is a #include, not a %include, because we want the C pre-processor 92 * to expand the macros into assembler assignment statements. 93 */ 94#include "asm_support.h" 95 96#define MTERP_PROFILE_BRANCHES 1 97#define MTERP_LOGGING 0 98 99/* During bringup, we'll use the shadow frame model instead of rFP */ 100/* single-purpose registers, given names for clarity */ 101#define rPC r4 102#define rFP r5 103#define rSELF r6 104#define rINST r7 105#define rIBASE r8 106#define rPROFILE r10 107#define rREFS r11 108 109/* 110 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, 111 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 112 */ 113#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 114#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 115#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 116#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 117#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 118#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 119#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 120#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET) 121#define OFF_FP_SHADOWFRAME OFF_FP(0) 122 123/* 124 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 125 * be done *before* something throws. 126 * 127 * It's okay to do this more than once. 128 * 129 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 130 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 131 * offset into the code_items_[] array. For effiency, we will "export" the 132 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 133 * to convert to a dex pc when needed. 134 */ 135.macro EXPORT_PC 136 str rPC, [rFP, #OFF_FP_DEX_PC_PTR] 137.endm 138 139.macro EXPORT_DEX_PC tmp 140 ldr \tmp, [rFP, #OFF_FP_CODE_ITEM] 141 str rPC, [rFP, #OFF_FP_DEX_PC_PTR] 142 add \tmp, #CODEITEM_INSNS_OFFSET 143 sub \tmp, rPC, \tmp 144 asr \tmp, #1 145 str \tmp, [rFP, #OFF_FP_DEX_PC] 146.endm 147 148/* 149 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 150 */ 151.macro FETCH_INST 152 ldrh rINST, [rPC] 153.endm 154 155/* 156 * Fetch the next instruction from the specified offset. Advances rPC 157 * to point to the next instruction. "_count" is in 16-bit code units. 158 * 159 * Because of the limited size of immediate constants on ARM, this is only 160 * suitable for small forward movements (i.e. don't try to implement "goto" 161 * with this). 162 * 163 * This must come AFTER anything that can throw an exception, or the 164 * exception catch may miss. (This also implies that it must come after 165 * EXPORT_PC.) 166 */ 167.macro FETCH_ADVANCE_INST count 168 ldrh rINST, [rPC, #((\count)*2)]! 169.endm 170 171/* 172 * The operation performed here is similar to FETCH_ADVANCE_INST, except the 173 * src and dest registers are parameterized (not hard-wired to rPC and rINST). 174 */ 175.macro PREFETCH_ADVANCE_INST dreg, sreg, count 176 ldrh \dreg, [\sreg, #((\count)*2)]! 177.endm 178 179/* 180 * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load 181 * rINST ahead of possible exception point. Be sure to manually advance rPC 182 * later. 183 */ 184.macro PREFETCH_INST count 185 ldrh rINST, [rPC, #((\count)*2)] 186.endm 187 188/* Advance rPC by some number of code units. */ 189.macro ADVANCE count 190 add rPC, #((\count)*2) 191.endm 192 193/* 194 * Fetch the next instruction from an offset specified by _reg. Updates 195 * rPC to point to the next instruction. "_reg" must specify the distance 196 * in bytes, *not* 16-bit code units, and may be a signed value. 197 * 198 * We want to write "ldrh rINST, [rPC, _reg, lsl #1]!", but some of the 199 * bits that hold the shift distance are used for the half/byte/sign flags. 200 * In some cases we can pre-double _reg for free, so we require a byte offset 201 * here. 202 */ 203.macro FETCH_ADVANCE_INST_RB reg 204 ldrh rINST, [rPC, \reg]! 205.endm 206 207/* 208 * Fetch a half-word code unit from an offset past the current PC. The 209 * "_count" value is in 16-bit code units. Does not advance rPC. 210 * 211 * The "_S" variant works the same but treats the value as signed. 212 */ 213.macro FETCH reg, count 214 ldrh \reg, [rPC, #((\count)*2)] 215.endm 216 217.macro FETCH_S reg, count 218 ldrsh \reg, [rPC, #((\count)*2)] 219.endm 220 221/* 222 * Fetch one byte from an offset past the current PC. Pass in the same 223 * "_count" as you would for FETCH, and an additional 0/1 indicating which 224 * byte of the halfword you want (lo/hi). 225 */ 226.macro FETCH_B reg, count, byte 227 ldrb \reg, [rPC, #((\count)*2+(\byte))] 228.endm 229 230/* 231 * Put the instruction's opcode field into the specified register. 232 */ 233.macro GET_INST_OPCODE reg 234 and \reg, rINST, #255 235.endm 236 237/* 238 * Put the prefetched instruction's opcode field into the specified register. 239 */ 240.macro GET_PREFETCHED_OPCODE oreg, ireg 241 and \oreg, \ireg, #255 242.endm 243 244/* 245 * Begin executing the opcode in _reg. Because this only jumps within the 246 * interpreter, we don't have to worry about pre-ARMv5 THUMB interwork. 247 */ 248.macro GOTO_OPCODE reg 249 add pc, rIBASE, \reg, lsl #7 250.endm 251.macro GOTO_OPCODE_BASE base,reg 252 add pc, \base, \reg, lsl #7 253.endm 254 255/* 256 * Get/set the 32-bit value from a Dalvik register. 257 */ 258.macro GET_VREG reg, vreg 259 ldr \reg, [rFP, \vreg, lsl #2] 260.endm 261.macro SET_VREG reg, vreg 262 str \reg, [rFP, \vreg, lsl #2] 263 mov \reg, #0 264 str \reg, [rREFS, \vreg, lsl #2] 265.endm 266.macro SET_VREG_OBJECT reg, vreg, tmpreg 267 str \reg, [rFP, \vreg, lsl #2] 268 str \reg, [rREFS, \vreg, lsl #2] 269.endm 270.macro SET_VREG_SHADOW reg, vreg 271 str \reg, [rREFS, \vreg, lsl #2] 272.endm 273 274/* 275 * Clear the corresponding shadow regs for a vreg pair 276 */ 277.macro CLEAR_SHADOW_PAIR vreg, tmp1, tmp2 278 mov \tmp1, #0 279 add \tmp2, \vreg, #1 280 SET_VREG_SHADOW \tmp1, \vreg 281 SET_VREG_SHADOW \tmp1, \tmp2 282.endm 283 284/* 285 * Convert a virtual register index into an address. 286 */ 287.macro VREG_INDEX_TO_ADDR reg, vreg 288 add \reg, rFP, \vreg, lsl #2 /* WARNING/FIXME: handle shadow frame vreg zero if store */ 289.endm 290 291/* 292 * Refresh handler table. 293 */ 294.macro REFRESH_IBASE 295 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] 296.endm 297 298/* 299 * cfi support macros. 300 */ 301.macro ENTRY name 302 .arm 303 .type \name, #function 304 .hidden \name // Hide this as a global symbol, so we do not incur plt calls. 305 .global \name 306 /* Cache alignment for function entry */ 307 .balign 16 308\name: 309 .cfi_startproc 310 .fnstart 311.endm 312 313.macro END name 314 .fnend 315 .cfi_endproc 316 .size \name, .-\name 317.endm 318 319/* File: arm/entry.S */ 320/* 321 * Copyright (C) 2016 The Android Open Source Project 322 * 323 * Licensed under the Apache License, Version 2.0 (the "License"); 324 * you may not use this file except in compliance with the License. 325 * You may obtain a copy of the License at 326 * 327 * http://www.apache.org/licenses/LICENSE-2.0 328 * 329 * Unless required by applicable law or agreed to in writing, software 330 * distributed under the License is distributed on an "AS IS" BASIS, 331 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 332 * See the License for the specific language governing permissions and 333 * limitations under the License. 334 */ 335/* 336 * Interpreter entry point. 337 */ 338 339 .text 340 .align 2 341 .global ExecuteMterpImpl 342 .type ExecuteMterpImpl, %function 343 344/* 345 * On entry: 346 * r0 Thread* self/ 347 * r1 code_item 348 * r2 ShadowFrame 349 * r3 JValue* result_register 350 * 351 */ 352 353ENTRY ExecuteMterpImpl 354 stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64) 355 .cfi_adjust_cfa_offset 40 356 .cfi_rel_offset r3, 0 357 .cfi_rel_offset r4, 4 358 .cfi_rel_offset r5, 8 359 .cfi_rel_offset r6, 12 360 .cfi_rel_offset r7, 16 361 .cfi_rel_offset r8, 20 362 .cfi_rel_offset r9, 24 363 .cfi_rel_offset r10, 28 364 .cfi_rel_offset fp, 32 365 .cfi_rel_offset lr, 36 366 367 /* Remember the return register */ 368 str r3, [r2, #SHADOWFRAME_RESULT_REGISTER_OFFSET] 369 370 /* Remember the code_item */ 371 str r1, [r2, #SHADOWFRAME_CODE_ITEM_OFFSET] 372 373 /* set up "named" registers */ 374 mov rSELF, r0 375 ldr r0, [r2, #SHADOWFRAME_NUMBER_OF_VREGS_OFFSET] 376 add rFP, r2, #SHADOWFRAME_VREGS_OFFSET @ point to vregs. 377 VREG_INDEX_TO_ADDR rREFS, r0 @ point to reference array in shadow frame 378 ldr r0, [r2, #SHADOWFRAME_DEX_PC_OFFSET] @ Get starting dex_pc. 379 add rPC, r1, #CODEITEM_INSNS_OFFSET @ Point to base of insns[] 380 add rPC, rPC, r0, lsl #1 @ Create direct pointer to 1st dex opcode 381 EXPORT_PC 382 383 /* Starting ibase */ 384 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] 385 386 /* Set up for backwards branches & osr profiling */ 387 ldr r0, [rFP, #OFF_FP_METHOD] 388 add r1, rFP, #OFF_FP_SHADOWFRAME 389 bl MterpSetUpHotnessCountdown 390 mov rPROFILE, r0 @ Starting hotness countdown to rPROFILE 391 392 /* start executing the instruction at rPC */ 393 FETCH_INST @ load rINST from rPC 394 GET_INST_OPCODE ip @ extract opcode from rINST 395 GOTO_OPCODE ip @ jump to next instruction 396 /* NOTE: no fallthrough */ 397 398 399 .global artMterpAsmInstructionStart 400 .type artMterpAsmInstructionStart, %function 401artMterpAsmInstructionStart = .L_op_nop 402 .text 403 404/* ------------------------------ */ 405 .balign 128 406.L_op_nop: /* 0x00 */ 407/* File: arm/op_nop.S */ 408 FETCH_ADVANCE_INST 1 @ advance to next instr, load rINST 409 GET_INST_OPCODE ip @ ip<- opcode from rINST 410 GOTO_OPCODE ip @ execute it 411 412/* ------------------------------ */ 413 .balign 128 414.L_op_move: /* 0x01 */ 415/* File: arm/op_move.S */ 416 /* for move, move-object, long-to-int */ 417 /* op vA, vB */ 418 mov r1, rINST, lsr #12 @ r1<- B from 15:12 419 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 420 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 421 GET_VREG r2, r1 @ r2<- fp[B] 422 GET_INST_OPCODE ip @ ip<- opcode from rINST 423 .if 0 424 SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 425 .else 426 SET_VREG r2, r0 @ fp[A]<- r2 427 .endif 428 GOTO_OPCODE ip @ execute next instruction 429 430/* ------------------------------ */ 431 .balign 128 432.L_op_move_from16: /* 0x02 */ 433/* File: arm/op_move_from16.S */ 434 /* for: move/from16, move-object/from16 */ 435 /* op vAA, vBBBB */ 436 FETCH r1, 1 @ r1<- BBBB 437 mov r0, rINST, lsr #8 @ r0<- AA 438 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 439 GET_VREG r2, r1 @ r2<- fp[BBBB] 440 GET_INST_OPCODE ip @ extract opcode from rINST 441 .if 0 442 SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 443 .else 444 SET_VREG r2, r0 @ fp[AA]<- r2 445 .endif 446 GOTO_OPCODE ip @ jump to next instruction 447 448/* ------------------------------ */ 449 .balign 128 450.L_op_move_16: /* 0x03 */ 451/* File: arm/op_move_16.S */ 452 /* for: move/16, move-object/16 */ 453 /* op vAAAA, vBBBB */ 454 FETCH r1, 2 @ r1<- BBBB 455 FETCH r0, 1 @ r0<- AAAA 456 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 457 GET_VREG r2, r1 @ r2<- fp[BBBB] 458 GET_INST_OPCODE ip @ extract opcode from rINST 459 .if 0 460 SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 461 .else 462 SET_VREG r2, r0 @ fp[AAAA]<- r2 463 .endif 464 GOTO_OPCODE ip @ jump to next instruction 465 466/* ------------------------------ */ 467 .balign 128 468.L_op_move_wide: /* 0x04 */ 469/* File: arm/op_move_wide.S */ 470 /* move-wide vA, vB */ 471 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 472 mov r3, rINST, lsr #12 @ r3<- B 473 ubfx rINST, rINST, #8, #4 @ rINST<- A 474 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 475 VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[A] 476 ldmia r3, {r0-r1} @ r0/r1<- fp[B] 477 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs 478 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 479 GET_INST_OPCODE ip @ extract opcode from rINST 480 stmia r2, {r0-r1} @ fp[A]<- r0/r1 481 GOTO_OPCODE ip @ jump to next instruction 482 483/* ------------------------------ */ 484 .balign 128 485.L_op_move_wide_from16: /* 0x05 */ 486/* File: arm/op_move_wide_from16.S */ 487 /* move-wide/from16 vAA, vBBBB */ 488 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 489 FETCH r3, 1 @ r3<- BBBB 490 mov rINST, rINST, lsr #8 @ rINST<- AA 491 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] 492 VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] 493 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 494 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs 495 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 496 GET_INST_OPCODE ip @ extract opcode from rINST 497 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 498 GOTO_OPCODE ip @ jump to next instruction 499 500/* ------------------------------ */ 501 .balign 128 502.L_op_move_wide_16: /* 0x06 */ 503/* File: arm/op_move_wide_16.S */ 504 /* move-wide/16 vAAAA, vBBBB */ 505 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 506 FETCH r3, 2 @ r3<- BBBB 507 FETCH r2, 1 @ r2<- AAAA 508 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BBBB] 509 VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA] 510 ldmia r3, {r0-r1} @ r0/r1<- fp[BBBB] 511 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 512 CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs 513 stmia lr, {r0-r1} @ fp[AAAA]<- r0/r1 514 GET_INST_OPCODE ip @ extract opcode from rINST 515 GOTO_OPCODE ip @ jump to next instruction 516 517/* ------------------------------ */ 518 .balign 128 519.L_op_move_object: /* 0x07 */ 520/* File: arm/op_move_object.S */ 521/* File: arm/op_move.S */ 522 /* for move, move-object, long-to-int */ 523 /* op vA, vB */ 524 mov r1, rINST, lsr #12 @ r1<- B from 15:12 525 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 526 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 527 GET_VREG r2, r1 @ r2<- fp[B] 528 GET_INST_OPCODE ip @ ip<- opcode from rINST 529 .if 1 530 SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 531 .else 532 SET_VREG r2, r0 @ fp[A]<- r2 533 .endif 534 GOTO_OPCODE ip @ execute next instruction 535 536 537/* ------------------------------ */ 538 .balign 128 539.L_op_move_object_from16: /* 0x08 */ 540/* File: arm/op_move_object_from16.S */ 541/* File: arm/op_move_from16.S */ 542 /* for: move/from16, move-object/from16 */ 543 /* op vAA, vBBBB */ 544 FETCH r1, 1 @ r1<- BBBB 545 mov r0, rINST, lsr #8 @ r0<- AA 546 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 547 GET_VREG r2, r1 @ r2<- fp[BBBB] 548 GET_INST_OPCODE ip @ extract opcode from rINST 549 .if 1 550 SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2 551 .else 552 SET_VREG r2, r0 @ fp[AA]<- r2 553 .endif 554 GOTO_OPCODE ip @ jump to next instruction 555 556 557/* ------------------------------ */ 558 .balign 128 559.L_op_move_object_16: /* 0x09 */ 560/* File: arm/op_move_object_16.S */ 561/* File: arm/op_move_16.S */ 562 /* for: move/16, move-object/16 */ 563 /* op vAAAA, vBBBB */ 564 FETCH r1, 2 @ r1<- BBBB 565 FETCH r0, 1 @ r0<- AAAA 566 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 567 GET_VREG r2, r1 @ r2<- fp[BBBB] 568 GET_INST_OPCODE ip @ extract opcode from rINST 569 .if 1 570 SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2 571 .else 572 SET_VREG r2, r0 @ fp[AAAA]<- r2 573 .endif 574 GOTO_OPCODE ip @ jump to next instruction 575 576 577/* ------------------------------ */ 578 .balign 128 579.L_op_move_result: /* 0x0a */ 580/* File: arm/op_move_result.S */ 581 /* for: move-result, move-result-object */ 582 /* op vAA */ 583 mov r2, rINST, lsr #8 @ r2<- AA 584 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 585 ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. 586 ldr r0, [r0] @ r0 <- result.i. 587 GET_INST_OPCODE ip @ extract opcode from rINST 588 .if 0 589 SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 590 .else 591 SET_VREG r0, r2 @ fp[AA]<- r0 592 .endif 593 GOTO_OPCODE ip @ jump to next instruction 594 595/* ------------------------------ */ 596 .balign 128 597.L_op_move_result_wide: /* 0x0b */ 598/* File: arm/op_move_result_wide.S */ 599 /* move-result-wide vAA */ 600 mov rINST, rINST, lsr #8 @ rINST<- AA 601 ldr r3, [rFP, #OFF_FP_RESULT_REGISTER] 602 VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] 603 ldmia r3, {r0-r1} @ r0/r1<- retval.j 604 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs 605 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 606 stmia r2, {r0-r1} @ fp[AA]<- r0/r1 607 GET_INST_OPCODE ip @ extract opcode from rINST 608 GOTO_OPCODE ip @ jump to next instruction 609 610/* ------------------------------ */ 611 .balign 128 612.L_op_move_result_object: /* 0x0c */ 613/* File: arm/op_move_result_object.S */ 614/* File: arm/op_move_result.S */ 615 /* for: move-result, move-result-object */ 616 /* op vAA */ 617 mov r2, rINST, lsr #8 @ r2<- AA 618 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 619 ldr r0, [rFP, #OFF_FP_RESULT_REGISTER] @ get pointer to result JType. 620 ldr r0, [r0] @ r0 <- result.i. 621 GET_INST_OPCODE ip @ extract opcode from rINST 622 .if 1 623 SET_VREG_OBJECT r0, r2, r1 @ fp[AA]<- r0 624 .else 625 SET_VREG r0, r2 @ fp[AA]<- r0 626 .endif 627 GOTO_OPCODE ip @ jump to next instruction 628 629 630/* ------------------------------ */ 631 .balign 128 632.L_op_move_exception: /* 0x0d */ 633/* File: arm/op_move_exception.S */ 634 /* move-exception vAA */ 635 mov r2, rINST, lsr #8 @ r2<- AA 636 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 637 mov r1, #0 @ r1<- 0 638 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 639 SET_VREG_OBJECT r3, r2 @ fp[AA]<- exception obj 640 GET_INST_OPCODE ip @ extract opcode from rINST 641 str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ clear exception 642 GOTO_OPCODE ip @ jump to next instruction 643 644/* ------------------------------ */ 645 .balign 128 646.L_op_return_void: /* 0x0e */ 647/* File: arm/op_return_void.S */ 648 .extern MterpThreadFenceForConstructor 649 bl MterpThreadFenceForConstructor 650 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 651 mov r0, rSELF 652 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 653 blne MterpSuspendCheck @ (self) 654 mov r0, #0 655 mov r1, #0 656 b MterpReturn 657 658/* ------------------------------ */ 659 .balign 128 660.L_op_return: /* 0x0f */ 661/* File: arm/op_return.S */ 662 /* 663 * Return a 32-bit value. 664 * 665 * for: return, return-object 666 */ 667 /* op vAA */ 668 .extern MterpThreadFenceForConstructor 669 bl MterpThreadFenceForConstructor 670 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 671 mov r0, rSELF 672 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 673 blne MterpSuspendCheck @ (self) 674 mov r2, rINST, lsr #8 @ r2<- AA 675 GET_VREG r0, r2 @ r0<- vAA 676 mov r1, #0 677 b MterpReturn 678 679/* ------------------------------ */ 680 .balign 128 681.L_op_return_wide: /* 0x10 */ 682/* File: arm/op_return_wide.S */ 683 /* 684 * Return a 64-bit value. 685 */ 686 /* return-wide vAA */ 687 .extern MterpThreadFenceForConstructor 688 bl MterpThreadFenceForConstructor 689 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 690 mov r0, rSELF 691 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 692 blne MterpSuspendCheck @ (self) 693 mov r2, rINST, lsr #8 @ r2<- AA 694 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[AA] 695 ldmia r2, {r0-r1} @ r0/r1 <- vAA/vAA+1 696 b MterpReturn 697 698/* ------------------------------ */ 699 .balign 128 700.L_op_return_object: /* 0x11 */ 701/* File: arm/op_return_object.S */ 702/* File: arm/op_return.S */ 703 /* 704 * Return a 32-bit value. 705 * 706 * for: return, return-object 707 */ 708 /* op vAA */ 709 .extern MterpThreadFenceForConstructor 710 bl MterpThreadFenceForConstructor 711 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 712 mov r0, rSELF 713 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 714 blne MterpSuspendCheck @ (self) 715 mov r2, rINST, lsr #8 @ r2<- AA 716 GET_VREG r0, r2 @ r0<- vAA 717 mov r1, #0 718 b MterpReturn 719 720 721/* ------------------------------ */ 722 .balign 128 723.L_op_const_4: /* 0x12 */ 724/* File: arm/op_const_4.S */ 725 /* const/4 vA, #+B */ 726 sbfx r1, rINST, #12, #4 @ r1<- sssssssB (sign-extended) 727 ubfx r0, rINST, #8, #4 @ r0<- A 728 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 729 GET_INST_OPCODE ip @ ip<- opcode from rINST 730 SET_VREG r1, r0 @ fp[A]<- r1 731 GOTO_OPCODE ip @ execute next instruction 732 733/* ------------------------------ */ 734 .balign 128 735.L_op_const_16: /* 0x13 */ 736/* File: arm/op_const_16.S */ 737 /* const/16 vAA, #+BBBB */ 738 FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) 739 mov r3, rINST, lsr #8 @ r3<- AA 740 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 741 SET_VREG r0, r3 @ vAA<- r0 742 GET_INST_OPCODE ip @ extract opcode from rINST 743 GOTO_OPCODE ip @ jump to next instruction 744 745/* ------------------------------ */ 746 .balign 128 747.L_op_const: /* 0x14 */ 748/* File: arm/op_const.S */ 749 /* const vAA, #+BBBBbbbb */ 750 mov r3, rINST, lsr #8 @ r3<- AA 751 FETCH r0, 1 @ r0<- bbbb (low) 752 FETCH r1, 2 @ r1<- BBBB (high) 753 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 754 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 755 GET_INST_OPCODE ip @ extract opcode from rINST 756 SET_VREG r0, r3 @ vAA<- r0 757 GOTO_OPCODE ip @ jump to next instruction 758 759/* ------------------------------ */ 760 .balign 128 761.L_op_const_high16: /* 0x15 */ 762/* File: arm/op_const_high16.S */ 763 /* const/high16 vAA, #+BBBB0000 */ 764 FETCH r0, 1 @ r0<- 0000BBBB (zero-extended) 765 mov r3, rINST, lsr #8 @ r3<- AA 766 mov r0, r0, lsl #16 @ r0<- BBBB0000 767 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 768 SET_VREG r0, r3 @ vAA<- r0 769 GET_INST_OPCODE ip @ extract opcode from rINST 770 GOTO_OPCODE ip @ jump to next instruction 771 772/* ------------------------------ */ 773 .balign 128 774.L_op_const_wide_16: /* 0x16 */ 775/* File: arm/op_const_wide_16.S */ 776 /* const-wide/16 vAA, #+BBBB */ 777 FETCH_S r0, 1 @ r0<- ssssBBBB (sign-extended) 778 mov r3, rINST, lsr #8 @ r3<- AA 779 mov r1, r0, asr #31 @ r1<- ssssssss 780 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 781 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs 782 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] 783 GET_INST_OPCODE ip @ extract opcode from rINST 784 stmia r3, {r0-r1} @ vAA<- r0/r1 785 GOTO_OPCODE ip @ jump to next instruction 786 787/* ------------------------------ */ 788 .balign 128 789.L_op_const_wide_32: /* 0x17 */ 790/* File: arm/op_const_wide_32.S */ 791 /* const-wide/32 vAA, #+BBBBbbbb */ 792 FETCH r0, 1 @ r0<- 0000bbbb (low) 793 mov r3, rINST, lsr #8 @ r3<- AA 794 FETCH_S r2, 2 @ r2<- ssssBBBB (high) 795 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 796 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb 797 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs 798 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] 799 mov r1, r0, asr #31 @ r1<- ssssssss 800 GET_INST_OPCODE ip @ extract opcode from rINST 801 stmia r3, {r0-r1} @ vAA<- r0/r1 802 GOTO_OPCODE ip @ jump to next instruction 803 804/* ------------------------------ */ 805 .balign 128 806.L_op_const_wide: /* 0x18 */ 807/* File: arm/op_const_wide.S */ 808 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 809 FETCH r0, 1 @ r0<- bbbb (low) 810 FETCH r1, 2 @ r1<- BBBB (low middle) 811 FETCH r2, 3 @ r2<- hhhh (high middle) 812 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word) 813 FETCH r3, 4 @ r3<- HHHH (high) 814 mov r9, rINST, lsr #8 @ r9<- AA 815 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word) 816 CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs 817 FETCH_ADVANCE_INST 5 @ advance rPC, load rINST 818 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 819 GET_INST_OPCODE ip @ extract opcode from rINST 820 stmia r9, {r0-r1} @ vAA<- r0/r1 821 GOTO_OPCODE ip @ jump to next instruction 822 823/* ------------------------------ */ 824 .balign 128 825.L_op_const_wide_high16: /* 0x19 */ 826/* File: arm/op_const_wide_high16.S */ 827 /* const-wide/high16 vAA, #+BBBB000000000000 */ 828 FETCH r1, 1 @ r1<- 0000BBBB (zero-extended) 829 mov r3, rINST, lsr #8 @ r3<- AA 830 mov r0, #0 @ r0<- 00000000 831 mov r1, r1, lsl #16 @ r1<- BBBB0000 832 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 833 CLEAR_SHADOW_PAIR r3, r0, r2 @ Zero shadow regs 834 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[AA] 835 GET_INST_OPCODE ip @ extract opcode from rINST 836 stmia r3, {r0-r1} @ vAA<- r0/r1 837 GOTO_OPCODE ip @ jump to next instruction 838 839/* ------------------------------ */ 840 .balign 128 841.L_op_const_string: /* 0x1a */ 842/* File: arm/op_const_string.S */ 843 /* const/string vAA, String@BBBB */ 844 EXPORT_PC 845 FETCH r0, 1 @ r0<- BBBB 846 mov r1, rINST, lsr #8 @ r1<- AA 847 add r2, rFP, #OFF_FP_SHADOWFRAME 848 mov r3, rSELF 849 bl MterpConstString @ (index, tgt_reg, shadow_frame, self) 850 PREFETCH_INST 2 @ load rINST 851 cmp r0, #0 @ fail? 852 bne MterpPossibleException @ let reference interpreter deal with it. 853 ADVANCE 2 @ advance rPC 854 GET_INST_OPCODE ip @ extract opcode from rINST 855 GOTO_OPCODE ip @ jump to next instruction 856 857/* ------------------------------ */ 858 .balign 128 859.L_op_const_string_jumbo: /* 0x1b */ 860/* File: arm/op_const_string_jumbo.S */ 861 /* const/string vAA, String@BBBBBBBB */ 862 EXPORT_PC 863 FETCH r0, 1 @ r0<- bbbb (low) 864 FETCH r2, 2 @ r2<- BBBB (high) 865 mov r1, rINST, lsr #8 @ r1<- AA 866 orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb 867 add r2, rFP, #OFF_FP_SHADOWFRAME 868 mov r3, rSELF 869 bl MterpConstString @ (index, tgt_reg, shadow_frame, self) 870 PREFETCH_INST 3 @ advance rPC 871 cmp r0, #0 @ fail? 872 bne MterpPossibleException @ let reference interpreter deal with it. 873 ADVANCE 3 @ advance rPC 874 GET_INST_OPCODE ip @ extract opcode from rINST 875 GOTO_OPCODE ip @ jump to next instruction 876 877/* ------------------------------ */ 878 .balign 128 879.L_op_const_class: /* 0x1c */ 880/* File: arm/op_const_class.S */ 881 /* const/class vAA, Class@BBBB */ 882 EXPORT_PC 883 FETCH r0, 1 @ r0<- BBBB 884 mov r1, rINST, lsr #8 @ r1<- AA 885 add r2, rFP, #OFF_FP_SHADOWFRAME 886 mov r3, rSELF 887 bl MterpConstClass @ (index, tgt_reg, shadow_frame, self) 888 PREFETCH_INST 2 889 cmp r0, #0 890 bne MterpPossibleException 891 ADVANCE 2 892 GET_INST_OPCODE ip @ extract opcode from rINST 893 GOTO_OPCODE ip @ jump to next instruction 894 895/* ------------------------------ */ 896 .balign 128 897.L_op_monitor_enter: /* 0x1d */ 898/* File: arm/op_monitor_enter.S */ 899 /* 900 * Synchronize on an object. 901 */ 902 /* monitor-enter vAA */ 903 EXPORT_PC 904 mov r2, rINST, lsr #8 @ r2<- AA 905 GET_VREG r0, r2 @ r0<- vAA (object) 906 mov r1, rSELF @ r1<- self 907 bl artLockObjectFromCode 908 cmp r0, #0 909 bne MterpException 910 FETCH_ADVANCE_INST 1 911 GET_INST_OPCODE ip @ extract opcode from rINST 912 GOTO_OPCODE ip @ jump to next instruction 913 914/* ------------------------------ */ 915 .balign 128 916.L_op_monitor_exit: /* 0x1e */ 917/* File: arm/op_monitor_exit.S */ 918 /* 919 * Unlock an object. 920 * 921 * Exceptions that occur when unlocking a monitor need to appear as 922 * if they happened at the following instruction. See the Dalvik 923 * instruction spec. 924 */ 925 /* monitor-exit vAA */ 926 EXPORT_PC 927 mov r2, rINST, lsr #8 @ r2<- AA 928 GET_VREG r0, r2 @ r0<- vAA (object) 929 mov r1, rSELF @ r0<- self 930 bl artUnlockObjectFromCode @ r0<- success for unlock(self, obj) 931 cmp r0, #0 @ failed? 932 bne MterpException 933 FETCH_ADVANCE_INST 1 @ before throw: advance rPC, load rINST 934 GET_INST_OPCODE ip @ extract opcode from rINST 935 GOTO_OPCODE ip @ jump to next instruction 936 937/* ------------------------------ */ 938 .balign 128 939.L_op_check_cast: /* 0x1f */ 940/* File: arm/op_check_cast.S */ 941 /* 942 * Check to see if a cast from one class to another is allowed. 943 */ 944 /* check-cast vAA, class@BBBB */ 945 EXPORT_PC 946 FETCH r0, 1 @ r0<- BBBB 947 mov r1, rINST, lsr #8 @ r1<- AA 948 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object 949 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method 950 mov r3, rSELF @ r3<- self 951 bl MterpCheckCast @ (index, &obj, method, self) 952 PREFETCH_INST 2 953 cmp r0, #0 954 bne MterpPossibleException 955 ADVANCE 2 956 GET_INST_OPCODE ip @ extract opcode from rINST 957 GOTO_OPCODE ip @ jump to next instruction 958 959/* ------------------------------ */ 960 .balign 128 961.L_op_instance_of: /* 0x20 */ 962/* File: arm/op_instance_of.S */ 963 /* 964 * Check to see if an object reference is an instance of a class. 965 * 966 * Most common situation is a non-null object, being compared against 967 * an already-resolved class. 968 */ 969 /* instance-of vA, vB, class@CCCC */ 970 EXPORT_PC 971 FETCH r0, 1 @ r0<- CCCC 972 mov r1, rINST, lsr #12 @ r1<- B 973 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &object 974 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- method 975 mov r3, rSELF @ r3<- self 976 bl MterpInstanceOf @ (index, &obj, method, self) 977 ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] 978 ubfx r9, rINST, #8, #4 @ r9<- A 979 PREFETCH_INST 2 980 cmp r1, #0 @ exception pending? 981 bne MterpException 982 ADVANCE 2 @ advance rPC 983 SET_VREG r0, r9 @ vA<- r0 984 GET_INST_OPCODE ip @ extract opcode from rINST 985 GOTO_OPCODE ip @ jump to next instruction 986 987/* ------------------------------ */ 988 .balign 128 989.L_op_array_length: /* 0x21 */ 990/* File: arm/op_array_length.S */ 991 /* 992 * Return the length of an array. 993 */ 994 mov r1, rINST, lsr #12 @ r1<- B 995 ubfx r2, rINST, #8, #4 @ r2<- A 996 GET_VREG r0, r1 @ r0<- vB (object ref) 997 cmp r0, #0 @ is object null? 998 beq common_errNullObject @ yup, fail 999 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 1000 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- array length 1001 GET_INST_OPCODE ip @ extract opcode from rINST 1002 SET_VREG r3, r2 @ vB<- length 1003 GOTO_OPCODE ip @ jump to next instruction 1004 1005/* ------------------------------ */ 1006 .balign 128 1007.L_op_new_instance: /* 0x22 */ 1008/* File: arm/op_new_instance.S */ 1009 /* 1010 * Create a new instance of a class. 1011 */ 1012 /* new-instance vAA, class@BBBB */ 1013 EXPORT_PC 1014 add r0, rFP, #OFF_FP_SHADOWFRAME 1015 mov r1, rSELF 1016 mov r2, rINST 1017 bl MterpNewInstance @ (shadow_frame, self, inst_data) 1018 cmp r0, #0 1019 beq MterpPossibleException 1020 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1021 GET_INST_OPCODE ip @ extract opcode from rINST 1022 GOTO_OPCODE ip @ jump to next instruction 1023 1024/* ------------------------------ */ 1025 .balign 128 1026.L_op_new_array: /* 0x23 */ 1027/* File: arm/op_new_array.S */ 1028 /* 1029 * Allocate an array of objects, specified with the array class 1030 * and a count. 1031 * 1032 * The verifier guarantees that this is an array class, so we don't 1033 * check for it here. 1034 */ 1035 /* new-array vA, vB, class@CCCC */ 1036 EXPORT_PC 1037 add r0, rFP, #OFF_FP_SHADOWFRAME 1038 mov r1, rPC 1039 mov r2, rINST 1040 mov r3, rSELF 1041 bl MterpNewArray 1042 cmp r0, #0 1043 beq MterpPossibleException 1044 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1045 GET_INST_OPCODE ip @ extract opcode from rINST 1046 GOTO_OPCODE ip @ jump to next instruction 1047 1048/* ------------------------------ */ 1049 .balign 128 1050.L_op_filled_new_array: /* 0x24 */ 1051/* File: arm/op_filled_new_array.S */ 1052 /* 1053 * Create a new array with elements filled from registers. 1054 * 1055 * for: filled-new-array, filled-new-array/range 1056 */ 1057 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1058 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1059 .extern MterpFilledNewArray 1060 EXPORT_PC 1061 add r0, rFP, #OFF_FP_SHADOWFRAME 1062 mov r1, rPC 1063 mov r2, rSELF 1064 bl MterpFilledNewArray 1065 cmp r0, #0 1066 beq MterpPossibleException 1067 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 1068 GET_INST_OPCODE ip @ extract opcode from rINST 1069 GOTO_OPCODE ip @ jump to next instruction 1070 1071/* ------------------------------ */ 1072 .balign 128 1073.L_op_filled_new_array_range: /* 0x25 */ 1074/* File: arm/op_filled_new_array_range.S */ 1075/* File: arm/op_filled_new_array.S */ 1076 /* 1077 * Create a new array with elements filled from registers. 1078 * 1079 * for: filled-new-array, filled-new-array/range 1080 */ 1081 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1082 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1083 .extern MterpFilledNewArrayRange 1084 EXPORT_PC 1085 add r0, rFP, #OFF_FP_SHADOWFRAME 1086 mov r1, rPC 1087 mov r2, rSELF 1088 bl MterpFilledNewArrayRange 1089 cmp r0, #0 1090 beq MterpPossibleException 1091 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 1092 GET_INST_OPCODE ip @ extract opcode from rINST 1093 GOTO_OPCODE ip @ jump to next instruction 1094 1095 1096/* ------------------------------ */ 1097 .balign 128 1098.L_op_fill_array_data: /* 0x26 */ 1099/* File: arm/op_fill_array_data.S */ 1100 /* fill-array-data vAA, +BBBBBBBB */ 1101 EXPORT_PC 1102 FETCH r0, 1 @ r0<- bbbb (lo) 1103 FETCH r1, 2 @ r1<- BBBB (hi) 1104 mov r3, rINST, lsr #8 @ r3<- AA 1105 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb 1106 GET_VREG r0, r3 @ r0<- vAA (array object) 1107 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.) 1108 bl MterpFillArrayData @ (obj, payload) 1109 cmp r0, #0 @ 0 means an exception is thrown 1110 beq MterpPossibleException @ exception? 1111 FETCH_ADVANCE_INST 3 @ advance rPC, load rINST 1112 GET_INST_OPCODE ip @ extract opcode from rINST 1113 GOTO_OPCODE ip @ jump to next instruction 1114 1115/* ------------------------------ */ 1116 .balign 128 1117.L_op_throw: /* 0x27 */ 1118/* File: arm/op_throw.S */ 1119 /* 1120 * Throw an exception object in the current thread. 1121 */ 1122 /* throw vAA */ 1123 EXPORT_PC 1124 mov r2, rINST, lsr #8 @ r2<- AA 1125 GET_VREG r1, r2 @ r1<- vAA (exception object) 1126 cmp r1, #0 @ null object? 1127 beq common_errNullObject @ yes, throw an NPE instead 1128 str r1, [rSELF, #THREAD_EXCEPTION_OFFSET] @ thread->exception<- obj 1129 b MterpException 1130 1131/* ------------------------------ */ 1132 .balign 128 1133.L_op_goto: /* 0x28 */ 1134/* File: arm/op_goto.S */ 1135 /* 1136 * Unconditional branch, 8-bit offset. 1137 * 1138 * The branch distance is a signed code-unit offset, which we need to 1139 * double to get a byte offset. 1140 */ 1141 /* goto +AA */ 1142 sbfx rINST, rINST, #8, #8 @ rINST<- ssssssAA (sign-extended) 1143 b MterpCommonTakenBranchNoFlags 1144 1145/* ------------------------------ */ 1146 .balign 128 1147.L_op_goto_16: /* 0x29 */ 1148/* File: arm/op_goto_16.S */ 1149 /* 1150 * Unconditional branch, 16-bit offset. 1151 * 1152 * The branch distance is a signed code-unit offset, which we need to 1153 * double to get a byte offset. 1154 */ 1155 /* goto/16 +AAAA */ 1156 FETCH_S rINST, 1 @ rINST<- ssssAAAA (sign-extended) 1157 b MterpCommonTakenBranchNoFlags 1158 1159/* ------------------------------ */ 1160 .balign 128 1161.L_op_goto_32: /* 0x2a */ 1162/* File: arm/op_goto_32.S */ 1163 /* 1164 * Unconditional branch, 32-bit offset. 1165 * 1166 * The branch distance is a signed code-unit offset, which we need to 1167 * double to get a byte offset. 1168 * 1169 * Unlike most opcodes, this one is allowed to branch to itself, so 1170 * our "backward branch" test must be "<=0" instead of "<0". Because 1171 * we need the V bit set, we'll use an adds to convert from Dalvik 1172 * offset to byte offset. 1173 */ 1174 /* goto/32 +AAAAAAAA */ 1175 FETCH r0, 1 @ r0<- aaaa (lo) 1176 FETCH r3, 2 @ r1<- AAAA (hi) 1177 orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa 1178 b MterpCommonTakenBranch 1179 1180/* ------------------------------ */ 1181 .balign 128 1182.L_op_packed_switch: /* 0x2b */ 1183/* File: arm/op_packed_switch.S */ 1184 /* 1185 * Handle a packed-switch or sparse-switch instruction. In both cases 1186 * we decode it and hand it off to a helper function. 1187 * 1188 * We don't really expect backward branches in a switch statement, but 1189 * they're perfectly legal, so we check for them here. 1190 * 1191 * for: packed-switch, sparse-switch 1192 */ 1193 /* op vAA, +BBBB */ 1194 FETCH r0, 1 @ r0<- bbbb (lo) 1195 FETCH r1, 2 @ r1<- BBBB (hi) 1196 mov r3, rINST, lsr #8 @ r3<- AA 1197 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1198 GET_VREG r1, r3 @ r1<- vAA 1199 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1200 bl MterpDoPackedSwitch @ r0<- code-unit branch offset 1201 movs rINST, r0 1202 b MterpCommonTakenBranch 1203 1204/* ------------------------------ */ 1205 .balign 128 1206.L_op_sparse_switch: /* 0x2c */ 1207/* File: arm/op_sparse_switch.S */ 1208/* File: arm/op_packed_switch.S */ 1209 /* 1210 * Handle a packed-switch or sparse-switch instruction. In both cases 1211 * we decode it and hand it off to a helper function. 1212 * 1213 * We don't really expect backward branches in a switch statement, but 1214 * they're perfectly legal, so we check for them here. 1215 * 1216 * for: packed-switch, sparse-switch 1217 */ 1218 /* op vAA, +BBBB */ 1219 FETCH r0, 1 @ r0<- bbbb (lo) 1220 FETCH r1, 2 @ r1<- BBBB (hi) 1221 mov r3, rINST, lsr #8 @ r3<- AA 1222 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb 1223 GET_VREG r1, r3 @ r1<- vAA 1224 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2 1225 bl MterpDoSparseSwitch @ r0<- code-unit branch offset 1226 movs rINST, r0 1227 b MterpCommonTakenBranch 1228 1229 1230/* ------------------------------ */ 1231 .balign 128 1232.L_op_cmpl_float: /* 0x2d */ 1233/* File: arm/op_cmpl_float.S */ 1234 /* 1235 * Compare two floating-point values. Puts 0, 1, or -1 into the 1236 * destination register based on the results of the comparison. 1237 * 1238 * int compare(x, y) { 1239 * if (x == y) { 1240 * return 0; 1241 * } else if (x > y) { 1242 * return 1; 1243 * } else if (x < y) { 1244 * return -1; 1245 * } else { 1246 * return -1; 1247 * } 1248 * } 1249 */ 1250 /* op vAA, vBB, vCC */ 1251 FETCH r0, 1 @ r0<- CCBB 1252 mov r9, rINST, lsr #8 @ r9<- AA 1253 and r2, r0, #255 @ r2<- BB 1254 mov r3, r0, lsr #8 @ r3<- CC 1255 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 1256 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 1257 flds s0, [r2] @ s0<- vBB 1258 flds s1, [r3] @ s1<- vCC 1259 vcmpe.f32 s0, s1 @ compare (vBB, vCC) 1260 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1261 mvn r0, #0 @ r0<- -1 (default) 1262 GET_INST_OPCODE ip @ extract opcode from rINST 1263 fmstat @ export status flags 1264 movgt r0, #1 @ (greater than) r1<- 1 1265 moveq r0, #0 @ (equal) r1<- 0 1266 SET_VREG r0, r9 @ vAA<- r0 1267 GOTO_OPCODE ip @ jump to next instruction 1268 1269/* ------------------------------ */ 1270 .balign 128 1271.L_op_cmpg_float: /* 0x2e */ 1272/* File: arm/op_cmpg_float.S */ 1273 /* 1274 * Compare two floating-point values. Puts 0, 1, or -1 into the 1275 * destination register based on the results of the comparison. 1276 * 1277 * int compare(x, y) { 1278 * if (x == y) { 1279 * return 0; 1280 * } else if (x < y) { 1281 * return -1; 1282 * } else if (x > y) { 1283 * return 1; 1284 * } else { 1285 * return 1; 1286 * } 1287 * } 1288 */ 1289 /* op vAA, vBB, vCC */ 1290 FETCH r0, 1 @ r0<- CCBB 1291 mov r9, rINST, lsr #8 @ r9<- AA 1292 and r2, r0, #255 @ r2<- BB 1293 mov r3, r0, lsr #8 @ r3<- CC 1294 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 1295 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 1296 flds s0, [r2] @ s0<- vBB 1297 flds s1, [r3] @ s1<- vCC 1298 vcmpe.f32 s0, s1 @ compare (vBB, vCC) 1299 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1300 mov r0, #1 @ r0<- 1 (default) 1301 GET_INST_OPCODE ip @ extract opcode from rINST 1302 fmstat @ export status flags 1303 mvnmi r0, #0 @ (less than) r1<- -1 1304 moveq r0, #0 @ (equal) r1<- 0 1305 SET_VREG r0, r9 @ vAA<- r0 1306 GOTO_OPCODE ip @ jump to next instruction 1307 1308/* ------------------------------ */ 1309 .balign 128 1310.L_op_cmpl_double: /* 0x2f */ 1311/* File: arm/op_cmpl_double.S */ 1312 /* 1313 * Compare two floating-point values. Puts 0, 1, or -1 into the 1314 * destination register based on the results of the comparison. 1315 * 1316 * int compare(x, y) { 1317 * if (x == y) { 1318 * return 0; 1319 * } else if (x > y) { 1320 * return 1; 1321 * } else if (x < y) { 1322 * return -1; 1323 * } else { 1324 * return -1; 1325 * } 1326 * } 1327 */ 1328 /* op vAA, vBB, vCC */ 1329 FETCH r0, 1 @ r0<- CCBB 1330 mov r9, rINST, lsr #8 @ r9<- AA 1331 and r2, r0, #255 @ r2<- BB 1332 mov r3, r0, lsr #8 @ r3<- CC 1333 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 1334 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 1335 fldd d0, [r2] @ d0<- vBB 1336 fldd d1, [r3] @ d1<- vCC 1337 vcmpe.f64 d0, d1 @ compare (vBB, vCC) 1338 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1339 mvn r0, #0 @ r0<- -1 (default) 1340 GET_INST_OPCODE ip @ extract opcode from rINST 1341 fmstat @ export status flags 1342 movgt r0, #1 @ (greater than) r1<- 1 1343 moveq r0, #0 @ (equal) r1<- 0 1344 SET_VREG r0, r9 @ vAA<- r0 1345 GOTO_OPCODE ip @ jump to next instruction 1346 1347/* ------------------------------ */ 1348 .balign 128 1349.L_op_cmpg_double: /* 0x30 */ 1350/* File: arm/op_cmpg_double.S */ 1351 /* 1352 * Compare two floating-point values. Puts 0, 1, or -1 into the 1353 * destination register based on the results of the comparison. 1354 * 1355 * int compare(x, y) { 1356 * if (x == y) { 1357 * return 0; 1358 * } else if (x < y) { 1359 * return -1; 1360 * } else if (x > y) { 1361 * return 1; 1362 * } else { 1363 * return 1; 1364 * } 1365 * } 1366 */ 1367 /* op vAA, vBB, vCC */ 1368 FETCH r0, 1 @ r0<- CCBB 1369 mov r9, rINST, lsr #8 @ r9<- AA 1370 and r2, r0, #255 @ r2<- BB 1371 mov r3, r0, lsr #8 @ r3<- CC 1372 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 1373 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 1374 fldd d0, [r2] @ d0<- vBB 1375 fldd d1, [r3] @ d1<- vCC 1376 vcmpe.f64 d0, d1 @ compare (vBB, vCC) 1377 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1378 mov r0, #1 @ r0<- 1 (default) 1379 GET_INST_OPCODE ip @ extract opcode from rINST 1380 fmstat @ export status flags 1381 mvnmi r0, #0 @ (less than) r1<- -1 1382 moveq r0, #0 @ (equal) r1<- 0 1383 SET_VREG r0, r9 @ vAA<- r0 1384 GOTO_OPCODE ip @ jump to next instruction 1385 1386/* ------------------------------ */ 1387 .balign 128 1388.L_op_cmp_long: /* 0x31 */ 1389/* File: arm/op_cmp_long.S */ 1390 /* 1391 * Compare two 64-bit values. Puts 0, 1, or -1 into the destination 1392 * register based on the results of the comparison. 1393 */ 1394 /* cmp-long vAA, vBB, vCC */ 1395 FETCH r0, 1 @ r0<- CCBB 1396 mov r9, rINST, lsr #8 @ r9<- AA 1397 and r2, r0, #255 @ r2<- BB 1398 mov r3, r0, lsr #8 @ r3<- CC 1399 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 1400 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 1401 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 1402 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 1403 cmp r0, r2 1404 sbcs ip, r1, r3 @ Sets correct CCs for checking LT (but not EQ/NE) 1405 mov ip, #0 1406 mvnlt ip, #0 @ -1 1407 cmpeq r0, r2 @ For correct EQ/NE, we may need to repeat the first CMP 1408 orrne ip, #1 1409 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1410 SET_VREG ip, r9 @ vAA<- ip 1411 GET_INST_OPCODE ip @ extract opcode from rINST 1412 GOTO_OPCODE ip @ jump to next instruction 1413 1414/* ------------------------------ */ 1415 .balign 128 1416.L_op_if_eq: /* 0x32 */ 1417/* File: arm/op_if_eq.S */ 1418/* File: arm/bincmp.S */ 1419 /* 1420 * Generic two-operand compare-and-branch operation. Provide a "condition" 1421 * fragment that specifies the comparison to perform. 1422 * 1423 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1424 */ 1425 /* if-cmp vA, vB, +CCCC */ 1426 mov r1, rINST, lsr #12 @ r1<- B 1427 ubfx r0, rINST, #8, #4 @ r0<- A 1428 GET_VREG r3, r1 @ r3<- vB 1429 GET_VREG r0, r0 @ r0<- vA 1430 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1431 cmp r0, r3 @ compare (vA, vB) 1432 beq MterpCommonTakenBranchNoFlags 1433 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1434 beq .L_check_not_taken_osr 1435 FETCH_ADVANCE_INST 2 1436 GET_INST_OPCODE ip @ extract opcode from rINST 1437 GOTO_OPCODE ip @ jump to next instruction 1438 1439 1440/* ------------------------------ */ 1441 .balign 128 1442.L_op_if_ne: /* 0x33 */ 1443/* File: arm/op_if_ne.S */ 1444/* File: arm/bincmp.S */ 1445 /* 1446 * Generic two-operand compare-and-branch operation. Provide a "condition" 1447 * fragment that specifies the comparison to perform. 1448 * 1449 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1450 */ 1451 /* if-cmp vA, vB, +CCCC */ 1452 mov r1, rINST, lsr #12 @ r1<- B 1453 ubfx r0, rINST, #8, #4 @ r0<- A 1454 GET_VREG r3, r1 @ r3<- vB 1455 GET_VREG r0, r0 @ r0<- vA 1456 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1457 cmp r0, r3 @ compare (vA, vB) 1458 bne MterpCommonTakenBranchNoFlags 1459 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1460 beq .L_check_not_taken_osr 1461 FETCH_ADVANCE_INST 2 1462 GET_INST_OPCODE ip @ extract opcode from rINST 1463 GOTO_OPCODE ip @ jump to next instruction 1464 1465 1466/* ------------------------------ */ 1467 .balign 128 1468.L_op_if_lt: /* 0x34 */ 1469/* File: arm/op_if_lt.S */ 1470/* File: arm/bincmp.S */ 1471 /* 1472 * Generic two-operand compare-and-branch operation. Provide a "condition" 1473 * fragment that specifies the comparison to perform. 1474 * 1475 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1476 */ 1477 /* if-cmp vA, vB, +CCCC */ 1478 mov r1, rINST, lsr #12 @ r1<- B 1479 ubfx r0, rINST, #8, #4 @ r0<- A 1480 GET_VREG r3, r1 @ r3<- vB 1481 GET_VREG r0, r0 @ r0<- vA 1482 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1483 cmp r0, r3 @ compare (vA, vB) 1484 blt MterpCommonTakenBranchNoFlags 1485 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1486 beq .L_check_not_taken_osr 1487 FETCH_ADVANCE_INST 2 1488 GET_INST_OPCODE ip @ extract opcode from rINST 1489 GOTO_OPCODE ip @ jump to next instruction 1490 1491 1492/* ------------------------------ */ 1493 .balign 128 1494.L_op_if_ge: /* 0x35 */ 1495/* File: arm/op_if_ge.S */ 1496/* File: arm/bincmp.S */ 1497 /* 1498 * Generic two-operand compare-and-branch operation. Provide a "condition" 1499 * fragment that specifies the comparison to perform. 1500 * 1501 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1502 */ 1503 /* if-cmp vA, vB, +CCCC */ 1504 mov r1, rINST, lsr #12 @ r1<- B 1505 ubfx r0, rINST, #8, #4 @ r0<- A 1506 GET_VREG r3, r1 @ r3<- vB 1507 GET_VREG r0, r0 @ r0<- vA 1508 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1509 cmp r0, r3 @ compare (vA, vB) 1510 bge MterpCommonTakenBranchNoFlags 1511 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1512 beq .L_check_not_taken_osr 1513 FETCH_ADVANCE_INST 2 1514 GET_INST_OPCODE ip @ extract opcode from rINST 1515 GOTO_OPCODE ip @ jump to next instruction 1516 1517 1518/* ------------------------------ */ 1519 .balign 128 1520.L_op_if_gt: /* 0x36 */ 1521/* File: arm/op_if_gt.S */ 1522/* File: arm/bincmp.S */ 1523 /* 1524 * Generic two-operand compare-and-branch operation. Provide a "condition" 1525 * fragment that specifies the comparison to perform. 1526 * 1527 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1528 */ 1529 /* if-cmp vA, vB, +CCCC */ 1530 mov r1, rINST, lsr #12 @ r1<- B 1531 ubfx r0, rINST, #8, #4 @ r0<- A 1532 GET_VREG r3, r1 @ r3<- vB 1533 GET_VREG r0, r0 @ r0<- vA 1534 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1535 cmp r0, r3 @ compare (vA, vB) 1536 bgt MterpCommonTakenBranchNoFlags 1537 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1538 beq .L_check_not_taken_osr 1539 FETCH_ADVANCE_INST 2 1540 GET_INST_OPCODE ip @ extract opcode from rINST 1541 GOTO_OPCODE ip @ jump to next instruction 1542 1543 1544/* ------------------------------ */ 1545 .balign 128 1546.L_op_if_le: /* 0x37 */ 1547/* File: arm/op_if_le.S */ 1548/* File: arm/bincmp.S */ 1549 /* 1550 * Generic two-operand compare-and-branch operation. Provide a "condition" 1551 * fragment that specifies the comparison to perform. 1552 * 1553 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1554 */ 1555 /* if-cmp vA, vB, +CCCC */ 1556 mov r1, rINST, lsr #12 @ r1<- B 1557 ubfx r0, rINST, #8, #4 @ r0<- A 1558 GET_VREG r3, r1 @ r3<- vB 1559 GET_VREG r0, r0 @ r0<- vA 1560 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1561 cmp r0, r3 @ compare (vA, vB) 1562 ble MterpCommonTakenBranchNoFlags 1563 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1564 beq .L_check_not_taken_osr 1565 FETCH_ADVANCE_INST 2 1566 GET_INST_OPCODE ip @ extract opcode from rINST 1567 GOTO_OPCODE ip @ jump to next instruction 1568 1569 1570/* ------------------------------ */ 1571 .balign 128 1572.L_op_if_eqz: /* 0x38 */ 1573/* File: arm/op_if_eqz.S */ 1574/* File: arm/zcmp.S */ 1575 /* 1576 * Generic one-operand compare-and-branch operation. Provide a "condition" 1577 * fragment that specifies the comparison to perform. 1578 * 1579 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1580 */ 1581 /* if-cmp vAA, +BBBB */ 1582 mov r0, rINST, lsr #8 @ r0<- AA 1583 GET_VREG r0, r0 @ r0<- vAA 1584 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1585 cmp r0, #0 @ compare (vA, 0) 1586 beq MterpCommonTakenBranchNoFlags 1587 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1588 beq .L_check_not_taken_osr 1589 FETCH_ADVANCE_INST 2 1590 GET_INST_OPCODE ip @ extract opcode from rINST 1591 GOTO_OPCODE ip @ jump to next instruction 1592 1593 1594/* ------------------------------ */ 1595 .balign 128 1596.L_op_if_nez: /* 0x39 */ 1597/* File: arm/op_if_nez.S */ 1598/* File: arm/zcmp.S */ 1599 /* 1600 * Generic one-operand compare-and-branch operation. Provide a "condition" 1601 * fragment that specifies the comparison to perform. 1602 * 1603 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1604 */ 1605 /* if-cmp vAA, +BBBB */ 1606 mov r0, rINST, lsr #8 @ r0<- AA 1607 GET_VREG r0, r0 @ r0<- vAA 1608 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1609 cmp r0, #0 @ compare (vA, 0) 1610 bne MterpCommonTakenBranchNoFlags 1611 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1612 beq .L_check_not_taken_osr 1613 FETCH_ADVANCE_INST 2 1614 GET_INST_OPCODE ip @ extract opcode from rINST 1615 GOTO_OPCODE ip @ jump to next instruction 1616 1617 1618/* ------------------------------ */ 1619 .balign 128 1620.L_op_if_ltz: /* 0x3a */ 1621/* File: arm/op_if_ltz.S */ 1622/* File: arm/zcmp.S */ 1623 /* 1624 * Generic one-operand compare-and-branch operation. Provide a "condition" 1625 * fragment that specifies the comparison to perform. 1626 * 1627 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1628 */ 1629 /* if-cmp vAA, +BBBB */ 1630 mov r0, rINST, lsr #8 @ r0<- AA 1631 GET_VREG r0, r0 @ r0<- vAA 1632 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1633 cmp r0, #0 @ compare (vA, 0) 1634 blt MterpCommonTakenBranchNoFlags 1635 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1636 beq .L_check_not_taken_osr 1637 FETCH_ADVANCE_INST 2 1638 GET_INST_OPCODE ip @ extract opcode from rINST 1639 GOTO_OPCODE ip @ jump to next instruction 1640 1641 1642/* ------------------------------ */ 1643 .balign 128 1644.L_op_if_gez: /* 0x3b */ 1645/* File: arm/op_if_gez.S */ 1646/* File: arm/zcmp.S */ 1647 /* 1648 * Generic one-operand compare-and-branch operation. Provide a "condition" 1649 * fragment that specifies the comparison to perform. 1650 * 1651 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1652 */ 1653 /* if-cmp vAA, +BBBB */ 1654 mov r0, rINST, lsr #8 @ r0<- AA 1655 GET_VREG r0, r0 @ r0<- vAA 1656 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1657 cmp r0, #0 @ compare (vA, 0) 1658 bge MterpCommonTakenBranchNoFlags 1659 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1660 beq .L_check_not_taken_osr 1661 FETCH_ADVANCE_INST 2 1662 GET_INST_OPCODE ip @ extract opcode from rINST 1663 GOTO_OPCODE ip @ jump to next instruction 1664 1665 1666/* ------------------------------ */ 1667 .balign 128 1668.L_op_if_gtz: /* 0x3c */ 1669/* File: arm/op_if_gtz.S */ 1670/* File: arm/zcmp.S */ 1671 /* 1672 * Generic one-operand compare-and-branch operation. Provide a "condition" 1673 * fragment that specifies the comparison to perform. 1674 * 1675 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1676 */ 1677 /* if-cmp vAA, +BBBB */ 1678 mov r0, rINST, lsr #8 @ r0<- AA 1679 GET_VREG r0, r0 @ r0<- vAA 1680 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1681 cmp r0, #0 @ compare (vA, 0) 1682 bgt MterpCommonTakenBranchNoFlags 1683 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1684 beq .L_check_not_taken_osr 1685 FETCH_ADVANCE_INST 2 1686 GET_INST_OPCODE ip @ extract opcode from rINST 1687 GOTO_OPCODE ip @ jump to next instruction 1688 1689 1690/* ------------------------------ */ 1691 .balign 128 1692.L_op_if_lez: /* 0x3d */ 1693/* File: arm/op_if_lez.S */ 1694/* File: arm/zcmp.S */ 1695 /* 1696 * Generic one-operand compare-and-branch operation. Provide a "condition" 1697 * fragment that specifies the comparison to perform. 1698 * 1699 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1700 */ 1701 /* if-cmp vAA, +BBBB */ 1702 mov r0, rINST, lsr #8 @ r0<- AA 1703 GET_VREG r0, r0 @ r0<- vAA 1704 FETCH_S rINST, 1 @ rINST<- branch offset, in code units 1705 cmp r0, #0 @ compare (vA, 0) 1706 ble MterpCommonTakenBranchNoFlags 1707 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 1708 beq .L_check_not_taken_osr 1709 FETCH_ADVANCE_INST 2 1710 GET_INST_OPCODE ip @ extract opcode from rINST 1711 GOTO_OPCODE ip @ jump to next instruction 1712 1713 1714/* ------------------------------ */ 1715 .balign 128 1716.L_op_unused_3e: /* 0x3e */ 1717/* File: arm/op_unused_3e.S */ 1718/* File: arm/unused.S */ 1719/* 1720 * Bail to reference interpreter to throw. 1721 */ 1722 b MterpFallback 1723 1724 1725/* ------------------------------ */ 1726 .balign 128 1727.L_op_unused_3f: /* 0x3f */ 1728/* File: arm/op_unused_3f.S */ 1729/* File: arm/unused.S */ 1730/* 1731 * Bail to reference interpreter to throw. 1732 */ 1733 b MterpFallback 1734 1735 1736/* ------------------------------ */ 1737 .balign 128 1738.L_op_unused_40: /* 0x40 */ 1739/* File: arm/op_unused_40.S */ 1740/* File: arm/unused.S */ 1741/* 1742 * Bail to reference interpreter to throw. 1743 */ 1744 b MterpFallback 1745 1746 1747/* ------------------------------ */ 1748 .balign 128 1749.L_op_unused_41: /* 0x41 */ 1750/* File: arm/op_unused_41.S */ 1751/* File: arm/unused.S */ 1752/* 1753 * Bail to reference interpreter to throw. 1754 */ 1755 b MterpFallback 1756 1757 1758/* ------------------------------ */ 1759 .balign 128 1760.L_op_unused_42: /* 0x42 */ 1761/* File: arm/op_unused_42.S */ 1762/* File: arm/unused.S */ 1763/* 1764 * Bail to reference interpreter to throw. 1765 */ 1766 b MterpFallback 1767 1768 1769/* ------------------------------ */ 1770 .balign 128 1771.L_op_unused_43: /* 0x43 */ 1772/* File: arm/op_unused_43.S */ 1773/* File: arm/unused.S */ 1774/* 1775 * Bail to reference interpreter to throw. 1776 */ 1777 b MterpFallback 1778 1779 1780/* ------------------------------ */ 1781 .balign 128 1782.L_op_aget: /* 0x44 */ 1783/* File: arm/op_aget.S */ 1784 /* 1785 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1786 * 1787 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1788 * instructions. We use a pair of FETCH_Bs instead. 1789 * 1790 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1791 * 1792 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1793 * If this changes, specialize. 1794 */ 1795 /* op vAA, vBB, vCC */ 1796 FETCH_B r2, 1, 0 @ r2<- BB 1797 mov r9, rINST, lsr #8 @ r9<- AA 1798 FETCH_B r3, 1, 1 @ r3<- CC 1799 GET_VREG r0, r2 @ r0<- vBB (array object) 1800 GET_VREG r1, r3 @ r1<- vCC (requested index) 1801 cmp r0, #0 @ null array object? 1802 beq common_errNullObject @ yes, bail 1803 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1804 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 1805 cmp r1, r3 @ compare unsigned index, length 1806 bcs common_errArrayIndex @ index >= length, bail 1807 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1808 ldr r2, [r0, #MIRROR_INT_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] 1809 GET_INST_OPCODE ip @ extract opcode from rINST 1810 SET_VREG r2, r9 @ vAA<- r2 1811 GOTO_OPCODE ip @ jump to next instruction 1812 1813/* ------------------------------ */ 1814 .balign 128 1815.L_op_aget_wide: /* 0x45 */ 1816/* File: arm/op_aget_wide.S */ 1817 /* 1818 * Array get, 64 bits. vAA <- vBB[vCC]. 1819 * 1820 * Arrays of long/double are 64-bit aligned, so it's okay to use LDRD. 1821 */ 1822 /* aget-wide vAA, vBB, vCC */ 1823 FETCH r0, 1 @ r0<- CCBB 1824 mov r9, rINST, lsr #8 @ r9<- AA 1825 and r2, r0, #255 @ r2<- BB 1826 mov r3, r0, lsr #8 @ r3<- CC 1827 GET_VREG r0, r2 @ r0<- vBB (array object) 1828 GET_VREG r1, r3 @ r1<- vCC (requested index) 1829 CLEAR_SHADOW_PAIR r9, r2, r3 @ Zero out the shadow regs 1830 cmp r0, #0 @ null array object? 1831 beq common_errNullObject @ yes, bail 1832 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1833 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 1834 cmp r1, r3 @ compare unsigned index, length 1835 bcs common_errArrayIndex @ index >= length, bail 1836 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1837 ldrd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] 1838 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 1839 GET_INST_OPCODE ip @ extract opcode from rINST 1840 stmia r9, {r2-r3} @ vAA/vAA+1<- r2/r3 1841 GOTO_OPCODE ip @ jump to next instruction 1842 1843/* ------------------------------ */ 1844 .balign 128 1845.L_op_aget_object: /* 0x46 */ 1846/* File: arm/op_aget_object.S */ 1847 /* 1848 * Array object get. vAA <- vBB[vCC]. 1849 * 1850 * for: aget-object 1851 */ 1852 /* op vAA, vBB, vCC */ 1853 FETCH_B r2, 1, 0 @ r2<- BB 1854 mov r9, rINST, lsr #8 @ r9<- AA 1855 FETCH_B r3, 1, 1 @ r3<- CC 1856 EXPORT_PC 1857 GET_VREG r0, r2 @ r0<- vBB (array object) 1858 GET_VREG r1, r3 @ r1<- vCC (requested index) 1859 bl artAGetObjectFromMterp @ (array, index) 1860 ldr r1, [rSELF, #THREAD_EXCEPTION_OFFSET] 1861 PREFETCH_INST 2 1862 cmp r1, #0 1863 bne MterpException 1864 SET_VREG_OBJECT r0, r9 1865 ADVANCE 2 1866 GET_INST_OPCODE ip 1867 GOTO_OPCODE ip @ jump to next instruction 1868 1869/* ------------------------------ */ 1870 .balign 128 1871.L_op_aget_boolean: /* 0x47 */ 1872/* File: arm/op_aget_boolean.S */ 1873/* File: arm/op_aget.S */ 1874 /* 1875 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1876 * 1877 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1878 * instructions. We use a pair of FETCH_Bs instead. 1879 * 1880 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1881 * 1882 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1883 * If this changes, specialize. 1884 */ 1885 /* op vAA, vBB, vCC */ 1886 FETCH_B r2, 1, 0 @ r2<- BB 1887 mov r9, rINST, lsr #8 @ r9<- AA 1888 FETCH_B r3, 1, 1 @ r3<- CC 1889 GET_VREG r0, r2 @ r0<- vBB (array object) 1890 GET_VREG r1, r3 @ r1<- vCC (requested index) 1891 cmp r0, #0 @ null array object? 1892 beq common_errNullObject @ yes, bail 1893 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1894 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 1895 cmp r1, r3 @ compare unsigned index, length 1896 bcs common_errArrayIndex @ index >= length, bail 1897 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1898 ldrb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] 1899 GET_INST_OPCODE ip @ extract opcode from rINST 1900 SET_VREG r2, r9 @ vAA<- r2 1901 GOTO_OPCODE ip @ jump to next instruction 1902 1903 1904/* ------------------------------ */ 1905 .balign 128 1906.L_op_aget_byte: /* 0x48 */ 1907/* File: arm/op_aget_byte.S */ 1908/* File: arm/op_aget.S */ 1909 /* 1910 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1911 * 1912 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1913 * instructions. We use a pair of FETCH_Bs instead. 1914 * 1915 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1916 * 1917 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1918 * If this changes, specialize. 1919 */ 1920 /* op vAA, vBB, vCC */ 1921 FETCH_B r2, 1, 0 @ r2<- BB 1922 mov r9, rINST, lsr #8 @ r9<- AA 1923 FETCH_B r3, 1, 1 @ r3<- CC 1924 GET_VREG r0, r2 @ r0<- vBB (array object) 1925 GET_VREG r1, r3 @ r1<- vCC (requested index) 1926 cmp r0, #0 @ null array object? 1927 beq common_errNullObject @ yes, bail 1928 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1929 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 1930 cmp r1, r3 @ compare unsigned index, length 1931 bcs common_errArrayIndex @ index >= length, bail 1932 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1933 ldrsb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] 1934 GET_INST_OPCODE ip @ extract opcode from rINST 1935 SET_VREG r2, r9 @ vAA<- r2 1936 GOTO_OPCODE ip @ jump to next instruction 1937 1938 1939/* ------------------------------ */ 1940 .balign 128 1941.L_op_aget_char: /* 0x49 */ 1942/* File: arm/op_aget_char.S */ 1943/* File: arm/op_aget.S */ 1944 /* 1945 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1946 * 1947 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1948 * instructions. We use a pair of FETCH_Bs instead. 1949 * 1950 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1951 * 1952 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1953 * If this changes, specialize. 1954 */ 1955 /* op vAA, vBB, vCC */ 1956 FETCH_B r2, 1, 0 @ r2<- BB 1957 mov r9, rINST, lsr #8 @ r9<- AA 1958 FETCH_B r3, 1, 1 @ r3<- CC 1959 GET_VREG r0, r2 @ r0<- vBB (array object) 1960 GET_VREG r1, r3 @ r1<- vCC (requested index) 1961 cmp r0, #0 @ null array object? 1962 beq common_errNullObject @ yes, bail 1963 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1964 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 1965 cmp r1, r3 @ compare unsigned index, length 1966 bcs common_errArrayIndex @ index >= length, bail 1967 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 1968 ldrh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] 1969 GET_INST_OPCODE ip @ extract opcode from rINST 1970 SET_VREG r2, r9 @ vAA<- r2 1971 GOTO_OPCODE ip @ jump to next instruction 1972 1973 1974/* ------------------------------ */ 1975 .balign 128 1976.L_op_aget_short: /* 0x4a */ 1977/* File: arm/op_aget_short.S */ 1978/* File: arm/op_aget.S */ 1979 /* 1980 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1981 * 1982 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 1983 * instructions. We use a pair of FETCH_Bs instead. 1984 * 1985 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1986 * 1987 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1988 * If this changes, specialize. 1989 */ 1990 /* op vAA, vBB, vCC */ 1991 FETCH_B r2, 1, 0 @ r2<- BB 1992 mov r9, rINST, lsr #8 @ r9<- AA 1993 FETCH_B r3, 1, 1 @ r3<- CC 1994 GET_VREG r0, r2 @ r0<- vBB (array object) 1995 GET_VREG r1, r3 @ r1<- vCC (requested index) 1996 cmp r0, #0 @ null array object? 1997 beq common_errNullObject @ yes, bail 1998 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 1999 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2000 cmp r1, r3 @ compare unsigned index, length 2001 bcs common_errArrayIndex @ index >= length, bail 2002 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2003 ldrsh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ r2<- vBB[vCC] 2004 GET_INST_OPCODE ip @ extract opcode from rINST 2005 SET_VREG r2, r9 @ vAA<- r2 2006 GOTO_OPCODE ip @ jump to next instruction 2007 2008 2009/* ------------------------------ */ 2010 .balign 128 2011.L_op_aput: /* 0x4b */ 2012/* File: arm/op_aput.S */ 2013 /* 2014 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2015 * 2016 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2017 * instructions. We use a pair of FETCH_Bs instead. 2018 * 2019 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2020 * 2021 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2022 * If this changes, specialize. 2023 */ 2024 /* op vAA, vBB, vCC */ 2025 FETCH_B r2, 1, 0 @ r2<- BB 2026 mov r9, rINST, lsr #8 @ r9<- AA 2027 FETCH_B r3, 1, 1 @ r3<- CC 2028 GET_VREG r0, r2 @ r0<- vBB (array object) 2029 GET_VREG r1, r3 @ r1<- vCC (requested index) 2030 cmp r0, #0 @ null array object? 2031 beq common_errNullObject @ yes, bail 2032 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2033 add r0, r0, r1, lsl #2 @ r0<- arrayObj + index*width 2034 cmp r1, r3 @ compare unsigned index, length 2035 bcs common_errArrayIndex @ index >= length, bail 2036 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2037 GET_VREG r2, r9 @ r2<- vAA 2038 GET_INST_OPCODE ip @ extract opcode from rINST 2039 str r2, [r0, #MIRROR_INT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 2040 GOTO_OPCODE ip @ jump to next instruction 2041 2042/* ------------------------------ */ 2043 .balign 128 2044.L_op_aput_wide: /* 0x4c */ 2045/* File: arm/op_aput_wide.S */ 2046 /* 2047 * Array put, 64 bits. vBB[vCC] <- vAA. 2048 * 2049 * Arrays of long/double are 64-bit aligned, so it's okay to use STRD. 2050 */ 2051 /* aput-wide vAA, vBB, vCC */ 2052 FETCH r0, 1 @ r0<- CCBB 2053 mov r9, rINST, lsr #8 @ r9<- AA 2054 and r2, r0, #255 @ r2<- BB 2055 mov r3, r0, lsr #8 @ r3<- CC 2056 GET_VREG r0, r2 @ r0<- vBB (array object) 2057 GET_VREG r1, r3 @ r1<- vCC (requested index) 2058 cmp r0, #0 @ null array object? 2059 beq common_errNullObject @ yes, bail 2060 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2061 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width 2062 cmp r1, r3 @ compare unsigned index, length 2063 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 2064 bcs common_errArrayIndex @ index >= length, bail 2065 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2066 ldmia r9, {r2-r3} @ r2/r3<- vAA/vAA+1 2067 GET_INST_OPCODE ip @ extract opcode from rINST 2068 strd r2, [r0, #MIRROR_WIDE_ARRAY_DATA_OFFSET] @ r2/r3<- vBB[vCC] 2069 GOTO_OPCODE ip @ jump to next instruction 2070 2071/* ------------------------------ */ 2072 .balign 128 2073.L_op_aput_object: /* 0x4d */ 2074/* File: arm/op_aput_object.S */ 2075 /* 2076 * Store an object into an array. vBB[vCC] <- vAA. 2077 */ 2078 /* op vAA, vBB, vCC */ 2079 EXPORT_PC 2080 add r0, rFP, #OFF_FP_SHADOWFRAME 2081 mov r1, rPC 2082 mov r2, rINST 2083 bl MterpAputObject 2084 cmp r0, #0 2085 beq MterpPossibleException 2086 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2087 GET_INST_OPCODE ip @ extract opcode from rINST 2088 GOTO_OPCODE ip @ jump to next instruction 2089 2090/* ------------------------------ */ 2091 .balign 128 2092.L_op_aput_boolean: /* 0x4e */ 2093/* File: arm/op_aput_boolean.S */ 2094/* File: arm/op_aput.S */ 2095 /* 2096 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2097 * 2098 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2099 * instructions. We use a pair of FETCH_Bs instead. 2100 * 2101 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2102 * 2103 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2104 * If this changes, specialize. 2105 */ 2106 /* op vAA, vBB, vCC */ 2107 FETCH_B r2, 1, 0 @ r2<- BB 2108 mov r9, rINST, lsr #8 @ r9<- AA 2109 FETCH_B r3, 1, 1 @ r3<- CC 2110 GET_VREG r0, r2 @ r0<- vBB (array object) 2111 GET_VREG r1, r3 @ r1<- vCC (requested index) 2112 cmp r0, #0 @ null array object? 2113 beq common_errNullObject @ yes, bail 2114 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2115 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2116 cmp r1, r3 @ compare unsigned index, length 2117 bcs common_errArrayIndex @ index >= length, bail 2118 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2119 GET_VREG r2, r9 @ r2<- vAA 2120 GET_INST_OPCODE ip @ extract opcode from rINST 2121 strb r2, [r0, #MIRROR_BOOLEAN_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 2122 GOTO_OPCODE ip @ jump to next instruction 2123 2124 2125/* ------------------------------ */ 2126 .balign 128 2127.L_op_aput_byte: /* 0x4f */ 2128/* File: arm/op_aput_byte.S */ 2129/* File: arm/op_aput.S */ 2130 /* 2131 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2132 * 2133 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2134 * instructions. We use a pair of FETCH_Bs instead. 2135 * 2136 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2137 * 2138 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2139 * If this changes, specialize. 2140 */ 2141 /* op vAA, vBB, vCC */ 2142 FETCH_B r2, 1, 0 @ r2<- BB 2143 mov r9, rINST, lsr #8 @ r9<- AA 2144 FETCH_B r3, 1, 1 @ r3<- CC 2145 GET_VREG r0, r2 @ r0<- vBB (array object) 2146 GET_VREG r1, r3 @ r1<- vCC (requested index) 2147 cmp r0, #0 @ null array object? 2148 beq common_errNullObject @ yes, bail 2149 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2150 add r0, r0, r1, lsl #0 @ r0<- arrayObj + index*width 2151 cmp r1, r3 @ compare unsigned index, length 2152 bcs common_errArrayIndex @ index >= length, bail 2153 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2154 GET_VREG r2, r9 @ r2<- vAA 2155 GET_INST_OPCODE ip @ extract opcode from rINST 2156 strb r2, [r0, #MIRROR_BYTE_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 2157 GOTO_OPCODE ip @ jump to next instruction 2158 2159 2160/* ------------------------------ */ 2161 .balign 128 2162.L_op_aput_char: /* 0x50 */ 2163/* File: arm/op_aput_char.S */ 2164/* File: arm/op_aput.S */ 2165 /* 2166 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2167 * 2168 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2169 * instructions. We use a pair of FETCH_Bs instead. 2170 * 2171 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2172 * 2173 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2174 * If this changes, specialize. 2175 */ 2176 /* op vAA, vBB, vCC */ 2177 FETCH_B r2, 1, 0 @ r2<- BB 2178 mov r9, rINST, lsr #8 @ r9<- AA 2179 FETCH_B r3, 1, 1 @ r3<- CC 2180 GET_VREG r0, r2 @ r0<- vBB (array object) 2181 GET_VREG r1, r3 @ r1<- vCC (requested index) 2182 cmp r0, #0 @ null array object? 2183 beq common_errNullObject @ yes, bail 2184 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2185 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2186 cmp r1, r3 @ compare unsigned index, length 2187 bcs common_errArrayIndex @ index >= length, bail 2188 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2189 GET_VREG r2, r9 @ r2<- vAA 2190 GET_INST_OPCODE ip @ extract opcode from rINST 2191 strh r2, [r0, #MIRROR_CHAR_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 2192 GOTO_OPCODE ip @ jump to next instruction 2193 2194 2195/* ------------------------------ */ 2196 .balign 128 2197.L_op_aput_short: /* 0x51 */ 2198/* File: arm/op_aput_short.S */ 2199/* File: arm/op_aput.S */ 2200 /* 2201 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2202 * 2203 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2204 * instructions. We use a pair of FETCH_Bs instead. 2205 * 2206 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2207 * 2208 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2209 * If this changes, specialize. 2210 */ 2211 /* op vAA, vBB, vCC */ 2212 FETCH_B r2, 1, 0 @ r2<- BB 2213 mov r9, rINST, lsr #8 @ r9<- AA 2214 FETCH_B r3, 1, 1 @ r3<- CC 2215 GET_VREG r0, r2 @ r0<- vBB (array object) 2216 GET_VREG r1, r3 @ r1<- vCC (requested index) 2217 cmp r0, #0 @ null array object? 2218 beq common_errNullObject @ yes, bail 2219 ldr r3, [r0, #MIRROR_ARRAY_LENGTH_OFFSET] @ r3<- arrayObj->length 2220 add r0, r0, r1, lsl #1 @ r0<- arrayObj + index*width 2221 cmp r1, r3 @ compare unsigned index, length 2222 bcs common_errArrayIndex @ index >= length, bail 2223 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2224 GET_VREG r2, r9 @ r2<- vAA 2225 GET_INST_OPCODE ip @ extract opcode from rINST 2226 strh r2, [r0, #MIRROR_SHORT_ARRAY_DATA_OFFSET] @ vBB[vCC]<- r2 2227 GOTO_OPCODE ip @ jump to next instruction 2228 2229 2230/* ------------------------------ */ 2231 .balign 128 2232.L_op_iget: /* 0x52 */ 2233/* File: arm/op_iget.S */ 2234 /* 2235 * General instance field get. 2236 * 2237 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2238 */ 2239 EXPORT_PC 2240 FETCH r0, 1 @ r0<- field ref CCCC 2241 mov r1, rINST, lsr #12 @ r1<- B 2242 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2243 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2244 mov r3, rSELF @ r3<- self 2245 bl artGet32InstanceFromCode 2246 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2247 ubfx r2, rINST, #8, #4 @ r2<- A 2248 PREFETCH_INST 2 2249 cmp r3, #0 2250 bne MterpPossibleException @ bail out 2251 .if 0 2252 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2253 .else 2254 SET_VREG r0, r2 @ fp[A]<- r0 2255 .endif 2256 ADVANCE 2 2257 GET_INST_OPCODE ip @ extract opcode from rINST 2258 GOTO_OPCODE ip @ jump to next instruction 2259 2260/* ------------------------------ */ 2261 .balign 128 2262.L_op_iget_wide: /* 0x53 */ 2263/* File: arm/op_iget_wide.S */ 2264 /* 2265 * 64-bit instance field get. 2266 * 2267 * for: iget-wide 2268 */ 2269 EXPORT_PC 2270 FETCH r0, 1 @ r0<- field ref CCCC 2271 mov r1, rINST, lsr #12 @ r1<- B 2272 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2273 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2274 mov r3, rSELF @ r3<- self 2275 bl artGet64InstanceFromCode 2276 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2277 ubfx r2, rINST, #8, #4 @ r2<- A 2278 PREFETCH_INST 2 2279 cmp r3, #0 2280 bne MterpException @ bail out 2281 CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs 2282 VREG_INDEX_TO_ADDR r3, r2 @ r3<- &fp[A] 2283 stmia r3, {r0-r1} @ fp[A]<- r0/r1 2284 ADVANCE 2 2285 GET_INST_OPCODE ip @ extract opcode from rINST 2286 GOTO_OPCODE ip @ jump to next instruction 2287 2288/* ------------------------------ */ 2289 .balign 128 2290.L_op_iget_object: /* 0x54 */ 2291/* File: arm/op_iget_object.S */ 2292/* File: arm/op_iget.S */ 2293 /* 2294 * General instance field get. 2295 * 2296 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2297 */ 2298 EXPORT_PC 2299 FETCH r0, 1 @ r0<- field ref CCCC 2300 mov r1, rINST, lsr #12 @ r1<- B 2301 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2302 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2303 mov r3, rSELF @ r3<- self 2304 bl artGetObjInstanceFromCode 2305 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2306 ubfx r2, rINST, #8, #4 @ r2<- A 2307 PREFETCH_INST 2 2308 cmp r3, #0 2309 bne MterpPossibleException @ bail out 2310 .if 1 2311 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2312 .else 2313 SET_VREG r0, r2 @ fp[A]<- r0 2314 .endif 2315 ADVANCE 2 2316 GET_INST_OPCODE ip @ extract opcode from rINST 2317 GOTO_OPCODE ip @ jump to next instruction 2318 2319 2320/* ------------------------------ */ 2321 .balign 128 2322.L_op_iget_boolean: /* 0x55 */ 2323/* File: arm/op_iget_boolean.S */ 2324/* File: arm/op_iget.S */ 2325 /* 2326 * General instance field get. 2327 * 2328 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2329 */ 2330 EXPORT_PC 2331 FETCH r0, 1 @ r0<- field ref CCCC 2332 mov r1, rINST, lsr #12 @ r1<- B 2333 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2334 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2335 mov r3, rSELF @ r3<- self 2336 bl artGetBooleanInstanceFromCode 2337 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2338 ubfx r2, rINST, #8, #4 @ r2<- A 2339 PREFETCH_INST 2 2340 cmp r3, #0 2341 bne MterpPossibleException @ bail out 2342 .if 0 2343 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2344 .else 2345 SET_VREG r0, r2 @ fp[A]<- r0 2346 .endif 2347 ADVANCE 2 2348 GET_INST_OPCODE ip @ extract opcode from rINST 2349 GOTO_OPCODE ip @ jump to next instruction 2350 2351 2352/* ------------------------------ */ 2353 .balign 128 2354.L_op_iget_byte: /* 0x56 */ 2355/* File: arm/op_iget_byte.S */ 2356/* File: arm/op_iget.S */ 2357 /* 2358 * General instance field get. 2359 * 2360 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2361 */ 2362 EXPORT_PC 2363 FETCH r0, 1 @ r0<- field ref CCCC 2364 mov r1, rINST, lsr #12 @ r1<- B 2365 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2366 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2367 mov r3, rSELF @ r3<- self 2368 bl artGetByteInstanceFromCode 2369 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2370 ubfx r2, rINST, #8, #4 @ r2<- A 2371 PREFETCH_INST 2 2372 cmp r3, #0 2373 bne MterpPossibleException @ bail out 2374 .if 0 2375 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2376 .else 2377 SET_VREG r0, r2 @ fp[A]<- r0 2378 .endif 2379 ADVANCE 2 2380 GET_INST_OPCODE ip @ extract opcode from rINST 2381 GOTO_OPCODE ip @ jump to next instruction 2382 2383 2384/* ------------------------------ */ 2385 .balign 128 2386.L_op_iget_char: /* 0x57 */ 2387/* File: arm/op_iget_char.S */ 2388/* File: arm/op_iget.S */ 2389 /* 2390 * General instance field get. 2391 * 2392 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2393 */ 2394 EXPORT_PC 2395 FETCH r0, 1 @ r0<- field ref CCCC 2396 mov r1, rINST, lsr #12 @ r1<- B 2397 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2398 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2399 mov r3, rSELF @ r3<- self 2400 bl artGetCharInstanceFromCode 2401 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2402 ubfx r2, rINST, #8, #4 @ r2<- A 2403 PREFETCH_INST 2 2404 cmp r3, #0 2405 bne MterpPossibleException @ bail out 2406 .if 0 2407 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2408 .else 2409 SET_VREG r0, r2 @ fp[A]<- r0 2410 .endif 2411 ADVANCE 2 2412 GET_INST_OPCODE ip @ extract opcode from rINST 2413 GOTO_OPCODE ip @ jump to next instruction 2414 2415 2416/* ------------------------------ */ 2417 .balign 128 2418.L_op_iget_short: /* 0x58 */ 2419/* File: arm/op_iget_short.S */ 2420/* File: arm/op_iget.S */ 2421 /* 2422 * General instance field get. 2423 * 2424 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2425 */ 2426 EXPORT_PC 2427 FETCH r0, 1 @ r0<- field ref CCCC 2428 mov r1, rINST, lsr #12 @ r1<- B 2429 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2430 ldr r2, [rFP, #OFF_FP_METHOD] @ r2<- referrer 2431 mov r3, rSELF @ r3<- self 2432 bl artGetShortInstanceFromCode 2433 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2434 ubfx r2, rINST, #8, #4 @ r2<- A 2435 PREFETCH_INST 2 2436 cmp r3, #0 2437 bne MterpPossibleException @ bail out 2438 .if 0 2439 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 2440 .else 2441 SET_VREG r0, r2 @ fp[A]<- r0 2442 .endif 2443 ADVANCE 2 2444 GET_INST_OPCODE ip @ extract opcode from rINST 2445 GOTO_OPCODE ip @ jump to next instruction 2446 2447 2448/* ------------------------------ */ 2449 .balign 128 2450.L_op_iput: /* 0x59 */ 2451/* File: arm/op_iput.S */ 2452 /* 2453 * General 32-bit instance field put. 2454 * 2455 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2456 */ 2457 /* op vA, vB, field@CCCC */ 2458 .extern artSet32InstanceFromMterp 2459 EXPORT_PC 2460 FETCH r0, 1 @ r0<- field ref CCCC 2461 mov r1, rINST, lsr #12 @ r1<- B 2462 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2463 ubfx r2, rINST, #8, #4 @ r2<- A 2464 GET_VREG r2, r2 @ r2<- fp[A] 2465 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2466 PREFETCH_INST 2 2467 bl artSet32InstanceFromMterp 2468 cmp r0, #0 2469 bne MterpPossibleException 2470 ADVANCE 2 @ advance rPC 2471 GET_INST_OPCODE ip @ extract opcode from rINST 2472 GOTO_OPCODE ip @ jump to next instruction 2473 2474/* ------------------------------ */ 2475 .balign 128 2476.L_op_iput_wide: /* 0x5a */ 2477/* File: arm/op_iput_wide.S */ 2478 /* iput-wide vA, vB, field@CCCC */ 2479 .extern artSet64InstanceFromMterp 2480 EXPORT_PC 2481 FETCH r0, 1 @ r0<- field ref CCCC 2482 mov r1, rINST, lsr #12 @ r1<- B 2483 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2484 ubfx r2, rINST, #8, #4 @ r2<- A 2485 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[A] 2486 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2487 PREFETCH_INST 2 2488 bl artSet64InstanceFromMterp 2489 cmp r0, #0 2490 bne MterpPossibleException 2491 ADVANCE 2 @ advance rPC 2492 GET_INST_OPCODE ip @ extract opcode from rINST 2493 GOTO_OPCODE ip @ jump to next instruction 2494 2495/* ------------------------------ */ 2496 .balign 128 2497.L_op_iput_object: /* 0x5b */ 2498/* File: arm/op_iput_object.S */ 2499 EXPORT_PC 2500 add r0, rFP, #OFF_FP_SHADOWFRAME 2501 mov r1, rPC 2502 mov r2, rINST 2503 mov r3, rSELF 2504 bl MterpIputObject 2505 cmp r0, #0 2506 beq MterpException 2507 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2508 GET_INST_OPCODE ip @ extract opcode from rINST 2509 GOTO_OPCODE ip @ jump to next instruction 2510 2511/* ------------------------------ */ 2512 .balign 128 2513.L_op_iput_boolean: /* 0x5c */ 2514/* File: arm/op_iput_boolean.S */ 2515/* File: arm/op_iput.S */ 2516 /* 2517 * General 32-bit instance field put. 2518 * 2519 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2520 */ 2521 /* op vA, vB, field@CCCC */ 2522 .extern artSet8InstanceFromMterp 2523 EXPORT_PC 2524 FETCH r0, 1 @ r0<- field ref CCCC 2525 mov r1, rINST, lsr #12 @ r1<- B 2526 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2527 ubfx r2, rINST, #8, #4 @ r2<- A 2528 GET_VREG r2, r2 @ r2<- fp[A] 2529 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2530 PREFETCH_INST 2 2531 bl artSet8InstanceFromMterp 2532 cmp r0, #0 2533 bne MterpPossibleException 2534 ADVANCE 2 @ advance rPC 2535 GET_INST_OPCODE ip @ extract opcode from rINST 2536 GOTO_OPCODE ip @ jump to next instruction 2537 2538 2539/* ------------------------------ */ 2540 .balign 128 2541.L_op_iput_byte: /* 0x5d */ 2542/* File: arm/op_iput_byte.S */ 2543/* File: arm/op_iput.S */ 2544 /* 2545 * General 32-bit instance field put. 2546 * 2547 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2548 */ 2549 /* op vA, vB, field@CCCC */ 2550 .extern artSet8InstanceFromMterp 2551 EXPORT_PC 2552 FETCH r0, 1 @ r0<- field ref CCCC 2553 mov r1, rINST, lsr #12 @ r1<- B 2554 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2555 ubfx r2, rINST, #8, #4 @ r2<- A 2556 GET_VREG r2, r2 @ r2<- fp[A] 2557 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2558 PREFETCH_INST 2 2559 bl artSet8InstanceFromMterp 2560 cmp r0, #0 2561 bne MterpPossibleException 2562 ADVANCE 2 @ advance rPC 2563 GET_INST_OPCODE ip @ extract opcode from rINST 2564 GOTO_OPCODE ip @ jump to next instruction 2565 2566 2567/* ------------------------------ */ 2568 .balign 128 2569.L_op_iput_char: /* 0x5e */ 2570/* File: arm/op_iput_char.S */ 2571/* File: arm/op_iput.S */ 2572 /* 2573 * General 32-bit instance field put. 2574 * 2575 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2576 */ 2577 /* op vA, vB, field@CCCC */ 2578 .extern artSet16InstanceFromMterp 2579 EXPORT_PC 2580 FETCH r0, 1 @ r0<- field ref CCCC 2581 mov r1, rINST, lsr #12 @ r1<- B 2582 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2583 ubfx r2, rINST, #8, #4 @ r2<- A 2584 GET_VREG r2, r2 @ r2<- fp[A] 2585 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2586 PREFETCH_INST 2 2587 bl artSet16InstanceFromMterp 2588 cmp r0, #0 2589 bne MterpPossibleException 2590 ADVANCE 2 @ advance rPC 2591 GET_INST_OPCODE ip @ extract opcode from rINST 2592 GOTO_OPCODE ip @ jump to next instruction 2593 2594 2595/* ------------------------------ */ 2596 .balign 128 2597.L_op_iput_short: /* 0x5f */ 2598/* File: arm/op_iput_short.S */ 2599/* File: arm/op_iput.S */ 2600 /* 2601 * General 32-bit instance field put. 2602 * 2603 * for: iput, iput-object, iput-boolean, iput-byte, iput-char, iput-short 2604 */ 2605 /* op vA, vB, field@CCCC */ 2606 .extern artSet16InstanceFromMterp 2607 EXPORT_PC 2608 FETCH r0, 1 @ r0<- field ref CCCC 2609 mov r1, rINST, lsr #12 @ r1<- B 2610 GET_VREG r1, r1 @ r1<- fp[B], the object pointer 2611 ubfx r2, rINST, #8, #4 @ r2<- A 2612 GET_VREG r2, r2 @ r2<- fp[A] 2613 ldr r3, [rFP, #OFF_FP_METHOD] @ r3<- referrer 2614 PREFETCH_INST 2 2615 bl artSet16InstanceFromMterp 2616 cmp r0, #0 2617 bne MterpPossibleException 2618 ADVANCE 2 @ advance rPC 2619 GET_INST_OPCODE ip @ extract opcode from rINST 2620 GOTO_OPCODE ip @ jump to next instruction 2621 2622 2623/* ------------------------------ */ 2624 .balign 128 2625.L_op_sget: /* 0x60 */ 2626/* File: arm/op_sget.S */ 2627 /* 2628 * General SGET handler wrapper. 2629 * 2630 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2631 */ 2632 /* op vAA, field@BBBB */ 2633 2634 .extern MterpGet32Static 2635 EXPORT_PC 2636 FETCH r0, 1 @ r0<- field ref BBBB 2637 ldr r1, [rFP, #OFF_FP_METHOD] 2638 mov r2, rSELF 2639 bl MterpGet32Static 2640 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2641 mov r2, rINST, lsr #8 @ r2<- AA 2642 PREFETCH_INST 2 2643 cmp r3, #0 @ Fail to resolve? 2644 bne MterpException @ bail out 2645.if 0 2646 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2647.else 2648 SET_VREG r0, r2 @ fp[AA]<- r0 2649.endif 2650 ADVANCE 2 2651 GET_INST_OPCODE ip @ extract opcode from rINST 2652 GOTO_OPCODE ip 2653 2654/* ------------------------------ */ 2655 .balign 128 2656.L_op_sget_wide: /* 0x61 */ 2657/* File: arm/op_sget_wide.S */ 2658 /* 2659 * SGET_WIDE handler wrapper. 2660 * 2661 */ 2662 /* sget-wide vAA, field@BBBB */ 2663 2664 .extern MterpGet64Static 2665 EXPORT_PC 2666 FETCH r0, 1 @ r0<- field ref BBBB 2667 ldr r1, [rFP, #OFF_FP_METHOD] 2668 mov r2, rSELF 2669 bl MterpGet64Static 2670 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2671 mov r9, rINST, lsr #8 @ r9<- AA 2672 VREG_INDEX_TO_ADDR lr, r9 @ r9<- &fp[AA] 2673 cmp r3, #0 @ Fail to resolve? 2674 bne MterpException @ bail out 2675 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2676 CLEAR_SHADOW_PAIR r9, r2, ip @ Zero out the shadow regs 2677 stmia lr, {r0-r1} @ vAA/vAA+1<- r0/r1 2678 GET_INST_OPCODE ip @ extract opcode from rINST 2679 GOTO_OPCODE ip @ jump to next instruction 2680 2681/* ------------------------------ */ 2682 .balign 128 2683.L_op_sget_object: /* 0x62 */ 2684/* File: arm/op_sget_object.S */ 2685/* File: arm/op_sget.S */ 2686 /* 2687 * General SGET handler wrapper. 2688 * 2689 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2690 */ 2691 /* op vAA, field@BBBB */ 2692 2693 .extern MterpGetObjStatic 2694 EXPORT_PC 2695 FETCH r0, 1 @ r0<- field ref BBBB 2696 ldr r1, [rFP, #OFF_FP_METHOD] 2697 mov r2, rSELF 2698 bl MterpGetObjStatic 2699 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2700 mov r2, rINST, lsr #8 @ r2<- AA 2701 PREFETCH_INST 2 2702 cmp r3, #0 @ Fail to resolve? 2703 bne MterpException @ bail out 2704.if 1 2705 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2706.else 2707 SET_VREG r0, r2 @ fp[AA]<- r0 2708.endif 2709 ADVANCE 2 2710 GET_INST_OPCODE ip @ extract opcode from rINST 2711 GOTO_OPCODE ip 2712 2713 2714/* ------------------------------ */ 2715 .balign 128 2716.L_op_sget_boolean: /* 0x63 */ 2717/* File: arm/op_sget_boolean.S */ 2718/* File: arm/op_sget.S */ 2719 /* 2720 * General SGET handler wrapper. 2721 * 2722 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2723 */ 2724 /* op vAA, field@BBBB */ 2725 2726 .extern MterpGetBooleanStatic 2727 EXPORT_PC 2728 FETCH r0, 1 @ r0<- field ref BBBB 2729 ldr r1, [rFP, #OFF_FP_METHOD] 2730 mov r2, rSELF 2731 bl MterpGetBooleanStatic 2732 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2733 mov r2, rINST, lsr #8 @ r2<- AA 2734 PREFETCH_INST 2 2735 cmp r3, #0 @ Fail to resolve? 2736 bne MterpException @ bail out 2737.if 0 2738 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2739.else 2740 SET_VREG r0, r2 @ fp[AA]<- r0 2741.endif 2742 ADVANCE 2 2743 GET_INST_OPCODE ip @ extract opcode from rINST 2744 GOTO_OPCODE ip 2745 2746 2747/* ------------------------------ */ 2748 .balign 128 2749.L_op_sget_byte: /* 0x64 */ 2750/* File: arm/op_sget_byte.S */ 2751/* File: arm/op_sget.S */ 2752 /* 2753 * General SGET handler wrapper. 2754 * 2755 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2756 */ 2757 /* op vAA, field@BBBB */ 2758 2759 .extern MterpGetByteStatic 2760 EXPORT_PC 2761 FETCH r0, 1 @ r0<- field ref BBBB 2762 ldr r1, [rFP, #OFF_FP_METHOD] 2763 mov r2, rSELF 2764 bl MterpGetByteStatic 2765 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2766 mov r2, rINST, lsr #8 @ r2<- AA 2767 PREFETCH_INST 2 2768 cmp r3, #0 @ Fail to resolve? 2769 bne MterpException @ bail out 2770.if 0 2771 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2772.else 2773 SET_VREG r0, r2 @ fp[AA]<- r0 2774.endif 2775 ADVANCE 2 2776 GET_INST_OPCODE ip @ extract opcode from rINST 2777 GOTO_OPCODE ip 2778 2779 2780/* ------------------------------ */ 2781 .balign 128 2782.L_op_sget_char: /* 0x65 */ 2783/* File: arm/op_sget_char.S */ 2784/* File: arm/op_sget.S */ 2785 /* 2786 * General SGET handler wrapper. 2787 * 2788 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2789 */ 2790 /* op vAA, field@BBBB */ 2791 2792 .extern MterpGetCharStatic 2793 EXPORT_PC 2794 FETCH r0, 1 @ r0<- field ref BBBB 2795 ldr r1, [rFP, #OFF_FP_METHOD] 2796 mov r2, rSELF 2797 bl MterpGetCharStatic 2798 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2799 mov r2, rINST, lsr #8 @ r2<- AA 2800 PREFETCH_INST 2 2801 cmp r3, #0 @ Fail to resolve? 2802 bne MterpException @ bail out 2803.if 0 2804 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2805.else 2806 SET_VREG r0, r2 @ fp[AA]<- r0 2807.endif 2808 ADVANCE 2 2809 GET_INST_OPCODE ip @ extract opcode from rINST 2810 GOTO_OPCODE ip 2811 2812 2813/* ------------------------------ */ 2814 .balign 128 2815.L_op_sget_short: /* 0x66 */ 2816/* File: arm/op_sget_short.S */ 2817/* File: arm/op_sget.S */ 2818 /* 2819 * General SGET handler wrapper. 2820 * 2821 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2822 */ 2823 /* op vAA, field@BBBB */ 2824 2825 .extern MterpGetShortStatic 2826 EXPORT_PC 2827 FETCH r0, 1 @ r0<- field ref BBBB 2828 ldr r1, [rFP, #OFF_FP_METHOD] 2829 mov r2, rSELF 2830 bl MterpGetShortStatic 2831 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 2832 mov r2, rINST, lsr #8 @ r2<- AA 2833 PREFETCH_INST 2 2834 cmp r3, #0 @ Fail to resolve? 2835 bne MterpException @ bail out 2836.if 0 2837 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0 2838.else 2839 SET_VREG r0, r2 @ fp[AA]<- r0 2840.endif 2841 ADVANCE 2 2842 GET_INST_OPCODE ip @ extract opcode from rINST 2843 GOTO_OPCODE ip 2844 2845 2846/* ------------------------------ */ 2847 .balign 128 2848.L_op_sput: /* 0x67 */ 2849/* File: arm/op_sput.S */ 2850 /* 2851 * General SPUT handler wrapper. 2852 * 2853 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2854 */ 2855 /* op vAA, field@BBBB */ 2856 EXPORT_PC 2857 FETCH r0, 1 @ r0<- field ref BBBB 2858 mov r3, rINST, lsr #8 @ r3<- AA 2859 GET_VREG r1, r3 @ r1<= fp[AA] 2860 ldr r2, [rFP, #OFF_FP_METHOD] 2861 mov r3, rSELF 2862 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 2863 bl MterpSet32Static 2864 cmp r0, #0 @ 0 on success, -1 on failure 2865 bne MterpException 2866 ADVANCE 2 @ Past exception point - now advance rPC 2867 GET_INST_OPCODE ip @ extract opcode from rINST 2868 GOTO_OPCODE ip @ jump to next instruction 2869 2870/* ------------------------------ */ 2871 .balign 128 2872.L_op_sput_wide: /* 0x68 */ 2873/* File: arm/op_sput_wide.S */ 2874 /* 2875 * SPUT_WIDE handler wrapper. 2876 * 2877 */ 2878 /* sput-wide vAA, field@BBBB */ 2879 .extern MterpSet64Static 2880 EXPORT_PC 2881 FETCH r0, 1 @ r0<- field ref BBBB 2882 mov r1, rINST, lsr #8 @ r1<- AA 2883 VREG_INDEX_TO_ADDR r1, r1 2884 ldr r2, [rFP, #OFF_FP_METHOD] 2885 mov r3, rSELF 2886 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 2887 bl MterpSet64Static 2888 cmp r0, #0 @ 0 on success, -1 on failure 2889 bne MterpException 2890 ADVANCE 2 @ Past exception point - now advance rPC 2891 GET_INST_OPCODE ip @ extract opcode from rINST 2892 GOTO_OPCODE ip @ jump to next instruction 2893 2894/* ------------------------------ */ 2895 .balign 128 2896.L_op_sput_object: /* 0x69 */ 2897/* File: arm/op_sput_object.S */ 2898 EXPORT_PC 2899 add r0, rFP, #OFF_FP_SHADOWFRAME 2900 mov r1, rPC 2901 mov r2, rINST 2902 mov r3, rSELF 2903 bl MterpSputObject 2904 cmp r0, #0 2905 beq MterpException 2906 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 2907 GET_INST_OPCODE ip @ extract opcode from rINST 2908 GOTO_OPCODE ip @ jump to next instruction 2909 2910/* ------------------------------ */ 2911 .balign 128 2912.L_op_sput_boolean: /* 0x6a */ 2913/* File: arm/op_sput_boolean.S */ 2914/* File: arm/op_sput.S */ 2915 /* 2916 * General SPUT handler wrapper. 2917 * 2918 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2919 */ 2920 /* op vAA, field@BBBB */ 2921 EXPORT_PC 2922 FETCH r0, 1 @ r0<- field ref BBBB 2923 mov r3, rINST, lsr #8 @ r3<- AA 2924 GET_VREG r1, r3 @ r1<= fp[AA] 2925 ldr r2, [rFP, #OFF_FP_METHOD] 2926 mov r3, rSELF 2927 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 2928 bl MterpSetBooleanStatic 2929 cmp r0, #0 @ 0 on success, -1 on failure 2930 bne MterpException 2931 ADVANCE 2 @ Past exception point - now advance rPC 2932 GET_INST_OPCODE ip @ extract opcode from rINST 2933 GOTO_OPCODE ip @ jump to next instruction 2934 2935 2936/* ------------------------------ */ 2937 .balign 128 2938.L_op_sput_byte: /* 0x6b */ 2939/* File: arm/op_sput_byte.S */ 2940/* File: arm/op_sput.S */ 2941 /* 2942 * General SPUT handler wrapper. 2943 * 2944 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2945 */ 2946 /* op vAA, field@BBBB */ 2947 EXPORT_PC 2948 FETCH r0, 1 @ r0<- field ref BBBB 2949 mov r3, rINST, lsr #8 @ r3<- AA 2950 GET_VREG r1, r3 @ r1<= fp[AA] 2951 ldr r2, [rFP, #OFF_FP_METHOD] 2952 mov r3, rSELF 2953 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 2954 bl MterpSetByteStatic 2955 cmp r0, #0 @ 0 on success, -1 on failure 2956 bne MterpException 2957 ADVANCE 2 @ Past exception point - now advance rPC 2958 GET_INST_OPCODE ip @ extract opcode from rINST 2959 GOTO_OPCODE ip @ jump to next instruction 2960 2961 2962/* ------------------------------ */ 2963 .balign 128 2964.L_op_sput_char: /* 0x6c */ 2965/* File: arm/op_sput_char.S */ 2966/* File: arm/op_sput.S */ 2967 /* 2968 * General SPUT handler wrapper. 2969 * 2970 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2971 */ 2972 /* op vAA, field@BBBB */ 2973 EXPORT_PC 2974 FETCH r0, 1 @ r0<- field ref BBBB 2975 mov r3, rINST, lsr #8 @ r3<- AA 2976 GET_VREG r1, r3 @ r1<= fp[AA] 2977 ldr r2, [rFP, #OFF_FP_METHOD] 2978 mov r3, rSELF 2979 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 2980 bl MterpSetCharStatic 2981 cmp r0, #0 @ 0 on success, -1 on failure 2982 bne MterpException 2983 ADVANCE 2 @ Past exception point - now advance rPC 2984 GET_INST_OPCODE ip @ extract opcode from rINST 2985 GOTO_OPCODE ip @ jump to next instruction 2986 2987 2988/* ------------------------------ */ 2989 .balign 128 2990.L_op_sput_short: /* 0x6d */ 2991/* File: arm/op_sput_short.S */ 2992/* File: arm/op_sput.S */ 2993 /* 2994 * General SPUT handler wrapper. 2995 * 2996 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2997 */ 2998 /* op vAA, field@BBBB */ 2999 EXPORT_PC 3000 FETCH r0, 1 @ r0<- field ref BBBB 3001 mov r3, rINST, lsr #8 @ r3<- AA 3002 GET_VREG r1, r3 @ r1<= fp[AA] 3003 ldr r2, [rFP, #OFF_FP_METHOD] 3004 mov r3, rSELF 3005 PREFETCH_INST 2 @ Get next inst, but don't advance rPC 3006 bl MterpSetShortStatic 3007 cmp r0, #0 @ 0 on success, -1 on failure 3008 bne MterpException 3009 ADVANCE 2 @ Past exception point - now advance rPC 3010 GET_INST_OPCODE ip @ extract opcode from rINST 3011 GOTO_OPCODE ip @ jump to next instruction 3012 3013 3014/* ------------------------------ */ 3015 .balign 128 3016.L_op_invoke_virtual: /* 0x6e */ 3017/* File: arm/op_invoke_virtual.S */ 3018/* File: arm/invoke.S */ 3019 /* 3020 * Generic invoke handler wrapper. 3021 */ 3022 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3023 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3024 .extern MterpInvokeVirtual 3025 EXPORT_PC 3026 mov r0, rSELF 3027 add r1, rFP, #OFF_FP_SHADOWFRAME 3028 mov r2, rPC 3029 mov r3, rINST 3030 bl MterpInvokeVirtual 3031 cmp r0, #0 3032 beq MterpException 3033 FETCH_ADVANCE_INST 3 3034 bl MterpShouldSwitchInterpreters 3035 cmp r0, #0 3036 bne MterpFallback 3037 GET_INST_OPCODE ip 3038 GOTO_OPCODE ip 3039 3040 3041 /* 3042 * Handle a virtual method call. 3043 * 3044 * for: invoke-virtual, invoke-virtual/range 3045 */ 3046 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3047 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3048 3049/* ------------------------------ */ 3050 .balign 128 3051.L_op_invoke_super: /* 0x6f */ 3052/* File: arm/op_invoke_super.S */ 3053/* File: arm/invoke.S */ 3054 /* 3055 * Generic invoke handler wrapper. 3056 */ 3057 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3058 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3059 .extern MterpInvokeSuper 3060 EXPORT_PC 3061 mov r0, rSELF 3062 add r1, rFP, #OFF_FP_SHADOWFRAME 3063 mov r2, rPC 3064 mov r3, rINST 3065 bl MterpInvokeSuper 3066 cmp r0, #0 3067 beq MterpException 3068 FETCH_ADVANCE_INST 3 3069 bl MterpShouldSwitchInterpreters 3070 cmp r0, #0 3071 bne MterpFallback 3072 GET_INST_OPCODE ip 3073 GOTO_OPCODE ip 3074 3075 3076 /* 3077 * Handle a "super" method call. 3078 * 3079 * for: invoke-super, invoke-super/range 3080 */ 3081 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3082 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3083 3084/* ------------------------------ */ 3085 .balign 128 3086.L_op_invoke_direct: /* 0x70 */ 3087/* File: arm/op_invoke_direct.S */ 3088/* File: arm/invoke.S */ 3089 /* 3090 * Generic invoke handler wrapper. 3091 */ 3092 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3093 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3094 .extern MterpInvokeDirect 3095 EXPORT_PC 3096 mov r0, rSELF 3097 add r1, rFP, #OFF_FP_SHADOWFRAME 3098 mov r2, rPC 3099 mov r3, rINST 3100 bl MterpInvokeDirect 3101 cmp r0, #0 3102 beq MterpException 3103 FETCH_ADVANCE_INST 3 3104 bl MterpShouldSwitchInterpreters 3105 cmp r0, #0 3106 bne MterpFallback 3107 GET_INST_OPCODE ip 3108 GOTO_OPCODE ip 3109 3110 3111 3112/* ------------------------------ */ 3113 .balign 128 3114.L_op_invoke_static: /* 0x71 */ 3115/* File: arm/op_invoke_static.S */ 3116/* File: arm/invoke.S */ 3117 /* 3118 * Generic invoke handler wrapper. 3119 */ 3120 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3121 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3122 .extern MterpInvokeStatic 3123 EXPORT_PC 3124 mov r0, rSELF 3125 add r1, rFP, #OFF_FP_SHADOWFRAME 3126 mov r2, rPC 3127 mov r3, rINST 3128 bl MterpInvokeStatic 3129 cmp r0, #0 3130 beq MterpException 3131 FETCH_ADVANCE_INST 3 3132 bl MterpShouldSwitchInterpreters 3133 cmp r0, #0 3134 bne MterpFallback 3135 GET_INST_OPCODE ip 3136 GOTO_OPCODE ip 3137 3138 3139 3140 3141/* ------------------------------ */ 3142 .balign 128 3143.L_op_invoke_interface: /* 0x72 */ 3144/* File: arm/op_invoke_interface.S */ 3145/* File: arm/invoke.S */ 3146 /* 3147 * Generic invoke handler wrapper. 3148 */ 3149 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3150 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3151 .extern MterpInvokeInterface 3152 EXPORT_PC 3153 mov r0, rSELF 3154 add r1, rFP, #OFF_FP_SHADOWFRAME 3155 mov r2, rPC 3156 mov r3, rINST 3157 bl MterpInvokeInterface 3158 cmp r0, #0 3159 beq MterpException 3160 FETCH_ADVANCE_INST 3 3161 bl MterpShouldSwitchInterpreters 3162 cmp r0, #0 3163 bne MterpFallback 3164 GET_INST_OPCODE ip 3165 GOTO_OPCODE ip 3166 3167 3168 /* 3169 * Handle an interface method call. 3170 * 3171 * for: invoke-interface, invoke-interface/range 3172 */ 3173 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3174 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3175 3176/* ------------------------------ */ 3177 .balign 128 3178.L_op_return_void_no_barrier: /* 0x73 */ 3179/* File: arm/op_return_void_no_barrier.S */ 3180 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 3181 mov r0, rSELF 3182 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 3183 blne MterpSuspendCheck @ (self) 3184 mov r0, #0 3185 mov r1, #0 3186 b MterpReturn 3187 3188/* ------------------------------ */ 3189 .balign 128 3190.L_op_invoke_virtual_range: /* 0x74 */ 3191/* File: arm/op_invoke_virtual_range.S */ 3192/* File: arm/invoke.S */ 3193 /* 3194 * Generic invoke handler wrapper. 3195 */ 3196 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3197 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3198 .extern MterpInvokeVirtualRange 3199 EXPORT_PC 3200 mov r0, rSELF 3201 add r1, rFP, #OFF_FP_SHADOWFRAME 3202 mov r2, rPC 3203 mov r3, rINST 3204 bl MterpInvokeVirtualRange 3205 cmp r0, #0 3206 beq MterpException 3207 FETCH_ADVANCE_INST 3 3208 bl MterpShouldSwitchInterpreters 3209 cmp r0, #0 3210 bne MterpFallback 3211 GET_INST_OPCODE ip 3212 GOTO_OPCODE ip 3213 3214 3215 3216/* ------------------------------ */ 3217 .balign 128 3218.L_op_invoke_super_range: /* 0x75 */ 3219/* File: arm/op_invoke_super_range.S */ 3220/* File: arm/invoke.S */ 3221 /* 3222 * Generic invoke handler wrapper. 3223 */ 3224 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3225 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3226 .extern MterpInvokeSuperRange 3227 EXPORT_PC 3228 mov r0, rSELF 3229 add r1, rFP, #OFF_FP_SHADOWFRAME 3230 mov r2, rPC 3231 mov r3, rINST 3232 bl MterpInvokeSuperRange 3233 cmp r0, #0 3234 beq MterpException 3235 FETCH_ADVANCE_INST 3 3236 bl MterpShouldSwitchInterpreters 3237 cmp r0, #0 3238 bne MterpFallback 3239 GET_INST_OPCODE ip 3240 GOTO_OPCODE ip 3241 3242 3243 3244/* ------------------------------ */ 3245 .balign 128 3246.L_op_invoke_direct_range: /* 0x76 */ 3247/* File: arm/op_invoke_direct_range.S */ 3248/* File: arm/invoke.S */ 3249 /* 3250 * Generic invoke handler wrapper. 3251 */ 3252 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3253 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3254 .extern MterpInvokeDirectRange 3255 EXPORT_PC 3256 mov r0, rSELF 3257 add r1, rFP, #OFF_FP_SHADOWFRAME 3258 mov r2, rPC 3259 mov r3, rINST 3260 bl MterpInvokeDirectRange 3261 cmp r0, #0 3262 beq MterpException 3263 FETCH_ADVANCE_INST 3 3264 bl MterpShouldSwitchInterpreters 3265 cmp r0, #0 3266 bne MterpFallback 3267 GET_INST_OPCODE ip 3268 GOTO_OPCODE ip 3269 3270 3271 3272/* ------------------------------ */ 3273 .balign 128 3274.L_op_invoke_static_range: /* 0x77 */ 3275/* File: arm/op_invoke_static_range.S */ 3276/* File: arm/invoke.S */ 3277 /* 3278 * Generic invoke handler wrapper. 3279 */ 3280 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3281 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3282 .extern MterpInvokeStaticRange 3283 EXPORT_PC 3284 mov r0, rSELF 3285 add r1, rFP, #OFF_FP_SHADOWFRAME 3286 mov r2, rPC 3287 mov r3, rINST 3288 bl MterpInvokeStaticRange 3289 cmp r0, #0 3290 beq MterpException 3291 FETCH_ADVANCE_INST 3 3292 bl MterpShouldSwitchInterpreters 3293 cmp r0, #0 3294 bne MterpFallback 3295 GET_INST_OPCODE ip 3296 GOTO_OPCODE ip 3297 3298 3299 3300/* ------------------------------ */ 3301 .balign 128 3302.L_op_invoke_interface_range: /* 0x78 */ 3303/* File: arm/op_invoke_interface_range.S */ 3304/* File: arm/invoke.S */ 3305 /* 3306 * Generic invoke handler wrapper. 3307 */ 3308 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3309 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3310 .extern MterpInvokeInterfaceRange 3311 EXPORT_PC 3312 mov r0, rSELF 3313 add r1, rFP, #OFF_FP_SHADOWFRAME 3314 mov r2, rPC 3315 mov r3, rINST 3316 bl MterpInvokeInterfaceRange 3317 cmp r0, #0 3318 beq MterpException 3319 FETCH_ADVANCE_INST 3 3320 bl MterpShouldSwitchInterpreters 3321 cmp r0, #0 3322 bne MterpFallback 3323 GET_INST_OPCODE ip 3324 GOTO_OPCODE ip 3325 3326 3327 3328/* ------------------------------ */ 3329 .balign 128 3330.L_op_unused_79: /* 0x79 */ 3331/* File: arm/op_unused_79.S */ 3332/* File: arm/unused.S */ 3333/* 3334 * Bail to reference interpreter to throw. 3335 */ 3336 b MterpFallback 3337 3338 3339/* ------------------------------ */ 3340 .balign 128 3341.L_op_unused_7a: /* 0x7a */ 3342/* File: arm/op_unused_7a.S */ 3343/* File: arm/unused.S */ 3344/* 3345 * Bail to reference interpreter to throw. 3346 */ 3347 b MterpFallback 3348 3349 3350/* ------------------------------ */ 3351 .balign 128 3352.L_op_neg_int: /* 0x7b */ 3353/* File: arm/op_neg_int.S */ 3354/* File: arm/unop.S */ 3355 /* 3356 * Generic 32-bit unary operation. Provide an "instr" line that 3357 * specifies an instruction that performs "result = op r0". 3358 * This could be an ARM instruction or a function call. 3359 * 3360 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3361 * int-to-byte, int-to-char, int-to-short 3362 */ 3363 /* unop vA, vB */ 3364 mov r3, rINST, lsr #12 @ r3<- B 3365 ubfx r9, rINST, #8, #4 @ r9<- A 3366 GET_VREG r0, r3 @ r0<- vB 3367 @ optional op; may set condition codes 3368 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3369 rsb r0, r0, #0 @ r0<- op, r0-r3 changed 3370 GET_INST_OPCODE ip @ extract opcode from rINST 3371 SET_VREG r0, r9 @ vAA<- r0 3372 GOTO_OPCODE ip @ jump to next instruction 3373 /* 8-9 instructions */ 3374 3375 3376/* ------------------------------ */ 3377 .balign 128 3378.L_op_not_int: /* 0x7c */ 3379/* File: arm/op_not_int.S */ 3380/* File: arm/unop.S */ 3381 /* 3382 * Generic 32-bit unary operation. Provide an "instr" line that 3383 * specifies an instruction that performs "result = op r0". 3384 * This could be an ARM instruction or a function call. 3385 * 3386 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3387 * int-to-byte, int-to-char, int-to-short 3388 */ 3389 /* unop vA, vB */ 3390 mov r3, rINST, lsr #12 @ r3<- B 3391 ubfx r9, rINST, #8, #4 @ r9<- A 3392 GET_VREG r0, r3 @ r0<- vB 3393 @ optional op; may set condition codes 3394 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3395 mvn r0, r0 @ r0<- op, r0-r3 changed 3396 GET_INST_OPCODE ip @ extract opcode from rINST 3397 SET_VREG r0, r9 @ vAA<- r0 3398 GOTO_OPCODE ip @ jump to next instruction 3399 /* 8-9 instructions */ 3400 3401 3402/* ------------------------------ */ 3403 .balign 128 3404.L_op_neg_long: /* 0x7d */ 3405/* File: arm/op_neg_long.S */ 3406/* File: arm/unopWide.S */ 3407 /* 3408 * Generic 64-bit unary operation. Provide an "instr" line that 3409 * specifies an instruction that performs "result = op r0/r1". 3410 * This could be an ARM instruction or a function call. 3411 * 3412 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3413 */ 3414 /* unop vA, vB */ 3415 mov r3, rINST, lsr #12 @ r3<- B 3416 ubfx rINST, rINST, #8, #4 @ rINST<- A 3417 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3418 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3419 ldmia r3, {r0-r1} @ r0/r1<- vAA 3420 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3421 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3422 rsbs r0, r0, #0 @ optional op; may set condition codes 3423 rsc r1, r1, #0 @ r0/r1<- op, r2-r3 changed 3424 GET_INST_OPCODE ip @ extract opcode from rINST 3425 stmia r9, {r0-r1} @ vAA<- r0/r1 3426 GOTO_OPCODE ip @ jump to next instruction 3427 /* 10-11 instructions */ 3428 3429 3430/* ------------------------------ */ 3431 .balign 128 3432.L_op_not_long: /* 0x7e */ 3433/* File: arm/op_not_long.S */ 3434/* File: arm/unopWide.S */ 3435 /* 3436 * Generic 64-bit unary operation. Provide an "instr" line that 3437 * specifies an instruction that performs "result = op r0/r1". 3438 * This could be an ARM instruction or a function call. 3439 * 3440 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3441 */ 3442 /* unop vA, vB */ 3443 mov r3, rINST, lsr #12 @ r3<- B 3444 ubfx rINST, rINST, #8, #4 @ rINST<- A 3445 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3446 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3447 ldmia r3, {r0-r1} @ r0/r1<- vAA 3448 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3449 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3450 mvn r0, r0 @ optional op; may set condition codes 3451 mvn r1, r1 @ r0/r1<- op, r2-r3 changed 3452 GET_INST_OPCODE ip @ extract opcode from rINST 3453 stmia r9, {r0-r1} @ vAA<- r0/r1 3454 GOTO_OPCODE ip @ jump to next instruction 3455 /* 10-11 instructions */ 3456 3457 3458/* ------------------------------ */ 3459 .balign 128 3460.L_op_neg_float: /* 0x7f */ 3461/* File: arm/op_neg_float.S */ 3462/* File: arm/unop.S */ 3463 /* 3464 * Generic 32-bit unary operation. Provide an "instr" line that 3465 * specifies an instruction that performs "result = op r0". 3466 * This could be an ARM instruction or a function call. 3467 * 3468 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3469 * int-to-byte, int-to-char, int-to-short 3470 */ 3471 /* unop vA, vB */ 3472 mov r3, rINST, lsr #12 @ r3<- B 3473 ubfx r9, rINST, #8, #4 @ r9<- A 3474 GET_VREG r0, r3 @ r0<- vB 3475 @ optional op; may set condition codes 3476 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3477 add r0, r0, #0x80000000 @ r0<- op, r0-r3 changed 3478 GET_INST_OPCODE ip @ extract opcode from rINST 3479 SET_VREG r0, r9 @ vAA<- r0 3480 GOTO_OPCODE ip @ jump to next instruction 3481 /* 8-9 instructions */ 3482 3483 3484/* ------------------------------ */ 3485 .balign 128 3486.L_op_neg_double: /* 0x80 */ 3487/* File: arm/op_neg_double.S */ 3488/* File: arm/unopWide.S */ 3489 /* 3490 * Generic 64-bit unary operation. Provide an "instr" line that 3491 * specifies an instruction that performs "result = op r0/r1". 3492 * This could be an ARM instruction or a function call. 3493 * 3494 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3495 */ 3496 /* unop vA, vB */ 3497 mov r3, rINST, lsr #12 @ r3<- B 3498 ubfx rINST, rINST, #8, #4 @ rINST<- A 3499 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3500 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3501 ldmia r3, {r0-r1} @ r0/r1<- vAA 3502 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3503 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3504 @ optional op; may set condition codes 3505 add r1, r1, #0x80000000 @ r0/r1<- op, r2-r3 changed 3506 GET_INST_OPCODE ip @ extract opcode from rINST 3507 stmia r9, {r0-r1} @ vAA<- r0/r1 3508 GOTO_OPCODE ip @ jump to next instruction 3509 /* 10-11 instructions */ 3510 3511 3512/* ------------------------------ */ 3513 .balign 128 3514.L_op_int_to_long: /* 0x81 */ 3515/* File: arm/op_int_to_long.S */ 3516/* File: arm/unopWider.S */ 3517 /* 3518 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3519 * that specifies an instruction that performs "result = op r0", where 3520 * "result" is a 64-bit quantity in r0/r1. 3521 * 3522 * For: int-to-long, int-to-double, float-to-long, float-to-double 3523 */ 3524 /* unop vA, vB */ 3525 mov r3, rINST, lsr #12 @ r3<- B 3526 ubfx rINST, rINST, #8, #4 @ rINST<- A 3527 GET_VREG r0, r3 @ r0<- vB 3528 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3529 @ optional op; may set condition codes 3530 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3531 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3532 mov r1, r0, asr #31 @ r0<- op, r0-r3 changed 3533 GET_INST_OPCODE ip @ extract opcode from rINST 3534 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3535 GOTO_OPCODE ip @ jump to next instruction 3536 /* 9-10 instructions */ 3537 3538 3539/* ------------------------------ */ 3540 .balign 128 3541.L_op_int_to_float: /* 0x82 */ 3542/* File: arm/op_int_to_float.S */ 3543/* File: arm/funop.S */ 3544 /* 3545 * Generic 32-bit unary floating-point operation. Provide an "instr" 3546 * line that specifies an instruction that performs "s1 = op s0". 3547 * 3548 * for: int-to-float, float-to-int 3549 */ 3550 /* unop vA, vB */ 3551 mov r3, rINST, lsr #12 @ r3<- B 3552 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3553 flds s0, [r3] @ s0<- vB 3554 ubfx r9, rINST, #8, #4 @ r9<- A 3555 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3556 fsitos s1, s0 @ s1<- op 3557 GET_INST_OPCODE ip @ extract opcode from rINST 3558 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3559 fsts s1, [r9] @ vA<- s1 3560 GOTO_OPCODE ip @ jump to next instruction 3561 3562 3563/* ------------------------------ */ 3564 .balign 128 3565.L_op_int_to_double: /* 0x83 */ 3566/* File: arm/op_int_to_double.S */ 3567/* File: arm/funopWider.S */ 3568 /* 3569 * Generic 32bit-to-64bit floating point unary operation. Provide an 3570 * "instr" line that specifies an instruction that performs "d0 = op s0". 3571 * 3572 * For: int-to-double, float-to-double 3573 */ 3574 /* unop vA, vB */ 3575 mov r3, rINST, lsr #12 @ r3<- B 3576 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3577 flds s0, [r3] @ s0<- vB 3578 ubfx r9, rINST, #8, #4 @ r9<- A 3579 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3580 fsitod d0, s0 @ d0<- op 3581 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 3582 GET_INST_OPCODE ip @ extract opcode from rINST 3583 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3584 fstd d0, [r9] @ vA<- d0 3585 GOTO_OPCODE ip @ jump to next instruction 3586 3587 3588/* ------------------------------ */ 3589 .balign 128 3590.L_op_long_to_int: /* 0x84 */ 3591/* File: arm/op_long_to_int.S */ 3592/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3593/* File: arm/op_move.S */ 3594 /* for move, move-object, long-to-int */ 3595 /* op vA, vB */ 3596 mov r1, rINST, lsr #12 @ r1<- B from 15:12 3597 ubfx r0, rINST, #8, #4 @ r0<- A from 11:8 3598 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3599 GET_VREG r2, r1 @ r2<- fp[B] 3600 GET_INST_OPCODE ip @ ip<- opcode from rINST 3601 .if 0 3602 SET_VREG_OBJECT r2, r0 @ fp[A]<- r2 3603 .else 3604 SET_VREG r2, r0 @ fp[A]<- r2 3605 .endif 3606 GOTO_OPCODE ip @ execute next instruction 3607 3608 3609/* ------------------------------ */ 3610 .balign 128 3611.L_op_long_to_float: /* 0x85 */ 3612/* File: arm/op_long_to_float.S */ 3613/* File: arm/unopNarrower.S */ 3614 /* 3615 * Generic 64bit-to-32bit unary operation. Provide an "instr" line 3616 * that specifies an instruction that performs "result = op r0/r1", where 3617 * "result" is a 32-bit quantity in r0. 3618 * 3619 * For: long-to-float, double-to-int, double-to-float 3620 * 3621 * (This would work for long-to-int, but that instruction is actually 3622 * an exact match for op_move.) 3623 */ 3624 /* unop vA, vB */ 3625 mov r3, rINST, lsr #12 @ r3<- B 3626 ubfx r9, rINST, #8, #4 @ r9<- A 3627 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3628 ldmia r3, {r0-r1} @ r0/r1<- vB/vB+1 3629 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3630 @ optional op; may set condition codes 3631 bl __aeabi_l2f @ r0<- op, r0-r3 changed 3632 GET_INST_OPCODE ip @ extract opcode from rINST 3633 SET_VREG r0, r9 @ vA<- r0 3634 GOTO_OPCODE ip @ jump to next instruction 3635 /* 9-10 instructions */ 3636 3637 3638/* ------------------------------ */ 3639 .balign 128 3640.L_op_long_to_double: /* 0x86 */ 3641/* File: arm/op_long_to_double.S */ 3642 /* 3643 * Specialised 64-bit floating point operation. 3644 * 3645 * Note: The result will be returned in d2. 3646 * 3647 * For: long-to-double 3648 */ 3649 mov r3, rINST, lsr #12 @ r3<- B 3650 ubfx r9, rINST, #8, #4 @ r9<- A 3651 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3652 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] 3653 vldr d0, [r3] @ d0<- vAA 3654 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3655 3656 vcvt.f64.s32 d1, s1 @ d1<- (double)(vAAh) 3657 vcvt.f64.u32 d2, s0 @ d2<- (double)(vAAl) 3658 vldr d3, constvalop_long_to_double 3659 vmla.f64 d2, d1, d3 @ d2<- vAAh*2^32 + vAAl 3660 3661 GET_INST_OPCODE ip @ extract opcode from rINST 3662 vstr.64 d2, [r9] @ vAA<- d2 3663 GOTO_OPCODE ip @ jump to next instruction 3664 3665 /* literal pool helper */ 3666constvalop_long_to_double: 3667 .8byte 0x41f0000000000000 3668 3669/* ------------------------------ */ 3670 .balign 128 3671.L_op_float_to_int: /* 0x87 */ 3672/* File: arm/op_float_to_int.S */ 3673/* File: arm/funop.S */ 3674 /* 3675 * Generic 32-bit unary floating-point operation. Provide an "instr" 3676 * line that specifies an instruction that performs "s1 = op s0". 3677 * 3678 * for: int-to-float, float-to-int 3679 */ 3680 /* unop vA, vB */ 3681 mov r3, rINST, lsr #12 @ r3<- B 3682 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3683 flds s0, [r3] @ s0<- vB 3684 ubfx r9, rINST, #8, #4 @ r9<- A 3685 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3686 ftosizs s1, s0 @ s1<- op 3687 GET_INST_OPCODE ip @ extract opcode from rINST 3688 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3689 fsts s1, [r9] @ vA<- s1 3690 GOTO_OPCODE ip @ jump to next instruction 3691 3692 3693/* ------------------------------ */ 3694 .balign 128 3695.L_op_float_to_long: /* 0x88 */ 3696/* File: arm/op_float_to_long.S */ 3697/* File: arm/unopWider.S */ 3698 /* 3699 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3700 * that specifies an instruction that performs "result = op r0", where 3701 * "result" is a 64-bit quantity in r0/r1. 3702 * 3703 * For: int-to-long, int-to-double, float-to-long, float-to-double 3704 */ 3705 /* unop vA, vB */ 3706 mov r3, rINST, lsr #12 @ r3<- B 3707 ubfx rINST, rINST, #8, #4 @ rINST<- A 3708 GET_VREG r0, r3 @ r0<- vB 3709 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3710 @ optional op; may set condition codes 3711 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3712 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3713 bl f2l_doconv @ r0<- op, r0-r3 changed 3714 GET_INST_OPCODE ip @ extract opcode from rINST 3715 stmia r9, {r0-r1} @ vA/vA+1<- r0/r1 3716 GOTO_OPCODE ip @ jump to next instruction 3717 /* 9-10 instructions */ 3718 3719 3720 3721/* ------------------------------ */ 3722 .balign 128 3723.L_op_float_to_double: /* 0x89 */ 3724/* File: arm/op_float_to_double.S */ 3725/* File: arm/funopWider.S */ 3726 /* 3727 * Generic 32bit-to-64bit floating point unary operation. Provide an 3728 * "instr" line that specifies an instruction that performs "d0 = op s0". 3729 * 3730 * For: int-to-double, float-to-double 3731 */ 3732 /* unop vA, vB */ 3733 mov r3, rINST, lsr #12 @ r3<- B 3734 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3735 flds s0, [r3] @ s0<- vB 3736 ubfx r9, rINST, #8, #4 @ r9<- A 3737 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3738 vcvt.f64.f32 d0, s0 @ d0<- op 3739 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 3740 GET_INST_OPCODE ip @ extract opcode from rINST 3741 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3742 fstd d0, [r9] @ vA<- d0 3743 GOTO_OPCODE ip @ jump to next instruction 3744 3745 3746/* ------------------------------ */ 3747 .balign 128 3748.L_op_double_to_int: /* 0x8a */ 3749/* File: arm/op_double_to_int.S */ 3750/* File: arm/funopNarrower.S */ 3751 /* 3752 * Generic 64bit-to-32bit unary floating point operation. Provide an 3753 * "instr" line that specifies an instruction that performs "s0 = op d0". 3754 * 3755 * For: double-to-int, double-to-float 3756 */ 3757 /* unop vA, vB */ 3758 mov r3, rINST, lsr #12 @ r3<- B 3759 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3760 fldd d0, [r3] @ d0<- vB 3761 ubfx r9, rINST, #8, #4 @ r9<- A 3762 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3763 ftosizd s0, d0 @ s0<- op 3764 GET_INST_OPCODE ip @ extract opcode from rINST 3765 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3766 fsts s0, [r9] @ vA<- s0 3767 GOTO_OPCODE ip @ jump to next instruction 3768 3769 3770/* ------------------------------ */ 3771 .balign 128 3772.L_op_double_to_long: /* 0x8b */ 3773/* File: arm/op_double_to_long.S */ 3774/* File: arm/unopWide.S */ 3775 /* 3776 * Generic 64-bit unary operation. Provide an "instr" line that 3777 * specifies an instruction that performs "result = op r0/r1". 3778 * This could be an ARM instruction or a function call. 3779 * 3780 * For: neg-long, not-long, neg-double, long-to-double, double-to-long 3781 */ 3782 /* unop vA, vB */ 3783 mov r3, rINST, lsr #12 @ r3<- B 3784 ubfx rINST, rINST, #8, #4 @ rINST<- A 3785 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[B] 3786 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 3787 ldmia r3, {r0-r1} @ r0/r1<- vAA 3788 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 3789 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3790 @ optional op; may set condition codes 3791 bl d2l_doconv @ r0/r1<- op, r2-r3 changed 3792 GET_INST_OPCODE ip @ extract opcode from rINST 3793 stmia r9, {r0-r1} @ vAA<- r0/r1 3794 GOTO_OPCODE ip @ jump to next instruction 3795 /* 10-11 instructions */ 3796 3797 3798 3799/* ------------------------------ */ 3800 .balign 128 3801.L_op_double_to_float: /* 0x8c */ 3802/* File: arm/op_double_to_float.S */ 3803/* File: arm/funopNarrower.S */ 3804 /* 3805 * Generic 64bit-to-32bit unary floating point operation. Provide an 3806 * "instr" line that specifies an instruction that performs "s0 = op d0". 3807 * 3808 * For: double-to-int, double-to-float 3809 */ 3810 /* unop vA, vB */ 3811 mov r3, rINST, lsr #12 @ r3<- B 3812 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 3813 fldd d0, [r3] @ d0<- vB 3814 ubfx r9, rINST, #8, #4 @ r9<- A 3815 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3816 vcvt.f32.f64 s0, d0 @ s0<- op 3817 GET_INST_OPCODE ip @ extract opcode from rINST 3818 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 3819 fsts s0, [r9] @ vA<- s0 3820 GOTO_OPCODE ip @ jump to next instruction 3821 3822 3823/* ------------------------------ */ 3824 .balign 128 3825.L_op_int_to_byte: /* 0x8d */ 3826/* File: arm/op_int_to_byte.S */ 3827/* File: arm/unop.S */ 3828 /* 3829 * Generic 32-bit unary operation. Provide an "instr" line that 3830 * specifies an instruction that performs "result = op r0". 3831 * This could be an ARM instruction or a function call. 3832 * 3833 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3834 * int-to-byte, int-to-char, int-to-short 3835 */ 3836 /* unop vA, vB */ 3837 mov r3, rINST, lsr #12 @ r3<- B 3838 ubfx r9, rINST, #8, #4 @ r9<- A 3839 GET_VREG r0, r3 @ r0<- vB 3840 @ optional op; may set condition codes 3841 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3842 sxtb r0, r0 @ r0<- op, r0-r3 changed 3843 GET_INST_OPCODE ip @ extract opcode from rINST 3844 SET_VREG r0, r9 @ vAA<- r0 3845 GOTO_OPCODE ip @ jump to next instruction 3846 /* 8-9 instructions */ 3847 3848 3849/* ------------------------------ */ 3850 .balign 128 3851.L_op_int_to_char: /* 0x8e */ 3852/* File: arm/op_int_to_char.S */ 3853/* File: arm/unop.S */ 3854 /* 3855 * Generic 32-bit unary operation. Provide an "instr" line that 3856 * specifies an instruction that performs "result = op r0". 3857 * This could be an ARM instruction or a function call. 3858 * 3859 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3860 * int-to-byte, int-to-char, int-to-short 3861 */ 3862 /* unop vA, vB */ 3863 mov r3, rINST, lsr #12 @ r3<- B 3864 ubfx r9, rINST, #8, #4 @ r9<- A 3865 GET_VREG r0, r3 @ r0<- vB 3866 @ optional op; may set condition codes 3867 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3868 uxth r0, r0 @ r0<- op, r0-r3 changed 3869 GET_INST_OPCODE ip @ extract opcode from rINST 3870 SET_VREG r0, r9 @ vAA<- r0 3871 GOTO_OPCODE ip @ jump to next instruction 3872 /* 8-9 instructions */ 3873 3874 3875/* ------------------------------ */ 3876 .balign 128 3877.L_op_int_to_short: /* 0x8f */ 3878/* File: arm/op_int_to_short.S */ 3879/* File: arm/unop.S */ 3880 /* 3881 * Generic 32-bit unary operation. Provide an "instr" line that 3882 * specifies an instruction that performs "result = op r0". 3883 * This could be an ARM instruction or a function call. 3884 * 3885 * for: neg-int, not-int, neg-float, int-to-float, float-to-int, 3886 * int-to-byte, int-to-char, int-to-short 3887 */ 3888 /* unop vA, vB */ 3889 mov r3, rINST, lsr #12 @ r3<- B 3890 ubfx r9, rINST, #8, #4 @ r9<- A 3891 GET_VREG r0, r3 @ r0<- vB 3892 @ optional op; may set condition codes 3893 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 3894 sxth r0, r0 @ r0<- op, r0-r3 changed 3895 GET_INST_OPCODE ip @ extract opcode from rINST 3896 SET_VREG r0, r9 @ vAA<- r0 3897 GOTO_OPCODE ip @ jump to next instruction 3898 /* 8-9 instructions */ 3899 3900 3901/* ------------------------------ */ 3902 .balign 128 3903.L_op_add_int: /* 0x90 */ 3904/* File: arm/op_add_int.S */ 3905/* File: arm/binop.S */ 3906 /* 3907 * Generic 32-bit binary operation. Provide an "instr" line that 3908 * specifies an instruction that performs "result = r0 op r1". 3909 * This could be an ARM instruction or a function call. (If the result 3910 * comes back in a register other than r0, you can override "result".) 3911 * 3912 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3913 * vCC (r1). Useful for integer division and modulus. Note that we 3914 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3915 * handles it correctly. 3916 * 3917 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3918 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3919 * mul-float, div-float, rem-float 3920 */ 3921 /* binop vAA, vBB, vCC */ 3922 FETCH r0, 1 @ r0<- CCBB 3923 mov r9, rINST, lsr #8 @ r9<- AA 3924 mov r3, r0, lsr #8 @ r3<- CC 3925 and r2, r0, #255 @ r2<- BB 3926 GET_VREG r1, r3 @ r1<- vCC 3927 GET_VREG r0, r2 @ r0<- vBB 3928 .if 0 3929 cmp r1, #0 @ is second operand zero? 3930 beq common_errDivideByZero 3931 .endif 3932 3933 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 3934 @ optional op; may set condition codes 3935 add r0, r0, r1 @ r0<- op, r0-r3 changed 3936 GET_INST_OPCODE ip @ extract opcode from rINST 3937 SET_VREG r0, r9 @ vAA<- r0 3938 GOTO_OPCODE ip @ jump to next instruction 3939 /* 11-14 instructions */ 3940 3941 3942/* ------------------------------ */ 3943 .balign 128 3944.L_op_sub_int: /* 0x91 */ 3945/* File: arm/op_sub_int.S */ 3946/* File: arm/binop.S */ 3947 /* 3948 * Generic 32-bit binary operation. Provide an "instr" line that 3949 * specifies an instruction that performs "result = r0 op r1". 3950 * This could be an ARM instruction or a function call. (If the result 3951 * comes back in a register other than r0, you can override "result".) 3952 * 3953 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3954 * vCC (r1). Useful for integer division and modulus. Note that we 3955 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3956 * handles it correctly. 3957 * 3958 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 3959 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 3960 * mul-float, div-float, rem-float 3961 */ 3962 /* binop vAA, vBB, vCC */ 3963 FETCH r0, 1 @ r0<- CCBB 3964 mov r9, rINST, lsr #8 @ r9<- AA 3965 mov r3, r0, lsr #8 @ r3<- CC 3966 and r2, r0, #255 @ r2<- BB 3967 GET_VREG r1, r3 @ r1<- vCC 3968 GET_VREG r0, r2 @ r0<- vBB 3969 .if 0 3970 cmp r1, #0 @ is second operand zero? 3971 beq common_errDivideByZero 3972 .endif 3973 3974 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 3975 @ optional op; may set condition codes 3976 sub r0, r0, r1 @ r0<- op, r0-r3 changed 3977 GET_INST_OPCODE ip @ extract opcode from rINST 3978 SET_VREG r0, r9 @ vAA<- r0 3979 GOTO_OPCODE ip @ jump to next instruction 3980 /* 11-14 instructions */ 3981 3982 3983/* ------------------------------ */ 3984 .balign 128 3985.L_op_mul_int: /* 0x92 */ 3986/* File: arm/op_mul_int.S */ 3987/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 3988/* File: arm/binop.S */ 3989 /* 3990 * Generic 32-bit binary operation. Provide an "instr" line that 3991 * specifies an instruction that performs "result = r0 op r1". 3992 * This could be an ARM instruction or a function call. (If the result 3993 * comes back in a register other than r0, you can override "result".) 3994 * 3995 * If "chkzero" is set to 1, we perform a divide-by-zero check on 3996 * vCC (r1). Useful for integer division and modulus. Note that we 3997 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 3998 * handles it correctly. 3999 * 4000 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4001 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4002 * mul-float, div-float, rem-float 4003 */ 4004 /* binop vAA, vBB, vCC */ 4005 FETCH r0, 1 @ r0<- CCBB 4006 mov r9, rINST, lsr #8 @ r9<- AA 4007 mov r3, r0, lsr #8 @ r3<- CC 4008 and r2, r0, #255 @ r2<- BB 4009 GET_VREG r1, r3 @ r1<- vCC 4010 GET_VREG r0, r2 @ r0<- vBB 4011 .if 0 4012 cmp r1, #0 @ is second operand zero? 4013 beq common_errDivideByZero 4014 .endif 4015 4016 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4017 @ optional op; may set condition codes 4018 mul r0, r1, r0 @ r0<- op, r0-r3 changed 4019 GET_INST_OPCODE ip @ extract opcode from rINST 4020 SET_VREG r0, r9 @ vAA<- r0 4021 GOTO_OPCODE ip @ jump to next instruction 4022 /* 11-14 instructions */ 4023 4024 4025/* ------------------------------ */ 4026 .balign 128 4027.L_op_div_int: /* 0x93 */ 4028/* File: arm/op_div_int.S */ 4029 /* 4030 * Specialized 32-bit binary operation 4031 * 4032 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper 4033 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 4034 * ARMv7 CPUs that have hardware division support). 4035 * 4036 * div-int 4037 * 4038 */ 4039 FETCH r0, 1 @ r0<- CCBB 4040 mov r9, rINST, lsr #8 @ r9<- AA 4041 mov r3, r0, lsr #8 @ r3<- CC 4042 and r2, r0, #255 @ r2<- BB 4043 GET_VREG r1, r3 @ r1<- vCC 4044 GET_VREG r0, r2 @ r0<- vBB 4045 cmp r1, #0 @ is second operand zero? 4046 beq common_errDivideByZero 4047 4048 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4049#ifdef __ARM_ARCH_EXT_IDIV__ 4050 sdiv r0, r0, r1 @ r0<- op 4051#else 4052 bl __aeabi_idiv @ r0<- op, r0-r3 changed 4053#endif 4054 GET_INST_OPCODE ip @ extract opcode from rINST 4055 SET_VREG r0, r9 @ vAA<- r0 4056 GOTO_OPCODE ip @ jump to next instruction 4057 /* 11-14 instructions */ 4058 4059/* ------------------------------ */ 4060 .balign 128 4061.L_op_rem_int: /* 0x94 */ 4062/* File: arm/op_rem_int.S */ 4063 /* 4064 * Specialized 32-bit binary operation 4065 * 4066 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 4067 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 4068 * ARMv7 CPUs that have hardware division support). 4069 * 4070 * NOTE: idivmod returns quotient in r0 and remainder in r1 4071 * 4072 * rem-int 4073 * 4074 */ 4075 FETCH r0, 1 @ r0<- CCBB 4076 mov r9, rINST, lsr #8 @ r9<- AA 4077 mov r3, r0, lsr #8 @ r3<- CC 4078 and r2, r0, #255 @ r2<- BB 4079 GET_VREG r1, r3 @ r1<- vCC 4080 GET_VREG r0, r2 @ r0<- vBB 4081 cmp r1, #0 @ is second operand zero? 4082 beq common_errDivideByZero 4083 4084 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4085#ifdef __ARM_ARCH_EXT_IDIV__ 4086 sdiv r2, r0, r1 4087 mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed 4088#else 4089 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 4090#endif 4091 GET_INST_OPCODE ip @ extract opcode from rINST 4092 SET_VREG r1, r9 @ vAA<- r1 4093 GOTO_OPCODE ip @ jump to next instruction 4094 /* 11-14 instructions */ 4095 4096/* ------------------------------ */ 4097 .balign 128 4098.L_op_and_int: /* 0x95 */ 4099/* File: arm/op_and_int.S */ 4100/* File: arm/binop.S */ 4101 /* 4102 * Generic 32-bit binary operation. Provide an "instr" line that 4103 * specifies an instruction that performs "result = r0 op r1". 4104 * This could be an ARM instruction or a function call. (If the result 4105 * comes back in a register other than r0, you can override "result".) 4106 * 4107 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4108 * vCC (r1). Useful for integer division and modulus. Note that we 4109 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4110 * handles it correctly. 4111 * 4112 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4113 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4114 * mul-float, div-float, rem-float 4115 */ 4116 /* binop vAA, vBB, vCC */ 4117 FETCH r0, 1 @ r0<- CCBB 4118 mov r9, rINST, lsr #8 @ r9<- AA 4119 mov r3, r0, lsr #8 @ r3<- CC 4120 and r2, r0, #255 @ r2<- BB 4121 GET_VREG r1, r3 @ r1<- vCC 4122 GET_VREG r0, r2 @ r0<- vBB 4123 .if 0 4124 cmp r1, #0 @ is second operand zero? 4125 beq common_errDivideByZero 4126 .endif 4127 4128 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4129 @ optional op; may set condition codes 4130 and r0, r0, r1 @ r0<- op, r0-r3 changed 4131 GET_INST_OPCODE ip @ extract opcode from rINST 4132 SET_VREG r0, r9 @ vAA<- r0 4133 GOTO_OPCODE ip @ jump to next instruction 4134 /* 11-14 instructions */ 4135 4136 4137/* ------------------------------ */ 4138 .balign 128 4139.L_op_or_int: /* 0x96 */ 4140/* File: arm/op_or_int.S */ 4141/* File: arm/binop.S */ 4142 /* 4143 * Generic 32-bit binary operation. Provide an "instr" line that 4144 * specifies an instruction that performs "result = r0 op r1". 4145 * This could be an ARM instruction or a function call. (If the result 4146 * comes back in a register other than r0, you can override "result".) 4147 * 4148 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4149 * vCC (r1). Useful for integer division and modulus. Note that we 4150 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4151 * handles it correctly. 4152 * 4153 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4154 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4155 * mul-float, div-float, rem-float 4156 */ 4157 /* binop vAA, vBB, vCC */ 4158 FETCH r0, 1 @ r0<- CCBB 4159 mov r9, rINST, lsr #8 @ r9<- AA 4160 mov r3, r0, lsr #8 @ r3<- CC 4161 and r2, r0, #255 @ r2<- BB 4162 GET_VREG r1, r3 @ r1<- vCC 4163 GET_VREG r0, r2 @ r0<- vBB 4164 .if 0 4165 cmp r1, #0 @ is second operand zero? 4166 beq common_errDivideByZero 4167 .endif 4168 4169 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4170 @ optional op; may set condition codes 4171 orr r0, r0, r1 @ r0<- op, r0-r3 changed 4172 GET_INST_OPCODE ip @ extract opcode from rINST 4173 SET_VREG r0, r9 @ vAA<- r0 4174 GOTO_OPCODE ip @ jump to next instruction 4175 /* 11-14 instructions */ 4176 4177 4178/* ------------------------------ */ 4179 .balign 128 4180.L_op_xor_int: /* 0x97 */ 4181/* File: arm/op_xor_int.S */ 4182/* File: arm/binop.S */ 4183 /* 4184 * Generic 32-bit binary operation. Provide an "instr" line that 4185 * specifies an instruction that performs "result = r0 op r1". 4186 * This could be an ARM instruction or a function call. (If the result 4187 * comes back in a register other than r0, you can override "result".) 4188 * 4189 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4190 * vCC (r1). Useful for integer division and modulus. Note that we 4191 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4192 * handles it correctly. 4193 * 4194 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4195 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4196 * mul-float, div-float, rem-float 4197 */ 4198 /* binop vAA, vBB, vCC */ 4199 FETCH r0, 1 @ r0<- CCBB 4200 mov r9, rINST, lsr #8 @ r9<- AA 4201 mov r3, r0, lsr #8 @ r3<- CC 4202 and r2, r0, #255 @ r2<- BB 4203 GET_VREG r1, r3 @ r1<- vCC 4204 GET_VREG r0, r2 @ r0<- vBB 4205 .if 0 4206 cmp r1, #0 @ is second operand zero? 4207 beq common_errDivideByZero 4208 .endif 4209 4210 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4211 @ optional op; may set condition codes 4212 eor r0, r0, r1 @ r0<- op, r0-r3 changed 4213 GET_INST_OPCODE ip @ extract opcode from rINST 4214 SET_VREG r0, r9 @ vAA<- r0 4215 GOTO_OPCODE ip @ jump to next instruction 4216 /* 11-14 instructions */ 4217 4218 4219/* ------------------------------ */ 4220 .balign 128 4221.L_op_shl_int: /* 0x98 */ 4222/* File: arm/op_shl_int.S */ 4223/* File: arm/binop.S */ 4224 /* 4225 * Generic 32-bit binary operation. Provide an "instr" line that 4226 * specifies an instruction that performs "result = r0 op r1". 4227 * This could be an ARM instruction or a function call. (If the result 4228 * comes back in a register other than r0, you can override "result".) 4229 * 4230 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4231 * vCC (r1). Useful for integer division and modulus. Note that we 4232 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4233 * handles it correctly. 4234 * 4235 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4236 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4237 * mul-float, div-float, rem-float 4238 */ 4239 /* binop vAA, vBB, vCC */ 4240 FETCH r0, 1 @ r0<- CCBB 4241 mov r9, rINST, lsr #8 @ r9<- AA 4242 mov r3, r0, lsr #8 @ r3<- CC 4243 and r2, r0, #255 @ r2<- BB 4244 GET_VREG r1, r3 @ r1<- vCC 4245 GET_VREG r0, r2 @ r0<- vBB 4246 .if 0 4247 cmp r1, #0 @ is second operand zero? 4248 beq common_errDivideByZero 4249 .endif 4250 4251 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4252 and r1, r1, #31 @ optional op; may set condition codes 4253 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 4254 GET_INST_OPCODE ip @ extract opcode from rINST 4255 SET_VREG r0, r9 @ vAA<- r0 4256 GOTO_OPCODE ip @ jump to next instruction 4257 /* 11-14 instructions */ 4258 4259 4260/* ------------------------------ */ 4261 .balign 128 4262.L_op_shr_int: /* 0x99 */ 4263/* File: arm/op_shr_int.S */ 4264/* File: arm/binop.S */ 4265 /* 4266 * Generic 32-bit binary operation. Provide an "instr" line that 4267 * specifies an instruction that performs "result = r0 op r1". 4268 * This could be an ARM instruction or a function call. (If the result 4269 * comes back in a register other than r0, you can override "result".) 4270 * 4271 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4272 * vCC (r1). Useful for integer division and modulus. Note that we 4273 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4274 * handles it correctly. 4275 * 4276 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4277 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4278 * mul-float, div-float, rem-float 4279 */ 4280 /* binop vAA, vBB, vCC */ 4281 FETCH r0, 1 @ r0<- CCBB 4282 mov r9, rINST, lsr #8 @ r9<- AA 4283 mov r3, r0, lsr #8 @ r3<- CC 4284 and r2, r0, #255 @ r2<- BB 4285 GET_VREG r1, r3 @ r1<- vCC 4286 GET_VREG r0, r2 @ r0<- vBB 4287 .if 0 4288 cmp r1, #0 @ is second operand zero? 4289 beq common_errDivideByZero 4290 .endif 4291 4292 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4293 and r1, r1, #31 @ optional op; may set condition codes 4294 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 4295 GET_INST_OPCODE ip @ extract opcode from rINST 4296 SET_VREG r0, r9 @ vAA<- r0 4297 GOTO_OPCODE ip @ jump to next instruction 4298 /* 11-14 instructions */ 4299 4300 4301/* ------------------------------ */ 4302 .balign 128 4303.L_op_ushr_int: /* 0x9a */ 4304/* File: arm/op_ushr_int.S */ 4305/* File: arm/binop.S */ 4306 /* 4307 * Generic 32-bit binary operation. Provide an "instr" line that 4308 * specifies an instruction that performs "result = r0 op r1". 4309 * This could be an ARM instruction or a function call. (If the result 4310 * comes back in a register other than r0, you can override "result".) 4311 * 4312 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4313 * vCC (r1). Useful for integer division and modulus. Note that we 4314 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4315 * handles it correctly. 4316 * 4317 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4318 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4319 * mul-float, div-float, rem-float 4320 */ 4321 /* binop vAA, vBB, vCC */ 4322 FETCH r0, 1 @ r0<- CCBB 4323 mov r9, rINST, lsr #8 @ r9<- AA 4324 mov r3, r0, lsr #8 @ r3<- CC 4325 and r2, r0, #255 @ r2<- BB 4326 GET_VREG r1, r3 @ r1<- vCC 4327 GET_VREG r0, r2 @ r0<- vBB 4328 .if 0 4329 cmp r1, #0 @ is second operand zero? 4330 beq common_errDivideByZero 4331 .endif 4332 4333 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4334 and r1, r1, #31 @ optional op; may set condition codes 4335 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 4336 GET_INST_OPCODE ip @ extract opcode from rINST 4337 SET_VREG r0, r9 @ vAA<- r0 4338 GOTO_OPCODE ip @ jump to next instruction 4339 /* 11-14 instructions */ 4340 4341 4342/* ------------------------------ */ 4343 .balign 128 4344.L_op_add_long: /* 0x9b */ 4345/* File: arm/op_add_long.S */ 4346/* File: arm/binopWide.S */ 4347 /* 4348 * Generic 64-bit binary operation. Provide an "instr" line that 4349 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4350 * This could be an ARM instruction or a function call. (If the result 4351 * comes back in a register other than r0, you can override "result".) 4352 * 4353 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4354 * vCC (r1). Useful for integer division and modulus. 4355 * 4356 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4357 * xor-long, add-double, sub-double, mul-double, div-double, 4358 * rem-double 4359 * 4360 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4361 */ 4362 /* binop vAA, vBB, vCC */ 4363 FETCH r0, 1 @ r0<- CCBB 4364 mov rINST, rINST, lsr #8 @ rINST<- AA 4365 and r2, r0, #255 @ r2<- BB 4366 mov r3, r0, lsr #8 @ r3<- CC 4367 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4368 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4369 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4370 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4371 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4372 .if 0 4373 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4374 beq common_errDivideByZero 4375 .endif 4376 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4377 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4378 adds r0, r0, r2 @ optional op; may set condition codes 4379 adc r1, r1, r3 @ result<- op, r0-r3 changed 4380 GET_INST_OPCODE ip @ extract opcode from rINST 4381 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4382 GOTO_OPCODE ip @ jump to next instruction 4383 /* 14-17 instructions */ 4384 4385 4386/* ------------------------------ */ 4387 .balign 128 4388.L_op_sub_long: /* 0x9c */ 4389/* File: arm/op_sub_long.S */ 4390/* File: arm/binopWide.S */ 4391 /* 4392 * Generic 64-bit binary operation. Provide an "instr" line that 4393 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4394 * This could be an ARM instruction or a function call. (If the result 4395 * comes back in a register other than r0, you can override "result".) 4396 * 4397 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4398 * vCC (r1). Useful for integer division and modulus. 4399 * 4400 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4401 * xor-long, add-double, sub-double, mul-double, div-double, 4402 * rem-double 4403 * 4404 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4405 */ 4406 /* binop vAA, vBB, vCC */ 4407 FETCH r0, 1 @ r0<- CCBB 4408 mov rINST, rINST, lsr #8 @ rINST<- AA 4409 and r2, r0, #255 @ r2<- BB 4410 mov r3, r0, lsr #8 @ r3<- CC 4411 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4412 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4413 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4414 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4415 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4416 .if 0 4417 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4418 beq common_errDivideByZero 4419 .endif 4420 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4421 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4422 subs r0, r0, r2 @ optional op; may set condition codes 4423 sbc r1, r1, r3 @ result<- op, r0-r3 changed 4424 GET_INST_OPCODE ip @ extract opcode from rINST 4425 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4426 GOTO_OPCODE ip @ jump to next instruction 4427 /* 14-17 instructions */ 4428 4429 4430/* ------------------------------ */ 4431 .balign 128 4432.L_op_mul_long: /* 0x9d */ 4433/* File: arm/op_mul_long.S */ 4434 /* 4435 * Signed 64-bit integer multiply. 4436 * 4437 * Consider WXxYZ (r1r0 x r3r2) with a long multiply: 4438 * WX 4439 * x YZ 4440 * -------- 4441 * ZW ZX 4442 * YW YX 4443 * 4444 * The low word of the result holds ZX, the high word holds 4445 * (ZW+YX) + (the high overflow from ZX). YW doesn't matter because 4446 * it doesn't fit in the low 64 bits. 4447 * 4448 * Unlike most ARM math operations, multiply instructions have 4449 * restrictions on using the same register more than once (Rd and Rm 4450 * cannot be the same). 4451 */ 4452 /* mul-long vAA, vBB, vCC */ 4453 FETCH r0, 1 @ r0<- CCBB 4454 and r2, r0, #255 @ r2<- BB 4455 mov r3, r0, lsr #8 @ r3<- CC 4456 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4457 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4458 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4459 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4460 mul ip, r2, r1 @ ip<- ZxW 4461 umull r1, lr, r2, r0 @ r1/lr <- ZxX 4462 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 4463 mov r0, rINST, lsr #8 @ r0<- AA 4464 add r2, r2, lr @ r2<- lr + low(ZxW + (YxX)) 4465 VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[AA] 4466 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4467 GET_INST_OPCODE ip @ extract opcode from rINST 4468 stmia r0, {r1-r2 } @ vAA/vAA+1<- r1/r2 4469 GOTO_OPCODE ip @ jump to next instruction 4470 4471/* ------------------------------ */ 4472 .balign 128 4473.L_op_div_long: /* 0x9e */ 4474/* File: arm/op_div_long.S */ 4475/* File: arm/binopWide.S */ 4476 /* 4477 * Generic 64-bit binary operation. Provide an "instr" line that 4478 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4479 * This could be an ARM instruction or a function call. (If the result 4480 * comes back in a register other than r0, you can override "result".) 4481 * 4482 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4483 * vCC (r1). Useful for integer division and modulus. 4484 * 4485 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4486 * xor-long, add-double, sub-double, mul-double, div-double, 4487 * rem-double 4488 * 4489 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4490 */ 4491 /* binop vAA, vBB, vCC */ 4492 FETCH r0, 1 @ r0<- CCBB 4493 mov rINST, rINST, lsr #8 @ rINST<- AA 4494 and r2, r0, #255 @ r2<- BB 4495 mov r3, r0, lsr #8 @ r3<- CC 4496 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4497 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4498 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4499 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4500 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4501 .if 1 4502 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4503 beq common_errDivideByZero 4504 .endif 4505 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4506 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4507 @ optional op; may set condition codes 4508 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4509 GET_INST_OPCODE ip @ extract opcode from rINST 4510 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4511 GOTO_OPCODE ip @ jump to next instruction 4512 /* 14-17 instructions */ 4513 4514 4515/* ------------------------------ */ 4516 .balign 128 4517.L_op_rem_long: /* 0x9f */ 4518/* File: arm/op_rem_long.S */ 4519/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 4520/* File: arm/binopWide.S */ 4521 /* 4522 * Generic 64-bit binary operation. Provide an "instr" line that 4523 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4524 * This could be an ARM instruction or a function call. (If the result 4525 * comes back in a register other than r0, you can override "result".) 4526 * 4527 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4528 * vCC (r1). Useful for integer division and modulus. 4529 * 4530 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4531 * xor-long, add-double, sub-double, mul-double, div-double, 4532 * rem-double 4533 * 4534 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4535 */ 4536 /* binop vAA, vBB, vCC */ 4537 FETCH r0, 1 @ r0<- CCBB 4538 mov rINST, rINST, lsr #8 @ rINST<- AA 4539 and r2, r0, #255 @ r2<- BB 4540 mov r3, r0, lsr #8 @ r3<- CC 4541 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4542 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4543 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4544 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4545 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4546 .if 1 4547 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4548 beq common_errDivideByZero 4549 .endif 4550 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4551 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4552 @ optional op; may set condition codes 4553 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 4554 GET_INST_OPCODE ip @ extract opcode from rINST 4555 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 4556 GOTO_OPCODE ip @ jump to next instruction 4557 /* 14-17 instructions */ 4558 4559 4560/* ------------------------------ */ 4561 .balign 128 4562.L_op_and_long: /* 0xa0 */ 4563/* File: arm/op_and_long.S */ 4564/* File: arm/binopWide.S */ 4565 /* 4566 * Generic 64-bit binary operation. Provide an "instr" line that 4567 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4568 * This could be an ARM instruction or a function call. (If the result 4569 * comes back in a register other than r0, you can override "result".) 4570 * 4571 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4572 * vCC (r1). Useful for integer division and modulus. 4573 * 4574 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4575 * xor-long, add-double, sub-double, mul-double, div-double, 4576 * rem-double 4577 * 4578 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4579 */ 4580 /* binop vAA, vBB, vCC */ 4581 FETCH r0, 1 @ r0<- CCBB 4582 mov rINST, rINST, lsr #8 @ rINST<- AA 4583 and r2, r0, #255 @ r2<- BB 4584 mov r3, r0, lsr #8 @ r3<- CC 4585 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4586 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4587 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4588 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4589 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4590 .if 0 4591 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4592 beq common_errDivideByZero 4593 .endif 4594 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4595 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4596 and r0, r0, r2 @ optional op; may set condition codes 4597 and r1, r1, r3 @ result<- op, r0-r3 changed 4598 GET_INST_OPCODE ip @ extract opcode from rINST 4599 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4600 GOTO_OPCODE ip @ jump to next instruction 4601 /* 14-17 instructions */ 4602 4603 4604/* ------------------------------ */ 4605 .balign 128 4606.L_op_or_long: /* 0xa1 */ 4607/* File: arm/op_or_long.S */ 4608/* File: arm/binopWide.S */ 4609 /* 4610 * Generic 64-bit binary operation. Provide an "instr" line that 4611 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4612 * This could be an ARM instruction or a function call. (If the result 4613 * comes back in a register other than r0, you can override "result".) 4614 * 4615 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4616 * vCC (r1). Useful for integer division and modulus. 4617 * 4618 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4619 * xor-long, add-double, sub-double, mul-double, div-double, 4620 * rem-double 4621 * 4622 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4623 */ 4624 /* binop vAA, vBB, vCC */ 4625 FETCH r0, 1 @ r0<- CCBB 4626 mov rINST, rINST, lsr #8 @ rINST<- AA 4627 and r2, r0, #255 @ r2<- BB 4628 mov r3, r0, lsr #8 @ r3<- CC 4629 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4630 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4631 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4632 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4633 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4634 .if 0 4635 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4636 beq common_errDivideByZero 4637 .endif 4638 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4639 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4640 orr r0, r0, r2 @ optional op; may set condition codes 4641 orr r1, r1, r3 @ result<- op, r0-r3 changed 4642 GET_INST_OPCODE ip @ extract opcode from rINST 4643 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4644 GOTO_OPCODE ip @ jump to next instruction 4645 /* 14-17 instructions */ 4646 4647 4648/* ------------------------------ */ 4649 .balign 128 4650.L_op_xor_long: /* 0xa2 */ 4651/* File: arm/op_xor_long.S */ 4652/* File: arm/binopWide.S */ 4653 /* 4654 * Generic 64-bit binary operation. Provide an "instr" line that 4655 * specifies an instruction that performs "result = r0-r1 op r2-r3". 4656 * This could be an ARM instruction or a function call. (If the result 4657 * comes back in a register other than r0, you can override "result".) 4658 * 4659 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4660 * vCC (r1). Useful for integer division and modulus. 4661 * 4662 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4663 * xor-long, add-double, sub-double, mul-double, div-double, 4664 * rem-double 4665 * 4666 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4667 */ 4668 /* binop vAA, vBB, vCC */ 4669 FETCH r0, 1 @ r0<- CCBB 4670 mov rINST, rINST, lsr #8 @ rINST<- AA 4671 and r2, r0, #255 @ r2<- BB 4672 mov r3, r0, lsr #8 @ r3<- CC 4673 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 4674 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 4675 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 4676 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 4677 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 4678 .if 0 4679 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 4680 beq common_errDivideByZero 4681 .endif 4682 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 4683 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4684 eor r0, r0, r2 @ optional op; may set condition codes 4685 eor r1, r1, r3 @ result<- op, r0-r3 changed 4686 GET_INST_OPCODE ip @ extract opcode from rINST 4687 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 4688 GOTO_OPCODE ip @ jump to next instruction 4689 /* 14-17 instructions */ 4690 4691 4692/* ------------------------------ */ 4693 .balign 128 4694.L_op_shl_long: /* 0xa3 */ 4695/* File: arm/op_shl_long.S */ 4696 /* 4697 * Long integer shift. This is different from the generic 32/64-bit 4698 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4699 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4700 * 6 bits of the shift distance. 4701 */ 4702 /* shl-long vAA, vBB, vCC */ 4703 FETCH r0, 1 @ r0<- CCBB 4704 mov r9, rINST, lsr #8 @ r9<- AA 4705 and r3, r0, #255 @ r3<- BB 4706 mov r0, r0, lsr #8 @ r0<- CC 4707 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] 4708 GET_VREG r2, r0 @ r2<- vCC 4709 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4710 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 4711 and r2, r2, #63 @ r2<- r2 & 0x3f 4712 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 4713 mov r1, r1, asl r2 @ r1<- r1 << r2 4714 rsb r3, r2, #32 @ r3<- 32 - r2 4715 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 4716 subs ip, r2, #32 @ ip<- r2 - 32 4717 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 4718 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4719 mov r0, r0, asl r2 @ r0<- r0 << r2 4720 GET_INST_OPCODE ip @ extract opcode from rINST 4721 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 4722 GOTO_OPCODE ip @ jump to next instruction 4723 4724/* ------------------------------ */ 4725 .balign 128 4726.L_op_shr_long: /* 0xa4 */ 4727/* File: arm/op_shr_long.S */ 4728 /* 4729 * Long integer shift. This is different from the generic 32/64-bit 4730 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4731 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4732 * 6 bits of the shift distance. 4733 */ 4734 /* shr-long vAA, vBB, vCC */ 4735 FETCH r0, 1 @ r0<- CCBB 4736 mov r9, rINST, lsr #8 @ r9<- AA 4737 and r3, r0, #255 @ r3<- BB 4738 mov r0, r0, lsr #8 @ r0<- CC 4739 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] 4740 GET_VREG r2, r0 @ r2<- vCC 4741 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4742 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 4743 and r2, r2, #63 @ r0<- r0 & 0x3f 4744 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 4745 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4746 rsb r3, r2, #32 @ r3<- 32 - r2 4747 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4748 subs ip, r2, #32 @ ip<- r2 - 32 4749 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 4750 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4751 mov r1, r1, asr r2 @ r1<- r1 >> r2 4752 GET_INST_OPCODE ip @ extract opcode from rINST 4753 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 4754 GOTO_OPCODE ip @ jump to next instruction 4755 4756/* ------------------------------ */ 4757 .balign 128 4758.L_op_ushr_long: /* 0xa5 */ 4759/* File: arm/op_ushr_long.S */ 4760 /* 4761 * Long integer shift. This is different from the generic 32/64-bit 4762 * binary operations because vAA/vBB are 64-bit but vCC (the shift 4763 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 4764 * 6 bits of the shift distance. 4765 */ 4766 /* ushr-long vAA, vBB, vCC */ 4767 FETCH r0, 1 @ r0<- CCBB 4768 mov r9, rINST, lsr #8 @ r9<- AA 4769 and r3, r0, #255 @ r3<- BB 4770 mov r0, r0, lsr #8 @ r0<- CC 4771 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[BB] 4772 GET_VREG r2, r0 @ r2<- vCC 4773 ldmia r3, {r0-r1} @ r0/r1<- vBB/vBB+1 4774 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 4775 and r2, r2, #63 @ r0<- r0 & 0x3f 4776 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[AA] 4777 mov r0, r0, lsr r2 @ r0<- r2 >> r2 4778 rsb r3, r2, #32 @ r3<- 32 - r2 4779 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 4780 subs ip, r2, #32 @ ip<- r2 - 32 4781 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 4782 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4783 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 4784 GET_INST_OPCODE ip @ extract opcode from rINST 4785 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 4786 GOTO_OPCODE ip @ jump to next instruction 4787 4788/* ------------------------------ */ 4789 .balign 128 4790.L_op_add_float: /* 0xa6 */ 4791/* File: arm/op_add_float.S */ 4792/* File: arm/fbinop.S */ 4793 /* 4794 * Generic 32-bit floating-point operation. Provide an "instr" line that 4795 * specifies an instruction that performs "s2 = s0 op s1". Because we 4796 * use the "softfp" ABI, this must be an instruction, not a function call. 4797 * 4798 * For: add-float, sub-float, mul-float, div-float 4799 */ 4800 /* floatop vAA, vBB, vCC */ 4801 FETCH r0, 1 @ r0<- CCBB 4802 mov r9, rINST, lsr #8 @ r9<- AA 4803 mov r3, r0, lsr #8 @ r3<- CC 4804 and r2, r0, #255 @ r2<- BB 4805 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4806 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4807 flds s1, [r3] @ s1<- vCC 4808 flds s0, [r2] @ s0<- vBB 4809 4810 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4811 fadds s2, s0, s1 @ s2<- op 4812 GET_INST_OPCODE ip @ extract opcode from rINST 4813 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 4814 fsts s2, [r9] @ vAA<- s2 4815 GOTO_OPCODE ip @ jump to next instruction 4816 4817 4818/* ------------------------------ */ 4819 .balign 128 4820.L_op_sub_float: /* 0xa7 */ 4821/* File: arm/op_sub_float.S */ 4822/* File: arm/fbinop.S */ 4823 /* 4824 * Generic 32-bit floating-point operation. Provide an "instr" line that 4825 * specifies an instruction that performs "s2 = s0 op s1". Because we 4826 * use the "softfp" ABI, this must be an instruction, not a function call. 4827 * 4828 * For: add-float, sub-float, mul-float, div-float 4829 */ 4830 /* floatop vAA, vBB, vCC */ 4831 FETCH r0, 1 @ r0<- CCBB 4832 mov r9, rINST, lsr #8 @ r9<- AA 4833 mov r3, r0, lsr #8 @ r3<- CC 4834 and r2, r0, #255 @ r2<- BB 4835 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4836 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4837 flds s1, [r3] @ s1<- vCC 4838 flds s0, [r2] @ s0<- vBB 4839 4840 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4841 fsubs s2, s0, s1 @ s2<- op 4842 GET_INST_OPCODE ip @ extract opcode from rINST 4843 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 4844 fsts s2, [r9] @ vAA<- s2 4845 GOTO_OPCODE ip @ jump to next instruction 4846 4847 4848/* ------------------------------ */ 4849 .balign 128 4850.L_op_mul_float: /* 0xa8 */ 4851/* File: arm/op_mul_float.S */ 4852/* File: arm/fbinop.S */ 4853 /* 4854 * Generic 32-bit floating-point operation. Provide an "instr" line that 4855 * specifies an instruction that performs "s2 = s0 op s1". Because we 4856 * use the "softfp" ABI, this must be an instruction, not a function call. 4857 * 4858 * For: add-float, sub-float, mul-float, div-float 4859 */ 4860 /* floatop vAA, vBB, vCC */ 4861 FETCH r0, 1 @ r0<- CCBB 4862 mov r9, rINST, lsr #8 @ r9<- AA 4863 mov r3, r0, lsr #8 @ r3<- CC 4864 and r2, r0, #255 @ r2<- BB 4865 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4866 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4867 flds s1, [r3] @ s1<- vCC 4868 flds s0, [r2] @ s0<- vBB 4869 4870 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4871 fmuls s2, s0, s1 @ s2<- op 4872 GET_INST_OPCODE ip @ extract opcode from rINST 4873 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 4874 fsts s2, [r9] @ vAA<- s2 4875 GOTO_OPCODE ip @ jump to next instruction 4876 4877 4878/* ------------------------------ */ 4879 .balign 128 4880.L_op_div_float: /* 0xa9 */ 4881/* File: arm/op_div_float.S */ 4882/* File: arm/fbinop.S */ 4883 /* 4884 * Generic 32-bit floating-point operation. Provide an "instr" line that 4885 * specifies an instruction that performs "s2 = s0 op s1". Because we 4886 * use the "softfp" ABI, this must be an instruction, not a function call. 4887 * 4888 * For: add-float, sub-float, mul-float, div-float 4889 */ 4890 /* floatop vAA, vBB, vCC */ 4891 FETCH r0, 1 @ r0<- CCBB 4892 mov r9, rINST, lsr #8 @ r9<- AA 4893 mov r3, r0, lsr #8 @ r3<- CC 4894 and r2, r0, #255 @ r2<- BB 4895 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4896 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4897 flds s1, [r3] @ s1<- vCC 4898 flds s0, [r2] @ s0<- vBB 4899 4900 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4901 fdivs s2, s0, s1 @ s2<- op 4902 GET_INST_OPCODE ip @ extract opcode from rINST 4903 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 4904 fsts s2, [r9] @ vAA<- s2 4905 GOTO_OPCODE ip @ jump to next instruction 4906 4907 4908/* ------------------------------ */ 4909 .balign 128 4910.L_op_rem_float: /* 0xaa */ 4911/* File: arm/op_rem_float.S */ 4912/* EABI doesn't define a float remainder function, but libm does */ 4913/* File: arm/binop.S */ 4914 /* 4915 * Generic 32-bit binary operation. Provide an "instr" line that 4916 * specifies an instruction that performs "result = r0 op r1". 4917 * This could be an ARM instruction or a function call. (If the result 4918 * comes back in a register other than r0, you can override "result".) 4919 * 4920 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4921 * vCC (r1). Useful for integer division and modulus. Note that we 4922 * *don't* check for (INT_MIN / -1) here, because the ARM math lib 4923 * handles it correctly. 4924 * 4925 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4926 * xor-int, shl-int, shr-int, ushr-int, add-float, sub-float, 4927 * mul-float, div-float, rem-float 4928 */ 4929 /* binop vAA, vBB, vCC */ 4930 FETCH r0, 1 @ r0<- CCBB 4931 mov r9, rINST, lsr #8 @ r9<- AA 4932 mov r3, r0, lsr #8 @ r3<- CC 4933 and r2, r0, #255 @ r2<- BB 4934 GET_VREG r1, r3 @ r1<- vCC 4935 GET_VREG r0, r2 @ r0<- vBB 4936 .if 0 4937 cmp r1, #0 @ is second operand zero? 4938 beq common_errDivideByZero 4939 .endif 4940 4941 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4942 @ optional op; may set condition codes 4943 bl fmodf @ r0<- op, r0-r3 changed 4944 GET_INST_OPCODE ip @ extract opcode from rINST 4945 SET_VREG r0, r9 @ vAA<- r0 4946 GOTO_OPCODE ip @ jump to next instruction 4947 /* 11-14 instructions */ 4948 4949 4950/* ------------------------------ */ 4951 .balign 128 4952.L_op_add_double: /* 0xab */ 4953/* File: arm/op_add_double.S */ 4954/* File: arm/fbinopWide.S */ 4955 /* 4956 * Generic 64-bit double-precision floating point binary operation. 4957 * Provide an "instr" line that specifies an instruction that performs 4958 * "d2 = d0 op d1". 4959 * 4960 * for: add-double, sub-double, mul-double, div-double 4961 */ 4962 /* doubleop vAA, vBB, vCC */ 4963 FETCH r0, 1 @ r0<- CCBB 4964 mov r9, rINST, lsr #8 @ r9<- AA 4965 mov r3, r0, lsr #8 @ r3<- CC 4966 and r2, r0, #255 @ r2<- BB 4967 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4968 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4969 fldd d1, [r3] @ d1<- vCC 4970 fldd d0, [r2] @ d0<- vBB 4971 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 4972 faddd d2, d0, d1 @ s2<- op 4973 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 4974 GET_INST_OPCODE ip @ extract opcode from rINST 4975 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 4976 fstd d2, [r9] @ vAA<- d2 4977 GOTO_OPCODE ip @ jump to next instruction 4978 4979 4980/* ------------------------------ */ 4981 .balign 128 4982.L_op_sub_double: /* 0xac */ 4983/* File: arm/op_sub_double.S */ 4984/* File: arm/fbinopWide.S */ 4985 /* 4986 * Generic 64-bit double-precision floating point binary operation. 4987 * Provide an "instr" line that specifies an instruction that performs 4988 * "d2 = d0 op d1". 4989 * 4990 * for: add-double, sub-double, mul-double, div-double 4991 */ 4992 /* doubleop vAA, vBB, vCC */ 4993 FETCH r0, 1 @ r0<- CCBB 4994 mov r9, rINST, lsr #8 @ r9<- AA 4995 mov r3, r0, lsr #8 @ r3<- CC 4996 and r2, r0, #255 @ r2<- BB 4997 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 4998 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 4999 fldd d1, [r3] @ d1<- vCC 5000 fldd d0, [r2] @ d0<- vBB 5001 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 5002 fsubd d2, d0, d1 @ s2<- op 5003 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 5004 GET_INST_OPCODE ip @ extract opcode from rINST 5005 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 5006 fstd d2, [r9] @ vAA<- d2 5007 GOTO_OPCODE ip @ jump to next instruction 5008 5009 5010/* ------------------------------ */ 5011 .balign 128 5012.L_op_mul_double: /* 0xad */ 5013/* File: arm/op_mul_double.S */ 5014/* File: arm/fbinopWide.S */ 5015 /* 5016 * Generic 64-bit double-precision floating point binary operation. 5017 * Provide an "instr" line that specifies an instruction that performs 5018 * "d2 = d0 op d1". 5019 * 5020 * for: add-double, sub-double, mul-double, div-double 5021 */ 5022 /* doubleop vAA, vBB, vCC */ 5023 FETCH r0, 1 @ r0<- CCBB 5024 mov r9, rINST, lsr #8 @ r9<- AA 5025 mov r3, r0, lsr #8 @ r3<- CC 5026 and r2, r0, #255 @ r2<- BB 5027 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 5028 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 5029 fldd d1, [r3] @ d1<- vCC 5030 fldd d0, [r2] @ d0<- vBB 5031 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 5032 fmuld d2, d0, d1 @ s2<- op 5033 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 5034 GET_INST_OPCODE ip @ extract opcode from rINST 5035 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 5036 fstd d2, [r9] @ vAA<- d2 5037 GOTO_OPCODE ip @ jump to next instruction 5038 5039 5040/* ------------------------------ */ 5041 .balign 128 5042.L_op_div_double: /* 0xae */ 5043/* File: arm/op_div_double.S */ 5044/* File: arm/fbinopWide.S */ 5045 /* 5046 * Generic 64-bit double-precision floating point binary operation. 5047 * Provide an "instr" line that specifies an instruction that performs 5048 * "d2 = d0 op d1". 5049 * 5050 * for: add-double, sub-double, mul-double, div-double 5051 */ 5052 /* doubleop vAA, vBB, vCC */ 5053 FETCH r0, 1 @ r0<- CCBB 5054 mov r9, rINST, lsr #8 @ r9<- AA 5055 mov r3, r0, lsr #8 @ r3<- CC 5056 and r2, r0, #255 @ r2<- BB 5057 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vCC 5058 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &vBB 5059 fldd d1, [r3] @ d1<- vCC 5060 fldd d0, [r2] @ d0<- vBB 5061 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 5062 fdivd d2, d0, d1 @ s2<- op 5063 CLEAR_SHADOW_PAIR r9, ip, lr @ Zero shadow regs 5064 GET_INST_OPCODE ip @ extract opcode from rINST 5065 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vAA 5066 fstd d2, [r9] @ vAA<- d2 5067 GOTO_OPCODE ip @ jump to next instruction 5068 5069 5070/* ------------------------------ */ 5071 .balign 128 5072.L_op_rem_double: /* 0xaf */ 5073/* File: arm/op_rem_double.S */ 5074/* EABI doesn't define a double remainder function, but libm does */ 5075/* File: arm/binopWide.S */ 5076 /* 5077 * Generic 64-bit binary operation. Provide an "instr" line that 5078 * specifies an instruction that performs "result = r0-r1 op r2-r3". 5079 * This could be an ARM instruction or a function call. (If the result 5080 * comes back in a register other than r0, you can override "result".) 5081 * 5082 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5083 * vCC (r1). Useful for integer division and modulus. 5084 * 5085 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5086 * xor-long, add-double, sub-double, mul-double, div-double, 5087 * rem-double 5088 * 5089 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5090 */ 5091 /* binop vAA, vBB, vCC */ 5092 FETCH r0, 1 @ r0<- CCBB 5093 mov rINST, rINST, lsr #8 @ rINST<- AA 5094 and r2, r0, #255 @ r2<- BB 5095 mov r3, r0, lsr #8 @ r3<- CC 5096 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[AA] 5097 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[BB] 5098 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &fp[CC] 5099 ldmia r2, {r0-r1} @ r0/r1<- vBB/vBB+1 5100 ldmia r3, {r2-r3} @ r2/r3<- vCC/vCC+1 5101 .if 0 5102 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5103 beq common_errDivideByZero 5104 .endif 5105 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs 5106 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 5107 @ optional op; may set condition codes 5108 bl fmod @ result<- op, r0-r3 changed 5109 GET_INST_OPCODE ip @ extract opcode from rINST 5110 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5111 GOTO_OPCODE ip @ jump to next instruction 5112 /* 14-17 instructions */ 5113 5114 5115/* ------------------------------ */ 5116 .balign 128 5117.L_op_add_int_2addr: /* 0xb0 */ 5118/* File: arm/op_add_int_2addr.S */ 5119/* File: arm/binop2addr.S */ 5120 /* 5121 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5122 * that specifies an instruction that performs "result = r0 op r1". 5123 * This could be an ARM instruction or a function call. (If the result 5124 * comes back in a register other than r0, you can override "result".) 5125 * 5126 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5127 * vCC (r1). Useful for integer division and modulus. 5128 * 5129 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5130 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5131 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5132 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5133 */ 5134 /* binop/2addr vA, vB */ 5135 mov r3, rINST, lsr #12 @ r3<- B 5136 ubfx r9, rINST, #8, #4 @ r9<- A 5137 GET_VREG r1, r3 @ r1<- vB 5138 GET_VREG r0, r9 @ r0<- vA 5139 .if 0 5140 cmp r1, #0 @ is second operand zero? 5141 beq common_errDivideByZero 5142 .endif 5143 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5144 5145 @ optional op; may set condition codes 5146 add r0, r0, r1 @ r0<- op, r0-r3 changed 5147 GET_INST_OPCODE ip @ extract opcode from rINST 5148 SET_VREG r0, r9 @ vAA<- r0 5149 GOTO_OPCODE ip @ jump to next instruction 5150 /* 10-13 instructions */ 5151 5152 5153/* ------------------------------ */ 5154 .balign 128 5155.L_op_sub_int_2addr: /* 0xb1 */ 5156/* File: arm/op_sub_int_2addr.S */ 5157/* File: arm/binop2addr.S */ 5158 /* 5159 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5160 * that specifies an instruction that performs "result = r0 op r1". 5161 * This could be an ARM instruction or a function call. (If the result 5162 * comes back in a register other than r0, you can override "result".) 5163 * 5164 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5165 * vCC (r1). Useful for integer division and modulus. 5166 * 5167 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5168 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5169 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5170 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5171 */ 5172 /* binop/2addr vA, vB */ 5173 mov r3, rINST, lsr #12 @ r3<- B 5174 ubfx r9, rINST, #8, #4 @ r9<- A 5175 GET_VREG r1, r3 @ r1<- vB 5176 GET_VREG r0, r9 @ r0<- vA 5177 .if 0 5178 cmp r1, #0 @ is second operand zero? 5179 beq common_errDivideByZero 5180 .endif 5181 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5182 5183 @ optional op; may set condition codes 5184 sub r0, r0, r1 @ r0<- op, r0-r3 changed 5185 GET_INST_OPCODE ip @ extract opcode from rINST 5186 SET_VREG r0, r9 @ vAA<- r0 5187 GOTO_OPCODE ip @ jump to next instruction 5188 /* 10-13 instructions */ 5189 5190 5191/* ------------------------------ */ 5192 .balign 128 5193.L_op_mul_int_2addr: /* 0xb2 */ 5194/* File: arm/op_mul_int_2addr.S */ 5195/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 5196/* File: arm/binop2addr.S */ 5197 /* 5198 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5199 * that specifies an instruction that performs "result = r0 op r1". 5200 * This could be an ARM instruction or a function call. (If the result 5201 * comes back in a register other than r0, you can override "result".) 5202 * 5203 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5204 * vCC (r1). Useful for integer division and modulus. 5205 * 5206 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5207 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5208 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5209 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5210 */ 5211 /* binop/2addr vA, vB */ 5212 mov r3, rINST, lsr #12 @ r3<- B 5213 ubfx r9, rINST, #8, #4 @ r9<- A 5214 GET_VREG r1, r3 @ r1<- vB 5215 GET_VREG r0, r9 @ r0<- vA 5216 .if 0 5217 cmp r1, #0 @ is second operand zero? 5218 beq common_errDivideByZero 5219 .endif 5220 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5221 5222 @ optional op; may set condition codes 5223 mul r0, r1, r0 @ r0<- op, r0-r3 changed 5224 GET_INST_OPCODE ip @ extract opcode from rINST 5225 SET_VREG r0, r9 @ vAA<- r0 5226 GOTO_OPCODE ip @ jump to next instruction 5227 /* 10-13 instructions */ 5228 5229 5230/* ------------------------------ */ 5231 .balign 128 5232.L_op_div_int_2addr: /* 0xb3 */ 5233/* File: arm/op_div_int_2addr.S */ 5234 /* 5235 * Specialized 32-bit binary operation 5236 * 5237 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper 5238 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 5239 * ARMv7 CPUs that have hardware division support). 5240 * 5241 * div-int/2addr 5242 * 5243 */ 5244 mov r3, rINST, lsr #12 @ r3<- B 5245 ubfx r9, rINST, #8, #4 @ r9<- A 5246 GET_VREG r1, r3 @ r1<- vB 5247 GET_VREG r0, r9 @ r0<- vA 5248 cmp r1, #0 @ is second operand zero? 5249 beq common_errDivideByZero 5250 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5251 5252#ifdef __ARM_ARCH_EXT_IDIV__ 5253 sdiv r0, r0, r1 @ r0<- op 5254#else 5255 bl __aeabi_idiv @ r0<- op, r0-r3 changed 5256#endif 5257 GET_INST_OPCODE ip @ extract opcode from rINST 5258 SET_VREG r0, r9 @ vAA<- r0 5259 GOTO_OPCODE ip @ jump to next instruction 5260 /* 10-13 instructions */ 5261 5262 5263/* ------------------------------ */ 5264 .balign 128 5265.L_op_rem_int_2addr: /* 0xb4 */ 5266/* File: arm/op_rem_int_2addr.S */ 5267 /* 5268 * Specialized 32-bit binary operation 5269 * 5270 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 5271 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 5272 * ARMv7 CPUs that have hardware division support). 5273 * 5274 * NOTE: idivmod returns quotient in r0 and remainder in r1 5275 * 5276 * rem-int/2addr 5277 * 5278 */ 5279 mov r3, rINST, lsr #12 @ r3<- B 5280 ubfx r9, rINST, #8, #4 @ r9<- A 5281 GET_VREG r1, r3 @ r1<- vB 5282 GET_VREG r0, r9 @ r0<- vA 5283 cmp r1, #0 @ is second operand zero? 5284 beq common_errDivideByZero 5285 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5286 5287#ifdef __ARM_ARCH_EXT_IDIV__ 5288 sdiv r2, r0, r1 5289 mls r1, r1, r2, r0 @ r1<- op 5290#else 5291 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 5292#endif 5293 GET_INST_OPCODE ip @ extract opcode from rINST 5294 SET_VREG r1, r9 @ vAA<- r1 5295 GOTO_OPCODE ip @ jump to next instruction 5296 /* 10-13 instructions */ 5297 5298 5299/* ------------------------------ */ 5300 .balign 128 5301.L_op_and_int_2addr: /* 0xb5 */ 5302/* File: arm/op_and_int_2addr.S */ 5303/* File: arm/binop2addr.S */ 5304 /* 5305 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5306 * that specifies an instruction that performs "result = r0 op r1". 5307 * This could be an ARM instruction or a function call. (If the result 5308 * comes back in a register other than r0, you can override "result".) 5309 * 5310 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5311 * vCC (r1). Useful for integer division and modulus. 5312 * 5313 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5314 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5315 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5316 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5317 */ 5318 /* binop/2addr vA, vB */ 5319 mov r3, rINST, lsr #12 @ r3<- B 5320 ubfx r9, rINST, #8, #4 @ r9<- A 5321 GET_VREG r1, r3 @ r1<- vB 5322 GET_VREG r0, r9 @ r0<- vA 5323 .if 0 5324 cmp r1, #0 @ is second operand zero? 5325 beq common_errDivideByZero 5326 .endif 5327 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5328 5329 @ optional op; may set condition codes 5330 and r0, r0, r1 @ r0<- op, r0-r3 changed 5331 GET_INST_OPCODE ip @ extract opcode from rINST 5332 SET_VREG r0, r9 @ vAA<- r0 5333 GOTO_OPCODE ip @ jump to next instruction 5334 /* 10-13 instructions */ 5335 5336 5337/* ------------------------------ */ 5338 .balign 128 5339.L_op_or_int_2addr: /* 0xb6 */ 5340/* File: arm/op_or_int_2addr.S */ 5341/* File: arm/binop2addr.S */ 5342 /* 5343 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5344 * that specifies an instruction that performs "result = r0 op r1". 5345 * This could be an ARM instruction or a function call. (If the result 5346 * comes back in a register other than r0, you can override "result".) 5347 * 5348 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5349 * vCC (r1). Useful for integer division and modulus. 5350 * 5351 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5352 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5353 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5354 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5355 */ 5356 /* binop/2addr vA, vB */ 5357 mov r3, rINST, lsr #12 @ r3<- B 5358 ubfx r9, rINST, #8, #4 @ r9<- A 5359 GET_VREG r1, r3 @ r1<- vB 5360 GET_VREG r0, r9 @ r0<- vA 5361 .if 0 5362 cmp r1, #0 @ is second operand zero? 5363 beq common_errDivideByZero 5364 .endif 5365 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5366 5367 @ optional op; may set condition codes 5368 orr r0, r0, r1 @ r0<- op, r0-r3 changed 5369 GET_INST_OPCODE ip @ extract opcode from rINST 5370 SET_VREG r0, r9 @ vAA<- r0 5371 GOTO_OPCODE ip @ jump to next instruction 5372 /* 10-13 instructions */ 5373 5374 5375/* ------------------------------ */ 5376 .balign 128 5377.L_op_xor_int_2addr: /* 0xb7 */ 5378/* File: arm/op_xor_int_2addr.S */ 5379/* File: arm/binop2addr.S */ 5380 /* 5381 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5382 * that specifies an instruction that performs "result = r0 op r1". 5383 * This could be an ARM instruction or a function call. (If the result 5384 * comes back in a register other than r0, you can override "result".) 5385 * 5386 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5387 * vCC (r1). Useful for integer division and modulus. 5388 * 5389 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5390 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5391 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5392 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5393 */ 5394 /* binop/2addr vA, vB */ 5395 mov r3, rINST, lsr #12 @ r3<- B 5396 ubfx r9, rINST, #8, #4 @ r9<- A 5397 GET_VREG r1, r3 @ r1<- vB 5398 GET_VREG r0, r9 @ r0<- vA 5399 .if 0 5400 cmp r1, #0 @ is second operand zero? 5401 beq common_errDivideByZero 5402 .endif 5403 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5404 5405 @ optional op; may set condition codes 5406 eor r0, r0, r1 @ r0<- op, r0-r3 changed 5407 GET_INST_OPCODE ip @ extract opcode from rINST 5408 SET_VREG r0, r9 @ vAA<- r0 5409 GOTO_OPCODE ip @ jump to next instruction 5410 /* 10-13 instructions */ 5411 5412 5413/* ------------------------------ */ 5414 .balign 128 5415.L_op_shl_int_2addr: /* 0xb8 */ 5416/* File: arm/op_shl_int_2addr.S */ 5417/* File: arm/binop2addr.S */ 5418 /* 5419 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5420 * that specifies an instruction that performs "result = r0 op r1". 5421 * This could be an ARM instruction or a function call. (If the result 5422 * comes back in a register other than r0, you can override "result".) 5423 * 5424 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5425 * vCC (r1). Useful for integer division and modulus. 5426 * 5427 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5428 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5429 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5430 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5431 */ 5432 /* binop/2addr vA, vB */ 5433 mov r3, rINST, lsr #12 @ r3<- B 5434 ubfx r9, rINST, #8, #4 @ r9<- A 5435 GET_VREG r1, r3 @ r1<- vB 5436 GET_VREG r0, r9 @ r0<- vA 5437 .if 0 5438 cmp r1, #0 @ is second operand zero? 5439 beq common_errDivideByZero 5440 .endif 5441 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5442 5443 and r1, r1, #31 @ optional op; may set condition codes 5444 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 5445 GET_INST_OPCODE ip @ extract opcode from rINST 5446 SET_VREG r0, r9 @ vAA<- r0 5447 GOTO_OPCODE ip @ jump to next instruction 5448 /* 10-13 instructions */ 5449 5450 5451/* ------------------------------ */ 5452 .balign 128 5453.L_op_shr_int_2addr: /* 0xb9 */ 5454/* File: arm/op_shr_int_2addr.S */ 5455/* File: arm/binop2addr.S */ 5456 /* 5457 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5458 * that specifies an instruction that performs "result = r0 op r1". 5459 * This could be an ARM instruction or a function call. (If the result 5460 * comes back in a register other than r0, you can override "result".) 5461 * 5462 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5463 * vCC (r1). Useful for integer division and modulus. 5464 * 5465 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5466 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5467 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5468 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5469 */ 5470 /* binop/2addr vA, vB */ 5471 mov r3, rINST, lsr #12 @ r3<- B 5472 ubfx r9, rINST, #8, #4 @ r9<- A 5473 GET_VREG r1, r3 @ r1<- vB 5474 GET_VREG r0, r9 @ r0<- vA 5475 .if 0 5476 cmp r1, #0 @ is second operand zero? 5477 beq common_errDivideByZero 5478 .endif 5479 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5480 5481 and r1, r1, #31 @ optional op; may set condition codes 5482 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 5483 GET_INST_OPCODE ip @ extract opcode from rINST 5484 SET_VREG r0, r9 @ vAA<- r0 5485 GOTO_OPCODE ip @ jump to next instruction 5486 /* 10-13 instructions */ 5487 5488 5489/* ------------------------------ */ 5490 .balign 128 5491.L_op_ushr_int_2addr: /* 0xba */ 5492/* File: arm/op_ushr_int_2addr.S */ 5493/* File: arm/binop2addr.S */ 5494 /* 5495 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5496 * that specifies an instruction that performs "result = r0 op r1". 5497 * This could be an ARM instruction or a function call. (If the result 5498 * comes back in a register other than r0, you can override "result".) 5499 * 5500 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5501 * vCC (r1). Useful for integer division and modulus. 5502 * 5503 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5504 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5505 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 5506 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 5507 */ 5508 /* binop/2addr vA, vB */ 5509 mov r3, rINST, lsr #12 @ r3<- B 5510 ubfx r9, rINST, #8, #4 @ r9<- A 5511 GET_VREG r1, r3 @ r1<- vB 5512 GET_VREG r0, r9 @ r0<- vA 5513 .if 0 5514 cmp r1, #0 @ is second operand zero? 5515 beq common_errDivideByZero 5516 .endif 5517 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5518 5519 and r1, r1, #31 @ optional op; may set condition codes 5520 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 5521 GET_INST_OPCODE ip @ extract opcode from rINST 5522 SET_VREG r0, r9 @ vAA<- r0 5523 GOTO_OPCODE ip @ jump to next instruction 5524 /* 10-13 instructions */ 5525 5526 5527/* ------------------------------ */ 5528 .balign 128 5529.L_op_add_long_2addr: /* 0xbb */ 5530/* File: arm/op_add_long_2addr.S */ 5531/* File: arm/binopWide2addr.S */ 5532 /* 5533 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5534 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5535 * This could be an ARM instruction or a function call. (If the result 5536 * comes back in a register other than r0, you can override "result".) 5537 * 5538 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5539 * vCC (r1). Useful for integer division and modulus. 5540 * 5541 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5542 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5543 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5544 * rem-double/2addr 5545 */ 5546 /* binop/2addr vA, vB */ 5547 mov r1, rINST, lsr #12 @ r1<- B 5548 ubfx rINST, rINST, #8, #4 @ rINST<- A 5549 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5550 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5551 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5552 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5553 .if 0 5554 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5555 beq common_errDivideByZero 5556 .endif 5557 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5558 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5559 adds r0, r0, r2 @ optional op; may set condition codes 5560 adc r1, r1, r3 @ result<- op, r0-r3 changed 5561 GET_INST_OPCODE ip @ extract opcode from rINST 5562 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5563 GOTO_OPCODE ip @ jump to next instruction 5564 /* 12-15 instructions */ 5565 5566 5567/* ------------------------------ */ 5568 .balign 128 5569.L_op_sub_long_2addr: /* 0xbc */ 5570/* File: arm/op_sub_long_2addr.S */ 5571/* File: arm/binopWide2addr.S */ 5572 /* 5573 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5574 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5575 * This could be an ARM instruction or a function call. (If the result 5576 * comes back in a register other than r0, you can override "result".) 5577 * 5578 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5579 * vCC (r1). Useful for integer division and modulus. 5580 * 5581 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5582 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5583 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5584 * rem-double/2addr 5585 */ 5586 /* binop/2addr vA, vB */ 5587 mov r1, rINST, lsr #12 @ r1<- B 5588 ubfx rINST, rINST, #8, #4 @ rINST<- A 5589 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5590 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5591 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5592 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5593 .if 0 5594 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5595 beq common_errDivideByZero 5596 .endif 5597 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5598 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5599 subs r0, r0, r2 @ optional op; may set condition codes 5600 sbc r1, r1, r3 @ result<- op, r0-r3 changed 5601 GET_INST_OPCODE ip @ extract opcode from rINST 5602 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5603 GOTO_OPCODE ip @ jump to next instruction 5604 /* 12-15 instructions */ 5605 5606 5607/* ------------------------------ */ 5608 .balign 128 5609.L_op_mul_long_2addr: /* 0xbd */ 5610/* File: arm/op_mul_long_2addr.S */ 5611 /* 5612 * Signed 64-bit integer multiply, "/2addr" version. 5613 * 5614 * See op_mul_long for an explanation. 5615 * 5616 * We get a little tight on registers, so to avoid looking up &fp[A] 5617 * again we stuff it into rINST. 5618 */ 5619 /* mul-long/2addr vA, vB */ 5620 mov r1, rINST, lsr #12 @ r1<- B 5621 ubfx r9, rINST, #8, #4 @ r9<- A 5622 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5623 VREG_INDEX_TO_ADDR rINST, r9 @ rINST<- &fp[A] 5624 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5625 ldmia rINST, {r0-r1} @ r0/r1<- vAA/vAA+1 5626 mul ip, r2, r1 @ ip<- ZxW 5627 umull r1, lr, r2, r0 @ r1/lr <- ZxX 5628 mla r2, r0, r3, ip @ r2<- YxX + (ZxW) 5629 mov r0, rINST @ r0<- &fp[A] (free up rINST) 5630 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5631 add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX)) 5632 GET_INST_OPCODE ip @ extract opcode from rINST 5633 stmia r0, {r1-r2} @ vAA/vAA+1<- r1/r2 5634 GOTO_OPCODE ip @ jump to next instruction 5635 5636/* ------------------------------ */ 5637 .balign 128 5638.L_op_div_long_2addr: /* 0xbe */ 5639/* File: arm/op_div_long_2addr.S */ 5640/* File: arm/binopWide2addr.S */ 5641 /* 5642 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5643 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5644 * This could be an ARM instruction or a function call. (If the result 5645 * comes back in a register other than r0, you can override "result".) 5646 * 5647 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5648 * vCC (r1). Useful for integer division and modulus. 5649 * 5650 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5651 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5652 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5653 * rem-double/2addr 5654 */ 5655 /* binop/2addr vA, vB */ 5656 mov r1, rINST, lsr #12 @ r1<- B 5657 ubfx rINST, rINST, #8, #4 @ rINST<- A 5658 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5659 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5660 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5661 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5662 .if 1 5663 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5664 beq common_errDivideByZero 5665 .endif 5666 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5667 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5668 @ optional op; may set condition codes 5669 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5670 GET_INST_OPCODE ip @ extract opcode from rINST 5671 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5672 GOTO_OPCODE ip @ jump to next instruction 5673 /* 12-15 instructions */ 5674 5675 5676/* ------------------------------ */ 5677 .balign 128 5678.L_op_rem_long_2addr: /* 0xbf */ 5679/* File: arm/op_rem_long_2addr.S */ 5680/* ldivmod returns quotient in r0/r1 and remainder in r2/r3 */ 5681/* File: arm/binopWide2addr.S */ 5682 /* 5683 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5684 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5685 * This could be an ARM instruction or a function call. (If the result 5686 * comes back in a register other than r0, you can override "result".) 5687 * 5688 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5689 * vCC (r1). Useful for integer division and modulus. 5690 * 5691 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5692 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5693 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5694 * rem-double/2addr 5695 */ 5696 /* binop/2addr vA, vB */ 5697 mov r1, rINST, lsr #12 @ r1<- B 5698 ubfx rINST, rINST, #8, #4 @ rINST<- A 5699 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5700 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5701 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5702 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5703 .if 1 5704 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5705 beq common_errDivideByZero 5706 .endif 5707 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5708 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5709 @ optional op; may set condition codes 5710 bl __aeabi_ldivmod @ result<- op, r0-r3 changed 5711 GET_INST_OPCODE ip @ extract opcode from rINST 5712 stmia r9, {r2,r3} @ vAA/vAA+1<- r2/r3 5713 GOTO_OPCODE ip @ jump to next instruction 5714 /* 12-15 instructions */ 5715 5716 5717/* ------------------------------ */ 5718 .balign 128 5719.L_op_and_long_2addr: /* 0xc0 */ 5720/* File: arm/op_and_long_2addr.S */ 5721/* File: arm/binopWide2addr.S */ 5722 /* 5723 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5724 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5725 * This could be an ARM instruction or a function call. (If the result 5726 * comes back in a register other than r0, you can override "result".) 5727 * 5728 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5729 * vCC (r1). Useful for integer division and modulus. 5730 * 5731 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5732 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5733 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5734 * rem-double/2addr 5735 */ 5736 /* binop/2addr vA, vB */ 5737 mov r1, rINST, lsr #12 @ r1<- B 5738 ubfx rINST, rINST, #8, #4 @ rINST<- A 5739 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5740 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5741 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5742 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5743 .if 0 5744 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5745 beq common_errDivideByZero 5746 .endif 5747 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5748 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5749 and r0, r0, r2 @ optional op; may set condition codes 5750 and r1, r1, r3 @ result<- op, r0-r3 changed 5751 GET_INST_OPCODE ip @ extract opcode from rINST 5752 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5753 GOTO_OPCODE ip @ jump to next instruction 5754 /* 12-15 instructions */ 5755 5756 5757/* ------------------------------ */ 5758 .balign 128 5759.L_op_or_long_2addr: /* 0xc1 */ 5760/* File: arm/op_or_long_2addr.S */ 5761/* File: arm/binopWide2addr.S */ 5762 /* 5763 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5764 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5765 * This could be an ARM instruction or a function call. (If the result 5766 * comes back in a register other than r0, you can override "result".) 5767 * 5768 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5769 * vCC (r1). Useful for integer division and modulus. 5770 * 5771 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5772 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5773 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5774 * rem-double/2addr 5775 */ 5776 /* binop/2addr vA, vB */ 5777 mov r1, rINST, lsr #12 @ r1<- B 5778 ubfx rINST, rINST, #8, #4 @ rINST<- A 5779 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5780 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5781 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5782 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5783 .if 0 5784 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5785 beq common_errDivideByZero 5786 .endif 5787 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5788 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5789 orr r0, r0, r2 @ optional op; may set condition codes 5790 orr r1, r1, r3 @ result<- op, r0-r3 changed 5791 GET_INST_OPCODE ip @ extract opcode from rINST 5792 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5793 GOTO_OPCODE ip @ jump to next instruction 5794 /* 12-15 instructions */ 5795 5796 5797/* ------------------------------ */ 5798 .balign 128 5799.L_op_xor_long_2addr: /* 0xc2 */ 5800/* File: arm/op_xor_long_2addr.S */ 5801/* File: arm/binopWide2addr.S */ 5802 /* 5803 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5804 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 5805 * This could be an ARM instruction or a function call. (If the result 5806 * comes back in a register other than r0, you can override "result".) 5807 * 5808 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5809 * vCC (r1). Useful for integer division and modulus. 5810 * 5811 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5812 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 5813 * sub-double/2addr, mul-double/2addr, div-double/2addr, 5814 * rem-double/2addr 5815 */ 5816 /* binop/2addr vA, vB */ 5817 mov r1, rINST, lsr #12 @ r1<- B 5818 ubfx rINST, rINST, #8, #4 @ rINST<- A 5819 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 5820 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 5821 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 5822 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5823 .if 0 5824 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 5825 beq common_errDivideByZero 5826 .endif 5827 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 5828 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5829 eor r0, r0, r2 @ optional op; may set condition codes 5830 eor r1, r1, r3 @ result<- op, r0-r3 changed 5831 GET_INST_OPCODE ip @ extract opcode from rINST 5832 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 5833 GOTO_OPCODE ip @ jump to next instruction 5834 /* 12-15 instructions */ 5835 5836 5837/* ------------------------------ */ 5838 .balign 128 5839.L_op_shl_long_2addr: /* 0xc3 */ 5840/* File: arm/op_shl_long_2addr.S */ 5841 /* 5842 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5843 * 32-bit shift distance. 5844 */ 5845 /* shl-long/2addr vA, vB */ 5846 mov r3, rINST, lsr #12 @ r3<- B 5847 ubfx r9, rINST, #8, #4 @ r9<- A 5848 GET_VREG r2, r3 @ r2<- vB 5849 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 5850 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] 5851 and r2, r2, #63 @ r2<- r2 & 0x3f 5852 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5853 mov r1, r1, asl r2 @ r1<- r1 << r2 5854 rsb r3, r2, #32 @ r3<- 32 - r2 5855 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2)) 5856 subs ip, r2, #32 @ ip<- r2 - 32 5857 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5858 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32) 5859 mov r0, r0, asl r2 @ r0<- r0 << r2 5860 GET_INST_OPCODE ip @ extract opcode from rINST 5861 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 5862 GOTO_OPCODE ip @ jump to next instruction 5863 5864/* ------------------------------ */ 5865 .balign 128 5866.L_op_shr_long_2addr: /* 0xc4 */ 5867/* File: arm/op_shr_long_2addr.S */ 5868 /* 5869 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5870 * 32-bit shift distance. 5871 */ 5872 /* shr-long/2addr vA, vB */ 5873 mov r3, rINST, lsr #12 @ r3<- B 5874 ubfx r9, rINST, #8, #4 @ r9<- A 5875 GET_VREG r2, r3 @ r2<- vB 5876 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 5877 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] 5878 and r2, r2, #63 @ r2<- r2 & 0x3f 5879 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5880 mov r0, r0, lsr r2 @ r0<- r2 >> r2 5881 rsb r3, r2, #32 @ r3<- 32 - r2 5882 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 5883 subs ip, r2, #32 @ ip<- r2 - 32 5884 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5885 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32) 5886 mov r1, r1, asr r2 @ r1<- r1 >> r2 5887 GET_INST_OPCODE ip @ extract opcode from rINST 5888 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 5889 GOTO_OPCODE ip @ jump to next instruction 5890 5891/* ------------------------------ */ 5892 .balign 128 5893.L_op_ushr_long_2addr: /* 0xc5 */ 5894/* File: arm/op_ushr_long_2addr.S */ 5895 /* 5896 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 5897 * 32-bit shift distance. 5898 */ 5899 /* ushr-long/2addr vA, vB */ 5900 mov r3, rINST, lsr #12 @ r3<- B 5901 ubfx r9, rINST, #8, #4 @ r9<- A 5902 GET_VREG r2, r3 @ r2<- vB 5903 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs 5904 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &fp[A] 5905 and r2, r2, #63 @ r2<- r2 & 0x3f 5906 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 5907 mov r0, r0, lsr r2 @ r0<- r2 >> r2 5908 rsb r3, r2, #32 @ r3<- 32 - r2 5909 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2)) 5910 subs ip, r2, #32 @ ip<- r2 - 32 5911 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5912 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32) 5913 mov r1, r1, lsr r2 @ r1<- r1 >>> r2 5914 GET_INST_OPCODE ip @ extract opcode from rINST 5915 stmia r9, {r0-r1} @ vAA/vAA+1<- r0/r1 5916 GOTO_OPCODE ip @ jump to next instruction 5917 5918/* ------------------------------ */ 5919 .balign 128 5920.L_op_add_float_2addr: /* 0xc6 */ 5921/* File: arm/op_add_float_2addr.S */ 5922/* File: arm/fbinop2addr.S */ 5923 /* 5924 * Generic 32-bit floating point "/2addr" binary operation. Provide 5925 * an "instr" line that specifies an instruction that performs 5926 * "s2 = s0 op s1". 5927 * 5928 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5929 */ 5930 /* binop/2addr vA, vB */ 5931 mov r3, rINST, lsr #12 @ r3<- B 5932 ubfx r9, rINST, #8, #4 @ r9<- A 5933 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 5934 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 5935 flds s1, [r3] @ s1<- vB 5936 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5937 flds s0, [r9] @ s0<- vA 5938 fadds s2, s0, s1 @ s2<- op 5939 GET_INST_OPCODE ip @ extract opcode from rINST 5940 fsts s2, [r9] @ vAA<- s2 5941 GOTO_OPCODE ip @ jump to next instruction 5942 5943 5944/* ------------------------------ */ 5945 .balign 128 5946.L_op_sub_float_2addr: /* 0xc7 */ 5947/* File: arm/op_sub_float_2addr.S */ 5948/* File: arm/fbinop2addr.S */ 5949 /* 5950 * Generic 32-bit floating point "/2addr" binary operation. Provide 5951 * an "instr" line that specifies an instruction that performs 5952 * "s2 = s0 op s1". 5953 * 5954 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5955 */ 5956 /* binop/2addr vA, vB */ 5957 mov r3, rINST, lsr #12 @ r3<- B 5958 ubfx r9, rINST, #8, #4 @ r9<- A 5959 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 5960 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 5961 flds s1, [r3] @ s1<- vB 5962 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5963 flds s0, [r9] @ s0<- vA 5964 fsubs s2, s0, s1 @ s2<- op 5965 GET_INST_OPCODE ip @ extract opcode from rINST 5966 fsts s2, [r9] @ vAA<- s2 5967 GOTO_OPCODE ip @ jump to next instruction 5968 5969 5970/* ------------------------------ */ 5971 .balign 128 5972.L_op_mul_float_2addr: /* 0xc8 */ 5973/* File: arm/op_mul_float_2addr.S */ 5974/* File: arm/fbinop2addr.S */ 5975 /* 5976 * Generic 32-bit floating point "/2addr" binary operation. Provide 5977 * an "instr" line that specifies an instruction that performs 5978 * "s2 = s0 op s1". 5979 * 5980 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 5981 */ 5982 /* binop/2addr vA, vB */ 5983 mov r3, rINST, lsr #12 @ r3<- B 5984 ubfx r9, rINST, #8, #4 @ r9<- A 5985 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 5986 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 5987 flds s1, [r3] @ s1<- vB 5988 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 5989 flds s0, [r9] @ s0<- vA 5990 fmuls s2, s0, s1 @ s2<- op 5991 GET_INST_OPCODE ip @ extract opcode from rINST 5992 fsts s2, [r9] @ vAA<- s2 5993 GOTO_OPCODE ip @ jump to next instruction 5994 5995 5996/* ------------------------------ */ 5997 .balign 128 5998.L_op_div_float_2addr: /* 0xc9 */ 5999/* File: arm/op_div_float_2addr.S */ 6000/* File: arm/fbinop2addr.S */ 6001 /* 6002 * Generic 32-bit floating point "/2addr" binary operation. Provide 6003 * an "instr" line that specifies an instruction that performs 6004 * "s2 = s0 op s1". 6005 * 6006 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr 6007 */ 6008 /* binop/2addr vA, vB */ 6009 mov r3, rINST, lsr #12 @ r3<- B 6010 ubfx r9, rINST, #8, #4 @ r9<- A 6011 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 6012 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 6013 flds s1, [r3] @ s1<- vB 6014 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6015 flds s0, [r9] @ s0<- vA 6016 fdivs s2, s0, s1 @ s2<- op 6017 GET_INST_OPCODE ip @ extract opcode from rINST 6018 fsts s2, [r9] @ vAA<- s2 6019 GOTO_OPCODE ip @ jump to next instruction 6020 6021 6022/* ------------------------------ */ 6023 .balign 128 6024.L_op_rem_float_2addr: /* 0xca */ 6025/* File: arm/op_rem_float_2addr.S */ 6026/* EABI doesn't define a float remainder function, but libm does */ 6027/* File: arm/binop2addr.S */ 6028 /* 6029 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 6030 * that specifies an instruction that performs "result = r0 op r1". 6031 * This could be an ARM instruction or a function call. (If the result 6032 * comes back in a register other than r0, you can override "result".) 6033 * 6034 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6035 * vCC (r1). Useful for integer division and modulus. 6036 * 6037 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 6038 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 6039 * shl-int/2addr, shr-int/2addr, ushr-int/2addr, add-float/2addr, 6040 * sub-float/2addr, mul-float/2addr, div-float/2addr, rem-float/2addr 6041 */ 6042 /* binop/2addr vA, vB */ 6043 mov r3, rINST, lsr #12 @ r3<- B 6044 ubfx r9, rINST, #8, #4 @ r9<- A 6045 GET_VREG r1, r3 @ r1<- vB 6046 GET_VREG r0, r9 @ r0<- vA 6047 .if 0 6048 cmp r1, #0 @ is second operand zero? 6049 beq common_errDivideByZero 6050 .endif 6051 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6052 6053 @ optional op; may set condition codes 6054 bl fmodf @ r0<- op, r0-r3 changed 6055 GET_INST_OPCODE ip @ extract opcode from rINST 6056 SET_VREG r0, r9 @ vAA<- r0 6057 GOTO_OPCODE ip @ jump to next instruction 6058 /* 10-13 instructions */ 6059 6060 6061/* ------------------------------ */ 6062 .balign 128 6063.L_op_add_double_2addr: /* 0xcb */ 6064/* File: arm/op_add_double_2addr.S */ 6065/* File: arm/fbinopWide2addr.S */ 6066 /* 6067 * Generic 64-bit floating point "/2addr" binary operation. Provide 6068 * an "instr" line that specifies an instruction that performs 6069 * "d2 = d0 op d1". 6070 * 6071 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6072 * div-double/2addr 6073 */ 6074 /* binop/2addr vA, vB */ 6075 mov r3, rINST, lsr #12 @ r3<- B 6076 ubfx r9, rINST, #8, #4 @ r9<- A 6077 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 6078 CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs 6079 fldd d1, [r3] @ d1<- vB 6080 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 6081 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6082 fldd d0, [r9] @ d0<- vA 6083 faddd d2, d0, d1 @ d2<- op 6084 GET_INST_OPCODE ip @ extract opcode from rINST 6085 fstd d2, [r9] @ vAA<- d2 6086 GOTO_OPCODE ip @ jump to next instruction 6087 6088 6089/* ------------------------------ */ 6090 .balign 128 6091.L_op_sub_double_2addr: /* 0xcc */ 6092/* File: arm/op_sub_double_2addr.S */ 6093/* File: arm/fbinopWide2addr.S */ 6094 /* 6095 * Generic 64-bit floating point "/2addr" binary operation. Provide 6096 * an "instr" line that specifies an instruction that performs 6097 * "d2 = d0 op d1". 6098 * 6099 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6100 * div-double/2addr 6101 */ 6102 /* binop/2addr vA, vB */ 6103 mov r3, rINST, lsr #12 @ r3<- B 6104 ubfx r9, rINST, #8, #4 @ r9<- A 6105 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 6106 CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs 6107 fldd d1, [r3] @ d1<- vB 6108 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 6109 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6110 fldd d0, [r9] @ d0<- vA 6111 fsubd d2, d0, d1 @ d2<- op 6112 GET_INST_OPCODE ip @ extract opcode from rINST 6113 fstd d2, [r9] @ vAA<- d2 6114 GOTO_OPCODE ip @ jump to next instruction 6115 6116 6117/* ------------------------------ */ 6118 .balign 128 6119.L_op_mul_double_2addr: /* 0xcd */ 6120/* File: arm/op_mul_double_2addr.S */ 6121/* File: arm/fbinopWide2addr.S */ 6122 /* 6123 * Generic 64-bit floating point "/2addr" binary operation. Provide 6124 * an "instr" line that specifies an instruction that performs 6125 * "d2 = d0 op d1". 6126 * 6127 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6128 * div-double/2addr 6129 */ 6130 /* binop/2addr vA, vB */ 6131 mov r3, rINST, lsr #12 @ r3<- B 6132 ubfx r9, rINST, #8, #4 @ r9<- A 6133 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 6134 CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs 6135 fldd d1, [r3] @ d1<- vB 6136 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 6137 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6138 fldd d0, [r9] @ d0<- vA 6139 fmuld d2, d0, d1 @ d2<- op 6140 GET_INST_OPCODE ip @ extract opcode from rINST 6141 fstd d2, [r9] @ vAA<- d2 6142 GOTO_OPCODE ip @ jump to next instruction 6143 6144 6145/* ------------------------------ */ 6146 .balign 128 6147.L_op_div_double_2addr: /* 0xce */ 6148/* File: arm/op_div_double_2addr.S */ 6149/* File: arm/fbinopWide2addr.S */ 6150 /* 6151 * Generic 64-bit floating point "/2addr" binary operation. Provide 6152 * an "instr" line that specifies an instruction that performs 6153 * "d2 = d0 op d1". 6154 * 6155 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6156 * div-double/2addr 6157 */ 6158 /* binop/2addr vA, vB */ 6159 mov r3, rINST, lsr #12 @ r3<- B 6160 ubfx r9, rINST, #8, #4 @ r9<- A 6161 VREG_INDEX_TO_ADDR r3, r3 @ r3<- &vB 6162 CLEAR_SHADOW_PAIR r9, ip, r0 @ Zero out shadow regs 6163 fldd d1, [r3] @ d1<- vB 6164 VREG_INDEX_TO_ADDR r9, r9 @ r9<- &vA 6165 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6166 fldd d0, [r9] @ d0<- vA 6167 fdivd d2, d0, d1 @ d2<- op 6168 GET_INST_OPCODE ip @ extract opcode from rINST 6169 fstd d2, [r9] @ vAA<- d2 6170 GOTO_OPCODE ip @ jump to next instruction 6171 6172 6173/* ------------------------------ */ 6174 .balign 128 6175.L_op_rem_double_2addr: /* 0xcf */ 6176/* File: arm/op_rem_double_2addr.S */ 6177/* EABI doesn't define a double remainder function, but libm does */ 6178/* File: arm/binopWide2addr.S */ 6179 /* 6180 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6181 * that specifies an instruction that performs "result = r0-r1 op r2-r3". 6182 * This could be an ARM instruction or a function call. (If the result 6183 * comes back in a register other than r0, you can override "result".) 6184 * 6185 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6186 * vCC (r1). Useful for integer division and modulus. 6187 * 6188 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6189 * and-long/2addr, or-long/2addr, xor-long/2addr, add-double/2addr, 6190 * sub-double/2addr, mul-double/2addr, div-double/2addr, 6191 * rem-double/2addr 6192 */ 6193 /* binop/2addr vA, vB */ 6194 mov r1, rINST, lsr #12 @ r1<- B 6195 ubfx rINST, rINST, #8, #4 @ rINST<- A 6196 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B] 6197 VREG_INDEX_TO_ADDR r9, rINST @ r9<- &fp[A] 6198 ldmia r1, {r2-r3} @ r2/r3<- vBB/vBB+1 6199 ldmia r9, {r0-r1} @ r0/r1<- vAA/vAA+1 6200 .if 0 6201 orrs ip, r2, r3 @ second arg (r2-r3) is zero? 6202 beq common_errDivideByZero 6203 .endif 6204 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs 6205 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 6206 @ optional op; may set condition codes 6207 bl fmod @ result<- op, r0-r3 changed 6208 GET_INST_OPCODE ip @ extract opcode from rINST 6209 stmia r9, {r0,r1} @ vAA/vAA+1<- r0/r1 6210 GOTO_OPCODE ip @ jump to next instruction 6211 /* 12-15 instructions */ 6212 6213 6214/* ------------------------------ */ 6215 .balign 128 6216.L_op_add_int_lit16: /* 0xd0 */ 6217/* File: arm/op_add_int_lit16.S */ 6218/* File: arm/binopLit16.S */ 6219 /* 6220 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6221 * that specifies an instruction that performs "result = r0 op r1". 6222 * This could be an ARM instruction or a function call. (If the result 6223 * comes back in a register other than r0, you can override "result".) 6224 * 6225 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6226 * vCC (r1). Useful for integer division and modulus. 6227 * 6228 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6229 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6230 */ 6231 /* binop/lit16 vA, vB, #+CCCC */ 6232 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6233 mov r2, rINST, lsr #12 @ r2<- B 6234 ubfx r9, rINST, #8, #4 @ r9<- A 6235 GET_VREG r0, r2 @ r0<- vB 6236 .if 0 6237 cmp r1, #0 @ is second operand zero? 6238 beq common_errDivideByZero 6239 .endif 6240 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6241 6242 add r0, r0, r1 @ r0<- op, r0-r3 changed 6243 GET_INST_OPCODE ip @ extract opcode from rINST 6244 SET_VREG r0, r9 @ vAA<- r0 6245 GOTO_OPCODE ip @ jump to next instruction 6246 /* 10-13 instructions */ 6247 6248 6249/* ------------------------------ */ 6250 .balign 128 6251.L_op_rsub_int: /* 0xd1 */ 6252/* File: arm/op_rsub_int.S */ 6253/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6254/* File: arm/binopLit16.S */ 6255 /* 6256 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6257 * that specifies an instruction that performs "result = r0 op r1". 6258 * This could be an ARM instruction or a function call. (If the result 6259 * comes back in a register other than r0, you can override "result".) 6260 * 6261 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6262 * vCC (r1). Useful for integer division and modulus. 6263 * 6264 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6265 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6266 */ 6267 /* binop/lit16 vA, vB, #+CCCC */ 6268 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6269 mov r2, rINST, lsr #12 @ r2<- B 6270 ubfx r9, rINST, #8, #4 @ r9<- A 6271 GET_VREG r0, r2 @ r0<- vB 6272 .if 0 6273 cmp r1, #0 @ is second operand zero? 6274 beq common_errDivideByZero 6275 .endif 6276 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6277 6278 rsb r0, r0, r1 @ r0<- op, r0-r3 changed 6279 GET_INST_OPCODE ip @ extract opcode from rINST 6280 SET_VREG r0, r9 @ vAA<- r0 6281 GOTO_OPCODE ip @ jump to next instruction 6282 /* 10-13 instructions */ 6283 6284 6285/* ------------------------------ */ 6286 .balign 128 6287.L_op_mul_int_lit16: /* 0xd2 */ 6288/* File: arm/op_mul_int_lit16.S */ 6289/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6290/* File: arm/binopLit16.S */ 6291 /* 6292 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6293 * that specifies an instruction that performs "result = r0 op r1". 6294 * This could be an ARM instruction or a function call. (If the result 6295 * comes back in a register other than r0, you can override "result".) 6296 * 6297 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6298 * vCC (r1). Useful for integer division and modulus. 6299 * 6300 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6301 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6302 */ 6303 /* binop/lit16 vA, vB, #+CCCC */ 6304 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6305 mov r2, rINST, lsr #12 @ r2<- B 6306 ubfx r9, rINST, #8, #4 @ r9<- A 6307 GET_VREG r0, r2 @ r0<- vB 6308 .if 0 6309 cmp r1, #0 @ is second operand zero? 6310 beq common_errDivideByZero 6311 .endif 6312 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6313 6314 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6315 GET_INST_OPCODE ip @ extract opcode from rINST 6316 SET_VREG r0, r9 @ vAA<- r0 6317 GOTO_OPCODE ip @ jump to next instruction 6318 /* 10-13 instructions */ 6319 6320 6321/* ------------------------------ */ 6322 .balign 128 6323.L_op_div_int_lit16: /* 0xd3 */ 6324/* File: arm/op_div_int_lit16.S */ 6325 /* 6326 * Specialized 32-bit binary operation 6327 * 6328 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper 6329 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 6330 * ARMv7 CPUs that have hardware division support). 6331 * 6332 * div-int/lit16 6333 * 6334 */ 6335 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6336 mov r2, rINST, lsr #12 @ r2<- B 6337 ubfx r9, rINST, #8, #4 @ r9<- A 6338 GET_VREG r0, r2 @ r0<- vB 6339 cmp r1, #0 @ is second operand zero? 6340 beq common_errDivideByZero 6341 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6342 6343#ifdef __ARM_ARCH_EXT_IDIV__ 6344 sdiv r0, r0, r1 @ r0<- op 6345#else 6346 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6347#endif 6348 GET_INST_OPCODE ip @ extract opcode from rINST 6349 SET_VREG r0, r9 @ vAA<- r0 6350 GOTO_OPCODE ip @ jump to next instruction 6351 /* 10-13 instructions */ 6352 6353/* ------------------------------ */ 6354 .balign 128 6355.L_op_rem_int_lit16: /* 0xd4 */ 6356/* File: arm/op_rem_int_lit16.S */ 6357 /* 6358 * Specialized 32-bit binary operation 6359 * 6360 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 6361 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 6362 * ARMv7 CPUs that have hardware division support). 6363 * 6364 * NOTE: idivmod returns quotient in r0 and remainder in r1 6365 * 6366 * rem-int/lit16 6367 * 6368 */ 6369 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6370 mov r2, rINST, lsr #12 @ r2<- B 6371 ubfx r9, rINST, #8, #4 @ r9<- A 6372 GET_VREG r0, r2 @ r0<- vB 6373 cmp r1, #0 @ is second operand zero? 6374 beq common_errDivideByZero 6375 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6376 6377#ifdef __ARM_ARCH_EXT_IDIV__ 6378 sdiv r2, r0, r1 6379 mls r1, r1, r2, r0 @ r1<- op 6380#else 6381 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6382#endif 6383 GET_INST_OPCODE ip @ extract opcode from rINST 6384 SET_VREG r1, r9 @ vAA<- r1 6385 GOTO_OPCODE ip @ jump to next instruction 6386 /* 10-13 instructions */ 6387 6388/* ------------------------------ */ 6389 .balign 128 6390.L_op_and_int_lit16: /* 0xd5 */ 6391/* File: arm/op_and_int_lit16.S */ 6392/* File: arm/binopLit16.S */ 6393 /* 6394 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6395 * that specifies an instruction that performs "result = r0 op r1". 6396 * This could be an ARM instruction or a function call. (If the result 6397 * comes back in a register other than r0, you can override "result".) 6398 * 6399 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6400 * vCC (r1). Useful for integer division and modulus. 6401 * 6402 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6403 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6404 */ 6405 /* binop/lit16 vA, vB, #+CCCC */ 6406 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6407 mov r2, rINST, lsr #12 @ r2<- B 6408 ubfx r9, rINST, #8, #4 @ r9<- A 6409 GET_VREG r0, r2 @ r0<- vB 6410 .if 0 6411 cmp r1, #0 @ is second operand zero? 6412 beq common_errDivideByZero 6413 .endif 6414 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6415 6416 and r0, r0, r1 @ r0<- op, r0-r3 changed 6417 GET_INST_OPCODE ip @ extract opcode from rINST 6418 SET_VREG r0, r9 @ vAA<- r0 6419 GOTO_OPCODE ip @ jump to next instruction 6420 /* 10-13 instructions */ 6421 6422 6423/* ------------------------------ */ 6424 .balign 128 6425.L_op_or_int_lit16: /* 0xd6 */ 6426/* File: arm/op_or_int_lit16.S */ 6427/* File: arm/binopLit16.S */ 6428 /* 6429 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6430 * that specifies an instruction that performs "result = r0 op r1". 6431 * This could be an ARM instruction or a function call. (If the result 6432 * comes back in a register other than r0, you can override "result".) 6433 * 6434 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6435 * vCC (r1). Useful for integer division and modulus. 6436 * 6437 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6438 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6439 */ 6440 /* binop/lit16 vA, vB, #+CCCC */ 6441 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6442 mov r2, rINST, lsr #12 @ r2<- B 6443 ubfx r9, rINST, #8, #4 @ r9<- A 6444 GET_VREG r0, r2 @ r0<- vB 6445 .if 0 6446 cmp r1, #0 @ is second operand zero? 6447 beq common_errDivideByZero 6448 .endif 6449 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6450 6451 orr r0, r0, r1 @ r0<- op, r0-r3 changed 6452 GET_INST_OPCODE ip @ extract opcode from rINST 6453 SET_VREG r0, r9 @ vAA<- r0 6454 GOTO_OPCODE ip @ jump to next instruction 6455 /* 10-13 instructions */ 6456 6457 6458/* ------------------------------ */ 6459 .balign 128 6460.L_op_xor_int_lit16: /* 0xd7 */ 6461/* File: arm/op_xor_int_lit16.S */ 6462/* File: arm/binopLit16.S */ 6463 /* 6464 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6465 * that specifies an instruction that performs "result = r0 op r1". 6466 * This could be an ARM instruction or a function call. (If the result 6467 * comes back in a register other than r0, you can override "result".) 6468 * 6469 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6470 * vCC (r1). Useful for integer division and modulus. 6471 * 6472 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6473 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6474 */ 6475 /* binop/lit16 vA, vB, #+CCCC */ 6476 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended) 6477 mov r2, rINST, lsr #12 @ r2<- B 6478 ubfx r9, rINST, #8, #4 @ r9<- A 6479 GET_VREG r0, r2 @ r0<- vB 6480 .if 0 6481 cmp r1, #0 @ is second operand zero? 6482 beq common_errDivideByZero 6483 .endif 6484 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6485 6486 eor r0, r0, r1 @ r0<- op, r0-r3 changed 6487 GET_INST_OPCODE ip @ extract opcode from rINST 6488 SET_VREG r0, r9 @ vAA<- r0 6489 GOTO_OPCODE ip @ jump to next instruction 6490 /* 10-13 instructions */ 6491 6492 6493/* ------------------------------ */ 6494 .balign 128 6495.L_op_add_int_lit8: /* 0xd8 */ 6496/* File: arm/op_add_int_lit8.S */ 6497/* File: arm/binopLit8.S */ 6498 /* 6499 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6500 * that specifies an instruction that performs "result = r0 op r1". 6501 * This could be an ARM instruction or a function call. (If the result 6502 * comes back in a register other than r0, you can override "result".) 6503 * 6504 * You can override "extract" if the extraction of the literal value 6505 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6506 * can be omitted completely if the shift is embedded in "instr". 6507 * 6508 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6509 * vCC (r1). Useful for integer division and modulus. 6510 * 6511 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6512 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6513 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6514 */ 6515 /* binop/lit8 vAA, vBB, #+CC */ 6516 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6517 mov r9, rINST, lsr #8 @ r9<- AA 6518 and r2, r3, #255 @ r2<- BB 6519 GET_VREG r0, r2 @ r0<- vBB 6520 @ optional; typically r1<- ssssssCC (sign extended) 6521 .if 0 6522 @cmp r1, #0 @ is second operand zero? 6523 beq common_errDivideByZero 6524 .endif 6525 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6526 6527 add r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed 6528 GET_INST_OPCODE ip @ extract opcode from rINST 6529 SET_VREG r0, r9 @ vAA<- r0 6530 GOTO_OPCODE ip @ jump to next instruction 6531 /* 10-12 instructions */ 6532 6533 6534/* ------------------------------ */ 6535 .balign 128 6536.L_op_rsub_int_lit8: /* 0xd9 */ 6537/* File: arm/op_rsub_int_lit8.S */ 6538/* File: arm/binopLit8.S */ 6539 /* 6540 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6541 * that specifies an instruction that performs "result = r0 op r1". 6542 * This could be an ARM instruction or a function call. (If the result 6543 * comes back in a register other than r0, you can override "result".) 6544 * 6545 * You can override "extract" if the extraction of the literal value 6546 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6547 * can be omitted completely if the shift is embedded in "instr". 6548 * 6549 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6550 * vCC (r1). Useful for integer division and modulus. 6551 * 6552 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6553 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6554 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6555 */ 6556 /* binop/lit8 vAA, vBB, #+CC */ 6557 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6558 mov r9, rINST, lsr #8 @ r9<- AA 6559 and r2, r3, #255 @ r2<- BB 6560 GET_VREG r0, r2 @ r0<- vBB 6561 @ optional; typically r1<- ssssssCC (sign extended) 6562 .if 0 6563 @cmp r1, #0 @ is second operand zero? 6564 beq common_errDivideByZero 6565 .endif 6566 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6567 6568 rsb r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed 6569 GET_INST_OPCODE ip @ extract opcode from rINST 6570 SET_VREG r0, r9 @ vAA<- r0 6571 GOTO_OPCODE ip @ jump to next instruction 6572 /* 10-12 instructions */ 6573 6574 6575/* ------------------------------ */ 6576 .balign 128 6577.L_op_mul_int_lit8: /* 0xda */ 6578/* File: arm/op_mul_int_lit8.S */ 6579/* must be "mul r0, r1, r0" -- "r0, r0, r1" is illegal */ 6580/* File: arm/binopLit8.S */ 6581 /* 6582 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6583 * that specifies an instruction that performs "result = r0 op r1". 6584 * This could be an ARM instruction or a function call. (If the result 6585 * comes back in a register other than r0, you can override "result".) 6586 * 6587 * You can override "extract" if the extraction of the literal value 6588 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6589 * can be omitted completely if the shift is embedded in "instr". 6590 * 6591 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6592 * vCC (r1). Useful for integer division and modulus. 6593 * 6594 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6595 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6596 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6597 */ 6598 /* binop/lit8 vAA, vBB, #+CC */ 6599 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6600 mov r9, rINST, lsr #8 @ r9<- AA 6601 and r2, r3, #255 @ r2<- BB 6602 GET_VREG r0, r2 @ r0<- vBB 6603 asr r1, r3, #8 @ optional; typically r1<- ssssssCC (sign extended) 6604 .if 0 6605 @cmp r1, #0 @ is second operand zero? 6606 beq common_errDivideByZero 6607 .endif 6608 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6609 6610 mul r0, r1, r0 @ r0<- op, r0-r3 changed 6611 GET_INST_OPCODE ip @ extract opcode from rINST 6612 SET_VREG r0, r9 @ vAA<- r0 6613 GOTO_OPCODE ip @ jump to next instruction 6614 /* 10-12 instructions */ 6615 6616 6617/* ------------------------------ */ 6618 .balign 128 6619.L_op_div_int_lit8: /* 0xdb */ 6620/* File: arm/op_div_int_lit8.S */ 6621 /* 6622 * Specialized 32-bit binary operation 6623 * 6624 * Performs "r0 = r0 div r1". The selection between sdiv or the gcc helper 6625 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 6626 * ARMv7 CPUs that have hardware division support). 6627 * 6628 * div-int/lit8 6629 * 6630 */ 6631 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC 6632 mov r9, rINST, lsr #8 @ r9<- AA 6633 and r2, r3, #255 @ r2<- BB 6634 GET_VREG r0, r2 @ r0<- vBB 6635 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6636 @cmp r1, #0 @ is second operand zero? 6637 beq common_errDivideByZero 6638 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6639 6640#ifdef __ARM_ARCH_EXT_IDIV__ 6641 sdiv r0, r0, r1 @ r0<- op 6642#else 6643 bl __aeabi_idiv @ r0<- op, r0-r3 changed 6644#endif 6645 GET_INST_OPCODE ip @ extract opcode from rINST 6646 SET_VREG r0, r9 @ vAA<- r0 6647 GOTO_OPCODE ip @ jump to next instruction 6648 /* 10-12 instructions */ 6649 6650/* ------------------------------ */ 6651 .balign 128 6652.L_op_rem_int_lit8: /* 0xdc */ 6653/* File: arm/op_rem_int_lit8.S */ 6654 /* 6655 * Specialized 32-bit binary operation 6656 * 6657 * Performs "r1 = r0 rem r1". The selection between sdiv block or the gcc helper 6658 * depends on the compile time value of __ARM_ARCH_EXT_IDIV__ (defined for 6659 * ARMv7 CPUs that have hardware division support). 6660 * 6661 * NOTE: idivmod returns quotient in r0 and remainder in r1 6662 * 6663 * rem-int/lit8 6664 * 6665 */ 6666 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6667 mov r9, rINST, lsr #8 @ r9<- AA 6668 and r2, r3, #255 @ r2<- BB 6669 GET_VREG r0, r2 @ r0<- vBB 6670 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended) 6671 @cmp r1, #0 @ is second operand zero? 6672 beq common_errDivideByZero 6673 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6674 6675#ifdef __ARM_ARCH_EXT_IDIV__ 6676 sdiv r2, r0, r1 6677 mls r1, r1, r2, r0 @ r1<- op 6678#else 6679 bl __aeabi_idivmod @ r1<- op, r0-r3 changed 6680#endif 6681 GET_INST_OPCODE ip @ extract opcode from rINST 6682 SET_VREG r1, r9 @ vAA<- r1 6683 GOTO_OPCODE ip @ jump to next instruction 6684 /* 10-12 instructions */ 6685 6686/* ------------------------------ */ 6687 .balign 128 6688.L_op_and_int_lit8: /* 0xdd */ 6689/* File: arm/op_and_int_lit8.S */ 6690/* File: arm/binopLit8.S */ 6691 /* 6692 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6693 * that specifies an instruction that performs "result = r0 op r1". 6694 * This could be an ARM instruction or a function call. (If the result 6695 * comes back in a register other than r0, you can override "result".) 6696 * 6697 * You can override "extract" if the extraction of the literal value 6698 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6699 * can be omitted completely if the shift is embedded in "instr". 6700 * 6701 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6702 * vCC (r1). Useful for integer division and modulus. 6703 * 6704 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6705 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6706 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6707 */ 6708 /* binop/lit8 vAA, vBB, #+CC */ 6709 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6710 mov r9, rINST, lsr #8 @ r9<- AA 6711 and r2, r3, #255 @ r2<- BB 6712 GET_VREG r0, r2 @ r0<- vBB 6713 @ optional; typically r1<- ssssssCC (sign extended) 6714 .if 0 6715 @cmp r1, #0 @ is second operand zero? 6716 beq common_errDivideByZero 6717 .endif 6718 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6719 6720 and r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed 6721 GET_INST_OPCODE ip @ extract opcode from rINST 6722 SET_VREG r0, r9 @ vAA<- r0 6723 GOTO_OPCODE ip @ jump to next instruction 6724 /* 10-12 instructions */ 6725 6726 6727/* ------------------------------ */ 6728 .balign 128 6729.L_op_or_int_lit8: /* 0xde */ 6730/* File: arm/op_or_int_lit8.S */ 6731/* File: arm/binopLit8.S */ 6732 /* 6733 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6734 * that specifies an instruction that performs "result = r0 op r1". 6735 * This could be an ARM instruction or a function call. (If the result 6736 * comes back in a register other than r0, you can override "result".) 6737 * 6738 * You can override "extract" if the extraction of the literal value 6739 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6740 * can be omitted completely if the shift is embedded in "instr". 6741 * 6742 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6743 * vCC (r1). Useful for integer division and modulus. 6744 * 6745 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6746 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6747 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6748 */ 6749 /* binop/lit8 vAA, vBB, #+CC */ 6750 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6751 mov r9, rINST, lsr #8 @ r9<- AA 6752 and r2, r3, #255 @ r2<- BB 6753 GET_VREG r0, r2 @ r0<- vBB 6754 @ optional; typically r1<- ssssssCC (sign extended) 6755 .if 0 6756 @cmp r1, #0 @ is second operand zero? 6757 beq common_errDivideByZero 6758 .endif 6759 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6760 6761 orr r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed 6762 GET_INST_OPCODE ip @ extract opcode from rINST 6763 SET_VREG r0, r9 @ vAA<- r0 6764 GOTO_OPCODE ip @ jump to next instruction 6765 /* 10-12 instructions */ 6766 6767 6768/* ------------------------------ */ 6769 .balign 128 6770.L_op_xor_int_lit8: /* 0xdf */ 6771/* File: arm/op_xor_int_lit8.S */ 6772/* File: arm/binopLit8.S */ 6773 /* 6774 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6775 * that specifies an instruction that performs "result = r0 op r1". 6776 * This could be an ARM instruction or a function call. (If the result 6777 * comes back in a register other than r0, you can override "result".) 6778 * 6779 * You can override "extract" if the extraction of the literal value 6780 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6781 * can be omitted completely if the shift is embedded in "instr". 6782 * 6783 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6784 * vCC (r1). Useful for integer division and modulus. 6785 * 6786 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6787 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6788 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6789 */ 6790 /* binop/lit8 vAA, vBB, #+CC */ 6791 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6792 mov r9, rINST, lsr #8 @ r9<- AA 6793 and r2, r3, #255 @ r2<- BB 6794 GET_VREG r0, r2 @ r0<- vBB 6795 @ optional; typically r1<- ssssssCC (sign extended) 6796 .if 0 6797 @cmp r1, #0 @ is second operand zero? 6798 beq common_errDivideByZero 6799 .endif 6800 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6801 6802 eor r0, r0, r3, asr #8 @ r0<- op, r0-r3 changed 6803 GET_INST_OPCODE ip @ extract opcode from rINST 6804 SET_VREG r0, r9 @ vAA<- r0 6805 GOTO_OPCODE ip @ jump to next instruction 6806 /* 10-12 instructions */ 6807 6808 6809/* ------------------------------ */ 6810 .balign 128 6811.L_op_shl_int_lit8: /* 0xe0 */ 6812/* File: arm/op_shl_int_lit8.S */ 6813/* File: arm/binopLit8.S */ 6814 /* 6815 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6816 * that specifies an instruction that performs "result = r0 op r1". 6817 * This could be an ARM instruction or a function call. (If the result 6818 * comes back in a register other than r0, you can override "result".) 6819 * 6820 * You can override "extract" if the extraction of the literal value 6821 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6822 * can be omitted completely if the shift is embedded in "instr". 6823 * 6824 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6825 * vCC (r1). Useful for integer division and modulus. 6826 * 6827 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6828 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6829 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6830 */ 6831 /* binop/lit8 vAA, vBB, #+CC */ 6832 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6833 mov r9, rINST, lsr #8 @ r9<- AA 6834 and r2, r3, #255 @ r2<- BB 6835 GET_VREG r0, r2 @ r0<- vBB 6836 ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) 6837 .if 0 6838 @cmp r1, #0 @ is second operand zero? 6839 beq common_errDivideByZero 6840 .endif 6841 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6842 6843 mov r0, r0, asl r1 @ r0<- op, r0-r3 changed 6844 GET_INST_OPCODE ip @ extract opcode from rINST 6845 SET_VREG r0, r9 @ vAA<- r0 6846 GOTO_OPCODE ip @ jump to next instruction 6847 /* 10-12 instructions */ 6848 6849 6850/* ------------------------------ */ 6851 .balign 128 6852.L_op_shr_int_lit8: /* 0xe1 */ 6853/* File: arm/op_shr_int_lit8.S */ 6854/* File: arm/binopLit8.S */ 6855 /* 6856 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6857 * that specifies an instruction that performs "result = r0 op r1". 6858 * This could be an ARM instruction or a function call. (If the result 6859 * comes back in a register other than r0, you can override "result".) 6860 * 6861 * You can override "extract" if the extraction of the literal value 6862 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6863 * can be omitted completely if the shift is embedded in "instr". 6864 * 6865 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6866 * vCC (r1). Useful for integer division and modulus. 6867 * 6868 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6869 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6870 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6871 */ 6872 /* binop/lit8 vAA, vBB, #+CC */ 6873 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6874 mov r9, rINST, lsr #8 @ r9<- AA 6875 and r2, r3, #255 @ r2<- BB 6876 GET_VREG r0, r2 @ r0<- vBB 6877 ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) 6878 .if 0 6879 @cmp r1, #0 @ is second operand zero? 6880 beq common_errDivideByZero 6881 .endif 6882 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6883 6884 mov r0, r0, asr r1 @ r0<- op, r0-r3 changed 6885 GET_INST_OPCODE ip @ extract opcode from rINST 6886 SET_VREG r0, r9 @ vAA<- r0 6887 GOTO_OPCODE ip @ jump to next instruction 6888 /* 10-12 instructions */ 6889 6890 6891/* ------------------------------ */ 6892 .balign 128 6893.L_op_ushr_int_lit8: /* 0xe2 */ 6894/* File: arm/op_ushr_int_lit8.S */ 6895/* File: arm/binopLit8.S */ 6896 /* 6897 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6898 * that specifies an instruction that performs "result = r0 op r1". 6899 * This could be an ARM instruction or a function call. (If the result 6900 * comes back in a register other than r0, you can override "result".) 6901 * 6902 * You can override "extract" if the extraction of the literal value 6903 * from r3 to r1 is not the default "asr r1, r3, #8". The extraction 6904 * can be omitted completely if the shift is embedded in "instr". 6905 * 6906 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6907 * vCC (r1). Useful for integer division and modulus. 6908 * 6909 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6910 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6911 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6912 */ 6913 /* binop/lit8 vAA, vBB, #+CC */ 6914 FETCH_S r3, 1 @ r3<- ssssCCBB (sign-extended for CC) 6915 mov r9, rINST, lsr #8 @ r9<- AA 6916 and r2, r3, #255 @ r2<- BB 6917 GET_VREG r0, r2 @ r0<- vBB 6918 ubfx r1, r3, #8, #5 @ optional; typically r1<- ssssssCC (sign extended) 6919 .if 0 6920 @cmp r1, #0 @ is second operand zero? 6921 beq common_errDivideByZero 6922 .endif 6923 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6924 6925 mov r0, r0, lsr r1 @ r0<- op, r0-r3 changed 6926 GET_INST_OPCODE ip @ extract opcode from rINST 6927 SET_VREG r0, r9 @ vAA<- r0 6928 GOTO_OPCODE ip @ jump to next instruction 6929 /* 10-12 instructions */ 6930 6931 6932/* ------------------------------ */ 6933 .balign 128 6934.L_op_iget_quick: /* 0xe3 */ 6935/* File: arm/op_iget_quick.S */ 6936 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6937 /* op vA, vB, offset@CCCC */ 6938 mov r2, rINST, lsr #12 @ r2<- B 6939 FETCH r1, 1 @ r1<- field byte offset 6940 GET_VREG r3, r2 @ r3<- object we're operating on 6941 ubfx r2, rINST, #8, #4 @ r2<- A 6942 cmp r3, #0 @ check object for null 6943 beq common_errNullObject @ object was null 6944 ldr r0, [r3, r1] @ r0<- obj.field 6945 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6946 SET_VREG r0, r2 @ fp[A]<- r0 6947 GET_INST_OPCODE ip @ extract opcode from rINST 6948 GOTO_OPCODE ip @ jump to next instruction 6949 6950/* ------------------------------ */ 6951 .balign 128 6952.L_op_iget_wide_quick: /* 0xe4 */ 6953/* File: arm/op_iget_wide_quick.S */ 6954 /* iget-wide-quick vA, vB, offset@CCCC */ 6955 mov r2, rINST, lsr #12 @ r2<- B 6956 FETCH ip, 1 @ ip<- field byte offset 6957 GET_VREG r3, r2 @ r3<- object we're operating on 6958 ubfx r2, rINST, #8, #4 @ r2<- A 6959 cmp r3, #0 @ check object for null 6960 beq common_errNullObject @ object was null 6961 ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) 6962 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 6963 VREG_INDEX_TO_ADDR r3, r2 @ r3<- &fp[A] 6964 CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs 6965 GET_INST_OPCODE ip @ extract opcode from rINST 6966 stmia r3, {r0-r1} @ fp[A]<- r0/r1 6967 GOTO_OPCODE ip @ jump to next instruction 6968 6969/* ------------------------------ */ 6970 .balign 128 6971.L_op_iget_object_quick: /* 0xe5 */ 6972/* File: arm/op_iget_object_quick.S */ 6973 /* For: iget-object-quick */ 6974 /* op vA, vB, offset@CCCC */ 6975 mov r2, rINST, lsr #12 @ r2<- B 6976 FETCH r1, 1 @ r1<- field byte offset 6977 EXPORT_PC 6978 GET_VREG r0, r2 @ r0<- object we're operating on 6979 bl artIGetObjectFromMterp @ (obj, offset) 6980 ldr r3, [rSELF, #THREAD_EXCEPTION_OFFSET] 6981 ubfx r2, rINST, #8, #4 @ r2<- A 6982 PREFETCH_INST 2 6983 cmp r3, #0 6984 bne MterpPossibleException @ bail out 6985 SET_VREG_OBJECT r0, r2 @ fp[A]<- r0 6986 ADVANCE 2 @ advance rPC 6987 GET_INST_OPCODE ip @ extract opcode from rINST 6988 GOTO_OPCODE ip @ jump to next instruction 6989 6990/* ------------------------------ */ 6991 .balign 128 6992.L_op_iput_quick: /* 0xe6 */ 6993/* File: arm/op_iput_quick.S */ 6994 /* For: iput-quick, iput-object-quick */ 6995 /* op vA, vB, offset@CCCC */ 6996 mov r2, rINST, lsr #12 @ r2<- B 6997 FETCH r1, 1 @ r1<- field byte offset 6998 GET_VREG r3, r2 @ r3<- fp[B], the object pointer 6999 ubfx r2, rINST, #8, #4 @ r2<- A 7000 cmp r3, #0 @ check object for null 7001 beq common_errNullObject @ object was null 7002 GET_VREG r0, r2 @ r0<- fp[A] 7003 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7004 str r0, [r3, r1] @ obj.field<- r0 7005 GET_INST_OPCODE ip @ extract opcode from rINST 7006 GOTO_OPCODE ip @ jump to next instruction 7007 7008/* ------------------------------ */ 7009 .balign 128 7010.L_op_iput_wide_quick: /* 0xe7 */ 7011/* File: arm/op_iput_wide_quick.S */ 7012 /* iput-wide-quick vA, vB, offset@CCCC */ 7013 mov r2, rINST, lsr #12 @ r2<- B 7014 FETCH r3, 1 @ r3<- field byte offset 7015 GET_VREG r2, r2 @ r2<- fp[B], the object pointer 7016 ubfx r0, rINST, #8, #4 @ r0<- A 7017 cmp r2, #0 @ check object for null 7018 beq common_errNullObject @ object was null 7019 VREG_INDEX_TO_ADDR r0, r0 @ r0<- &fp[A] 7020 ldmia r0, {r0-r1} @ r0/r1<- fp[A]/fp[A+1] 7021 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7022 strd r0, [r2, r3] @ obj.field<- r0/r1 7023 GET_INST_OPCODE ip @ extract opcode from rINST 7024 GOTO_OPCODE ip @ jump to next instruction 7025 7026/* ------------------------------ */ 7027 .balign 128 7028.L_op_iput_object_quick: /* 0xe8 */ 7029/* File: arm/op_iput_object_quick.S */ 7030 EXPORT_PC 7031 add r0, rFP, #OFF_FP_SHADOWFRAME 7032 mov r1, rPC 7033 mov r2, rINST 7034 bl MterpIputObjectQuick 7035 cmp r0, #0 7036 beq MterpException 7037 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7038 GET_INST_OPCODE ip @ extract opcode from rINST 7039 GOTO_OPCODE ip @ jump to next instruction 7040 7041/* ------------------------------ */ 7042 .balign 128 7043.L_op_invoke_virtual_quick: /* 0xe9 */ 7044/* File: arm/op_invoke_virtual_quick.S */ 7045/* File: arm/invoke.S */ 7046 /* 7047 * Generic invoke handler wrapper. 7048 */ 7049 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7050 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7051 .extern MterpInvokeVirtualQuick 7052 EXPORT_PC 7053 mov r0, rSELF 7054 add r1, rFP, #OFF_FP_SHADOWFRAME 7055 mov r2, rPC 7056 mov r3, rINST 7057 bl MterpInvokeVirtualQuick 7058 cmp r0, #0 7059 beq MterpException 7060 FETCH_ADVANCE_INST 3 7061 bl MterpShouldSwitchInterpreters 7062 cmp r0, #0 7063 bne MterpFallback 7064 GET_INST_OPCODE ip 7065 GOTO_OPCODE ip 7066 7067 7068 7069/* ------------------------------ */ 7070 .balign 128 7071.L_op_invoke_virtual_range_quick: /* 0xea */ 7072/* File: arm/op_invoke_virtual_range_quick.S */ 7073/* File: arm/invoke.S */ 7074 /* 7075 * Generic invoke handler wrapper. 7076 */ 7077 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7078 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7079 .extern MterpInvokeVirtualQuickRange 7080 EXPORT_PC 7081 mov r0, rSELF 7082 add r1, rFP, #OFF_FP_SHADOWFRAME 7083 mov r2, rPC 7084 mov r3, rINST 7085 bl MterpInvokeVirtualQuickRange 7086 cmp r0, #0 7087 beq MterpException 7088 FETCH_ADVANCE_INST 3 7089 bl MterpShouldSwitchInterpreters 7090 cmp r0, #0 7091 bne MterpFallback 7092 GET_INST_OPCODE ip 7093 GOTO_OPCODE ip 7094 7095 7096 7097/* ------------------------------ */ 7098 .balign 128 7099.L_op_iput_boolean_quick: /* 0xeb */ 7100/* File: arm/op_iput_boolean_quick.S */ 7101/* File: arm/op_iput_quick.S */ 7102 /* For: iput-quick, iput-object-quick */ 7103 /* op vA, vB, offset@CCCC */ 7104 mov r2, rINST, lsr #12 @ r2<- B 7105 FETCH r1, 1 @ r1<- field byte offset 7106 GET_VREG r3, r2 @ r3<- fp[B], the object pointer 7107 ubfx r2, rINST, #8, #4 @ r2<- A 7108 cmp r3, #0 @ check object for null 7109 beq common_errNullObject @ object was null 7110 GET_VREG r0, r2 @ r0<- fp[A] 7111 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7112 strb r0, [r3, r1] @ obj.field<- r0 7113 GET_INST_OPCODE ip @ extract opcode from rINST 7114 GOTO_OPCODE ip @ jump to next instruction 7115 7116 7117/* ------------------------------ */ 7118 .balign 128 7119.L_op_iput_byte_quick: /* 0xec */ 7120/* File: arm/op_iput_byte_quick.S */ 7121/* File: arm/op_iput_quick.S */ 7122 /* For: iput-quick, iput-object-quick */ 7123 /* op vA, vB, offset@CCCC */ 7124 mov r2, rINST, lsr #12 @ r2<- B 7125 FETCH r1, 1 @ r1<- field byte offset 7126 GET_VREG r3, r2 @ r3<- fp[B], the object pointer 7127 ubfx r2, rINST, #8, #4 @ r2<- A 7128 cmp r3, #0 @ check object for null 7129 beq common_errNullObject @ object was null 7130 GET_VREG r0, r2 @ r0<- fp[A] 7131 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7132 strb r0, [r3, r1] @ obj.field<- r0 7133 GET_INST_OPCODE ip @ extract opcode from rINST 7134 GOTO_OPCODE ip @ jump to next instruction 7135 7136 7137/* ------------------------------ */ 7138 .balign 128 7139.L_op_iput_char_quick: /* 0xed */ 7140/* File: arm/op_iput_char_quick.S */ 7141/* File: arm/op_iput_quick.S */ 7142 /* For: iput-quick, iput-object-quick */ 7143 /* op vA, vB, offset@CCCC */ 7144 mov r2, rINST, lsr #12 @ r2<- B 7145 FETCH r1, 1 @ r1<- field byte offset 7146 GET_VREG r3, r2 @ r3<- fp[B], the object pointer 7147 ubfx r2, rINST, #8, #4 @ r2<- A 7148 cmp r3, #0 @ check object for null 7149 beq common_errNullObject @ object was null 7150 GET_VREG r0, r2 @ r0<- fp[A] 7151 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7152 strh r0, [r3, r1] @ obj.field<- r0 7153 GET_INST_OPCODE ip @ extract opcode from rINST 7154 GOTO_OPCODE ip @ jump to next instruction 7155 7156 7157/* ------------------------------ */ 7158 .balign 128 7159.L_op_iput_short_quick: /* 0xee */ 7160/* File: arm/op_iput_short_quick.S */ 7161/* File: arm/op_iput_quick.S */ 7162 /* For: iput-quick, iput-object-quick */ 7163 /* op vA, vB, offset@CCCC */ 7164 mov r2, rINST, lsr #12 @ r2<- B 7165 FETCH r1, 1 @ r1<- field byte offset 7166 GET_VREG r3, r2 @ r3<- fp[B], the object pointer 7167 ubfx r2, rINST, #8, #4 @ r2<- A 7168 cmp r3, #0 @ check object for null 7169 beq common_errNullObject @ object was null 7170 GET_VREG r0, r2 @ r0<- fp[A] 7171 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7172 strh r0, [r3, r1] @ obj.field<- r0 7173 GET_INST_OPCODE ip @ extract opcode from rINST 7174 GOTO_OPCODE ip @ jump to next instruction 7175 7176 7177/* ------------------------------ */ 7178 .balign 128 7179.L_op_iget_boolean_quick: /* 0xef */ 7180/* File: arm/op_iget_boolean_quick.S */ 7181/* File: arm/op_iget_quick.S */ 7182 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7183 /* op vA, vB, offset@CCCC */ 7184 mov r2, rINST, lsr #12 @ r2<- B 7185 FETCH r1, 1 @ r1<- field byte offset 7186 GET_VREG r3, r2 @ r3<- object we're operating on 7187 ubfx r2, rINST, #8, #4 @ r2<- A 7188 cmp r3, #0 @ check object for null 7189 beq common_errNullObject @ object was null 7190 ldrb r0, [r3, r1] @ r0<- obj.field 7191 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7192 SET_VREG r0, r2 @ fp[A]<- r0 7193 GET_INST_OPCODE ip @ extract opcode from rINST 7194 GOTO_OPCODE ip @ jump to next instruction 7195 7196 7197/* ------------------------------ */ 7198 .balign 128 7199.L_op_iget_byte_quick: /* 0xf0 */ 7200/* File: arm/op_iget_byte_quick.S */ 7201/* File: arm/op_iget_quick.S */ 7202 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7203 /* op vA, vB, offset@CCCC */ 7204 mov r2, rINST, lsr #12 @ r2<- B 7205 FETCH r1, 1 @ r1<- field byte offset 7206 GET_VREG r3, r2 @ r3<- object we're operating on 7207 ubfx r2, rINST, #8, #4 @ r2<- A 7208 cmp r3, #0 @ check object for null 7209 beq common_errNullObject @ object was null 7210 ldrsb r0, [r3, r1] @ r0<- obj.field 7211 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7212 SET_VREG r0, r2 @ fp[A]<- r0 7213 GET_INST_OPCODE ip @ extract opcode from rINST 7214 GOTO_OPCODE ip @ jump to next instruction 7215 7216 7217/* ------------------------------ */ 7218 .balign 128 7219.L_op_iget_char_quick: /* 0xf1 */ 7220/* File: arm/op_iget_char_quick.S */ 7221/* File: arm/op_iget_quick.S */ 7222 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7223 /* op vA, vB, offset@CCCC */ 7224 mov r2, rINST, lsr #12 @ r2<- B 7225 FETCH r1, 1 @ r1<- field byte offset 7226 GET_VREG r3, r2 @ r3<- object we're operating on 7227 ubfx r2, rINST, #8, #4 @ r2<- A 7228 cmp r3, #0 @ check object for null 7229 beq common_errNullObject @ object was null 7230 ldrh r0, [r3, r1] @ r0<- obj.field 7231 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7232 SET_VREG r0, r2 @ fp[A]<- r0 7233 GET_INST_OPCODE ip @ extract opcode from rINST 7234 GOTO_OPCODE ip @ jump to next instruction 7235 7236 7237/* ------------------------------ */ 7238 .balign 128 7239.L_op_iget_short_quick: /* 0xf2 */ 7240/* File: arm/op_iget_short_quick.S */ 7241/* File: arm/op_iget_quick.S */ 7242 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7243 /* op vA, vB, offset@CCCC */ 7244 mov r2, rINST, lsr #12 @ r2<- B 7245 FETCH r1, 1 @ r1<- field byte offset 7246 GET_VREG r3, r2 @ r3<- object we're operating on 7247 ubfx r2, rINST, #8, #4 @ r2<- A 7248 cmp r3, #0 @ check object for null 7249 beq common_errNullObject @ object was null 7250 ldrsh r0, [r3, r1] @ r0<- obj.field 7251 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 7252 SET_VREG r0, r2 @ fp[A]<- r0 7253 GET_INST_OPCODE ip @ extract opcode from rINST 7254 GOTO_OPCODE ip @ jump to next instruction 7255 7256 7257/* ------------------------------ */ 7258 .balign 128 7259.L_op_unused_f3: /* 0xf3 */ 7260/* File: arm/op_unused_f3.S */ 7261/* File: arm/unused.S */ 7262/* 7263 * Bail to reference interpreter to throw. 7264 */ 7265 b MterpFallback 7266 7267 7268/* ------------------------------ */ 7269 .balign 128 7270.L_op_unused_f4: /* 0xf4 */ 7271/* File: arm/op_unused_f4.S */ 7272/* File: arm/unused.S */ 7273/* 7274 * Bail to reference interpreter to throw. 7275 */ 7276 b MterpFallback 7277 7278 7279/* ------------------------------ */ 7280 .balign 128 7281.L_op_unused_f5: /* 0xf5 */ 7282/* File: arm/op_unused_f5.S */ 7283/* File: arm/unused.S */ 7284/* 7285 * Bail to reference interpreter to throw. 7286 */ 7287 b MterpFallback 7288 7289 7290/* ------------------------------ */ 7291 .balign 128 7292.L_op_unused_f6: /* 0xf6 */ 7293/* File: arm/op_unused_f6.S */ 7294/* File: arm/unused.S */ 7295/* 7296 * Bail to reference interpreter to throw. 7297 */ 7298 b MterpFallback 7299 7300 7301/* ------------------------------ */ 7302 .balign 128 7303.L_op_unused_f7: /* 0xf7 */ 7304/* File: arm/op_unused_f7.S */ 7305/* File: arm/unused.S */ 7306/* 7307 * Bail to reference interpreter to throw. 7308 */ 7309 b MterpFallback 7310 7311 7312/* ------------------------------ */ 7313 .balign 128 7314.L_op_unused_f8: /* 0xf8 */ 7315/* File: arm/op_unused_f8.S */ 7316/* File: arm/unused.S */ 7317/* 7318 * Bail to reference interpreter to throw. 7319 */ 7320 b MterpFallback 7321 7322 7323/* ------------------------------ */ 7324 .balign 128 7325.L_op_unused_f9: /* 0xf9 */ 7326/* File: arm/op_unused_f9.S */ 7327/* File: arm/unused.S */ 7328/* 7329 * Bail to reference interpreter to throw. 7330 */ 7331 b MterpFallback 7332 7333 7334/* ------------------------------ */ 7335 .balign 128 7336.L_op_invoke_polymorphic: /* 0xfa */ 7337/* Transfer stub to alternate interpreter */ 7338 b MterpFallback 7339 7340 7341/* ------------------------------ */ 7342 .balign 128 7343.L_op_invoke_polymorphic_range: /* 0xfb */ 7344/* Transfer stub to alternate interpreter */ 7345 b MterpFallback 7346 7347 7348/* ------------------------------ */ 7349 .balign 128 7350.L_op_invoke_custom: /* 0xfc */ 7351/* Transfer stub to alternate interpreter */ 7352 b MterpFallback 7353 7354 7355/* ------------------------------ */ 7356 .balign 128 7357.L_op_invoke_custom_range: /* 0xfd */ 7358/* Transfer stub to alternate interpreter */ 7359 b MterpFallback 7360 7361 7362/* ------------------------------ */ 7363 .balign 128 7364.L_op_unused_fe: /* 0xfe */ 7365/* File: arm/op_unused_fe.S */ 7366/* File: arm/unused.S */ 7367/* 7368 * Bail to reference interpreter to throw. 7369 */ 7370 b MterpFallback 7371 7372 7373/* ------------------------------ */ 7374 .balign 128 7375.L_op_unused_ff: /* 0xff */ 7376/* File: arm/op_unused_ff.S */ 7377/* File: arm/unused.S */ 7378/* 7379 * Bail to reference interpreter to throw. 7380 */ 7381 b MterpFallback 7382 7383 7384 .balign 128 7385 .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart 7386 .global artMterpAsmInstructionEnd 7387artMterpAsmInstructionEnd: 7388 7389/* 7390 * =========================================================================== 7391 * Sister implementations 7392 * =========================================================================== 7393 */ 7394 .global artMterpAsmSisterStart 7395 .type artMterpAsmSisterStart, %function 7396 .text 7397 .balign 4 7398artMterpAsmSisterStart: 7399 7400/* continuation for op_float_to_long */ 7401/* 7402 * Convert the float in r0 to a long in r0/r1. 7403 * 7404 * We have to clip values to long min/max per the specification. The 7405 * expected common case is a "reasonable" value that converts directly 7406 * to modest integer. The EABI convert function isn't doing this for us. 7407 */ 7408f2l_doconv: 7409 ubfx r2, r0, #23, #8 @ grab the exponent 7410 cmp r2, #0xbe @ MININT < x > MAXINT? 7411 bhs f2l_special_cases 7412 b __aeabi_f2lz @ tail call to convert float to long 7413f2l_special_cases: 7414 cmp r2, #0xff @ NaN or infinity? 7415 beq f2l_maybeNaN 7416f2l_notNaN: 7417 adds r0, r0, r0 @ sign bit to carry 7418 mov r0, #0xffffffff @ assume maxlong for lsw 7419 mov r1, #0x7fffffff @ assume maxlong for msw 7420 adc r0, r0, #0 7421 adc r1, r1, #0 @ convert maxlong to minlong if exp negative 7422 bx lr @ return 7423f2l_maybeNaN: 7424 lsls r3, r0, #9 7425 beq f2l_notNaN @ if fraction is non-zero, it's a NaN 7426 mov r0, #0 7427 mov r1, #0 7428 bx lr @ return 0 for NaN 7429 7430/* continuation for op_double_to_long */ 7431/* 7432 * Convert the double in r0/r1 to a long in r0/r1. 7433 * 7434 * We have to clip values to long min/max per the specification. The 7435 * expected common case is a "reasonable" value that converts directly 7436 * to modest integer. The EABI convert function isn't doing this for us. 7437 */ 7438d2l_doconv: 7439 ubfx r2, r1, #20, #11 @ grab the exponent 7440 movw r3, #0x43e 7441 cmp r2, r3 @ MINLONG < x > MAXLONG? 7442 bhs d2l_special_cases 7443 b __aeabi_d2lz @ tail call to convert double to long 7444d2l_special_cases: 7445 movw r3, #0x7ff 7446 cmp r2, r3 7447 beq d2l_maybeNaN @ NaN? 7448d2l_notNaN: 7449 adds r1, r1, r1 @ sign bit to carry 7450 mov r0, #0xffffffff @ assume maxlong for lsw 7451 mov r1, #0x7fffffff @ assume maxlong for msw 7452 adc r0, r0, #0 7453 adc r1, r1, #0 @ convert maxlong to minlong if exp negative 7454 bx lr @ return 7455d2l_maybeNaN: 7456 orrs r3, r0, r1, lsl #12 7457 beq d2l_notNaN @ if fraction is non-zero, it's a NaN 7458 mov r0, #0 7459 mov r1, #0 7460 bx lr @ return 0 for NaN 7461 7462 .size artMterpAsmSisterStart, .-artMterpAsmSisterStart 7463 .global artMterpAsmSisterEnd 7464artMterpAsmSisterEnd: 7465 7466 7467 .global artMterpAsmAltInstructionStart 7468 .type artMterpAsmAltInstructionStart, %function 7469 .text 7470 7471artMterpAsmAltInstructionStart = .L_ALT_op_nop 7472/* ------------------------------ */ 7473 .balign 128 7474.L_ALT_op_nop: /* 0x00 */ 7475/* File: arm/alt_stub.S */ 7476/* 7477 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7478 * any interesting requests and then jump to the real instruction 7479 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7480 */ 7481 .extern MterpCheckBefore 7482 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7483 adrl lr, artMterpAsmInstructionStart + (0 * 128) @ Addr of primary handler. 7484 mov r0, rSELF 7485 add r1, rFP, #OFF_FP_SHADOWFRAME 7486 mov r2, rPC 7487 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7488 7489/* ------------------------------ */ 7490 .balign 128 7491.L_ALT_op_move: /* 0x01 */ 7492/* File: arm/alt_stub.S */ 7493/* 7494 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7495 * any interesting requests and then jump to the real instruction 7496 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7497 */ 7498 .extern MterpCheckBefore 7499 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7500 adrl lr, artMterpAsmInstructionStart + (1 * 128) @ Addr of primary handler. 7501 mov r0, rSELF 7502 add r1, rFP, #OFF_FP_SHADOWFRAME 7503 mov r2, rPC 7504 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7505 7506/* ------------------------------ */ 7507 .balign 128 7508.L_ALT_op_move_from16: /* 0x02 */ 7509/* File: arm/alt_stub.S */ 7510/* 7511 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7512 * any interesting requests and then jump to the real instruction 7513 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7514 */ 7515 .extern MterpCheckBefore 7516 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7517 adrl lr, artMterpAsmInstructionStart + (2 * 128) @ Addr of primary handler. 7518 mov r0, rSELF 7519 add r1, rFP, #OFF_FP_SHADOWFRAME 7520 mov r2, rPC 7521 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7522 7523/* ------------------------------ */ 7524 .balign 128 7525.L_ALT_op_move_16: /* 0x03 */ 7526/* File: arm/alt_stub.S */ 7527/* 7528 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7529 * any interesting requests and then jump to the real instruction 7530 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7531 */ 7532 .extern MterpCheckBefore 7533 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7534 adrl lr, artMterpAsmInstructionStart + (3 * 128) @ Addr of primary handler. 7535 mov r0, rSELF 7536 add r1, rFP, #OFF_FP_SHADOWFRAME 7537 mov r2, rPC 7538 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7539 7540/* ------------------------------ */ 7541 .balign 128 7542.L_ALT_op_move_wide: /* 0x04 */ 7543/* File: arm/alt_stub.S */ 7544/* 7545 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7546 * any interesting requests and then jump to the real instruction 7547 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7548 */ 7549 .extern MterpCheckBefore 7550 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7551 adrl lr, artMterpAsmInstructionStart + (4 * 128) @ Addr of primary handler. 7552 mov r0, rSELF 7553 add r1, rFP, #OFF_FP_SHADOWFRAME 7554 mov r2, rPC 7555 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7556 7557/* ------------------------------ */ 7558 .balign 128 7559.L_ALT_op_move_wide_from16: /* 0x05 */ 7560/* File: arm/alt_stub.S */ 7561/* 7562 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7563 * any interesting requests and then jump to the real instruction 7564 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7565 */ 7566 .extern MterpCheckBefore 7567 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7568 adrl lr, artMterpAsmInstructionStart + (5 * 128) @ Addr of primary handler. 7569 mov r0, rSELF 7570 add r1, rFP, #OFF_FP_SHADOWFRAME 7571 mov r2, rPC 7572 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7573 7574/* ------------------------------ */ 7575 .balign 128 7576.L_ALT_op_move_wide_16: /* 0x06 */ 7577/* File: arm/alt_stub.S */ 7578/* 7579 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7580 * any interesting requests and then jump to the real instruction 7581 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7582 */ 7583 .extern MterpCheckBefore 7584 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7585 adrl lr, artMterpAsmInstructionStart + (6 * 128) @ Addr of primary handler. 7586 mov r0, rSELF 7587 add r1, rFP, #OFF_FP_SHADOWFRAME 7588 mov r2, rPC 7589 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7590 7591/* ------------------------------ */ 7592 .balign 128 7593.L_ALT_op_move_object: /* 0x07 */ 7594/* File: arm/alt_stub.S */ 7595/* 7596 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7597 * any interesting requests and then jump to the real instruction 7598 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7599 */ 7600 .extern MterpCheckBefore 7601 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7602 adrl lr, artMterpAsmInstructionStart + (7 * 128) @ Addr of primary handler. 7603 mov r0, rSELF 7604 add r1, rFP, #OFF_FP_SHADOWFRAME 7605 mov r2, rPC 7606 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7607 7608/* ------------------------------ */ 7609 .balign 128 7610.L_ALT_op_move_object_from16: /* 0x08 */ 7611/* File: arm/alt_stub.S */ 7612/* 7613 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7614 * any interesting requests and then jump to the real instruction 7615 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7616 */ 7617 .extern MterpCheckBefore 7618 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7619 adrl lr, artMterpAsmInstructionStart + (8 * 128) @ Addr of primary handler. 7620 mov r0, rSELF 7621 add r1, rFP, #OFF_FP_SHADOWFRAME 7622 mov r2, rPC 7623 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7624 7625/* ------------------------------ */ 7626 .balign 128 7627.L_ALT_op_move_object_16: /* 0x09 */ 7628/* File: arm/alt_stub.S */ 7629/* 7630 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7631 * any interesting requests and then jump to the real instruction 7632 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7633 */ 7634 .extern MterpCheckBefore 7635 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7636 adrl lr, artMterpAsmInstructionStart + (9 * 128) @ Addr of primary handler. 7637 mov r0, rSELF 7638 add r1, rFP, #OFF_FP_SHADOWFRAME 7639 mov r2, rPC 7640 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7641 7642/* ------------------------------ */ 7643 .balign 128 7644.L_ALT_op_move_result: /* 0x0a */ 7645/* File: arm/alt_stub.S */ 7646/* 7647 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7648 * any interesting requests and then jump to the real instruction 7649 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7650 */ 7651 .extern MterpCheckBefore 7652 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7653 adrl lr, artMterpAsmInstructionStart + (10 * 128) @ Addr of primary handler. 7654 mov r0, rSELF 7655 add r1, rFP, #OFF_FP_SHADOWFRAME 7656 mov r2, rPC 7657 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7658 7659/* ------------------------------ */ 7660 .balign 128 7661.L_ALT_op_move_result_wide: /* 0x0b */ 7662/* File: arm/alt_stub.S */ 7663/* 7664 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7665 * any interesting requests and then jump to the real instruction 7666 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7667 */ 7668 .extern MterpCheckBefore 7669 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7670 adrl lr, artMterpAsmInstructionStart + (11 * 128) @ Addr of primary handler. 7671 mov r0, rSELF 7672 add r1, rFP, #OFF_FP_SHADOWFRAME 7673 mov r2, rPC 7674 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7675 7676/* ------------------------------ */ 7677 .balign 128 7678.L_ALT_op_move_result_object: /* 0x0c */ 7679/* File: arm/alt_stub.S */ 7680/* 7681 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7682 * any interesting requests and then jump to the real instruction 7683 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7684 */ 7685 .extern MterpCheckBefore 7686 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7687 adrl lr, artMterpAsmInstructionStart + (12 * 128) @ Addr of primary handler. 7688 mov r0, rSELF 7689 add r1, rFP, #OFF_FP_SHADOWFRAME 7690 mov r2, rPC 7691 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7692 7693/* ------------------------------ */ 7694 .balign 128 7695.L_ALT_op_move_exception: /* 0x0d */ 7696/* File: arm/alt_stub.S */ 7697/* 7698 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7699 * any interesting requests and then jump to the real instruction 7700 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7701 */ 7702 .extern MterpCheckBefore 7703 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7704 adrl lr, artMterpAsmInstructionStart + (13 * 128) @ Addr of primary handler. 7705 mov r0, rSELF 7706 add r1, rFP, #OFF_FP_SHADOWFRAME 7707 mov r2, rPC 7708 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7709 7710/* ------------------------------ */ 7711 .balign 128 7712.L_ALT_op_return_void: /* 0x0e */ 7713/* File: arm/alt_stub.S */ 7714/* 7715 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7716 * any interesting requests and then jump to the real instruction 7717 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7718 */ 7719 .extern MterpCheckBefore 7720 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7721 adrl lr, artMterpAsmInstructionStart + (14 * 128) @ Addr of primary handler. 7722 mov r0, rSELF 7723 add r1, rFP, #OFF_FP_SHADOWFRAME 7724 mov r2, rPC 7725 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7726 7727/* ------------------------------ */ 7728 .balign 128 7729.L_ALT_op_return: /* 0x0f */ 7730/* File: arm/alt_stub.S */ 7731/* 7732 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7733 * any interesting requests and then jump to the real instruction 7734 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7735 */ 7736 .extern MterpCheckBefore 7737 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7738 adrl lr, artMterpAsmInstructionStart + (15 * 128) @ Addr of primary handler. 7739 mov r0, rSELF 7740 add r1, rFP, #OFF_FP_SHADOWFRAME 7741 mov r2, rPC 7742 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7743 7744/* ------------------------------ */ 7745 .balign 128 7746.L_ALT_op_return_wide: /* 0x10 */ 7747/* File: arm/alt_stub.S */ 7748/* 7749 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7750 * any interesting requests and then jump to the real instruction 7751 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7752 */ 7753 .extern MterpCheckBefore 7754 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7755 adrl lr, artMterpAsmInstructionStart + (16 * 128) @ Addr of primary handler. 7756 mov r0, rSELF 7757 add r1, rFP, #OFF_FP_SHADOWFRAME 7758 mov r2, rPC 7759 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7760 7761/* ------------------------------ */ 7762 .balign 128 7763.L_ALT_op_return_object: /* 0x11 */ 7764/* File: arm/alt_stub.S */ 7765/* 7766 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7767 * any interesting requests and then jump to the real instruction 7768 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7769 */ 7770 .extern MterpCheckBefore 7771 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7772 adrl lr, artMterpAsmInstructionStart + (17 * 128) @ Addr of primary handler. 7773 mov r0, rSELF 7774 add r1, rFP, #OFF_FP_SHADOWFRAME 7775 mov r2, rPC 7776 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7777 7778/* ------------------------------ */ 7779 .balign 128 7780.L_ALT_op_const_4: /* 0x12 */ 7781/* File: arm/alt_stub.S */ 7782/* 7783 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7784 * any interesting requests and then jump to the real instruction 7785 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7786 */ 7787 .extern MterpCheckBefore 7788 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7789 adrl lr, artMterpAsmInstructionStart + (18 * 128) @ Addr of primary handler. 7790 mov r0, rSELF 7791 add r1, rFP, #OFF_FP_SHADOWFRAME 7792 mov r2, rPC 7793 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7794 7795/* ------------------------------ */ 7796 .balign 128 7797.L_ALT_op_const_16: /* 0x13 */ 7798/* File: arm/alt_stub.S */ 7799/* 7800 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7801 * any interesting requests and then jump to the real instruction 7802 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7803 */ 7804 .extern MterpCheckBefore 7805 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7806 adrl lr, artMterpAsmInstructionStart + (19 * 128) @ Addr of primary handler. 7807 mov r0, rSELF 7808 add r1, rFP, #OFF_FP_SHADOWFRAME 7809 mov r2, rPC 7810 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7811 7812/* ------------------------------ */ 7813 .balign 128 7814.L_ALT_op_const: /* 0x14 */ 7815/* File: arm/alt_stub.S */ 7816/* 7817 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7818 * any interesting requests and then jump to the real instruction 7819 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7820 */ 7821 .extern MterpCheckBefore 7822 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7823 adrl lr, artMterpAsmInstructionStart + (20 * 128) @ Addr of primary handler. 7824 mov r0, rSELF 7825 add r1, rFP, #OFF_FP_SHADOWFRAME 7826 mov r2, rPC 7827 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7828 7829/* ------------------------------ */ 7830 .balign 128 7831.L_ALT_op_const_high16: /* 0x15 */ 7832/* File: arm/alt_stub.S */ 7833/* 7834 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7835 * any interesting requests and then jump to the real instruction 7836 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7837 */ 7838 .extern MterpCheckBefore 7839 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7840 adrl lr, artMterpAsmInstructionStart + (21 * 128) @ Addr of primary handler. 7841 mov r0, rSELF 7842 add r1, rFP, #OFF_FP_SHADOWFRAME 7843 mov r2, rPC 7844 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7845 7846/* ------------------------------ */ 7847 .balign 128 7848.L_ALT_op_const_wide_16: /* 0x16 */ 7849/* File: arm/alt_stub.S */ 7850/* 7851 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7852 * any interesting requests and then jump to the real instruction 7853 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7854 */ 7855 .extern MterpCheckBefore 7856 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7857 adrl lr, artMterpAsmInstructionStart + (22 * 128) @ Addr of primary handler. 7858 mov r0, rSELF 7859 add r1, rFP, #OFF_FP_SHADOWFRAME 7860 mov r2, rPC 7861 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7862 7863/* ------------------------------ */ 7864 .balign 128 7865.L_ALT_op_const_wide_32: /* 0x17 */ 7866/* File: arm/alt_stub.S */ 7867/* 7868 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7869 * any interesting requests and then jump to the real instruction 7870 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7871 */ 7872 .extern MterpCheckBefore 7873 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7874 adrl lr, artMterpAsmInstructionStart + (23 * 128) @ Addr of primary handler. 7875 mov r0, rSELF 7876 add r1, rFP, #OFF_FP_SHADOWFRAME 7877 mov r2, rPC 7878 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7879 7880/* ------------------------------ */ 7881 .balign 128 7882.L_ALT_op_const_wide: /* 0x18 */ 7883/* File: arm/alt_stub.S */ 7884/* 7885 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7886 * any interesting requests and then jump to the real instruction 7887 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7888 */ 7889 .extern MterpCheckBefore 7890 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7891 adrl lr, artMterpAsmInstructionStart + (24 * 128) @ Addr of primary handler. 7892 mov r0, rSELF 7893 add r1, rFP, #OFF_FP_SHADOWFRAME 7894 mov r2, rPC 7895 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7896 7897/* ------------------------------ */ 7898 .balign 128 7899.L_ALT_op_const_wide_high16: /* 0x19 */ 7900/* File: arm/alt_stub.S */ 7901/* 7902 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7903 * any interesting requests and then jump to the real instruction 7904 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7905 */ 7906 .extern MterpCheckBefore 7907 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7908 adrl lr, artMterpAsmInstructionStart + (25 * 128) @ Addr of primary handler. 7909 mov r0, rSELF 7910 add r1, rFP, #OFF_FP_SHADOWFRAME 7911 mov r2, rPC 7912 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7913 7914/* ------------------------------ */ 7915 .balign 128 7916.L_ALT_op_const_string: /* 0x1a */ 7917/* File: arm/alt_stub.S */ 7918/* 7919 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7920 * any interesting requests and then jump to the real instruction 7921 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7922 */ 7923 .extern MterpCheckBefore 7924 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7925 adrl lr, artMterpAsmInstructionStart + (26 * 128) @ Addr of primary handler. 7926 mov r0, rSELF 7927 add r1, rFP, #OFF_FP_SHADOWFRAME 7928 mov r2, rPC 7929 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7930 7931/* ------------------------------ */ 7932 .balign 128 7933.L_ALT_op_const_string_jumbo: /* 0x1b */ 7934/* File: arm/alt_stub.S */ 7935/* 7936 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7937 * any interesting requests and then jump to the real instruction 7938 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7939 */ 7940 .extern MterpCheckBefore 7941 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7942 adrl lr, artMterpAsmInstructionStart + (27 * 128) @ Addr of primary handler. 7943 mov r0, rSELF 7944 add r1, rFP, #OFF_FP_SHADOWFRAME 7945 mov r2, rPC 7946 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7947 7948/* ------------------------------ */ 7949 .balign 128 7950.L_ALT_op_const_class: /* 0x1c */ 7951/* File: arm/alt_stub.S */ 7952/* 7953 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7954 * any interesting requests and then jump to the real instruction 7955 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7956 */ 7957 .extern MterpCheckBefore 7958 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7959 adrl lr, artMterpAsmInstructionStart + (28 * 128) @ Addr of primary handler. 7960 mov r0, rSELF 7961 add r1, rFP, #OFF_FP_SHADOWFRAME 7962 mov r2, rPC 7963 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7964 7965/* ------------------------------ */ 7966 .balign 128 7967.L_ALT_op_monitor_enter: /* 0x1d */ 7968/* File: arm/alt_stub.S */ 7969/* 7970 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7971 * any interesting requests and then jump to the real instruction 7972 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7973 */ 7974 .extern MterpCheckBefore 7975 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7976 adrl lr, artMterpAsmInstructionStart + (29 * 128) @ Addr of primary handler. 7977 mov r0, rSELF 7978 add r1, rFP, #OFF_FP_SHADOWFRAME 7979 mov r2, rPC 7980 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7981 7982/* ------------------------------ */ 7983 .balign 128 7984.L_ALT_op_monitor_exit: /* 0x1e */ 7985/* File: arm/alt_stub.S */ 7986/* 7987 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7988 * any interesting requests and then jump to the real instruction 7989 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7990 */ 7991 .extern MterpCheckBefore 7992 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 7993 adrl lr, artMterpAsmInstructionStart + (30 * 128) @ Addr of primary handler. 7994 mov r0, rSELF 7995 add r1, rFP, #OFF_FP_SHADOWFRAME 7996 mov r2, rPC 7997 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 7998 7999/* ------------------------------ */ 8000 .balign 128 8001.L_ALT_op_check_cast: /* 0x1f */ 8002/* File: arm/alt_stub.S */ 8003/* 8004 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8005 * any interesting requests and then jump to the real instruction 8006 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8007 */ 8008 .extern MterpCheckBefore 8009 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8010 adrl lr, artMterpAsmInstructionStart + (31 * 128) @ Addr of primary handler. 8011 mov r0, rSELF 8012 add r1, rFP, #OFF_FP_SHADOWFRAME 8013 mov r2, rPC 8014 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8015 8016/* ------------------------------ */ 8017 .balign 128 8018.L_ALT_op_instance_of: /* 0x20 */ 8019/* File: arm/alt_stub.S */ 8020/* 8021 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8022 * any interesting requests and then jump to the real instruction 8023 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8024 */ 8025 .extern MterpCheckBefore 8026 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8027 adrl lr, artMterpAsmInstructionStart + (32 * 128) @ Addr of primary handler. 8028 mov r0, rSELF 8029 add r1, rFP, #OFF_FP_SHADOWFRAME 8030 mov r2, rPC 8031 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8032 8033/* ------------------------------ */ 8034 .balign 128 8035.L_ALT_op_array_length: /* 0x21 */ 8036/* File: arm/alt_stub.S */ 8037/* 8038 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8039 * any interesting requests and then jump to the real instruction 8040 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8041 */ 8042 .extern MterpCheckBefore 8043 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8044 adrl lr, artMterpAsmInstructionStart + (33 * 128) @ Addr of primary handler. 8045 mov r0, rSELF 8046 add r1, rFP, #OFF_FP_SHADOWFRAME 8047 mov r2, rPC 8048 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8049 8050/* ------------------------------ */ 8051 .balign 128 8052.L_ALT_op_new_instance: /* 0x22 */ 8053/* File: arm/alt_stub.S */ 8054/* 8055 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8056 * any interesting requests and then jump to the real instruction 8057 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8058 */ 8059 .extern MterpCheckBefore 8060 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8061 adrl lr, artMterpAsmInstructionStart + (34 * 128) @ Addr of primary handler. 8062 mov r0, rSELF 8063 add r1, rFP, #OFF_FP_SHADOWFRAME 8064 mov r2, rPC 8065 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8066 8067/* ------------------------------ */ 8068 .balign 128 8069.L_ALT_op_new_array: /* 0x23 */ 8070/* File: arm/alt_stub.S */ 8071/* 8072 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8073 * any interesting requests and then jump to the real instruction 8074 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8075 */ 8076 .extern MterpCheckBefore 8077 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8078 adrl lr, artMterpAsmInstructionStart + (35 * 128) @ Addr of primary handler. 8079 mov r0, rSELF 8080 add r1, rFP, #OFF_FP_SHADOWFRAME 8081 mov r2, rPC 8082 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8083 8084/* ------------------------------ */ 8085 .balign 128 8086.L_ALT_op_filled_new_array: /* 0x24 */ 8087/* File: arm/alt_stub.S */ 8088/* 8089 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8090 * any interesting requests and then jump to the real instruction 8091 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8092 */ 8093 .extern MterpCheckBefore 8094 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8095 adrl lr, artMterpAsmInstructionStart + (36 * 128) @ Addr of primary handler. 8096 mov r0, rSELF 8097 add r1, rFP, #OFF_FP_SHADOWFRAME 8098 mov r2, rPC 8099 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8100 8101/* ------------------------------ */ 8102 .balign 128 8103.L_ALT_op_filled_new_array_range: /* 0x25 */ 8104/* File: arm/alt_stub.S */ 8105/* 8106 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8107 * any interesting requests and then jump to the real instruction 8108 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8109 */ 8110 .extern MterpCheckBefore 8111 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8112 adrl lr, artMterpAsmInstructionStart + (37 * 128) @ Addr of primary handler. 8113 mov r0, rSELF 8114 add r1, rFP, #OFF_FP_SHADOWFRAME 8115 mov r2, rPC 8116 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8117 8118/* ------------------------------ */ 8119 .balign 128 8120.L_ALT_op_fill_array_data: /* 0x26 */ 8121/* File: arm/alt_stub.S */ 8122/* 8123 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8124 * any interesting requests and then jump to the real instruction 8125 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8126 */ 8127 .extern MterpCheckBefore 8128 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8129 adrl lr, artMterpAsmInstructionStart + (38 * 128) @ Addr of primary handler. 8130 mov r0, rSELF 8131 add r1, rFP, #OFF_FP_SHADOWFRAME 8132 mov r2, rPC 8133 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8134 8135/* ------------------------------ */ 8136 .balign 128 8137.L_ALT_op_throw: /* 0x27 */ 8138/* File: arm/alt_stub.S */ 8139/* 8140 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8141 * any interesting requests and then jump to the real instruction 8142 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8143 */ 8144 .extern MterpCheckBefore 8145 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8146 adrl lr, artMterpAsmInstructionStart + (39 * 128) @ Addr of primary handler. 8147 mov r0, rSELF 8148 add r1, rFP, #OFF_FP_SHADOWFRAME 8149 mov r2, rPC 8150 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8151 8152/* ------------------------------ */ 8153 .balign 128 8154.L_ALT_op_goto: /* 0x28 */ 8155/* File: arm/alt_stub.S */ 8156/* 8157 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8158 * any interesting requests and then jump to the real instruction 8159 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8160 */ 8161 .extern MterpCheckBefore 8162 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8163 adrl lr, artMterpAsmInstructionStart + (40 * 128) @ Addr of primary handler. 8164 mov r0, rSELF 8165 add r1, rFP, #OFF_FP_SHADOWFRAME 8166 mov r2, rPC 8167 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8168 8169/* ------------------------------ */ 8170 .balign 128 8171.L_ALT_op_goto_16: /* 0x29 */ 8172/* File: arm/alt_stub.S */ 8173/* 8174 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8175 * any interesting requests and then jump to the real instruction 8176 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8177 */ 8178 .extern MterpCheckBefore 8179 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8180 adrl lr, artMterpAsmInstructionStart + (41 * 128) @ Addr of primary handler. 8181 mov r0, rSELF 8182 add r1, rFP, #OFF_FP_SHADOWFRAME 8183 mov r2, rPC 8184 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8185 8186/* ------------------------------ */ 8187 .balign 128 8188.L_ALT_op_goto_32: /* 0x2a */ 8189/* File: arm/alt_stub.S */ 8190/* 8191 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8192 * any interesting requests and then jump to the real instruction 8193 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8194 */ 8195 .extern MterpCheckBefore 8196 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8197 adrl lr, artMterpAsmInstructionStart + (42 * 128) @ Addr of primary handler. 8198 mov r0, rSELF 8199 add r1, rFP, #OFF_FP_SHADOWFRAME 8200 mov r2, rPC 8201 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8202 8203/* ------------------------------ */ 8204 .balign 128 8205.L_ALT_op_packed_switch: /* 0x2b */ 8206/* File: arm/alt_stub.S */ 8207/* 8208 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8209 * any interesting requests and then jump to the real instruction 8210 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8211 */ 8212 .extern MterpCheckBefore 8213 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8214 adrl lr, artMterpAsmInstructionStart + (43 * 128) @ Addr of primary handler. 8215 mov r0, rSELF 8216 add r1, rFP, #OFF_FP_SHADOWFRAME 8217 mov r2, rPC 8218 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8219 8220/* ------------------------------ */ 8221 .balign 128 8222.L_ALT_op_sparse_switch: /* 0x2c */ 8223/* File: arm/alt_stub.S */ 8224/* 8225 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8226 * any interesting requests and then jump to the real instruction 8227 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8228 */ 8229 .extern MterpCheckBefore 8230 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8231 adrl lr, artMterpAsmInstructionStart + (44 * 128) @ Addr of primary handler. 8232 mov r0, rSELF 8233 add r1, rFP, #OFF_FP_SHADOWFRAME 8234 mov r2, rPC 8235 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8236 8237/* ------------------------------ */ 8238 .balign 128 8239.L_ALT_op_cmpl_float: /* 0x2d */ 8240/* File: arm/alt_stub.S */ 8241/* 8242 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8243 * any interesting requests and then jump to the real instruction 8244 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8245 */ 8246 .extern MterpCheckBefore 8247 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8248 adrl lr, artMterpAsmInstructionStart + (45 * 128) @ Addr of primary handler. 8249 mov r0, rSELF 8250 add r1, rFP, #OFF_FP_SHADOWFRAME 8251 mov r2, rPC 8252 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8253 8254/* ------------------------------ */ 8255 .balign 128 8256.L_ALT_op_cmpg_float: /* 0x2e */ 8257/* File: arm/alt_stub.S */ 8258/* 8259 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8260 * any interesting requests and then jump to the real instruction 8261 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8262 */ 8263 .extern MterpCheckBefore 8264 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8265 adrl lr, artMterpAsmInstructionStart + (46 * 128) @ Addr of primary handler. 8266 mov r0, rSELF 8267 add r1, rFP, #OFF_FP_SHADOWFRAME 8268 mov r2, rPC 8269 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8270 8271/* ------------------------------ */ 8272 .balign 128 8273.L_ALT_op_cmpl_double: /* 0x2f */ 8274/* File: arm/alt_stub.S */ 8275/* 8276 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8277 * any interesting requests and then jump to the real instruction 8278 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8279 */ 8280 .extern MterpCheckBefore 8281 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8282 adrl lr, artMterpAsmInstructionStart + (47 * 128) @ Addr of primary handler. 8283 mov r0, rSELF 8284 add r1, rFP, #OFF_FP_SHADOWFRAME 8285 mov r2, rPC 8286 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8287 8288/* ------------------------------ */ 8289 .balign 128 8290.L_ALT_op_cmpg_double: /* 0x30 */ 8291/* File: arm/alt_stub.S */ 8292/* 8293 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8294 * any interesting requests and then jump to the real instruction 8295 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8296 */ 8297 .extern MterpCheckBefore 8298 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8299 adrl lr, artMterpAsmInstructionStart + (48 * 128) @ Addr of primary handler. 8300 mov r0, rSELF 8301 add r1, rFP, #OFF_FP_SHADOWFRAME 8302 mov r2, rPC 8303 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8304 8305/* ------------------------------ */ 8306 .balign 128 8307.L_ALT_op_cmp_long: /* 0x31 */ 8308/* File: arm/alt_stub.S */ 8309/* 8310 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8311 * any interesting requests and then jump to the real instruction 8312 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8313 */ 8314 .extern MterpCheckBefore 8315 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8316 adrl lr, artMterpAsmInstructionStart + (49 * 128) @ Addr of primary handler. 8317 mov r0, rSELF 8318 add r1, rFP, #OFF_FP_SHADOWFRAME 8319 mov r2, rPC 8320 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8321 8322/* ------------------------------ */ 8323 .balign 128 8324.L_ALT_op_if_eq: /* 0x32 */ 8325/* File: arm/alt_stub.S */ 8326/* 8327 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8328 * any interesting requests and then jump to the real instruction 8329 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8330 */ 8331 .extern MterpCheckBefore 8332 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8333 adrl lr, artMterpAsmInstructionStart + (50 * 128) @ Addr of primary handler. 8334 mov r0, rSELF 8335 add r1, rFP, #OFF_FP_SHADOWFRAME 8336 mov r2, rPC 8337 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8338 8339/* ------------------------------ */ 8340 .balign 128 8341.L_ALT_op_if_ne: /* 0x33 */ 8342/* File: arm/alt_stub.S */ 8343/* 8344 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8345 * any interesting requests and then jump to the real instruction 8346 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8347 */ 8348 .extern MterpCheckBefore 8349 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8350 adrl lr, artMterpAsmInstructionStart + (51 * 128) @ Addr of primary handler. 8351 mov r0, rSELF 8352 add r1, rFP, #OFF_FP_SHADOWFRAME 8353 mov r2, rPC 8354 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8355 8356/* ------------------------------ */ 8357 .balign 128 8358.L_ALT_op_if_lt: /* 0x34 */ 8359/* File: arm/alt_stub.S */ 8360/* 8361 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8362 * any interesting requests and then jump to the real instruction 8363 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8364 */ 8365 .extern MterpCheckBefore 8366 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8367 adrl lr, artMterpAsmInstructionStart + (52 * 128) @ Addr of primary handler. 8368 mov r0, rSELF 8369 add r1, rFP, #OFF_FP_SHADOWFRAME 8370 mov r2, rPC 8371 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8372 8373/* ------------------------------ */ 8374 .balign 128 8375.L_ALT_op_if_ge: /* 0x35 */ 8376/* File: arm/alt_stub.S */ 8377/* 8378 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8379 * any interesting requests and then jump to the real instruction 8380 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8381 */ 8382 .extern MterpCheckBefore 8383 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8384 adrl lr, artMterpAsmInstructionStart + (53 * 128) @ Addr of primary handler. 8385 mov r0, rSELF 8386 add r1, rFP, #OFF_FP_SHADOWFRAME 8387 mov r2, rPC 8388 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8389 8390/* ------------------------------ */ 8391 .balign 128 8392.L_ALT_op_if_gt: /* 0x36 */ 8393/* File: arm/alt_stub.S */ 8394/* 8395 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8396 * any interesting requests and then jump to the real instruction 8397 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8398 */ 8399 .extern MterpCheckBefore 8400 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8401 adrl lr, artMterpAsmInstructionStart + (54 * 128) @ Addr of primary handler. 8402 mov r0, rSELF 8403 add r1, rFP, #OFF_FP_SHADOWFRAME 8404 mov r2, rPC 8405 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8406 8407/* ------------------------------ */ 8408 .balign 128 8409.L_ALT_op_if_le: /* 0x37 */ 8410/* File: arm/alt_stub.S */ 8411/* 8412 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8413 * any interesting requests and then jump to the real instruction 8414 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8415 */ 8416 .extern MterpCheckBefore 8417 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8418 adrl lr, artMterpAsmInstructionStart + (55 * 128) @ Addr of primary handler. 8419 mov r0, rSELF 8420 add r1, rFP, #OFF_FP_SHADOWFRAME 8421 mov r2, rPC 8422 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8423 8424/* ------------------------------ */ 8425 .balign 128 8426.L_ALT_op_if_eqz: /* 0x38 */ 8427/* File: arm/alt_stub.S */ 8428/* 8429 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8430 * any interesting requests and then jump to the real instruction 8431 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8432 */ 8433 .extern MterpCheckBefore 8434 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8435 adrl lr, artMterpAsmInstructionStart + (56 * 128) @ Addr of primary handler. 8436 mov r0, rSELF 8437 add r1, rFP, #OFF_FP_SHADOWFRAME 8438 mov r2, rPC 8439 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8440 8441/* ------------------------------ */ 8442 .balign 128 8443.L_ALT_op_if_nez: /* 0x39 */ 8444/* File: arm/alt_stub.S */ 8445/* 8446 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8447 * any interesting requests and then jump to the real instruction 8448 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8449 */ 8450 .extern MterpCheckBefore 8451 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8452 adrl lr, artMterpAsmInstructionStart + (57 * 128) @ Addr of primary handler. 8453 mov r0, rSELF 8454 add r1, rFP, #OFF_FP_SHADOWFRAME 8455 mov r2, rPC 8456 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8457 8458/* ------------------------------ */ 8459 .balign 128 8460.L_ALT_op_if_ltz: /* 0x3a */ 8461/* File: arm/alt_stub.S */ 8462/* 8463 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8464 * any interesting requests and then jump to the real instruction 8465 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8466 */ 8467 .extern MterpCheckBefore 8468 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8469 adrl lr, artMterpAsmInstructionStart + (58 * 128) @ Addr of primary handler. 8470 mov r0, rSELF 8471 add r1, rFP, #OFF_FP_SHADOWFRAME 8472 mov r2, rPC 8473 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8474 8475/* ------------------------------ */ 8476 .balign 128 8477.L_ALT_op_if_gez: /* 0x3b */ 8478/* File: arm/alt_stub.S */ 8479/* 8480 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8481 * any interesting requests and then jump to the real instruction 8482 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8483 */ 8484 .extern MterpCheckBefore 8485 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8486 adrl lr, artMterpAsmInstructionStart + (59 * 128) @ Addr of primary handler. 8487 mov r0, rSELF 8488 add r1, rFP, #OFF_FP_SHADOWFRAME 8489 mov r2, rPC 8490 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8491 8492/* ------------------------------ */ 8493 .balign 128 8494.L_ALT_op_if_gtz: /* 0x3c */ 8495/* File: arm/alt_stub.S */ 8496/* 8497 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8498 * any interesting requests and then jump to the real instruction 8499 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8500 */ 8501 .extern MterpCheckBefore 8502 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8503 adrl lr, artMterpAsmInstructionStart + (60 * 128) @ Addr of primary handler. 8504 mov r0, rSELF 8505 add r1, rFP, #OFF_FP_SHADOWFRAME 8506 mov r2, rPC 8507 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8508 8509/* ------------------------------ */ 8510 .balign 128 8511.L_ALT_op_if_lez: /* 0x3d */ 8512/* File: arm/alt_stub.S */ 8513/* 8514 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8515 * any interesting requests and then jump to the real instruction 8516 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8517 */ 8518 .extern MterpCheckBefore 8519 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8520 adrl lr, artMterpAsmInstructionStart + (61 * 128) @ Addr of primary handler. 8521 mov r0, rSELF 8522 add r1, rFP, #OFF_FP_SHADOWFRAME 8523 mov r2, rPC 8524 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8525 8526/* ------------------------------ */ 8527 .balign 128 8528.L_ALT_op_unused_3e: /* 0x3e */ 8529/* File: arm/alt_stub.S */ 8530/* 8531 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8532 * any interesting requests and then jump to the real instruction 8533 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8534 */ 8535 .extern MterpCheckBefore 8536 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8537 adrl lr, artMterpAsmInstructionStart + (62 * 128) @ Addr of primary handler. 8538 mov r0, rSELF 8539 add r1, rFP, #OFF_FP_SHADOWFRAME 8540 mov r2, rPC 8541 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8542 8543/* ------------------------------ */ 8544 .balign 128 8545.L_ALT_op_unused_3f: /* 0x3f */ 8546/* File: arm/alt_stub.S */ 8547/* 8548 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8549 * any interesting requests and then jump to the real instruction 8550 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8551 */ 8552 .extern MterpCheckBefore 8553 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8554 adrl lr, artMterpAsmInstructionStart + (63 * 128) @ Addr of primary handler. 8555 mov r0, rSELF 8556 add r1, rFP, #OFF_FP_SHADOWFRAME 8557 mov r2, rPC 8558 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8559 8560/* ------------------------------ */ 8561 .balign 128 8562.L_ALT_op_unused_40: /* 0x40 */ 8563/* File: arm/alt_stub.S */ 8564/* 8565 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8566 * any interesting requests and then jump to the real instruction 8567 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8568 */ 8569 .extern MterpCheckBefore 8570 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8571 adrl lr, artMterpAsmInstructionStart + (64 * 128) @ Addr of primary handler. 8572 mov r0, rSELF 8573 add r1, rFP, #OFF_FP_SHADOWFRAME 8574 mov r2, rPC 8575 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8576 8577/* ------------------------------ */ 8578 .balign 128 8579.L_ALT_op_unused_41: /* 0x41 */ 8580/* File: arm/alt_stub.S */ 8581/* 8582 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8583 * any interesting requests and then jump to the real instruction 8584 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8585 */ 8586 .extern MterpCheckBefore 8587 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8588 adrl lr, artMterpAsmInstructionStart + (65 * 128) @ Addr of primary handler. 8589 mov r0, rSELF 8590 add r1, rFP, #OFF_FP_SHADOWFRAME 8591 mov r2, rPC 8592 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8593 8594/* ------------------------------ */ 8595 .balign 128 8596.L_ALT_op_unused_42: /* 0x42 */ 8597/* File: arm/alt_stub.S */ 8598/* 8599 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8600 * any interesting requests and then jump to the real instruction 8601 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8602 */ 8603 .extern MterpCheckBefore 8604 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8605 adrl lr, artMterpAsmInstructionStart + (66 * 128) @ Addr of primary handler. 8606 mov r0, rSELF 8607 add r1, rFP, #OFF_FP_SHADOWFRAME 8608 mov r2, rPC 8609 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8610 8611/* ------------------------------ */ 8612 .balign 128 8613.L_ALT_op_unused_43: /* 0x43 */ 8614/* File: arm/alt_stub.S */ 8615/* 8616 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8617 * any interesting requests and then jump to the real instruction 8618 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8619 */ 8620 .extern MterpCheckBefore 8621 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8622 adrl lr, artMterpAsmInstructionStart + (67 * 128) @ Addr of primary handler. 8623 mov r0, rSELF 8624 add r1, rFP, #OFF_FP_SHADOWFRAME 8625 mov r2, rPC 8626 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8627 8628/* ------------------------------ */ 8629 .balign 128 8630.L_ALT_op_aget: /* 0x44 */ 8631/* File: arm/alt_stub.S */ 8632/* 8633 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8634 * any interesting requests and then jump to the real instruction 8635 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8636 */ 8637 .extern MterpCheckBefore 8638 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8639 adrl lr, artMterpAsmInstructionStart + (68 * 128) @ Addr of primary handler. 8640 mov r0, rSELF 8641 add r1, rFP, #OFF_FP_SHADOWFRAME 8642 mov r2, rPC 8643 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8644 8645/* ------------------------------ */ 8646 .balign 128 8647.L_ALT_op_aget_wide: /* 0x45 */ 8648/* File: arm/alt_stub.S */ 8649/* 8650 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8651 * any interesting requests and then jump to the real instruction 8652 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8653 */ 8654 .extern MterpCheckBefore 8655 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8656 adrl lr, artMterpAsmInstructionStart + (69 * 128) @ Addr of primary handler. 8657 mov r0, rSELF 8658 add r1, rFP, #OFF_FP_SHADOWFRAME 8659 mov r2, rPC 8660 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8661 8662/* ------------------------------ */ 8663 .balign 128 8664.L_ALT_op_aget_object: /* 0x46 */ 8665/* File: arm/alt_stub.S */ 8666/* 8667 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8668 * any interesting requests and then jump to the real instruction 8669 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8670 */ 8671 .extern MterpCheckBefore 8672 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8673 adrl lr, artMterpAsmInstructionStart + (70 * 128) @ Addr of primary handler. 8674 mov r0, rSELF 8675 add r1, rFP, #OFF_FP_SHADOWFRAME 8676 mov r2, rPC 8677 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8678 8679/* ------------------------------ */ 8680 .balign 128 8681.L_ALT_op_aget_boolean: /* 0x47 */ 8682/* File: arm/alt_stub.S */ 8683/* 8684 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8685 * any interesting requests and then jump to the real instruction 8686 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8687 */ 8688 .extern MterpCheckBefore 8689 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8690 adrl lr, artMterpAsmInstructionStart + (71 * 128) @ Addr of primary handler. 8691 mov r0, rSELF 8692 add r1, rFP, #OFF_FP_SHADOWFRAME 8693 mov r2, rPC 8694 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8695 8696/* ------------------------------ */ 8697 .balign 128 8698.L_ALT_op_aget_byte: /* 0x48 */ 8699/* File: arm/alt_stub.S */ 8700/* 8701 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8702 * any interesting requests and then jump to the real instruction 8703 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8704 */ 8705 .extern MterpCheckBefore 8706 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8707 adrl lr, artMterpAsmInstructionStart + (72 * 128) @ Addr of primary handler. 8708 mov r0, rSELF 8709 add r1, rFP, #OFF_FP_SHADOWFRAME 8710 mov r2, rPC 8711 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8712 8713/* ------------------------------ */ 8714 .balign 128 8715.L_ALT_op_aget_char: /* 0x49 */ 8716/* File: arm/alt_stub.S */ 8717/* 8718 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8719 * any interesting requests and then jump to the real instruction 8720 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8721 */ 8722 .extern MterpCheckBefore 8723 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8724 adrl lr, artMterpAsmInstructionStart + (73 * 128) @ Addr of primary handler. 8725 mov r0, rSELF 8726 add r1, rFP, #OFF_FP_SHADOWFRAME 8727 mov r2, rPC 8728 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8729 8730/* ------------------------------ */ 8731 .balign 128 8732.L_ALT_op_aget_short: /* 0x4a */ 8733/* File: arm/alt_stub.S */ 8734/* 8735 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8736 * any interesting requests and then jump to the real instruction 8737 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8738 */ 8739 .extern MterpCheckBefore 8740 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8741 adrl lr, artMterpAsmInstructionStart + (74 * 128) @ Addr of primary handler. 8742 mov r0, rSELF 8743 add r1, rFP, #OFF_FP_SHADOWFRAME 8744 mov r2, rPC 8745 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8746 8747/* ------------------------------ */ 8748 .balign 128 8749.L_ALT_op_aput: /* 0x4b */ 8750/* File: arm/alt_stub.S */ 8751/* 8752 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8753 * any interesting requests and then jump to the real instruction 8754 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8755 */ 8756 .extern MterpCheckBefore 8757 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8758 adrl lr, artMterpAsmInstructionStart + (75 * 128) @ Addr of primary handler. 8759 mov r0, rSELF 8760 add r1, rFP, #OFF_FP_SHADOWFRAME 8761 mov r2, rPC 8762 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8763 8764/* ------------------------------ */ 8765 .balign 128 8766.L_ALT_op_aput_wide: /* 0x4c */ 8767/* File: arm/alt_stub.S */ 8768/* 8769 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8770 * any interesting requests and then jump to the real instruction 8771 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8772 */ 8773 .extern MterpCheckBefore 8774 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8775 adrl lr, artMterpAsmInstructionStart + (76 * 128) @ Addr of primary handler. 8776 mov r0, rSELF 8777 add r1, rFP, #OFF_FP_SHADOWFRAME 8778 mov r2, rPC 8779 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8780 8781/* ------------------------------ */ 8782 .balign 128 8783.L_ALT_op_aput_object: /* 0x4d */ 8784/* File: arm/alt_stub.S */ 8785/* 8786 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8787 * any interesting requests and then jump to the real instruction 8788 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8789 */ 8790 .extern MterpCheckBefore 8791 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8792 adrl lr, artMterpAsmInstructionStart + (77 * 128) @ Addr of primary handler. 8793 mov r0, rSELF 8794 add r1, rFP, #OFF_FP_SHADOWFRAME 8795 mov r2, rPC 8796 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8797 8798/* ------------------------------ */ 8799 .balign 128 8800.L_ALT_op_aput_boolean: /* 0x4e */ 8801/* File: arm/alt_stub.S */ 8802/* 8803 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8804 * any interesting requests and then jump to the real instruction 8805 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8806 */ 8807 .extern MterpCheckBefore 8808 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8809 adrl lr, artMterpAsmInstructionStart + (78 * 128) @ Addr of primary handler. 8810 mov r0, rSELF 8811 add r1, rFP, #OFF_FP_SHADOWFRAME 8812 mov r2, rPC 8813 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8814 8815/* ------------------------------ */ 8816 .balign 128 8817.L_ALT_op_aput_byte: /* 0x4f */ 8818/* File: arm/alt_stub.S */ 8819/* 8820 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8821 * any interesting requests and then jump to the real instruction 8822 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8823 */ 8824 .extern MterpCheckBefore 8825 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8826 adrl lr, artMterpAsmInstructionStart + (79 * 128) @ Addr of primary handler. 8827 mov r0, rSELF 8828 add r1, rFP, #OFF_FP_SHADOWFRAME 8829 mov r2, rPC 8830 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8831 8832/* ------------------------------ */ 8833 .balign 128 8834.L_ALT_op_aput_char: /* 0x50 */ 8835/* File: arm/alt_stub.S */ 8836/* 8837 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8838 * any interesting requests and then jump to the real instruction 8839 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8840 */ 8841 .extern MterpCheckBefore 8842 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8843 adrl lr, artMterpAsmInstructionStart + (80 * 128) @ Addr of primary handler. 8844 mov r0, rSELF 8845 add r1, rFP, #OFF_FP_SHADOWFRAME 8846 mov r2, rPC 8847 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8848 8849/* ------------------------------ */ 8850 .balign 128 8851.L_ALT_op_aput_short: /* 0x51 */ 8852/* File: arm/alt_stub.S */ 8853/* 8854 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8855 * any interesting requests and then jump to the real instruction 8856 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8857 */ 8858 .extern MterpCheckBefore 8859 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8860 adrl lr, artMterpAsmInstructionStart + (81 * 128) @ Addr of primary handler. 8861 mov r0, rSELF 8862 add r1, rFP, #OFF_FP_SHADOWFRAME 8863 mov r2, rPC 8864 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8865 8866/* ------------------------------ */ 8867 .balign 128 8868.L_ALT_op_iget: /* 0x52 */ 8869/* File: arm/alt_stub.S */ 8870/* 8871 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8872 * any interesting requests and then jump to the real instruction 8873 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8874 */ 8875 .extern MterpCheckBefore 8876 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8877 adrl lr, artMterpAsmInstructionStart + (82 * 128) @ Addr of primary handler. 8878 mov r0, rSELF 8879 add r1, rFP, #OFF_FP_SHADOWFRAME 8880 mov r2, rPC 8881 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8882 8883/* ------------------------------ */ 8884 .balign 128 8885.L_ALT_op_iget_wide: /* 0x53 */ 8886/* File: arm/alt_stub.S */ 8887/* 8888 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8889 * any interesting requests and then jump to the real instruction 8890 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8891 */ 8892 .extern MterpCheckBefore 8893 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8894 adrl lr, artMterpAsmInstructionStart + (83 * 128) @ Addr of primary handler. 8895 mov r0, rSELF 8896 add r1, rFP, #OFF_FP_SHADOWFRAME 8897 mov r2, rPC 8898 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8899 8900/* ------------------------------ */ 8901 .balign 128 8902.L_ALT_op_iget_object: /* 0x54 */ 8903/* File: arm/alt_stub.S */ 8904/* 8905 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8906 * any interesting requests and then jump to the real instruction 8907 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8908 */ 8909 .extern MterpCheckBefore 8910 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8911 adrl lr, artMterpAsmInstructionStart + (84 * 128) @ Addr of primary handler. 8912 mov r0, rSELF 8913 add r1, rFP, #OFF_FP_SHADOWFRAME 8914 mov r2, rPC 8915 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8916 8917/* ------------------------------ */ 8918 .balign 128 8919.L_ALT_op_iget_boolean: /* 0x55 */ 8920/* File: arm/alt_stub.S */ 8921/* 8922 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8923 * any interesting requests and then jump to the real instruction 8924 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8925 */ 8926 .extern MterpCheckBefore 8927 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8928 adrl lr, artMterpAsmInstructionStart + (85 * 128) @ Addr of primary handler. 8929 mov r0, rSELF 8930 add r1, rFP, #OFF_FP_SHADOWFRAME 8931 mov r2, rPC 8932 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8933 8934/* ------------------------------ */ 8935 .balign 128 8936.L_ALT_op_iget_byte: /* 0x56 */ 8937/* File: arm/alt_stub.S */ 8938/* 8939 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8940 * any interesting requests and then jump to the real instruction 8941 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8942 */ 8943 .extern MterpCheckBefore 8944 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8945 adrl lr, artMterpAsmInstructionStart + (86 * 128) @ Addr of primary handler. 8946 mov r0, rSELF 8947 add r1, rFP, #OFF_FP_SHADOWFRAME 8948 mov r2, rPC 8949 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8950 8951/* ------------------------------ */ 8952 .balign 128 8953.L_ALT_op_iget_char: /* 0x57 */ 8954/* File: arm/alt_stub.S */ 8955/* 8956 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8957 * any interesting requests and then jump to the real instruction 8958 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8959 */ 8960 .extern MterpCheckBefore 8961 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8962 adrl lr, artMterpAsmInstructionStart + (87 * 128) @ Addr of primary handler. 8963 mov r0, rSELF 8964 add r1, rFP, #OFF_FP_SHADOWFRAME 8965 mov r2, rPC 8966 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8967 8968/* ------------------------------ */ 8969 .balign 128 8970.L_ALT_op_iget_short: /* 0x58 */ 8971/* File: arm/alt_stub.S */ 8972/* 8973 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8974 * any interesting requests and then jump to the real instruction 8975 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8976 */ 8977 .extern MterpCheckBefore 8978 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8979 adrl lr, artMterpAsmInstructionStart + (88 * 128) @ Addr of primary handler. 8980 mov r0, rSELF 8981 add r1, rFP, #OFF_FP_SHADOWFRAME 8982 mov r2, rPC 8983 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 8984 8985/* ------------------------------ */ 8986 .balign 128 8987.L_ALT_op_iput: /* 0x59 */ 8988/* File: arm/alt_stub.S */ 8989/* 8990 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8991 * any interesting requests and then jump to the real instruction 8992 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8993 */ 8994 .extern MterpCheckBefore 8995 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 8996 adrl lr, artMterpAsmInstructionStart + (89 * 128) @ Addr of primary handler. 8997 mov r0, rSELF 8998 add r1, rFP, #OFF_FP_SHADOWFRAME 8999 mov r2, rPC 9000 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9001 9002/* ------------------------------ */ 9003 .balign 128 9004.L_ALT_op_iput_wide: /* 0x5a */ 9005/* File: arm/alt_stub.S */ 9006/* 9007 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9008 * any interesting requests and then jump to the real instruction 9009 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9010 */ 9011 .extern MterpCheckBefore 9012 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9013 adrl lr, artMterpAsmInstructionStart + (90 * 128) @ Addr of primary handler. 9014 mov r0, rSELF 9015 add r1, rFP, #OFF_FP_SHADOWFRAME 9016 mov r2, rPC 9017 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9018 9019/* ------------------------------ */ 9020 .balign 128 9021.L_ALT_op_iput_object: /* 0x5b */ 9022/* File: arm/alt_stub.S */ 9023/* 9024 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9025 * any interesting requests and then jump to the real instruction 9026 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9027 */ 9028 .extern MterpCheckBefore 9029 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9030 adrl lr, artMterpAsmInstructionStart + (91 * 128) @ Addr of primary handler. 9031 mov r0, rSELF 9032 add r1, rFP, #OFF_FP_SHADOWFRAME 9033 mov r2, rPC 9034 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9035 9036/* ------------------------------ */ 9037 .balign 128 9038.L_ALT_op_iput_boolean: /* 0x5c */ 9039/* File: arm/alt_stub.S */ 9040/* 9041 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9042 * any interesting requests and then jump to the real instruction 9043 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9044 */ 9045 .extern MterpCheckBefore 9046 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9047 adrl lr, artMterpAsmInstructionStart + (92 * 128) @ Addr of primary handler. 9048 mov r0, rSELF 9049 add r1, rFP, #OFF_FP_SHADOWFRAME 9050 mov r2, rPC 9051 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9052 9053/* ------------------------------ */ 9054 .balign 128 9055.L_ALT_op_iput_byte: /* 0x5d */ 9056/* File: arm/alt_stub.S */ 9057/* 9058 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9059 * any interesting requests and then jump to the real instruction 9060 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9061 */ 9062 .extern MterpCheckBefore 9063 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9064 adrl lr, artMterpAsmInstructionStart + (93 * 128) @ Addr of primary handler. 9065 mov r0, rSELF 9066 add r1, rFP, #OFF_FP_SHADOWFRAME 9067 mov r2, rPC 9068 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9069 9070/* ------------------------------ */ 9071 .balign 128 9072.L_ALT_op_iput_char: /* 0x5e */ 9073/* File: arm/alt_stub.S */ 9074/* 9075 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9076 * any interesting requests and then jump to the real instruction 9077 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9078 */ 9079 .extern MterpCheckBefore 9080 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9081 adrl lr, artMterpAsmInstructionStart + (94 * 128) @ Addr of primary handler. 9082 mov r0, rSELF 9083 add r1, rFP, #OFF_FP_SHADOWFRAME 9084 mov r2, rPC 9085 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9086 9087/* ------------------------------ */ 9088 .balign 128 9089.L_ALT_op_iput_short: /* 0x5f */ 9090/* File: arm/alt_stub.S */ 9091/* 9092 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9093 * any interesting requests and then jump to the real instruction 9094 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9095 */ 9096 .extern MterpCheckBefore 9097 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9098 adrl lr, artMterpAsmInstructionStart + (95 * 128) @ Addr of primary handler. 9099 mov r0, rSELF 9100 add r1, rFP, #OFF_FP_SHADOWFRAME 9101 mov r2, rPC 9102 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9103 9104/* ------------------------------ */ 9105 .balign 128 9106.L_ALT_op_sget: /* 0x60 */ 9107/* File: arm/alt_stub.S */ 9108/* 9109 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9110 * any interesting requests and then jump to the real instruction 9111 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9112 */ 9113 .extern MterpCheckBefore 9114 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9115 adrl lr, artMterpAsmInstructionStart + (96 * 128) @ Addr of primary handler. 9116 mov r0, rSELF 9117 add r1, rFP, #OFF_FP_SHADOWFRAME 9118 mov r2, rPC 9119 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9120 9121/* ------------------------------ */ 9122 .balign 128 9123.L_ALT_op_sget_wide: /* 0x61 */ 9124/* File: arm/alt_stub.S */ 9125/* 9126 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9127 * any interesting requests and then jump to the real instruction 9128 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9129 */ 9130 .extern MterpCheckBefore 9131 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9132 adrl lr, artMterpAsmInstructionStart + (97 * 128) @ Addr of primary handler. 9133 mov r0, rSELF 9134 add r1, rFP, #OFF_FP_SHADOWFRAME 9135 mov r2, rPC 9136 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9137 9138/* ------------------------------ */ 9139 .balign 128 9140.L_ALT_op_sget_object: /* 0x62 */ 9141/* File: arm/alt_stub.S */ 9142/* 9143 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9144 * any interesting requests and then jump to the real instruction 9145 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9146 */ 9147 .extern MterpCheckBefore 9148 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9149 adrl lr, artMterpAsmInstructionStart + (98 * 128) @ Addr of primary handler. 9150 mov r0, rSELF 9151 add r1, rFP, #OFF_FP_SHADOWFRAME 9152 mov r2, rPC 9153 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9154 9155/* ------------------------------ */ 9156 .balign 128 9157.L_ALT_op_sget_boolean: /* 0x63 */ 9158/* File: arm/alt_stub.S */ 9159/* 9160 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9161 * any interesting requests and then jump to the real instruction 9162 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9163 */ 9164 .extern MterpCheckBefore 9165 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9166 adrl lr, artMterpAsmInstructionStart + (99 * 128) @ Addr of primary handler. 9167 mov r0, rSELF 9168 add r1, rFP, #OFF_FP_SHADOWFRAME 9169 mov r2, rPC 9170 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9171 9172/* ------------------------------ */ 9173 .balign 128 9174.L_ALT_op_sget_byte: /* 0x64 */ 9175/* File: arm/alt_stub.S */ 9176/* 9177 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9178 * any interesting requests and then jump to the real instruction 9179 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9180 */ 9181 .extern MterpCheckBefore 9182 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9183 adrl lr, artMterpAsmInstructionStart + (100 * 128) @ Addr of primary handler. 9184 mov r0, rSELF 9185 add r1, rFP, #OFF_FP_SHADOWFRAME 9186 mov r2, rPC 9187 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9188 9189/* ------------------------------ */ 9190 .balign 128 9191.L_ALT_op_sget_char: /* 0x65 */ 9192/* File: arm/alt_stub.S */ 9193/* 9194 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9195 * any interesting requests and then jump to the real instruction 9196 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9197 */ 9198 .extern MterpCheckBefore 9199 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9200 adrl lr, artMterpAsmInstructionStart + (101 * 128) @ Addr of primary handler. 9201 mov r0, rSELF 9202 add r1, rFP, #OFF_FP_SHADOWFRAME 9203 mov r2, rPC 9204 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9205 9206/* ------------------------------ */ 9207 .balign 128 9208.L_ALT_op_sget_short: /* 0x66 */ 9209/* File: arm/alt_stub.S */ 9210/* 9211 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9212 * any interesting requests and then jump to the real instruction 9213 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9214 */ 9215 .extern MterpCheckBefore 9216 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9217 adrl lr, artMterpAsmInstructionStart + (102 * 128) @ Addr of primary handler. 9218 mov r0, rSELF 9219 add r1, rFP, #OFF_FP_SHADOWFRAME 9220 mov r2, rPC 9221 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9222 9223/* ------------------------------ */ 9224 .balign 128 9225.L_ALT_op_sput: /* 0x67 */ 9226/* File: arm/alt_stub.S */ 9227/* 9228 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9229 * any interesting requests and then jump to the real instruction 9230 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9231 */ 9232 .extern MterpCheckBefore 9233 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9234 adrl lr, artMterpAsmInstructionStart + (103 * 128) @ Addr of primary handler. 9235 mov r0, rSELF 9236 add r1, rFP, #OFF_FP_SHADOWFRAME 9237 mov r2, rPC 9238 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9239 9240/* ------------------------------ */ 9241 .balign 128 9242.L_ALT_op_sput_wide: /* 0x68 */ 9243/* File: arm/alt_stub.S */ 9244/* 9245 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9246 * any interesting requests and then jump to the real instruction 9247 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9248 */ 9249 .extern MterpCheckBefore 9250 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9251 adrl lr, artMterpAsmInstructionStart + (104 * 128) @ Addr of primary handler. 9252 mov r0, rSELF 9253 add r1, rFP, #OFF_FP_SHADOWFRAME 9254 mov r2, rPC 9255 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9256 9257/* ------------------------------ */ 9258 .balign 128 9259.L_ALT_op_sput_object: /* 0x69 */ 9260/* File: arm/alt_stub.S */ 9261/* 9262 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9263 * any interesting requests and then jump to the real instruction 9264 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9265 */ 9266 .extern MterpCheckBefore 9267 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9268 adrl lr, artMterpAsmInstructionStart + (105 * 128) @ Addr of primary handler. 9269 mov r0, rSELF 9270 add r1, rFP, #OFF_FP_SHADOWFRAME 9271 mov r2, rPC 9272 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9273 9274/* ------------------------------ */ 9275 .balign 128 9276.L_ALT_op_sput_boolean: /* 0x6a */ 9277/* File: arm/alt_stub.S */ 9278/* 9279 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9280 * any interesting requests and then jump to the real instruction 9281 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9282 */ 9283 .extern MterpCheckBefore 9284 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9285 adrl lr, artMterpAsmInstructionStart + (106 * 128) @ Addr of primary handler. 9286 mov r0, rSELF 9287 add r1, rFP, #OFF_FP_SHADOWFRAME 9288 mov r2, rPC 9289 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9290 9291/* ------------------------------ */ 9292 .balign 128 9293.L_ALT_op_sput_byte: /* 0x6b */ 9294/* File: arm/alt_stub.S */ 9295/* 9296 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9297 * any interesting requests and then jump to the real instruction 9298 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9299 */ 9300 .extern MterpCheckBefore 9301 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9302 adrl lr, artMterpAsmInstructionStart + (107 * 128) @ Addr of primary handler. 9303 mov r0, rSELF 9304 add r1, rFP, #OFF_FP_SHADOWFRAME 9305 mov r2, rPC 9306 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9307 9308/* ------------------------------ */ 9309 .balign 128 9310.L_ALT_op_sput_char: /* 0x6c */ 9311/* File: arm/alt_stub.S */ 9312/* 9313 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9314 * any interesting requests and then jump to the real instruction 9315 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9316 */ 9317 .extern MterpCheckBefore 9318 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9319 adrl lr, artMterpAsmInstructionStart + (108 * 128) @ Addr of primary handler. 9320 mov r0, rSELF 9321 add r1, rFP, #OFF_FP_SHADOWFRAME 9322 mov r2, rPC 9323 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9324 9325/* ------------------------------ */ 9326 .balign 128 9327.L_ALT_op_sput_short: /* 0x6d */ 9328/* File: arm/alt_stub.S */ 9329/* 9330 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9331 * any interesting requests and then jump to the real instruction 9332 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9333 */ 9334 .extern MterpCheckBefore 9335 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9336 adrl lr, artMterpAsmInstructionStart + (109 * 128) @ Addr of primary handler. 9337 mov r0, rSELF 9338 add r1, rFP, #OFF_FP_SHADOWFRAME 9339 mov r2, rPC 9340 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9341 9342/* ------------------------------ */ 9343 .balign 128 9344.L_ALT_op_invoke_virtual: /* 0x6e */ 9345/* File: arm/alt_stub.S */ 9346/* 9347 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9348 * any interesting requests and then jump to the real instruction 9349 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9350 */ 9351 .extern MterpCheckBefore 9352 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9353 adrl lr, artMterpAsmInstructionStart + (110 * 128) @ Addr of primary handler. 9354 mov r0, rSELF 9355 add r1, rFP, #OFF_FP_SHADOWFRAME 9356 mov r2, rPC 9357 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9358 9359/* ------------------------------ */ 9360 .balign 128 9361.L_ALT_op_invoke_super: /* 0x6f */ 9362/* File: arm/alt_stub.S */ 9363/* 9364 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9365 * any interesting requests and then jump to the real instruction 9366 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9367 */ 9368 .extern MterpCheckBefore 9369 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9370 adrl lr, artMterpAsmInstructionStart + (111 * 128) @ Addr of primary handler. 9371 mov r0, rSELF 9372 add r1, rFP, #OFF_FP_SHADOWFRAME 9373 mov r2, rPC 9374 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9375 9376/* ------------------------------ */ 9377 .balign 128 9378.L_ALT_op_invoke_direct: /* 0x70 */ 9379/* File: arm/alt_stub.S */ 9380/* 9381 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9382 * any interesting requests and then jump to the real instruction 9383 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9384 */ 9385 .extern MterpCheckBefore 9386 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9387 adrl lr, artMterpAsmInstructionStart + (112 * 128) @ Addr of primary handler. 9388 mov r0, rSELF 9389 add r1, rFP, #OFF_FP_SHADOWFRAME 9390 mov r2, rPC 9391 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9392 9393/* ------------------------------ */ 9394 .balign 128 9395.L_ALT_op_invoke_static: /* 0x71 */ 9396/* File: arm/alt_stub.S */ 9397/* 9398 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9399 * any interesting requests and then jump to the real instruction 9400 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9401 */ 9402 .extern MterpCheckBefore 9403 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9404 adrl lr, artMterpAsmInstructionStart + (113 * 128) @ Addr of primary handler. 9405 mov r0, rSELF 9406 add r1, rFP, #OFF_FP_SHADOWFRAME 9407 mov r2, rPC 9408 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9409 9410/* ------------------------------ */ 9411 .balign 128 9412.L_ALT_op_invoke_interface: /* 0x72 */ 9413/* File: arm/alt_stub.S */ 9414/* 9415 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9416 * any interesting requests and then jump to the real instruction 9417 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9418 */ 9419 .extern MterpCheckBefore 9420 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9421 adrl lr, artMterpAsmInstructionStart + (114 * 128) @ Addr of primary handler. 9422 mov r0, rSELF 9423 add r1, rFP, #OFF_FP_SHADOWFRAME 9424 mov r2, rPC 9425 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9426 9427/* ------------------------------ */ 9428 .balign 128 9429.L_ALT_op_return_void_no_barrier: /* 0x73 */ 9430/* File: arm/alt_stub.S */ 9431/* 9432 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9433 * any interesting requests and then jump to the real instruction 9434 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9435 */ 9436 .extern MterpCheckBefore 9437 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9438 adrl lr, artMterpAsmInstructionStart + (115 * 128) @ Addr of primary handler. 9439 mov r0, rSELF 9440 add r1, rFP, #OFF_FP_SHADOWFRAME 9441 mov r2, rPC 9442 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9443 9444/* ------------------------------ */ 9445 .balign 128 9446.L_ALT_op_invoke_virtual_range: /* 0x74 */ 9447/* File: arm/alt_stub.S */ 9448/* 9449 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9450 * any interesting requests and then jump to the real instruction 9451 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9452 */ 9453 .extern MterpCheckBefore 9454 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9455 adrl lr, artMterpAsmInstructionStart + (116 * 128) @ Addr of primary handler. 9456 mov r0, rSELF 9457 add r1, rFP, #OFF_FP_SHADOWFRAME 9458 mov r2, rPC 9459 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9460 9461/* ------------------------------ */ 9462 .balign 128 9463.L_ALT_op_invoke_super_range: /* 0x75 */ 9464/* File: arm/alt_stub.S */ 9465/* 9466 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9467 * any interesting requests and then jump to the real instruction 9468 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9469 */ 9470 .extern MterpCheckBefore 9471 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9472 adrl lr, artMterpAsmInstructionStart + (117 * 128) @ Addr of primary handler. 9473 mov r0, rSELF 9474 add r1, rFP, #OFF_FP_SHADOWFRAME 9475 mov r2, rPC 9476 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9477 9478/* ------------------------------ */ 9479 .balign 128 9480.L_ALT_op_invoke_direct_range: /* 0x76 */ 9481/* File: arm/alt_stub.S */ 9482/* 9483 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9484 * any interesting requests and then jump to the real instruction 9485 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9486 */ 9487 .extern MterpCheckBefore 9488 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9489 adrl lr, artMterpAsmInstructionStart + (118 * 128) @ Addr of primary handler. 9490 mov r0, rSELF 9491 add r1, rFP, #OFF_FP_SHADOWFRAME 9492 mov r2, rPC 9493 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9494 9495/* ------------------------------ */ 9496 .balign 128 9497.L_ALT_op_invoke_static_range: /* 0x77 */ 9498/* File: arm/alt_stub.S */ 9499/* 9500 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9501 * any interesting requests and then jump to the real instruction 9502 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9503 */ 9504 .extern MterpCheckBefore 9505 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9506 adrl lr, artMterpAsmInstructionStart + (119 * 128) @ Addr of primary handler. 9507 mov r0, rSELF 9508 add r1, rFP, #OFF_FP_SHADOWFRAME 9509 mov r2, rPC 9510 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9511 9512/* ------------------------------ */ 9513 .balign 128 9514.L_ALT_op_invoke_interface_range: /* 0x78 */ 9515/* File: arm/alt_stub.S */ 9516/* 9517 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9518 * any interesting requests and then jump to the real instruction 9519 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9520 */ 9521 .extern MterpCheckBefore 9522 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9523 adrl lr, artMterpAsmInstructionStart + (120 * 128) @ Addr of primary handler. 9524 mov r0, rSELF 9525 add r1, rFP, #OFF_FP_SHADOWFRAME 9526 mov r2, rPC 9527 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9528 9529/* ------------------------------ */ 9530 .balign 128 9531.L_ALT_op_unused_79: /* 0x79 */ 9532/* File: arm/alt_stub.S */ 9533/* 9534 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9535 * any interesting requests and then jump to the real instruction 9536 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9537 */ 9538 .extern MterpCheckBefore 9539 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9540 adrl lr, artMterpAsmInstructionStart + (121 * 128) @ Addr of primary handler. 9541 mov r0, rSELF 9542 add r1, rFP, #OFF_FP_SHADOWFRAME 9543 mov r2, rPC 9544 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9545 9546/* ------------------------------ */ 9547 .balign 128 9548.L_ALT_op_unused_7a: /* 0x7a */ 9549/* File: arm/alt_stub.S */ 9550/* 9551 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9552 * any interesting requests and then jump to the real instruction 9553 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9554 */ 9555 .extern MterpCheckBefore 9556 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9557 adrl lr, artMterpAsmInstructionStart + (122 * 128) @ Addr of primary handler. 9558 mov r0, rSELF 9559 add r1, rFP, #OFF_FP_SHADOWFRAME 9560 mov r2, rPC 9561 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9562 9563/* ------------------------------ */ 9564 .balign 128 9565.L_ALT_op_neg_int: /* 0x7b */ 9566/* File: arm/alt_stub.S */ 9567/* 9568 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9569 * any interesting requests and then jump to the real instruction 9570 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9571 */ 9572 .extern MterpCheckBefore 9573 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9574 adrl lr, artMterpAsmInstructionStart + (123 * 128) @ Addr of primary handler. 9575 mov r0, rSELF 9576 add r1, rFP, #OFF_FP_SHADOWFRAME 9577 mov r2, rPC 9578 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9579 9580/* ------------------------------ */ 9581 .balign 128 9582.L_ALT_op_not_int: /* 0x7c */ 9583/* File: arm/alt_stub.S */ 9584/* 9585 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9586 * any interesting requests and then jump to the real instruction 9587 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9588 */ 9589 .extern MterpCheckBefore 9590 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9591 adrl lr, artMterpAsmInstructionStart + (124 * 128) @ Addr of primary handler. 9592 mov r0, rSELF 9593 add r1, rFP, #OFF_FP_SHADOWFRAME 9594 mov r2, rPC 9595 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9596 9597/* ------------------------------ */ 9598 .balign 128 9599.L_ALT_op_neg_long: /* 0x7d */ 9600/* File: arm/alt_stub.S */ 9601/* 9602 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9603 * any interesting requests and then jump to the real instruction 9604 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9605 */ 9606 .extern MterpCheckBefore 9607 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9608 adrl lr, artMterpAsmInstructionStart + (125 * 128) @ Addr of primary handler. 9609 mov r0, rSELF 9610 add r1, rFP, #OFF_FP_SHADOWFRAME 9611 mov r2, rPC 9612 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9613 9614/* ------------------------------ */ 9615 .balign 128 9616.L_ALT_op_not_long: /* 0x7e */ 9617/* File: arm/alt_stub.S */ 9618/* 9619 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9620 * any interesting requests and then jump to the real instruction 9621 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9622 */ 9623 .extern MterpCheckBefore 9624 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9625 adrl lr, artMterpAsmInstructionStart + (126 * 128) @ Addr of primary handler. 9626 mov r0, rSELF 9627 add r1, rFP, #OFF_FP_SHADOWFRAME 9628 mov r2, rPC 9629 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9630 9631/* ------------------------------ */ 9632 .balign 128 9633.L_ALT_op_neg_float: /* 0x7f */ 9634/* File: arm/alt_stub.S */ 9635/* 9636 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9637 * any interesting requests and then jump to the real instruction 9638 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9639 */ 9640 .extern MterpCheckBefore 9641 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9642 adrl lr, artMterpAsmInstructionStart + (127 * 128) @ Addr of primary handler. 9643 mov r0, rSELF 9644 add r1, rFP, #OFF_FP_SHADOWFRAME 9645 mov r2, rPC 9646 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9647 9648/* ------------------------------ */ 9649 .balign 128 9650.L_ALT_op_neg_double: /* 0x80 */ 9651/* File: arm/alt_stub.S */ 9652/* 9653 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9654 * any interesting requests and then jump to the real instruction 9655 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9656 */ 9657 .extern MterpCheckBefore 9658 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9659 adrl lr, artMterpAsmInstructionStart + (128 * 128) @ Addr of primary handler. 9660 mov r0, rSELF 9661 add r1, rFP, #OFF_FP_SHADOWFRAME 9662 mov r2, rPC 9663 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9664 9665/* ------------------------------ */ 9666 .balign 128 9667.L_ALT_op_int_to_long: /* 0x81 */ 9668/* File: arm/alt_stub.S */ 9669/* 9670 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9671 * any interesting requests and then jump to the real instruction 9672 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9673 */ 9674 .extern MterpCheckBefore 9675 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9676 adrl lr, artMterpAsmInstructionStart + (129 * 128) @ Addr of primary handler. 9677 mov r0, rSELF 9678 add r1, rFP, #OFF_FP_SHADOWFRAME 9679 mov r2, rPC 9680 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9681 9682/* ------------------------------ */ 9683 .balign 128 9684.L_ALT_op_int_to_float: /* 0x82 */ 9685/* File: arm/alt_stub.S */ 9686/* 9687 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9688 * any interesting requests and then jump to the real instruction 9689 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9690 */ 9691 .extern MterpCheckBefore 9692 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9693 adrl lr, artMterpAsmInstructionStart + (130 * 128) @ Addr of primary handler. 9694 mov r0, rSELF 9695 add r1, rFP, #OFF_FP_SHADOWFRAME 9696 mov r2, rPC 9697 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9698 9699/* ------------------------------ */ 9700 .balign 128 9701.L_ALT_op_int_to_double: /* 0x83 */ 9702/* File: arm/alt_stub.S */ 9703/* 9704 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9705 * any interesting requests and then jump to the real instruction 9706 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9707 */ 9708 .extern MterpCheckBefore 9709 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9710 adrl lr, artMterpAsmInstructionStart + (131 * 128) @ Addr of primary handler. 9711 mov r0, rSELF 9712 add r1, rFP, #OFF_FP_SHADOWFRAME 9713 mov r2, rPC 9714 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9715 9716/* ------------------------------ */ 9717 .balign 128 9718.L_ALT_op_long_to_int: /* 0x84 */ 9719/* File: arm/alt_stub.S */ 9720/* 9721 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9722 * any interesting requests and then jump to the real instruction 9723 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9724 */ 9725 .extern MterpCheckBefore 9726 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9727 adrl lr, artMterpAsmInstructionStart + (132 * 128) @ Addr of primary handler. 9728 mov r0, rSELF 9729 add r1, rFP, #OFF_FP_SHADOWFRAME 9730 mov r2, rPC 9731 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9732 9733/* ------------------------------ */ 9734 .balign 128 9735.L_ALT_op_long_to_float: /* 0x85 */ 9736/* File: arm/alt_stub.S */ 9737/* 9738 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9739 * any interesting requests and then jump to the real instruction 9740 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9741 */ 9742 .extern MterpCheckBefore 9743 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9744 adrl lr, artMterpAsmInstructionStart + (133 * 128) @ Addr of primary handler. 9745 mov r0, rSELF 9746 add r1, rFP, #OFF_FP_SHADOWFRAME 9747 mov r2, rPC 9748 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9749 9750/* ------------------------------ */ 9751 .balign 128 9752.L_ALT_op_long_to_double: /* 0x86 */ 9753/* File: arm/alt_stub.S */ 9754/* 9755 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9756 * any interesting requests and then jump to the real instruction 9757 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9758 */ 9759 .extern MterpCheckBefore 9760 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9761 adrl lr, artMterpAsmInstructionStart + (134 * 128) @ Addr of primary handler. 9762 mov r0, rSELF 9763 add r1, rFP, #OFF_FP_SHADOWFRAME 9764 mov r2, rPC 9765 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9766 9767/* ------------------------------ */ 9768 .balign 128 9769.L_ALT_op_float_to_int: /* 0x87 */ 9770/* File: arm/alt_stub.S */ 9771/* 9772 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9773 * any interesting requests and then jump to the real instruction 9774 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9775 */ 9776 .extern MterpCheckBefore 9777 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9778 adrl lr, artMterpAsmInstructionStart + (135 * 128) @ Addr of primary handler. 9779 mov r0, rSELF 9780 add r1, rFP, #OFF_FP_SHADOWFRAME 9781 mov r2, rPC 9782 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9783 9784/* ------------------------------ */ 9785 .balign 128 9786.L_ALT_op_float_to_long: /* 0x88 */ 9787/* File: arm/alt_stub.S */ 9788/* 9789 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9790 * any interesting requests and then jump to the real instruction 9791 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9792 */ 9793 .extern MterpCheckBefore 9794 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9795 adrl lr, artMterpAsmInstructionStart + (136 * 128) @ Addr of primary handler. 9796 mov r0, rSELF 9797 add r1, rFP, #OFF_FP_SHADOWFRAME 9798 mov r2, rPC 9799 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9800 9801/* ------------------------------ */ 9802 .balign 128 9803.L_ALT_op_float_to_double: /* 0x89 */ 9804/* File: arm/alt_stub.S */ 9805/* 9806 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9807 * any interesting requests and then jump to the real instruction 9808 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9809 */ 9810 .extern MterpCheckBefore 9811 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9812 adrl lr, artMterpAsmInstructionStart + (137 * 128) @ Addr of primary handler. 9813 mov r0, rSELF 9814 add r1, rFP, #OFF_FP_SHADOWFRAME 9815 mov r2, rPC 9816 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9817 9818/* ------------------------------ */ 9819 .balign 128 9820.L_ALT_op_double_to_int: /* 0x8a */ 9821/* File: arm/alt_stub.S */ 9822/* 9823 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9824 * any interesting requests and then jump to the real instruction 9825 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9826 */ 9827 .extern MterpCheckBefore 9828 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9829 adrl lr, artMterpAsmInstructionStart + (138 * 128) @ Addr of primary handler. 9830 mov r0, rSELF 9831 add r1, rFP, #OFF_FP_SHADOWFRAME 9832 mov r2, rPC 9833 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9834 9835/* ------------------------------ */ 9836 .balign 128 9837.L_ALT_op_double_to_long: /* 0x8b */ 9838/* File: arm/alt_stub.S */ 9839/* 9840 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9841 * any interesting requests and then jump to the real instruction 9842 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9843 */ 9844 .extern MterpCheckBefore 9845 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9846 adrl lr, artMterpAsmInstructionStart + (139 * 128) @ Addr of primary handler. 9847 mov r0, rSELF 9848 add r1, rFP, #OFF_FP_SHADOWFRAME 9849 mov r2, rPC 9850 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9851 9852/* ------------------------------ */ 9853 .balign 128 9854.L_ALT_op_double_to_float: /* 0x8c */ 9855/* File: arm/alt_stub.S */ 9856/* 9857 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9858 * any interesting requests and then jump to the real instruction 9859 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9860 */ 9861 .extern MterpCheckBefore 9862 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9863 adrl lr, artMterpAsmInstructionStart + (140 * 128) @ Addr of primary handler. 9864 mov r0, rSELF 9865 add r1, rFP, #OFF_FP_SHADOWFRAME 9866 mov r2, rPC 9867 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9868 9869/* ------------------------------ */ 9870 .balign 128 9871.L_ALT_op_int_to_byte: /* 0x8d */ 9872/* File: arm/alt_stub.S */ 9873/* 9874 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9875 * any interesting requests and then jump to the real instruction 9876 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9877 */ 9878 .extern MterpCheckBefore 9879 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9880 adrl lr, artMterpAsmInstructionStart + (141 * 128) @ Addr of primary handler. 9881 mov r0, rSELF 9882 add r1, rFP, #OFF_FP_SHADOWFRAME 9883 mov r2, rPC 9884 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9885 9886/* ------------------------------ */ 9887 .balign 128 9888.L_ALT_op_int_to_char: /* 0x8e */ 9889/* File: arm/alt_stub.S */ 9890/* 9891 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9892 * any interesting requests and then jump to the real instruction 9893 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9894 */ 9895 .extern MterpCheckBefore 9896 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9897 adrl lr, artMterpAsmInstructionStart + (142 * 128) @ Addr of primary handler. 9898 mov r0, rSELF 9899 add r1, rFP, #OFF_FP_SHADOWFRAME 9900 mov r2, rPC 9901 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9902 9903/* ------------------------------ */ 9904 .balign 128 9905.L_ALT_op_int_to_short: /* 0x8f */ 9906/* File: arm/alt_stub.S */ 9907/* 9908 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9909 * any interesting requests and then jump to the real instruction 9910 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9911 */ 9912 .extern MterpCheckBefore 9913 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9914 adrl lr, artMterpAsmInstructionStart + (143 * 128) @ Addr of primary handler. 9915 mov r0, rSELF 9916 add r1, rFP, #OFF_FP_SHADOWFRAME 9917 mov r2, rPC 9918 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9919 9920/* ------------------------------ */ 9921 .balign 128 9922.L_ALT_op_add_int: /* 0x90 */ 9923/* File: arm/alt_stub.S */ 9924/* 9925 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9926 * any interesting requests and then jump to the real instruction 9927 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9928 */ 9929 .extern MterpCheckBefore 9930 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9931 adrl lr, artMterpAsmInstructionStart + (144 * 128) @ Addr of primary handler. 9932 mov r0, rSELF 9933 add r1, rFP, #OFF_FP_SHADOWFRAME 9934 mov r2, rPC 9935 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9936 9937/* ------------------------------ */ 9938 .balign 128 9939.L_ALT_op_sub_int: /* 0x91 */ 9940/* File: arm/alt_stub.S */ 9941/* 9942 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9943 * any interesting requests and then jump to the real instruction 9944 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9945 */ 9946 .extern MterpCheckBefore 9947 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9948 adrl lr, artMterpAsmInstructionStart + (145 * 128) @ Addr of primary handler. 9949 mov r0, rSELF 9950 add r1, rFP, #OFF_FP_SHADOWFRAME 9951 mov r2, rPC 9952 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9953 9954/* ------------------------------ */ 9955 .balign 128 9956.L_ALT_op_mul_int: /* 0x92 */ 9957/* File: arm/alt_stub.S */ 9958/* 9959 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9960 * any interesting requests and then jump to the real instruction 9961 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9962 */ 9963 .extern MterpCheckBefore 9964 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9965 adrl lr, artMterpAsmInstructionStart + (146 * 128) @ Addr of primary handler. 9966 mov r0, rSELF 9967 add r1, rFP, #OFF_FP_SHADOWFRAME 9968 mov r2, rPC 9969 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9970 9971/* ------------------------------ */ 9972 .balign 128 9973.L_ALT_op_div_int: /* 0x93 */ 9974/* File: arm/alt_stub.S */ 9975/* 9976 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9977 * any interesting requests and then jump to the real instruction 9978 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9979 */ 9980 .extern MterpCheckBefore 9981 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9982 adrl lr, artMterpAsmInstructionStart + (147 * 128) @ Addr of primary handler. 9983 mov r0, rSELF 9984 add r1, rFP, #OFF_FP_SHADOWFRAME 9985 mov r2, rPC 9986 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 9987 9988/* ------------------------------ */ 9989 .balign 128 9990.L_ALT_op_rem_int: /* 0x94 */ 9991/* File: arm/alt_stub.S */ 9992/* 9993 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9994 * any interesting requests and then jump to the real instruction 9995 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9996 */ 9997 .extern MterpCheckBefore 9998 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 9999 adrl lr, artMterpAsmInstructionStart + (148 * 128) @ Addr of primary handler. 10000 mov r0, rSELF 10001 add r1, rFP, #OFF_FP_SHADOWFRAME 10002 mov r2, rPC 10003 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10004 10005/* ------------------------------ */ 10006 .balign 128 10007.L_ALT_op_and_int: /* 0x95 */ 10008/* File: arm/alt_stub.S */ 10009/* 10010 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10011 * any interesting requests and then jump to the real instruction 10012 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10013 */ 10014 .extern MterpCheckBefore 10015 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10016 adrl lr, artMterpAsmInstructionStart + (149 * 128) @ Addr of primary handler. 10017 mov r0, rSELF 10018 add r1, rFP, #OFF_FP_SHADOWFRAME 10019 mov r2, rPC 10020 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10021 10022/* ------------------------------ */ 10023 .balign 128 10024.L_ALT_op_or_int: /* 0x96 */ 10025/* File: arm/alt_stub.S */ 10026/* 10027 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10028 * any interesting requests and then jump to the real instruction 10029 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10030 */ 10031 .extern MterpCheckBefore 10032 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10033 adrl lr, artMterpAsmInstructionStart + (150 * 128) @ Addr of primary handler. 10034 mov r0, rSELF 10035 add r1, rFP, #OFF_FP_SHADOWFRAME 10036 mov r2, rPC 10037 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10038 10039/* ------------------------------ */ 10040 .balign 128 10041.L_ALT_op_xor_int: /* 0x97 */ 10042/* File: arm/alt_stub.S */ 10043/* 10044 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10045 * any interesting requests and then jump to the real instruction 10046 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10047 */ 10048 .extern MterpCheckBefore 10049 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10050 adrl lr, artMterpAsmInstructionStart + (151 * 128) @ Addr of primary handler. 10051 mov r0, rSELF 10052 add r1, rFP, #OFF_FP_SHADOWFRAME 10053 mov r2, rPC 10054 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10055 10056/* ------------------------------ */ 10057 .balign 128 10058.L_ALT_op_shl_int: /* 0x98 */ 10059/* File: arm/alt_stub.S */ 10060/* 10061 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10062 * any interesting requests and then jump to the real instruction 10063 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10064 */ 10065 .extern MterpCheckBefore 10066 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10067 adrl lr, artMterpAsmInstructionStart + (152 * 128) @ Addr of primary handler. 10068 mov r0, rSELF 10069 add r1, rFP, #OFF_FP_SHADOWFRAME 10070 mov r2, rPC 10071 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10072 10073/* ------------------------------ */ 10074 .balign 128 10075.L_ALT_op_shr_int: /* 0x99 */ 10076/* File: arm/alt_stub.S */ 10077/* 10078 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10079 * any interesting requests and then jump to the real instruction 10080 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10081 */ 10082 .extern MterpCheckBefore 10083 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10084 adrl lr, artMterpAsmInstructionStart + (153 * 128) @ Addr of primary handler. 10085 mov r0, rSELF 10086 add r1, rFP, #OFF_FP_SHADOWFRAME 10087 mov r2, rPC 10088 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10089 10090/* ------------------------------ */ 10091 .balign 128 10092.L_ALT_op_ushr_int: /* 0x9a */ 10093/* File: arm/alt_stub.S */ 10094/* 10095 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10096 * any interesting requests and then jump to the real instruction 10097 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10098 */ 10099 .extern MterpCheckBefore 10100 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10101 adrl lr, artMterpAsmInstructionStart + (154 * 128) @ Addr of primary handler. 10102 mov r0, rSELF 10103 add r1, rFP, #OFF_FP_SHADOWFRAME 10104 mov r2, rPC 10105 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10106 10107/* ------------------------------ */ 10108 .balign 128 10109.L_ALT_op_add_long: /* 0x9b */ 10110/* File: arm/alt_stub.S */ 10111/* 10112 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10113 * any interesting requests and then jump to the real instruction 10114 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10115 */ 10116 .extern MterpCheckBefore 10117 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10118 adrl lr, artMterpAsmInstructionStart + (155 * 128) @ Addr of primary handler. 10119 mov r0, rSELF 10120 add r1, rFP, #OFF_FP_SHADOWFRAME 10121 mov r2, rPC 10122 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10123 10124/* ------------------------------ */ 10125 .balign 128 10126.L_ALT_op_sub_long: /* 0x9c */ 10127/* File: arm/alt_stub.S */ 10128/* 10129 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10130 * any interesting requests and then jump to the real instruction 10131 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10132 */ 10133 .extern MterpCheckBefore 10134 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10135 adrl lr, artMterpAsmInstructionStart + (156 * 128) @ Addr of primary handler. 10136 mov r0, rSELF 10137 add r1, rFP, #OFF_FP_SHADOWFRAME 10138 mov r2, rPC 10139 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10140 10141/* ------------------------------ */ 10142 .balign 128 10143.L_ALT_op_mul_long: /* 0x9d */ 10144/* File: arm/alt_stub.S */ 10145/* 10146 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10147 * any interesting requests and then jump to the real instruction 10148 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10149 */ 10150 .extern MterpCheckBefore 10151 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10152 adrl lr, artMterpAsmInstructionStart + (157 * 128) @ Addr of primary handler. 10153 mov r0, rSELF 10154 add r1, rFP, #OFF_FP_SHADOWFRAME 10155 mov r2, rPC 10156 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10157 10158/* ------------------------------ */ 10159 .balign 128 10160.L_ALT_op_div_long: /* 0x9e */ 10161/* File: arm/alt_stub.S */ 10162/* 10163 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10164 * any interesting requests and then jump to the real instruction 10165 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10166 */ 10167 .extern MterpCheckBefore 10168 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10169 adrl lr, artMterpAsmInstructionStart + (158 * 128) @ Addr of primary handler. 10170 mov r0, rSELF 10171 add r1, rFP, #OFF_FP_SHADOWFRAME 10172 mov r2, rPC 10173 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10174 10175/* ------------------------------ */ 10176 .balign 128 10177.L_ALT_op_rem_long: /* 0x9f */ 10178/* File: arm/alt_stub.S */ 10179/* 10180 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10181 * any interesting requests and then jump to the real instruction 10182 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10183 */ 10184 .extern MterpCheckBefore 10185 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10186 adrl lr, artMterpAsmInstructionStart + (159 * 128) @ Addr of primary handler. 10187 mov r0, rSELF 10188 add r1, rFP, #OFF_FP_SHADOWFRAME 10189 mov r2, rPC 10190 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10191 10192/* ------------------------------ */ 10193 .balign 128 10194.L_ALT_op_and_long: /* 0xa0 */ 10195/* File: arm/alt_stub.S */ 10196/* 10197 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10198 * any interesting requests and then jump to the real instruction 10199 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10200 */ 10201 .extern MterpCheckBefore 10202 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10203 adrl lr, artMterpAsmInstructionStart + (160 * 128) @ Addr of primary handler. 10204 mov r0, rSELF 10205 add r1, rFP, #OFF_FP_SHADOWFRAME 10206 mov r2, rPC 10207 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10208 10209/* ------------------------------ */ 10210 .balign 128 10211.L_ALT_op_or_long: /* 0xa1 */ 10212/* File: arm/alt_stub.S */ 10213/* 10214 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10215 * any interesting requests and then jump to the real instruction 10216 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10217 */ 10218 .extern MterpCheckBefore 10219 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10220 adrl lr, artMterpAsmInstructionStart + (161 * 128) @ Addr of primary handler. 10221 mov r0, rSELF 10222 add r1, rFP, #OFF_FP_SHADOWFRAME 10223 mov r2, rPC 10224 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10225 10226/* ------------------------------ */ 10227 .balign 128 10228.L_ALT_op_xor_long: /* 0xa2 */ 10229/* File: arm/alt_stub.S */ 10230/* 10231 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10232 * any interesting requests and then jump to the real instruction 10233 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10234 */ 10235 .extern MterpCheckBefore 10236 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10237 adrl lr, artMterpAsmInstructionStart + (162 * 128) @ Addr of primary handler. 10238 mov r0, rSELF 10239 add r1, rFP, #OFF_FP_SHADOWFRAME 10240 mov r2, rPC 10241 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10242 10243/* ------------------------------ */ 10244 .balign 128 10245.L_ALT_op_shl_long: /* 0xa3 */ 10246/* File: arm/alt_stub.S */ 10247/* 10248 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10249 * any interesting requests and then jump to the real instruction 10250 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10251 */ 10252 .extern MterpCheckBefore 10253 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10254 adrl lr, artMterpAsmInstructionStart + (163 * 128) @ Addr of primary handler. 10255 mov r0, rSELF 10256 add r1, rFP, #OFF_FP_SHADOWFRAME 10257 mov r2, rPC 10258 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10259 10260/* ------------------------------ */ 10261 .balign 128 10262.L_ALT_op_shr_long: /* 0xa4 */ 10263/* File: arm/alt_stub.S */ 10264/* 10265 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10266 * any interesting requests and then jump to the real instruction 10267 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10268 */ 10269 .extern MterpCheckBefore 10270 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10271 adrl lr, artMterpAsmInstructionStart + (164 * 128) @ Addr of primary handler. 10272 mov r0, rSELF 10273 add r1, rFP, #OFF_FP_SHADOWFRAME 10274 mov r2, rPC 10275 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10276 10277/* ------------------------------ */ 10278 .balign 128 10279.L_ALT_op_ushr_long: /* 0xa5 */ 10280/* File: arm/alt_stub.S */ 10281/* 10282 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10283 * any interesting requests and then jump to the real instruction 10284 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10285 */ 10286 .extern MterpCheckBefore 10287 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10288 adrl lr, artMterpAsmInstructionStart + (165 * 128) @ Addr of primary handler. 10289 mov r0, rSELF 10290 add r1, rFP, #OFF_FP_SHADOWFRAME 10291 mov r2, rPC 10292 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10293 10294/* ------------------------------ */ 10295 .balign 128 10296.L_ALT_op_add_float: /* 0xa6 */ 10297/* File: arm/alt_stub.S */ 10298/* 10299 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10300 * any interesting requests and then jump to the real instruction 10301 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10302 */ 10303 .extern MterpCheckBefore 10304 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10305 adrl lr, artMterpAsmInstructionStart + (166 * 128) @ Addr of primary handler. 10306 mov r0, rSELF 10307 add r1, rFP, #OFF_FP_SHADOWFRAME 10308 mov r2, rPC 10309 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10310 10311/* ------------------------------ */ 10312 .balign 128 10313.L_ALT_op_sub_float: /* 0xa7 */ 10314/* File: arm/alt_stub.S */ 10315/* 10316 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10317 * any interesting requests and then jump to the real instruction 10318 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10319 */ 10320 .extern MterpCheckBefore 10321 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10322 adrl lr, artMterpAsmInstructionStart + (167 * 128) @ Addr of primary handler. 10323 mov r0, rSELF 10324 add r1, rFP, #OFF_FP_SHADOWFRAME 10325 mov r2, rPC 10326 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10327 10328/* ------------------------------ */ 10329 .balign 128 10330.L_ALT_op_mul_float: /* 0xa8 */ 10331/* File: arm/alt_stub.S */ 10332/* 10333 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10334 * any interesting requests and then jump to the real instruction 10335 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10336 */ 10337 .extern MterpCheckBefore 10338 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10339 adrl lr, artMterpAsmInstructionStart + (168 * 128) @ Addr of primary handler. 10340 mov r0, rSELF 10341 add r1, rFP, #OFF_FP_SHADOWFRAME 10342 mov r2, rPC 10343 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10344 10345/* ------------------------------ */ 10346 .balign 128 10347.L_ALT_op_div_float: /* 0xa9 */ 10348/* File: arm/alt_stub.S */ 10349/* 10350 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10351 * any interesting requests and then jump to the real instruction 10352 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10353 */ 10354 .extern MterpCheckBefore 10355 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10356 adrl lr, artMterpAsmInstructionStart + (169 * 128) @ Addr of primary handler. 10357 mov r0, rSELF 10358 add r1, rFP, #OFF_FP_SHADOWFRAME 10359 mov r2, rPC 10360 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10361 10362/* ------------------------------ */ 10363 .balign 128 10364.L_ALT_op_rem_float: /* 0xaa */ 10365/* File: arm/alt_stub.S */ 10366/* 10367 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10368 * any interesting requests and then jump to the real instruction 10369 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10370 */ 10371 .extern MterpCheckBefore 10372 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10373 adrl lr, artMterpAsmInstructionStart + (170 * 128) @ Addr of primary handler. 10374 mov r0, rSELF 10375 add r1, rFP, #OFF_FP_SHADOWFRAME 10376 mov r2, rPC 10377 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10378 10379/* ------------------------------ */ 10380 .balign 128 10381.L_ALT_op_add_double: /* 0xab */ 10382/* File: arm/alt_stub.S */ 10383/* 10384 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10385 * any interesting requests and then jump to the real instruction 10386 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10387 */ 10388 .extern MterpCheckBefore 10389 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10390 adrl lr, artMterpAsmInstructionStart + (171 * 128) @ Addr of primary handler. 10391 mov r0, rSELF 10392 add r1, rFP, #OFF_FP_SHADOWFRAME 10393 mov r2, rPC 10394 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10395 10396/* ------------------------------ */ 10397 .balign 128 10398.L_ALT_op_sub_double: /* 0xac */ 10399/* File: arm/alt_stub.S */ 10400/* 10401 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10402 * any interesting requests and then jump to the real instruction 10403 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10404 */ 10405 .extern MterpCheckBefore 10406 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10407 adrl lr, artMterpAsmInstructionStart + (172 * 128) @ Addr of primary handler. 10408 mov r0, rSELF 10409 add r1, rFP, #OFF_FP_SHADOWFRAME 10410 mov r2, rPC 10411 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10412 10413/* ------------------------------ */ 10414 .balign 128 10415.L_ALT_op_mul_double: /* 0xad */ 10416/* File: arm/alt_stub.S */ 10417/* 10418 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10419 * any interesting requests and then jump to the real instruction 10420 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10421 */ 10422 .extern MterpCheckBefore 10423 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10424 adrl lr, artMterpAsmInstructionStart + (173 * 128) @ Addr of primary handler. 10425 mov r0, rSELF 10426 add r1, rFP, #OFF_FP_SHADOWFRAME 10427 mov r2, rPC 10428 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10429 10430/* ------------------------------ */ 10431 .balign 128 10432.L_ALT_op_div_double: /* 0xae */ 10433/* File: arm/alt_stub.S */ 10434/* 10435 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10436 * any interesting requests and then jump to the real instruction 10437 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10438 */ 10439 .extern MterpCheckBefore 10440 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10441 adrl lr, artMterpAsmInstructionStart + (174 * 128) @ Addr of primary handler. 10442 mov r0, rSELF 10443 add r1, rFP, #OFF_FP_SHADOWFRAME 10444 mov r2, rPC 10445 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10446 10447/* ------------------------------ */ 10448 .balign 128 10449.L_ALT_op_rem_double: /* 0xaf */ 10450/* File: arm/alt_stub.S */ 10451/* 10452 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10453 * any interesting requests and then jump to the real instruction 10454 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10455 */ 10456 .extern MterpCheckBefore 10457 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10458 adrl lr, artMterpAsmInstructionStart + (175 * 128) @ Addr of primary handler. 10459 mov r0, rSELF 10460 add r1, rFP, #OFF_FP_SHADOWFRAME 10461 mov r2, rPC 10462 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10463 10464/* ------------------------------ */ 10465 .balign 128 10466.L_ALT_op_add_int_2addr: /* 0xb0 */ 10467/* File: arm/alt_stub.S */ 10468/* 10469 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10470 * any interesting requests and then jump to the real instruction 10471 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10472 */ 10473 .extern MterpCheckBefore 10474 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10475 adrl lr, artMterpAsmInstructionStart + (176 * 128) @ Addr of primary handler. 10476 mov r0, rSELF 10477 add r1, rFP, #OFF_FP_SHADOWFRAME 10478 mov r2, rPC 10479 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10480 10481/* ------------------------------ */ 10482 .balign 128 10483.L_ALT_op_sub_int_2addr: /* 0xb1 */ 10484/* File: arm/alt_stub.S */ 10485/* 10486 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10487 * any interesting requests and then jump to the real instruction 10488 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10489 */ 10490 .extern MterpCheckBefore 10491 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10492 adrl lr, artMterpAsmInstructionStart + (177 * 128) @ Addr of primary handler. 10493 mov r0, rSELF 10494 add r1, rFP, #OFF_FP_SHADOWFRAME 10495 mov r2, rPC 10496 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10497 10498/* ------------------------------ */ 10499 .balign 128 10500.L_ALT_op_mul_int_2addr: /* 0xb2 */ 10501/* File: arm/alt_stub.S */ 10502/* 10503 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10504 * any interesting requests and then jump to the real instruction 10505 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10506 */ 10507 .extern MterpCheckBefore 10508 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10509 adrl lr, artMterpAsmInstructionStart + (178 * 128) @ Addr of primary handler. 10510 mov r0, rSELF 10511 add r1, rFP, #OFF_FP_SHADOWFRAME 10512 mov r2, rPC 10513 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10514 10515/* ------------------------------ */ 10516 .balign 128 10517.L_ALT_op_div_int_2addr: /* 0xb3 */ 10518/* File: arm/alt_stub.S */ 10519/* 10520 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10521 * any interesting requests and then jump to the real instruction 10522 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10523 */ 10524 .extern MterpCheckBefore 10525 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10526 adrl lr, artMterpAsmInstructionStart + (179 * 128) @ Addr of primary handler. 10527 mov r0, rSELF 10528 add r1, rFP, #OFF_FP_SHADOWFRAME 10529 mov r2, rPC 10530 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10531 10532/* ------------------------------ */ 10533 .balign 128 10534.L_ALT_op_rem_int_2addr: /* 0xb4 */ 10535/* File: arm/alt_stub.S */ 10536/* 10537 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10538 * any interesting requests and then jump to the real instruction 10539 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10540 */ 10541 .extern MterpCheckBefore 10542 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10543 adrl lr, artMterpAsmInstructionStart + (180 * 128) @ Addr of primary handler. 10544 mov r0, rSELF 10545 add r1, rFP, #OFF_FP_SHADOWFRAME 10546 mov r2, rPC 10547 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10548 10549/* ------------------------------ */ 10550 .balign 128 10551.L_ALT_op_and_int_2addr: /* 0xb5 */ 10552/* File: arm/alt_stub.S */ 10553/* 10554 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10555 * any interesting requests and then jump to the real instruction 10556 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10557 */ 10558 .extern MterpCheckBefore 10559 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10560 adrl lr, artMterpAsmInstructionStart + (181 * 128) @ Addr of primary handler. 10561 mov r0, rSELF 10562 add r1, rFP, #OFF_FP_SHADOWFRAME 10563 mov r2, rPC 10564 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10565 10566/* ------------------------------ */ 10567 .balign 128 10568.L_ALT_op_or_int_2addr: /* 0xb6 */ 10569/* File: arm/alt_stub.S */ 10570/* 10571 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10572 * any interesting requests and then jump to the real instruction 10573 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10574 */ 10575 .extern MterpCheckBefore 10576 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10577 adrl lr, artMterpAsmInstructionStart + (182 * 128) @ Addr of primary handler. 10578 mov r0, rSELF 10579 add r1, rFP, #OFF_FP_SHADOWFRAME 10580 mov r2, rPC 10581 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10582 10583/* ------------------------------ */ 10584 .balign 128 10585.L_ALT_op_xor_int_2addr: /* 0xb7 */ 10586/* File: arm/alt_stub.S */ 10587/* 10588 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10589 * any interesting requests and then jump to the real instruction 10590 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10591 */ 10592 .extern MterpCheckBefore 10593 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10594 adrl lr, artMterpAsmInstructionStart + (183 * 128) @ Addr of primary handler. 10595 mov r0, rSELF 10596 add r1, rFP, #OFF_FP_SHADOWFRAME 10597 mov r2, rPC 10598 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10599 10600/* ------------------------------ */ 10601 .balign 128 10602.L_ALT_op_shl_int_2addr: /* 0xb8 */ 10603/* File: arm/alt_stub.S */ 10604/* 10605 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10606 * any interesting requests and then jump to the real instruction 10607 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10608 */ 10609 .extern MterpCheckBefore 10610 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10611 adrl lr, artMterpAsmInstructionStart + (184 * 128) @ Addr of primary handler. 10612 mov r0, rSELF 10613 add r1, rFP, #OFF_FP_SHADOWFRAME 10614 mov r2, rPC 10615 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10616 10617/* ------------------------------ */ 10618 .balign 128 10619.L_ALT_op_shr_int_2addr: /* 0xb9 */ 10620/* File: arm/alt_stub.S */ 10621/* 10622 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10623 * any interesting requests and then jump to the real instruction 10624 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10625 */ 10626 .extern MterpCheckBefore 10627 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10628 adrl lr, artMterpAsmInstructionStart + (185 * 128) @ Addr of primary handler. 10629 mov r0, rSELF 10630 add r1, rFP, #OFF_FP_SHADOWFRAME 10631 mov r2, rPC 10632 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10633 10634/* ------------------------------ */ 10635 .balign 128 10636.L_ALT_op_ushr_int_2addr: /* 0xba */ 10637/* File: arm/alt_stub.S */ 10638/* 10639 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10640 * any interesting requests and then jump to the real instruction 10641 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10642 */ 10643 .extern MterpCheckBefore 10644 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10645 adrl lr, artMterpAsmInstructionStart + (186 * 128) @ Addr of primary handler. 10646 mov r0, rSELF 10647 add r1, rFP, #OFF_FP_SHADOWFRAME 10648 mov r2, rPC 10649 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10650 10651/* ------------------------------ */ 10652 .balign 128 10653.L_ALT_op_add_long_2addr: /* 0xbb */ 10654/* File: arm/alt_stub.S */ 10655/* 10656 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10657 * any interesting requests and then jump to the real instruction 10658 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10659 */ 10660 .extern MterpCheckBefore 10661 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10662 adrl lr, artMterpAsmInstructionStart + (187 * 128) @ Addr of primary handler. 10663 mov r0, rSELF 10664 add r1, rFP, #OFF_FP_SHADOWFRAME 10665 mov r2, rPC 10666 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10667 10668/* ------------------------------ */ 10669 .balign 128 10670.L_ALT_op_sub_long_2addr: /* 0xbc */ 10671/* File: arm/alt_stub.S */ 10672/* 10673 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10674 * any interesting requests and then jump to the real instruction 10675 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10676 */ 10677 .extern MterpCheckBefore 10678 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10679 adrl lr, artMterpAsmInstructionStart + (188 * 128) @ Addr of primary handler. 10680 mov r0, rSELF 10681 add r1, rFP, #OFF_FP_SHADOWFRAME 10682 mov r2, rPC 10683 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10684 10685/* ------------------------------ */ 10686 .balign 128 10687.L_ALT_op_mul_long_2addr: /* 0xbd */ 10688/* File: arm/alt_stub.S */ 10689/* 10690 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10691 * any interesting requests and then jump to the real instruction 10692 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10693 */ 10694 .extern MterpCheckBefore 10695 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10696 adrl lr, artMterpAsmInstructionStart + (189 * 128) @ Addr of primary handler. 10697 mov r0, rSELF 10698 add r1, rFP, #OFF_FP_SHADOWFRAME 10699 mov r2, rPC 10700 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10701 10702/* ------------------------------ */ 10703 .balign 128 10704.L_ALT_op_div_long_2addr: /* 0xbe */ 10705/* File: arm/alt_stub.S */ 10706/* 10707 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10708 * any interesting requests and then jump to the real instruction 10709 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10710 */ 10711 .extern MterpCheckBefore 10712 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10713 adrl lr, artMterpAsmInstructionStart + (190 * 128) @ Addr of primary handler. 10714 mov r0, rSELF 10715 add r1, rFP, #OFF_FP_SHADOWFRAME 10716 mov r2, rPC 10717 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10718 10719/* ------------------------------ */ 10720 .balign 128 10721.L_ALT_op_rem_long_2addr: /* 0xbf */ 10722/* File: arm/alt_stub.S */ 10723/* 10724 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10725 * any interesting requests and then jump to the real instruction 10726 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10727 */ 10728 .extern MterpCheckBefore 10729 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10730 adrl lr, artMterpAsmInstructionStart + (191 * 128) @ Addr of primary handler. 10731 mov r0, rSELF 10732 add r1, rFP, #OFF_FP_SHADOWFRAME 10733 mov r2, rPC 10734 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10735 10736/* ------------------------------ */ 10737 .balign 128 10738.L_ALT_op_and_long_2addr: /* 0xc0 */ 10739/* File: arm/alt_stub.S */ 10740/* 10741 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10742 * any interesting requests and then jump to the real instruction 10743 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10744 */ 10745 .extern MterpCheckBefore 10746 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10747 adrl lr, artMterpAsmInstructionStart + (192 * 128) @ Addr of primary handler. 10748 mov r0, rSELF 10749 add r1, rFP, #OFF_FP_SHADOWFRAME 10750 mov r2, rPC 10751 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10752 10753/* ------------------------------ */ 10754 .balign 128 10755.L_ALT_op_or_long_2addr: /* 0xc1 */ 10756/* File: arm/alt_stub.S */ 10757/* 10758 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10759 * any interesting requests and then jump to the real instruction 10760 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10761 */ 10762 .extern MterpCheckBefore 10763 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10764 adrl lr, artMterpAsmInstructionStart + (193 * 128) @ Addr of primary handler. 10765 mov r0, rSELF 10766 add r1, rFP, #OFF_FP_SHADOWFRAME 10767 mov r2, rPC 10768 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10769 10770/* ------------------------------ */ 10771 .balign 128 10772.L_ALT_op_xor_long_2addr: /* 0xc2 */ 10773/* File: arm/alt_stub.S */ 10774/* 10775 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10776 * any interesting requests and then jump to the real instruction 10777 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10778 */ 10779 .extern MterpCheckBefore 10780 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10781 adrl lr, artMterpAsmInstructionStart + (194 * 128) @ Addr of primary handler. 10782 mov r0, rSELF 10783 add r1, rFP, #OFF_FP_SHADOWFRAME 10784 mov r2, rPC 10785 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10786 10787/* ------------------------------ */ 10788 .balign 128 10789.L_ALT_op_shl_long_2addr: /* 0xc3 */ 10790/* File: arm/alt_stub.S */ 10791/* 10792 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10793 * any interesting requests and then jump to the real instruction 10794 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10795 */ 10796 .extern MterpCheckBefore 10797 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10798 adrl lr, artMterpAsmInstructionStart + (195 * 128) @ Addr of primary handler. 10799 mov r0, rSELF 10800 add r1, rFP, #OFF_FP_SHADOWFRAME 10801 mov r2, rPC 10802 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10803 10804/* ------------------------------ */ 10805 .balign 128 10806.L_ALT_op_shr_long_2addr: /* 0xc4 */ 10807/* File: arm/alt_stub.S */ 10808/* 10809 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10810 * any interesting requests and then jump to the real instruction 10811 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10812 */ 10813 .extern MterpCheckBefore 10814 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10815 adrl lr, artMterpAsmInstructionStart + (196 * 128) @ Addr of primary handler. 10816 mov r0, rSELF 10817 add r1, rFP, #OFF_FP_SHADOWFRAME 10818 mov r2, rPC 10819 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10820 10821/* ------------------------------ */ 10822 .balign 128 10823.L_ALT_op_ushr_long_2addr: /* 0xc5 */ 10824/* File: arm/alt_stub.S */ 10825/* 10826 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10827 * any interesting requests and then jump to the real instruction 10828 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10829 */ 10830 .extern MterpCheckBefore 10831 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10832 adrl lr, artMterpAsmInstructionStart + (197 * 128) @ Addr of primary handler. 10833 mov r0, rSELF 10834 add r1, rFP, #OFF_FP_SHADOWFRAME 10835 mov r2, rPC 10836 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10837 10838/* ------------------------------ */ 10839 .balign 128 10840.L_ALT_op_add_float_2addr: /* 0xc6 */ 10841/* File: arm/alt_stub.S */ 10842/* 10843 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10844 * any interesting requests and then jump to the real instruction 10845 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10846 */ 10847 .extern MterpCheckBefore 10848 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10849 adrl lr, artMterpAsmInstructionStart + (198 * 128) @ Addr of primary handler. 10850 mov r0, rSELF 10851 add r1, rFP, #OFF_FP_SHADOWFRAME 10852 mov r2, rPC 10853 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10854 10855/* ------------------------------ */ 10856 .balign 128 10857.L_ALT_op_sub_float_2addr: /* 0xc7 */ 10858/* File: arm/alt_stub.S */ 10859/* 10860 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10861 * any interesting requests and then jump to the real instruction 10862 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10863 */ 10864 .extern MterpCheckBefore 10865 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10866 adrl lr, artMterpAsmInstructionStart + (199 * 128) @ Addr of primary handler. 10867 mov r0, rSELF 10868 add r1, rFP, #OFF_FP_SHADOWFRAME 10869 mov r2, rPC 10870 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10871 10872/* ------------------------------ */ 10873 .balign 128 10874.L_ALT_op_mul_float_2addr: /* 0xc8 */ 10875/* File: arm/alt_stub.S */ 10876/* 10877 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10878 * any interesting requests and then jump to the real instruction 10879 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10880 */ 10881 .extern MterpCheckBefore 10882 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10883 adrl lr, artMterpAsmInstructionStart + (200 * 128) @ Addr of primary handler. 10884 mov r0, rSELF 10885 add r1, rFP, #OFF_FP_SHADOWFRAME 10886 mov r2, rPC 10887 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10888 10889/* ------------------------------ */ 10890 .balign 128 10891.L_ALT_op_div_float_2addr: /* 0xc9 */ 10892/* File: arm/alt_stub.S */ 10893/* 10894 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10895 * any interesting requests and then jump to the real instruction 10896 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10897 */ 10898 .extern MterpCheckBefore 10899 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10900 adrl lr, artMterpAsmInstructionStart + (201 * 128) @ Addr of primary handler. 10901 mov r0, rSELF 10902 add r1, rFP, #OFF_FP_SHADOWFRAME 10903 mov r2, rPC 10904 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10905 10906/* ------------------------------ */ 10907 .balign 128 10908.L_ALT_op_rem_float_2addr: /* 0xca */ 10909/* File: arm/alt_stub.S */ 10910/* 10911 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10912 * any interesting requests and then jump to the real instruction 10913 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10914 */ 10915 .extern MterpCheckBefore 10916 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10917 adrl lr, artMterpAsmInstructionStart + (202 * 128) @ Addr of primary handler. 10918 mov r0, rSELF 10919 add r1, rFP, #OFF_FP_SHADOWFRAME 10920 mov r2, rPC 10921 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10922 10923/* ------------------------------ */ 10924 .balign 128 10925.L_ALT_op_add_double_2addr: /* 0xcb */ 10926/* File: arm/alt_stub.S */ 10927/* 10928 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10929 * any interesting requests and then jump to the real instruction 10930 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10931 */ 10932 .extern MterpCheckBefore 10933 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10934 adrl lr, artMterpAsmInstructionStart + (203 * 128) @ Addr of primary handler. 10935 mov r0, rSELF 10936 add r1, rFP, #OFF_FP_SHADOWFRAME 10937 mov r2, rPC 10938 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10939 10940/* ------------------------------ */ 10941 .balign 128 10942.L_ALT_op_sub_double_2addr: /* 0xcc */ 10943/* File: arm/alt_stub.S */ 10944/* 10945 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10946 * any interesting requests and then jump to the real instruction 10947 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10948 */ 10949 .extern MterpCheckBefore 10950 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10951 adrl lr, artMterpAsmInstructionStart + (204 * 128) @ Addr of primary handler. 10952 mov r0, rSELF 10953 add r1, rFP, #OFF_FP_SHADOWFRAME 10954 mov r2, rPC 10955 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10956 10957/* ------------------------------ */ 10958 .balign 128 10959.L_ALT_op_mul_double_2addr: /* 0xcd */ 10960/* File: arm/alt_stub.S */ 10961/* 10962 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10963 * any interesting requests and then jump to the real instruction 10964 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10965 */ 10966 .extern MterpCheckBefore 10967 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10968 adrl lr, artMterpAsmInstructionStart + (205 * 128) @ Addr of primary handler. 10969 mov r0, rSELF 10970 add r1, rFP, #OFF_FP_SHADOWFRAME 10971 mov r2, rPC 10972 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10973 10974/* ------------------------------ */ 10975 .balign 128 10976.L_ALT_op_div_double_2addr: /* 0xce */ 10977/* File: arm/alt_stub.S */ 10978/* 10979 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10980 * any interesting requests and then jump to the real instruction 10981 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10982 */ 10983 .extern MterpCheckBefore 10984 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 10985 adrl lr, artMterpAsmInstructionStart + (206 * 128) @ Addr of primary handler. 10986 mov r0, rSELF 10987 add r1, rFP, #OFF_FP_SHADOWFRAME 10988 mov r2, rPC 10989 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 10990 10991/* ------------------------------ */ 10992 .balign 128 10993.L_ALT_op_rem_double_2addr: /* 0xcf */ 10994/* File: arm/alt_stub.S */ 10995/* 10996 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10997 * any interesting requests and then jump to the real instruction 10998 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10999 */ 11000 .extern MterpCheckBefore 11001 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11002 adrl lr, artMterpAsmInstructionStart + (207 * 128) @ Addr of primary handler. 11003 mov r0, rSELF 11004 add r1, rFP, #OFF_FP_SHADOWFRAME 11005 mov r2, rPC 11006 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11007 11008/* ------------------------------ */ 11009 .balign 128 11010.L_ALT_op_add_int_lit16: /* 0xd0 */ 11011/* File: arm/alt_stub.S */ 11012/* 11013 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11014 * any interesting requests and then jump to the real instruction 11015 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11016 */ 11017 .extern MterpCheckBefore 11018 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11019 adrl lr, artMterpAsmInstructionStart + (208 * 128) @ Addr of primary handler. 11020 mov r0, rSELF 11021 add r1, rFP, #OFF_FP_SHADOWFRAME 11022 mov r2, rPC 11023 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11024 11025/* ------------------------------ */ 11026 .balign 128 11027.L_ALT_op_rsub_int: /* 0xd1 */ 11028/* File: arm/alt_stub.S */ 11029/* 11030 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11031 * any interesting requests and then jump to the real instruction 11032 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11033 */ 11034 .extern MterpCheckBefore 11035 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11036 adrl lr, artMterpAsmInstructionStart + (209 * 128) @ Addr of primary handler. 11037 mov r0, rSELF 11038 add r1, rFP, #OFF_FP_SHADOWFRAME 11039 mov r2, rPC 11040 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11041 11042/* ------------------------------ */ 11043 .balign 128 11044.L_ALT_op_mul_int_lit16: /* 0xd2 */ 11045/* File: arm/alt_stub.S */ 11046/* 11047 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11048 * any interesting requests and then jump to the real instruction 11049 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11050 */ 11051 .extern MterpCheckBefore 11052 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11053 adrl lr, artMterpAsmInstructionStart + (210 * 128) @ Addr of primary handler. 11054 mov r0, rSELF 11055 add r1, rFP, #OFF_FP_SHADOWFRAME 11056 mov r2, rPC 11057 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11058 11059/* ------------------------------ */ 11060 .balign 128 11061.L_ALT_op_div_int_lit16: /* 0xd3 */ 11062/* File: arm/alt_stub.S */ 11063/* 11064 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11065 * any interesting requests and then jump to the real instruction 11066 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11067 */ 11068 .extern MterpCheckBefore 11069 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11070 adrl lr, artMterpAsmInstructionStart + (211 * 128) @ Addr of primary handler. 11071 mov r0, rSELF 11072 add r1, rFP, #OFF_FP_SHADOWFRAME 11073 mov r2, rPC 11074 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11075 11076/* ------------------------------ */ 11077 .balign 128 11078.L_ALT_op_rem_int_lit16: /* 0xd4 */ 11079/* File: arm/alt_stub.S */ 11080/* 11081 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11082 * any interesting requests and then jump to the real instruction 11083 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11084 */ 11085 .extern MterpCheckBefore 11086 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11087 adrl lr, artMterpAsmInstructionStart + (212 * 128) @ Addr of primary handler. 11088 mov r0, rSELF 11089 add r1, rFP, #OFF_FP_SHADOWFRAME 11090 mov r2, rPC 11091 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11092 11093/* ------------------------------ */ 11094 .balign 128 11095.L_ALT_op_and_int_lit16: /* 0xd5 */ 11096/* File: arm/alt_stub.S */ 11097/* 11098 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11099 * any interesting requests and then jump to the real instruction 11100 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11101 */ 11102 .extern MterpCheckBefore 11103 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11104 adrl lr, artMterpAsmInstructionStart + (213 * 128) @ Addr of primary handler. 11105 mov r0, rSELF 11106 add r1, rFP, #OFF_FP_SHADOWFRAME 11107 mov r2, rPC 11108 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11109 11110/* ------------------------------ */ 11111 .balign 128 11112.L_ALT_op_or_int_lit16: /* 0xd6 */ 11113/* File: arm/alt_stub.S */ 11114/* 11115 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11116 * any interesting requests and then jump to the real instruction 11117 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11118 */ 11119 .extern MterpCheckBefore 11120 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11121 adrl lr, artMterpAsmInstructionStart + (214 * 128) @ Addr of primary handler. 11122 mov r0, rSELF 11123 add r1, rFP, #OFF_FP_SHADOWFRAME 11124 mov r2, rPC 11125 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11126 11127/* ------------------------------ */ 11128 .balign 128 11129.L_ALT_op_xor_int_lit16: /* 0xd7 */ 11130/* File: arm/alt_stub.S */ 11131/* 11132 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11133 * any interesting requests and then jump to the real instruction 11134 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11135 */ 11136 .extern MterpCheckBefore 11137 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11138 adrl lr, artMterpAsmInstructionStart + (215 * 128) @ Addr of primary handler. 11139 mov r0, rSELF 11140 add r1, rFP, #OFF_FP_SHADOWFRAME 11141 mov r2, rPC 11142 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11143 11144/* ------------------------------ */ 11145 .balign 128 11146.L_ALT_op_add_int_lit8: /* 0xd8 */ 11147/* File: arm/alt_stub.S */ 11148/* 11149 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11150 * any interesting requests and then jump to the real instruction 11151 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11152 */ 11153 .extern MterpCheckBefore 11154 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11155 adrl lr, artMterpAsmInstructionStart + (216 * 128) @ Addr of primary handler. 11156 mov r0, rSELF 11157 add r1, rFP, #OFF_FP_SHADOWFRAME 11158 mov r2, rPC 11159 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11160 11161/* ------------------------------ */ 11162 .balign 128 11163.L_ALT_op_rsub_int_lit8: /* 0xd9 */ 11164/* File: arm/alt_stub.S */ 11165/* 11166 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11167 * any interesting requests and then jump to the real instruction 11168 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11169 */ 11170 .extern MterpCheckBefore 11171 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11172 adrl lr, artMterpAsmInstructionStart + (217 * 128) @ Addr of primary handler. 11173 mov r0, rSELF 11174 add r1, rFP, #OFF_FP_SHADOWFRAME 11175 mov r2, rPC 11176 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11177 11178/* ------------------------------ */ 11179 .balign 128 11180.L_ALT_op_mul_int_lit8: /* 0xda */ 11181/* File: arm/alt_stub.S */ 11182/* 11183 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11184 * any interesting requests and then jump to the real instruction 11185 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11186 */ 11187 .extern MterpCheckBefore 11188 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11189 adrl lr, artMterpAsmInstructionStart + (218 * 128) @ Addr of primary handler. 11190 mov r0, rSELF 11191 add r1, rFP, #OFF_FP_SHADOWFRAME 11192 mov r2, rPC 11193 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11194 11195/* ------------------------------ */ 11196 .balign 128 11197.L_ALT_op_div_int_lit8: /* 0xdb */ 11198/* File: arm/alt_stub.S */ 11199/* 11200 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11201 * any interesting requests and then jump to the real instruction 11202 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11203 */ 11204 .extern MterpCheckBefore 11205 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11206 adrl lr, artMterpAsmInstructionStart + (219 * 128) @ Addr of primary handler. 11207 mov r0, rSELF 11208 add r1, rFP, #OFF_FP_SHADOWFRAME 11209 mov r2, rPC 11210 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11211 11212/* ------------------------------ */ 11213 .balign 128 11214.L_ALT_op_rem_int_lit8: /* 0xdc */ 11215/* File: arm/alt_stub.S */ 11216/* 11217 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11218 * any interesting requests and then jump to the real instruction 11219 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11220 */ 11221 .extern MterpCheckBefore 11222 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11223 adrl lr, artMterpAsmInstructionStart + (220 * 128) @ Addr of primary handler. 11224 mov r0, rSELF 11225 add r1, rFP, #OFF_FP_SHADOWFRAME 11226 mov r2, rPC 11227 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11228 11229/* ------------------------------ */ 11230 .balign 128 11231.L_ALT_op_and_int_lit8: /* 0xdd */ 11232/* File: arm/alt_stub.S */ 11233/* 11234 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11235 * any interesting requests and then jump to the real instruction 11236 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11237 */ 11238 .extern MterpCheckBefore 11239 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11240 adrl lr, artMterpAsmInstructionStart + (221 * 128) @ Addr of primary handler. 11241 mov r0, rSELF 11242 add r1, rFP, #OFF_FP_SHADOWFRAME 11243 mov r2, rPC 11244 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11245 11246/* ------------------------------ */ 11247 .balign 128 11248.L_ALT_op_or_int_lit8: /* 0xde */ 11249/* File: arm/alt_stub.S */ 11250/* 11251 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11252 * any interesting requests and then jump to the real instruction 11253 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11254 */ 11255 .extern MterpCheckBefore 11256 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11257 adrl lr, artMterpAsmInstructionStart + (222 * 128) @ Addr of primary handler. 11258 mov r0, rSELF 11259 add r1, rFP, #OFF_FP_SHADOWFRAME 11260 mov r2, rPC 11261 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11262 11263/* ------------------------------ */ 11264 .balign 128 11265.L_ALT_op_xor_int_lit8: /* 0xdf */ 11266/* File: arm/alt_stub.S */ 11267/* 11268 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11269 * any interesting requests and then jump to the real instruction 11270 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11271 */ 11272 .extern MterpCheckBefore 11273 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11274 adrl lr, artMterpAsmInstructionStart + (223 * 128) @ Addr of primary handler. 11275 mov r0, rSELF 11276 add r1, rFP, #OFF_FP_SHADOWFRAME 11277 mov r2, rPC 11278 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11279 11280/* ------------------------------ */ 11281 .balign 128 11282.L_ALT_op_shl_int_lit8: /* 0xe0 */ 11283/* File: arm/alt_stub.S */ 11284/* 11285 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11286 * any interesting requests and then jump to the real instruction 11287 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11288 */ 11289 .extern MterpCheckBefore 11290 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11291 adrl lr, artMterpAsmInstructionStart + (224 * 128) @ Addr of primary handler. 11292 mov r0, rSELF 11293 add r1, rFP, #OFF_FP_SHADOWFRAME 11294 mov r2, rPC 11295 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11296 11297/* ------------------------------ */ 11298 .balign 128 11299.L_ALT_op_shr_int_lit8: /* 0xe1 */ 11300/* File: arm/alt_stub.S */ 11301/* 11302 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11303 * any interesting requests and then jump to the real instruction 11304 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11305 */ 11306 .extern MterpCheckBefore 11307 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11308 adrl lr, artMterpAsmInstructionStart + (225 * 128) @ Addr of primary handler. 11309 mov r0, rSELF 11310 add r1, rFP, #OFF_FP_SHADOWFRAME 11311 mov r2, rPC 11312 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11313 11314/* ------------------------------ */ 11315 .balign 128 11316.L_ALT_op_ushr_int_lit8: /* 0xe2 */ 11317/* File: arm/alt_stub.S */ 11318/* 11319 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11320 * any interesting requests and then jump to the real instruction 11321 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11322 */ 11323 .extern MterpCheckBefore 11324 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11325 adrl lr, artMterpAsmInstructionStart + (226 * 128) @ Addr of primary handler. 11326 mov r0, rSELF 11327 add r1, rFP, #OFF_FP_SHADOWFRAME 11328 mov r2, rPC 11329 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11330 11331/* ------------------------------ */ 11332 .balign 128 11333.L_ALT_op_iget_quick: /* 0xe3 */ 11334/* File: arm/alt_stub.S */ 11335/* 11336 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11337 * any interesting requests and then jump to the real instruction 11338 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11339 */ 11340 .extern MterpCheckBefore 11341 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11342 adrl lr, artMterpAsmInstructionStart + (227 * 128) @ Addr of primary handler. 11343 mov r0, rSELF 11344 add r1, rFP, #OFF_FP_SHADOWFRAME 11345 mov r2, rPC 11346 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11347 11348/* ------------------------------ */ 11349 .balign 128 11350.L_ALT_op_iget_wide_quick: /* 0xe4 */ 11351/* File: arm/alt_stub.S */ 11352/* 11353 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11354 * any interesting requests and then jump to the real instruction 11355 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11356 */ 11357 .extern MterpCheckBefore 11358 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11359 adrl lr, artMterpAsmInstructionStart + (228 * 128) @ Addr of primary handler. 11360 mov r0, rSELF 11361 add r1, rFP, #OFF_FP_SHADOWFRAME 11362 mov r2, rPC 11363 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11364 11365/* ------------------------------ */ 11366 .balign 128 11367.L_ALT_op_iget_object_quick: /* 0xe5 */ 11368/* File: arm/alt_stub.S */ 11369/* 11370 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11371 * any interesting requests and then jump to the real instruction 11372 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11373 */ 11374 .extern MterpCheckBefore 11375 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11376 adrl lr, artMterpAsmInstructionStart + (229 * 128) @ Addr of primary handler. 11377 mov r0, rSELF 11378 add r1, rFP, #OFF_FP_SHADOWFRAME 11379 mov r2, rPC 11380 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11381 11382/* ------------------------------ */ 11383 .balign 128 11384.L_ALT_op_iput_quick: /* 0xe6 */ 11385/* File: arm/alt_stub.S */ 11386/* 11387 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11388 * any interesting requests and then jump to the real instruction 11389 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11390 */ 11391 .extern MterpCheckBefore 11392 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11393 adrl lr, artMterpAsmInstructionStart + (230 * 128) @ Addr of primary handler. 11394 mov r0, rSELF 11395 add r1, rFP, #OFF_FP_SHADOWFRAME 11396 mov r2, rPC 11397 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11398 11399/* ------------------------------ */ 11400 .balign 128 11401.L_ALT_op_iput_wide_quick: /* 0xe7 */ 11402/* File: arm/alt_stub.S */ 11403/* 11404 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11405 * any interesting requests and then jump to the real instruction 11406 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11407 */ 11408 .extern MterpCheckBefore 11409 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11410 adrl lr, artMterpAsmInstructionStart + (231 * 128) @ Addr of primary handler. 11411 mov r0, rSELF 11412 add r1, rFP, #OFF_FP_SHADOWFRAME 11413 mov r2, rPC 11414 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11415 11416/* ------------------------------ */ 11417 .balign 128 11418.L_ALT_op_iput_object_quick: /* 0xe8 */ 11419/* File: arm/alt_stub.S */ 11420/* 11421 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11422 * any interesting requests and then jump to the real instruction 11423 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11424 */ 11425 .extern MterpCheckBefore 11426 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11427 adrl lr, artMterpAsmInstructionStart + (232 * 128) @ Addr of primary handler. 11428 mov r0, rSELF 11429 add r1, rFP, #OFF_FP_SHADOWFRAME 11430 mov r2, rPC 11431 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11432 11433/* ------------------------------ */ 11434 .balign 128 11435.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ 11436/* File: arm/alt_stub.S */ 11437/* 11438 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11439 * any interesting requests and then jump to the real instruction 11440 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11441 */ 11442 .extern MterpCheckBefore 11443 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11444 adrl lr, artMterpAsmInstructionStart + (233 * 128) @ Addr of primary handler. 11445 mov r0, rSELF 11446 add r1, rFP, #OFF_FP_SHADOWFRAME 11447 mov r2, rPC 11448 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11449 11450/* ------------------------------ */ 11451 .balign 128 11452.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ 11453/* File: arm/alt_stub.S */ 11454/* 11455 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11456 * any interesting requests and then jump to the real instruction 11457 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11458 */ 11459 .extern MterpCheckBefore 11460 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11461 adrl lr, artMterpAsmInstructionStart + (234 * 128) @ Addr of primary handler. 11462 mov r0, rSELF 11463 add r1, rFP, #OFF_FP_SHADOWFRAME 11464 mov r2, rPC 11465 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11466 11467/* ------------------------------ */ 11468 .balign 128 11469.L_ALT_op_iput_boolean_quick: /* 0xeb */ 11470/* File: arm/alt_stub.S */ 11471/* 11472 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11473 * any interesting requests and then jump to the real instruction 11474 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11475 */ 11476 .extern MterpCheckBefore 11477 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11478 adrl lr, artMterpAsmInstructionStart + (235 * 128) @ Addr of primary handler. 11479 mov r0, rSELF 11480 add r1, rFP, #OFF_FP_SHADOWFRAME 11481 mov r2, rPC 11482 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11483 11484/* ------------------------------ */ 11485 .balign 128 11486.L_ALT_op_iput_byte_quick: /* 0xec */ 11487/* File: arm/alt_stub.S */ 11488/* 11489 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11490 * any interesting requests and then jump to the real instruction 11491 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11492 */ 11493 .extern MterpCheckBefore 11494 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11495 adrl lr, artMterpAsmInstructionStart + (236 * 128) @ Addr of primary handler. 11496 mov r0, rSELF 11497 add r1, rFP, #OFF_FP_SHADOWFRAME 11498 mov r2, rPC 11499 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11500 11501/* ------------------------------ */ 11502 .balign 128 11503.L_ALT_op_iput_char_quick: /* 0xed */ 11504/* File: arm/alt_stub.S */ 11505/* 11506 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11507 * any interesting requests and then jump to the real instruction 11508 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11509 */ 11510 .extern MterpCheckBefore 11511 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11512 adrl lr, artMterpAsmInstructionStart + (237 * 128) @ Addr of primary handler. 11513 mov r0, rSELF 11514 add r1, rFP, #OFF_FP_SHADOWFRAME 11515 mov r2, rPC 11516 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11517 11518/* ------------------------------ */ 11519 .balign 128 11520.L_ALT_op_iput_short_quick: /* 0xee */ 11521/* File: arm/alt_stub.S */ 11522/* 11523 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11524 * any interesting requests and then jump to the real instruction 11525 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11526 */ 11527 .extern MterpCheckBefore 11528 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11529 adrl lr, artMterpAsmInstructionStart + (238 * 128) @ Addr of primary handler. 11530 mov r0, rSELF 11531 add r1, rFP, #OFF_FP_SHADOWFRAME 11532 mov r2, rPC 11533 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11534 11535/* ------------------------------ */ 11536 .balign 128 11537.L_ALT_op_iget_boolean_quick: /* 0xef */ 11538/* File: arm/alt_stub.S */ 11539/* 11540 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11541 * any interesting requests and then jump to the real instruction 11542 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11543 */ 11544 .extern MterpCheckBefore 11545 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11546 adrl lr, artMterpAsmInstructionStart + (239 * 128) @ Addr of primary handler. 11547 mov r0, rSELF 11548 add r1, rFP, #OFF_FP_SHADOWFRAME 11549 mov r2, rPC 11550 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11551 11552/* ------------------------------ */ 11553 .balign 128 11554.L_ALT_op_iget_byte_quick: /* 0xf0 */ 11555/* File: arm/alt_stub.S */ 11556/* 11557 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11558 * any interesting requests and then jump to the real instruction 11559 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11560 */ 11561 .extern MterpCheckBefore 11562 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11563 adrl lr, artMterpAsmInstructionStart + (240 * 128) @ Addr of primary handler. 11564 mov r0, rSELF 11565 add r1, rFP, #OFF_FP_SHADOWFRAME 11566 mov r2, rPC 11567 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11568 11569/* ------------------------------ */ 11570 .balign 128 11571.L_ALT_op_iget_char_quick: /* 0xf1 */ 11572/* File: arm/alt_stub.S */ 11573/* 11574 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11575 * any interesting requests and then jump to the real instruction 11576 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11577 */ 11578 .extern MterpCheckBefore 11579 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11580 adrl lr, artMterpAsmInstructionStart + (241 * 128) @ Addr of primary handler. 11581 mov r0, rSELF 11582 add r1, rFP, #OFF_FP_SHADOWFRAME 11583 mov r2, rPC 11584 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11585 11586/* ------------------------------ */ 11587 .balign 128 11588.L_ALT_op_iget_short_quick: /* 0xf2 */ 11589/* File: arm/alt_stub.S */ 11590/* 11591 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11592 * any interesting requests and then jump to the real instruction 11593 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11594 */ 11595 .extern MterpCheckBefore 11596 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11597 adrl lr, artMterpAsmInstructionStart + (242 * 128) @ Addr of primary handler. 11598 mov r0, rSELF 11599 add r1, rFP, #OFF_FP_SHADOWFRAME 11600 mov r2, rPC 11601 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11602 11603/* ------------------------------ */ 11604 .balign 128 11605.L_ALT_op_unused_f3: /* 0xf3 */ 11606/* File: arm/alt_stub.S */ 11607/* 11608 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11609 * any interesting requests and then jump to the real instruction 11610 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11611 */ 11612 .extern MterpCheckBefore 11613 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11614 adrl lr, artMterpAsmInstructionStart + (243 * 128) @ Addr of primary handler. 11615 mov r0, rSELF 11616 add r1, rFP, #OFF_FP_SHADOWFRAME 11617 mov r2, rPC 11618 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11619 11620/* ------------------------------ */ 11621 .balign 128 11622.L_ALT_op_unused_f4: /* 0xf4 */ 11623/* File: arm/alt_stub.S */ 11624/* 11625 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11626 * any interesting requests and then jump to the real instruction 11627 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11628 */ 11629 .extern MterpCheckBefore 11630 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11631 adrl lr, artMterpAsmInstructionStart + (244 * 128) @ Addr of primary handler. 11632 mov r0, rSELF 11633 add r1, rFP, #OFF_FP_SHADOWFRAME 11634 mov r2, rPC 11635 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11636 11637/* ------------------------------ */ 11638 .balign 128 11639.L_ALT_op_unused_f5: /* 0xf5 */ 11640/* File: arm/alt_stub.S */ 11641/* 11642 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11643 * any interesting requests and then jump to the real instruction 11644 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11645 */ 11646 .extern MterpCheckBefore 11647 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11648 adrl lr, artMterpAsmInstructionStart + (245 * 128) @ Addr of primary handler. 11649 mov r0, rSELF 11650 add r1, rFP, #OFF_FP_SHADOWFRAME 11651 mov r2, rPC 11652 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11653 11654/* ------------------------------ */ 11655 .balign 128 11656.L_ALT_op_unused_f6: /* 0xf6 */ 11657/* File: arm/alt_stub.S */ 11658/* 11659 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11660 * any interesting requests and then jump to the real instruction 11661 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11662 */ 11663 .extern MterpCheckBefore 11664 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11665 adrl lr, artMterpAsmInstructionStart + (246 * 128) @ Addr of primary handler. 11666 mov r0, rSELF 11667 add r1, rFP, #OFF_FP_SHADOWFRAME 11668 mov r2, rPC 11669 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11670 11671/* ------------------------------ */ 11672 .balign 128 11673.L_ALT_op_unused_f7: /* 0xf7 */ 11674/* File: arm/alt_stub.S */ 11675/* 11676 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11677 * any interesting requests and then jump to the real instruction 11678 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11679 */ 11680 .extern MterpCheckBefore 11681 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11682 adrl lr, artMterpAsmInstructionStart + (247 * 128) @ Addr of primary handler. 11683 mov r0, rSELF 11684 add r1, rFP, #OFF_FP_SHADOWFRAME 11685 mov r2, rPC 11686 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11687 11688/* ------------------------------ */ 11689 .balign 128 11690.L_ALT_op_unused_f8: /* 0xf8 */ 11691/* File: arm/alt_stub.S */ 11692/* 11693 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11694 * any interesting requests and then jump to the real instruction 11695 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11696 */ 11697 .extern MterpCheckBefore 11698 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11699 adrl lr, artMterpAsmInstructionStart + (248 * 128) @ Addr of primary handler. 11700 mov r0, rSELF 11701 add r1, rFP, #OFF_FP_SHADOWFRAME 11702 mov r2, rPC 11703 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11704 11705/* ------------------------------ */ 11706 .balign 128 11707.L_ALT_op_unused_f9: /* 0xf9 */ 11708/* File: arm/alt_stub.S */ 11709/* 11710 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11711 * any interesting requests and then jump to the real instruction 11712 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11713 */ 11714 .extern MterpCheckBefore 11715 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11716 adrl lr, artMterpAsmInstructionStart + (249 * 128) @ Addr of primary handler. 11717 mov r0, rSELF 11718 add r1, rFP, #OFF_FP_SHADOWFRAME 11719 mov r2, rPC 11720 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11721 11722/* ------------------------------ */ 11723 .balign 128 11724.L_ALT_op_invoke_polymorphic: /* 0xfa */ 11725/* File: arm/alt_stub.S */ 11726/* 11727 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11728 * any interesting requests and then jump to the real instruction 11729 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11730 */ 11731 .extern MterpCheckBefore 11732 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11733 adrl lr, artMterpAsmInstructionStart + (250 * 128) @ Addr of primary handler. 11734 mov r0, rSELF 11735 add r1, rFP, #OFF_FP_SHADOWFRAME 11736 mov r2, rPC 11737 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11738 11739/* ------------------------------ */ 11740 .balign 128 11741.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ 11742/* File: arm/alt_stub.S */ 11743/* 11744 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11745 * any interesting requests and then jump to the real instruction 11746 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11747 */ 11748 .extern MterpCheckBefore 11749 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11750 adrl lr, artMterpAsmInstructionStart + (251 * 128) @ Addr of primary handler. 11751 mov r0, rSELF 11752 add r1, rFP, #OFF_FP_SHADOWFRAME 11753 mov r2, rPC 11754 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11755 11756/* ------------------------------ */ 11757 .balign 128 11758.L_ALT_op_invoke_custom: /* 0xfc */ 11759/* File: arm/alt_stub.S */ 11760/* 11761 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11762 * any interesting requests and then jump to the real instruction 11763 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11764 */ 11765 .extern MterpCheckBefore 11766 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11767 adrl lr, artMterpAsmInstructionStart + (252 * 128) @ Addr of primary handler. 11768 mov r0, rSELF 11769 add r1, rFP, #OFF_FP_SHADOWFRAME 11770 mov r2, rPC 11771 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11772 11773/* ------------------------------ */ 11774 .balign 128 11775.L_ALT_op_invoke_custom_range: /* 0xfd */ 11776/* File: arm/alt_stub.S */ 11777/* 11778 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11779 * any interesting requests and then jump to the real instruction 11780 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11781 */ 11782 .extern MterpCheckBefore 11783 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11784 adrl lr, artMterpAsmInstructionStart + (253 * 128) @ Addr of primary handler. 11785 mov r0, rSELF 11786 add r1, rFP, #OFF_FP_SHADOWFRAME 11787 mov r2, rPC 11788 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11789 11790/* ------------------------------ */ 11791 .balign 128 11792.L_ALT_op_unused_fe: /* 0xfe */ 11793/* File: arm/alt_stub.S */ 11794/* 11795 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11796 * any interesting requests and then jump to the real instruction 11797 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11798 */ 11799 .extern MterpCheckBefore 11800 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11801 adrl lr, artMterpAsmInstructionStart + (254 * 128) @ Addr of primary handler. 11802 mov r0, rSELF 11803 add r1, rFP, #OFF_FP_SHADOWFRAME 11804 mov r2, rPC 11805 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11806 11807/* ------------------------------ */ 11808 .balign 128 11809.L_ALT_op_unused_ff: /* 0xff */ 11810/* File: arm/alt_stub.S */ 11811/* 11812 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11813 * any interesting requests and then jump to the real instruction 11814 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11815 */ 11816 .extern MterpCheckBefore 11817 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] @ refresh IBASE. 11818 adrl lr, artMterpAsmInstructionStart + (255 * 128) @ Addr of primary handler. 11819 mov r0, rSELF 11820 add r1, rFP, #OFF_FP_SHADOWFRAME 11821 mov r2, rPC 11822 b MterpCheckBefore @ (self, shadow_frame, dex_pc_ptr) @ Tail call. 11823 11824 .balign 128 11825 .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart 11826 .global artMterpAsmAltInstructionEnd 11827artMterpAsmAltInstructionEnd: 11828/* File: arm/footer.S */ 11829/* 11830 * =========================================================================== 11831 * Common subroutines and data 11832 * =========================================================================== 11833 */ 11834 11835 .text 11836 .align 2 11837 11838/* 11839 * We've detected a condition that will result in an exception, but the exception 11840 * has not yet been thrown. Just bail out to the reference interpreter to deal with it. 11841 * TUNING: for consistency, we may want to just go ahead and handle these here. 11842 */ 11843common_errDivideByZero: 11844 EXPORT_PC 11845#if MTERP_LOGGING 11846 mov r0, rSELF 11847 add r1, rFP, #OFF_FP_SHADOWFRAME 11848 bl MterpLogDivideByZeroException 11849#endif 11850 b MterpCommonFallback 11851 11852common_errArrayIndex: 11853 EXPORT_PC 11854#if MTERP_LOGGING 11855 mov r0, rSELF 11856 add r1, rFP, #OFF_FP_SHADOWFRAME 11857 bl MterpLogArrayIndexException 11858#endif 11859 b MterpCommonFallback 11860 11861common_errNegativeArraySize: 11862 EXPORT_PC 11863#if MTERP_LOGGING 11864 mov r0, rSELF 11865 add r1, rFP, #OFF_FP_SHADOWFRAME 11866 bl MterpLogNegativeArraySizeException 11867#endif 11868 b MterpCommonFallback 11869 11870common_errNoSuchMethod: 11871 EXPORT_PC 11872#if MTERP_LOGGING 11873 mov r0, rSELF 11874 add r1, rFP, #OFF_FP_SHADOWFRAME 11875 bl MterpLogNoSuchMethodException 11876#endif 11877 b MterpCommonFallback 11878 11879common_errNullObject: 11880 EXPORT_PC 11881#if MTERP_LOGGING 11882 mov r0, rSELF 11883 add r1, rFP, #OFF_FP_SHADOWFRAME 11884 bl MterpLogNullObjectException 11885#endif 11886 b MterpCommonFallback 11887 11888common_exceptionThrown: 11889 EXPORT_PC 11890#if MTERP_LOGGING 11891 mov r0, rSELF 11892 add r1, rFP, #OFF_FP_SHADOWFRAME 11893 bl MterpLogExceptionThrownException 11894#endif 11895 b MterpCommonFallback 11896 11897MterpSuspendFallback: 11898 EXPORT_PC 11899#if MTERP_LOGGING 11900 mov r0, rSELF 11901 add r1, rFP, #OFF_FP_SHADOWFRAME 11902 ldr r2, [rSELF, #THREAD_FLAGS_OFFSET] 11903 bl MterpLogSuspendFallback 11904#endif 11905 b MterpCommonFallback 11906 11907/* 11908 * If we're here, something is out of the ordinary. If there is a pending 11909 * exception, handle it. Otherwise, roll back and retry with the reference 11910 * interpreter. 11911 */ 11912MterpPossibleException: 11913 ldr r0, [rSELF, #THREAD_EXCEPTION_OFFSET] 11914 cmp r0, #0 @ Exception pending? 11915 beq MterpFallback @ If not, fall back to reference interpreter. 11916 /* intentional fallthrough - handle pending exception. */ 11917/* 11918 * On return from a runtime helper routine, we've found a pending exception. 11919 * Can we handle it here - or need to bail out to caller? 11920 * 11921 */ 11922MterpException: 11923 mov r0, rSELF 11924 add r1, rFP, #OFF_FP_SHADOWFRAME 11925 bl MterpHandleException @ (self, shadow_frame) 11926 cmp r0, #0 11927 beq MterpExceptionReturn @ no local catch, back to caller. 11928 ldr r0, [rFP, #OFF_FP_CODE_ITEM] 11929 ldr r1, [rFP, #OFF_FP_DEX_PC] 11930 ldr rIBASE, [rSELF, #THREAD_CURRENT_IBASE_OFFSET] 11931 add rPC, r0, #CODEITEM_INSNS_OFFSET 11932 add rPC, rPC, r1, lsl #1 @ generate new dex_pc_ptr 11933 /* Do we need to switch interpreters? */ 11934 bl MterpShouldSwitchInterpreters 11935 cmp r0, #0 11936 bne MterpFallback 11937 /* resume execution at catch block */ 11938 EXPORT_PC 11939 FETCH_INST 11940 GET_INST_OPCODE ip 11941 GOTO_OPCODE ip 11942 /* NOTE: no fallthrough */ 11943 11944/* 11945 * Common handling for branches with support for Jit profiling. 11946 * On entry: 11947 * rINST <= signed offset 11948 * rPROFILE <= signed hotness countdown (expanded to 32 bits) 11949 * condition bits <= set to establish sign of offset (use "NoFlags" entry if not) 11950 * 11951 * We have quite a few different cases for branch profiling, OSR detection and 11952 * suspend check support here. 11953 * 11954 * Taken backward branches: 11955 * If profiling active, do hotness countdown and report if we hit zero. 11956 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 11957 * Is there a pending suspend request? If so, suspend. 11958 * 11959 * Taken forward branches and not-taken backward branches: 11960 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 11961 * 11962 * Our most common case is expected to be a taken backward branch with active jit profiling, 11963 * but no full OSR check and no pending suspend request. 11964 * Next most common case is not-taken branch with no full OSR check. 11965 * 11966 */ 11967MterpCommonTakenBranchNoFlags: 11968 cmp rINST, #0 11969MterpCommonTakenBranch: 11970 bgt .L_forward_branch @ don't add forward branches to hotness 11971/* 11972 * We need to subtract 1 from positive values and we should not see 0 here, 11973 * so we may use the result of the comparison with -1. 11974 */ 11975#if JIT_CHECK_OSR != -1 11976# error "JIT_CHECK_OSR must be -1." 11977#endif 11978 cmp rPROFILE, #JIT_CHECK_OSR 11979 beq .L_osr_check 11980 subgts rPROFILE, #1 11981 beq .L_add_batch @ counted down to zero - report 11982.L_resume_backward_branch: 11983 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET] 11984 REFRESH_IBASE 11985 add r2, rINST, rINST @ r2<- byte offset 11986 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST 11987 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 11988 bne .L_suspend_request_pending 11989 GET_INST_OPCODE ip @ extract opcode from rINST 11990 GOTO_OPCODE ip @ jump to next instruction 11991 11992.L_suspend_request_pending: 11993 EXPORT_PC 11994 mov r0, rSELF 11995 bl MterpSuspendCheck @ (self) 11996 cmp r0, #0 11997 bne MterpFallback 11998 REFRESH_IBASE @ might have changed during suspend 11999 GET_INST_OPCODE ip @ extract opcode from rINST 12000 GOTO_OPCODE ip @ jump to next instruction 12001 12002.L_no_count_backwards: 12003 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 12004 bne .L_resume_backward_branch 12005.L_osr_check: 12006 mov r0, rSELF 12007 add r1, rFP, #OFF_FP_SHADOWFRAME 12008 mov r2, rINST 12009 EXPORT_PC 12010 bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) 12011 cmp r0, #0 12012 bne MterpOnStackReplacement 12013 b .L_resume_backward_branch 12014 12015.L_forward_branch: 12016 cmp rPROFILE, #JIT_CHECK_OSR @ possible OSR re-entry? 12017 beq .L_check_osr_forward 12018.L_resume_forward_branch: 12019 add r2, rINST, rINST @ r2<- byte offset 12020 FETCH_ADVANCE_INST_RB r2 @ update rPC, load rINST 12021 GET_INST_OPCODE ip @ extract opcode from rINST 12022 GOTO_OPCODE ip @ jump to next instruction 12023 12024.L_check_osr_forward: 12025 mov r0, rSELF 12026 add r1, rFP, #OFF_FP_SHADOWFRAME 12027 mov r2, rINST 12028 EXPORT_PC 12029 bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) 12030 cmp r0, #0 12031 bne MterpOnStackReplacement 12032 b .L_resume_forward_branch 12033 12034.L_add_batch: 12035 add r1, rFP, #OFF_FP_SHADOWFRAME 12036 strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] 12037 ldr r0, [rFP, #OFF_FP_METHOD] 12038 mov r2, rSELF 12039 bl MterpAddHotnessBatch @ (method, shadow_frame, self) 12040 mov rPROFILE, r0 @ restore new hotness countdown to rPROFILE 12041 b .L_no_count_backwards 12042 12043/* 12044 * Entered from the conditional branch handlers when OSR check request active on 12045 * not-taken path. All Dalvik not-taken conditional branch offsets are 2. 12046 */ 12047.L_check_not_taken_osr: 12048 mov r0, rSELF 12049 add r1, rFP, #OFF_FP_SHADOWFRAME 12050 mov r2, #2 12051 EXPORT_PC 12052 bl MterpMaybeDoOnStackReplacement @ (self, shadow_frame, offset) 12053 cmp r0, #0 12054 bne MterpOnStackReplacement 12055 FETCH_ADVANCE_INST 2 12056 GET_INST_OPCODE ip @ extract opcode from rINST 12057 GOTO_OPCODE ip @ jump to next instruction 12058 12059/* 12060 * On-stack replacement has happened, and now we've returned from the compiled method. 12061 */ 12062MterpOnStackReplacement: 12063#if MTERP_LOGGING 12064 mov r0, rSELF 12065 add r1, rFP, #OFF_FP_SHADOWFRAME 12066 mov r2, rINST 12067 bl MterpLogOSR 12068#endif 12069 mov r0, #1 @ Signal normal return 12070 b MterpDone 12071 12072/* 12073 * Bail out to reference interpreter. 12074 */ 12075MterpFallback: 12076 EXPORT_PC 12077#if MTERP_LOGGING 12078 mov r0, rSELF 12079 add r1, rFP, #OFF_FP_SHADOWFRAME 12080 bl MterpLogFallback 12081#endif 12082MterpCommonFallback: 12083 mov r0, #0 @ signal retry with reference interpreter. 12084 b MterpDone 12085 12086/* 12087 * We pushed some registers on the stack in ExecuteMterpImpl, then saved 12088 * SP and LR. Here we restore SP, restore the registers, and then restore 12089 * LR to PC. 12090 * 12091 * On entry: 12092 * uint32_t* rFP (should still be live, pointer to base of vregs) 12093 */ 12094MterpExceptionReturn: 12095 mov r0, #1 @ signal return to caller. 12096 b MterpDone 12097MterpReturn: 12098 ldr r2, [rFP, #OFF_FP_RESULT_REGISTER] 12099 str r0, [r2] 12100 str r1, [r2, #4] 12101 mov r0, #1 @ signal return to caller. 12102MterpDone: 12103/* 12104 * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're 12105 * checking for OSR. If greater than zero, we might have unreported hotness to register 12106 * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE 12107 * should only reach zero immediately after a hotness decrement, and is then reset to either 12108 * a negative special state or the new non-zero countdown value. 12109 */ 12110 cmp rPROFILE, #0 12111 bgt MterpProfileActive @ if > 0, we may have some counts to report. 12112 ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return 12113 12114MterpProfileActive: 12115 mov rINST, r0 @ stash return value 12116 /* Report cached hotness counts */ 12117 ldr r0, [rFP, #OFF_FP_METHOD] 12118 add r1, rFP, #OFF_FP_SHADOWFRAME 12119 mov r2, rSELF 12120 strh rPROFILE, [r1, #SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET] 12121 bl MterpAddHotnessBatch @ (method, shadow_frame, self) 12122 mov r0, rINST @ restore return value 12123 ldmfd sp!, {r3-r10,fp,pc} @ restore 10 regs and return 12124 12125 END ExecuteMterpImpl 12126 12127 12128