1/* 2 * This file was generated automatically by gen-mterp.py for 'mips'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: mips/header.S */ 8/* 9 * Copyright (C) 2016 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24/* 25 Art assembly interpreter notes: 26 27 First validate assembly code by implementing ExecuteXXXImpl() style body (doesn't 28 handle invoke, allows higher-level code to create frame & shadow frame. 29 30 Once that's working, support direct entry code & eliminate shadow frame (and 31 excess locals allocation. 32 33 Some (hopefully) temporary ugliness. We'll treat rFP as pointing to the 34 base of the vreg array within the shadow frame. Access the other fields, 35 dex_pc_, method_ and number_of_vregs_ via negative offsets. For now, we'll continue 36 the shadow frame mechanism of double-storing object references - via rFP & 37 number_of_vregs_. 38 39 */ 40 41#include "asm_support.h" 42 43#if (__mips==32) && (__mips_isa_rev>=2) 44#define MIPS32REVGE2 /* mips32r2 and greater */ 45#if (__mips==32) && (__mips_isa_rev>=5) 46#define FPU64 /* 64 bit FPU */ 47#if (__mips==32) && (__mips_isa_rev>=6) 48#define MIPS32REVGE6 /* mips32r6 and greater */ 49#endif 50#endif 51#endif 52 53/* MIPS definitions and declarations 54 55 reg nick purpose 56 s0 rPC interpreted program counter, used for fetching instructions 57 s1 rFP interpreted frame pointer, used for accessing locals and args 58 s2 rSELF self (Thread) pointer 59 s3 rIBASE interpreted instruction base pointer, used for computed goto 60 s4 rINST first 16-bit code unit of current instruction 61 s5 rOBJ object pointer 62 s6 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). 63 s7 rTEMP used as temp storage that can survive a function call 64 s8 rPROFILE branch profiling countdown 65 66*/ 67 68/* single-purpose registers, given names for clarity */ 69#define rPC s0 70#define rFP s1 71#define rSELF s2 72#define rIBASE s3 73#define rINST s4 74#define rOBJ s5 75#define rREFS s6 76#define rTEMP s7 77#define rPROFILE s8 78 79#define rARG0 a0 80#define rARG1 a1 81#define rARG2 a2 82#define rARG3 a3 83#define rRESULT0 v0 84#define rRESULT1 v1 85 86/* GP register definitions */ 87#define zero $0 /* always zero */ 88#define AT $at /* assembler temp */ 89#define v0 $2 /* return value */ 90#define v1 $3 91#define a0 $4 /* argument registers */ 92#define a1 $5 93#define a2 $6 94#define a3 $7 95#define t0 $8 /* temp registers (not saved across subroutine calls) */ 96#define t1 $9 97#define t2 $10 98#define t3 $11 99#define t4 $12 100#define t5 $13 101#define t6 $14 102#define t7 $15 103#define ta0 $12 /* alias */ 104#define ta1 $13 105#define ta2 $14 106#define ta3 $15 107#define s0 $16 /* saved across subroutine calls (callee saved) */ 108#define s1 $17 109#define s2 $18 110#define s3 $19 111#define s4 $20 112#define s5 $21 113#define s6 $22 114#define s7 $23 115#define t8 $24 /* two more temp registers */ 116#define t9 $25 117#define k0 $26 /* kernel temporary */ 118#define k1 $27 119#define gp $28 /* global pointer */ 120#define sp $29 /* stack pointer */ 121#define s8 $30 /* one more callee saved */ 122#define ra $31 /* return address */ 123 124/* FP register definitions */ 125#define fv0 $f0 126#define fv0f $f1 127#define fv1 $f2 128#define fv1f $f3 129#define fa0 $f12 130#define fa0f $f13 131#define fa1 $f14 132#define fa1f $f15 133#define ft0 $f4 134#define ft0f $f5 135#define ft1 $f6 136#define ft1f $f7 137#define ft2 $f8 138#define ft2f $f9 139#define ft3 $f10 140#define ft3f $f11 141#define ft4 $f16 142#define ft4f $f17 143#define ft5 $f18 144#define ft5f $f19 145#define fs0 $f20 146#define fs0f $f21 147#define fs1 $f22 148#define fs1f $f23 149#define fs2 $f24 150#define fs2f $f25 151#define fs3 $f26 152#define fs3f $f27 153#define fs4 $f28 154#define fs4f $f29 155#define fs5 $f30 156#define fs5f $f31 157 158#ifndef MIPS32REVGE6 159#define fcc0 $fcc0 160#define fcc1 $fcc1 161#endif 162 163#ifdef MIPS32REVGE2 164#define SEB(rd, rt) \ 165 seb rd, rt 166#define SEH(rd, rt) \ 167 seh rd, rt 168#define INSERT_HIGH_HALF(rd_lo, rt_hi) \ 169 ins rd_lo, rt_hi, 16, 16 170#else 171#define SEB(rd, rt) \ 172 sll rd, rt, 24; \ 173 sra rd, rd, 24 174#define SEH(rd, rt) \ 175 sll rd, rt, 16; \ 176 sra rd, rd, 16 177/* Clobbers rt_hi on pre-R2. */ 178#define INSERT_HIGH_HALF(rd_lo, rt_hi) \ 179 sll rt_hi, rt_hi, 16; \ 180 or rd_lo, rt_hi 181#endif 182 183#ifdef FPU64 184#define MOVE_TO_FPU_HIGH(r, flo, fhi) \ 185 mthc1 r, flo 186#else 187#define MOVE_TO_FPU_HIGH(r, flo, fhi) \ 188 mtc1 r, fhi 189#endif 190 191#ifdef MIPS32REVGE6 192#define JR(rt) \ 193 jic rt, 0 194#define LSA(rd, rs, rt, sa) \ 195 .if sa; \ 196 lsa rd, rs, rt, sa; \ 197 .else; \ 198 addu rd, rs, rt; \ 199 .endif 200#else 201#define JR(rt) \ 202 jalr zero, rt 203#define LSA(rd, rs, rt, sa) \ 204 .if sa; \ 205 .set push; \ 206 .set noat; \ 207 sll AT, rs, sa; \ 208 addu rd, AT, rt; \ 209 .set pop; \ 210 .else; \ 211 addu rd, rs, rt; \ 212 .endif 213#endif 214 215/* 216 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, 217 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 218 */ 219#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 220#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 221#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 222#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 223#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 224#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 225#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 226#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET) 227#define OFF_FP_SHADOWFRAME OFF_FP(0) 228 229#define MTERP_PROFILE_BRANCHES 1 230#define MTERP_LOGGING 0 231 232/* 233 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 234 * be done *before* something throws. 235 * 236 * It's okay to do this more than once. 237 * 238 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 239 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 240 * offset into the code_items_[] array. For effiency, we will "export" the 241 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 242 * to convert to a dex pc when needed. 243 */ 244#define EXPORT_PC() \ 245 sw rPC, OFF_FP_DEX_PC_PTR(rFP) 246 247#define EXPORT_DEX_PC(tmp) \ 248 lw tmp, OFF_FP_CODE_ITEM(rFP); \ 249 sw rPC, OFF_FP_DEX_PC_PTR(rFP); \ 250 addu tmp, CODEITEM_INSNS_OFFSET; \ 251 subu tmp, rPC, tmp; \ 252 sra tmp, tmp, 1; \ 253 sw tmp, OFF_FP_DEX_PC(rFP) 254 255/* 256 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 257 */ 258#define FETCH_INST() lhu rINST, (rPC) 259 260/* 261 * Fetch the next instruction from the specified offset. Advances rPC 262 * to point to the next instruction. "_count" is in 16-bit code units. 263 * 264 * This must come AFTER anything that can throw an exception, or the 265 * exception catch may miss. (This also implies that it must come after 266 * EXPORT_PC().) 267 */ 268#define FETCH_ADVANCE_INST(_count) \ 269 lhu rINST, ((_count)*2)(rPC); \ 270 addu rPC, rPC, ((_count) * 2) 271 272/* 273 * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load 274 * rINST ahead of possible exception point. Be sure to manually advance rPC 275 * later. 276 */ 277#define PREFETCH_INST(_count) lhu rINST, ((_count)*2)(rPC) 278 279/* Advance rPC by some number of code units. */ 280#define ADVANCE(_count) addu rPC, rPC, ((_count) * 2) 281 282/* 283 * Fetch the next instruction from an offset specified by rd. Updates 284 * rPC to point to the next instruction. "rd" must specify the distance 285 * in bytes, *not* 16-bit code units, and may be a signed value. 286 */ 287#define FETCH_ADVANCE_INST_RB(rd) \ 288 addu rPC, rPC, rd; \ 289 lhu rINST, (rPC) 290 291/* 292 * Fetch a half-word code unit from an offset past the current PC. The 293 * "_count" value is in 16-bit code units. Does not advance rPC. 294 * 295 * The "_S" variant works the same but treats the value as signed. 296 */ 297#define FETCH(rd, _count) lhu rd, ((_count) * 2)(rPC) 298#define FETCH_S(rd, _count) lh rd, ((_count) * 2)(rPC) 299 300/* 301 * Fetch one byte from an offset past the current PC. Pass in the same 302 * "_count" as you would for FETCH, and an additional 0/1 indicating which 303 * byte of the halfword you want (lo/hi). 304 */ 305#define FETCH_B(rd, _count, _byte) lbu rd, ((_count) * 2 + _byte)(rPC) 306 307/* 308 * Put the instruction's opcode field into the specified register. 309 */ 310#define GET_INST_OPCODE(rd) and rd, rINST, 0xFF 311 312/* 313 * Transform opcode into branch target address. 314 */ 315#define GET_OPCODE_TARGET(rd) \ 316 sll rd, rd, 7; \ 317 addu rd, rIBASE, rd 318 319/* 320 * Begin executing the opcode in rd. 321 */ 322#define GOTO_OPCODE(rd) \ 323 GET_OPCODE_TARGET(rd); \ 324 JR(rd) 325 326/* 327 * Get/set the 32-bit value from a Dalvik register. 328 */ 329#define GET_VREG(rd, rix) LOAD_eas2(rd, rFP, rix) 330 331#define GET_VREG_F(rd, rix) \ 332 .set noat; \ 333 EAS2(AT, rFP, rix); \ 334 l.s rd, (AT); \ 335 .set at 336 337#ifdef MIPS32REVGE6 338#define SET_VREG(rd, rix) \ 339 lsa t8, rix, rFP, 2; \ 340 sw rd, 0(t8); \ 341 lsa t8, rix, rREFS, 2; \ 342 sw zero, 0(t8) 343#else 344#define SET_VREG(rd, rix) \ 345 .set noat; \ 346 sll AT, rix, 2; \ 347 addu t8, rFP, AT; \ 348 sw rd, 0(t8); \ 349 addu t8, rREFS, AT; \ 350 .set at; \ 351 sw zero, 0(t8) 352#endif 353 354#ifdef MIPS32REVGE6 355#define SET_VREG_OBJECT(rd, rix) \ 356 lsa t8, rix, rFP, 2; \ 357 sw rd, 0(t8); \ 358 lsa t8, rix, rREFS, 2; \ 359 sw rd, 0(t8) 360#else 361#define SET_VREG_OBJECT(rd, rix) \ 362 .set noat; \ 363 sll AT, rix, 2; \ 364 addu t8, rFP, AT; \ 365 sw rd, 0(t8); \ 366 addu t8, rREFS, AT; \ 367 .set at; \ 368 sw rd, 0(t8) 369#endif 370 371#ifdef MIPS32REVGE6 372#define SET_VREG64(rlo, rhi, rix) \ 373 lsa t8, rix, rFP, 2; \ 374 sw rlo, 0(t8); \ 375 sw rhi, 4(t8); \ 376 lsa t8, rix, rREFS, 2; \ 377 sw zero, 0(t8); \ 378 sw zero, 4(t8) 379#else 380#define SET_VREG64(rlo, rhi, rix) \ 381 .set noat; \ 382 sll AT, rix, 2; \ 383 addu t8, rFP, AT; \ 384 sw rlo, 0(t8); \ 385 sw rhi, 4(t8); \ 386 addu t8, rREFS, AT; \ 387 .set at; \ 388 sw zero, 0(t8); \ 389 sw zero, 4(t8) 390#endif 391 392#ifdef MIPS32REVGE6 393#define SET_VREG_F(rd, rix) \ 394 lsa t8, rix, rFP, 2; \ 395 s.s rd, 0(t8); \ 396 lsa t8, rix, rREFS, 2; \ 397 sw zero, 0(t8) 398#else 399#define SET_VREG_F(rd, rix) \ 400 .set noat; \ 401 sll AT, rix, 2; \ 402 addu t8, rFP, AT; \ 403 s.s rd, 0(t8); \ 404 addu t8, rREFS, AT; \ 405 .set at; \ 406 sw zero, 0(t8) 407#endif 408 409#ifdef MIPS32REVGE6 410#define SET_VREG64_F(rlo, rhi, rix) \ 411 lsa t8, rix, rFP, 2; \ 412 .set noat; \ 413 mfhc1 AT, rlo; \ 414 s.s rlo, 0(t8); \ 415 sw AT, 4(t8); \ 416 .set at; \ 417 lsa t8, rix, rREFS, 2; \ 418 sw zero, 0(t8); \ 419 sw zero, 4(t8) 420#elif defined(FPU64) 421#define SET_VREG64_F(rlo, rhi, rix) \ 422 .set noat; \ 423 sll AT, rix, 2; \ 424 addu t8, rREFS, AT; \ 425 sw zero, 0(t8); \ 426 sw zero, 4(t8); \ 427 addu t8, rFP, AT; \ 428 mfhc1 AT, rlo; \ 429 sw AT, 4(t8); \ 430 .set at; \ 431 s.s rlo, 0(t8) 432#else 433#define SET_VREG64_F(rlo, rhi, rix) \ 434 .set noat; \ 435 sll AT, rix, 2; \ 436 addu t8, rFP, AT; \ 437 s.s rlo, 0(t8); \ 438 s.s rhi, 4(t8); \ 439 addu t8, rREFS, AT; \ 440 .set at; \ 441 sw zero, 0(t8); \ 442 sw zero, 4(t8) 443#endif 444 445/* Combination of the SET_VREG and GOTO_OPCODE functions to save 1 instruction */ 446#ifdef MIPS32REVGE6 447#define SET_VREG_GOTO(rd, rix, dst) \ 448 .set noreorder; \ 449 GET_OPCODE_TARGET(dst); \ 450 lsa t8, rix, rFP, 2; \ 451 sw rd, 0(t8); \ 452 lsa t8, rix, rREFS, 2; \ 453 jalr zero, dst; \ 454 sw zero, 0(t8); \ 455 .set reorder 456#else 457#define SET_VREG_GOTO(rd, rix, dst) \ 458 .set noreorder; \ 459 GET_OPCODE_TARGET(dst); \ 460 .set noat; \ 461 sll AT, rix, 2; \ 462 addu t8, rFP, AT; \ 463 sw rd, 0(t8); \ 464 addu t8, rREFS, AT; \ 465 .set at; \ 466 jalr zero, dst; \ 467 sw zero, 0(t8); \ 468 .set reorder 469#endif 470 471/* Combination of the SET_VREG_OBJECT and GOTO_OPCODE functions to save 1 instruction */ 472#ifdef MIPS32REVGE6 473#define SET_VREG_OBJECT_GOTO(rd, rix, dst) \ 474 .set noreorder; \ 475 GET_OPCODE_TARGET(dst); \ 476 lsa t8, rix, rFP, 2; \ 477 sw rd, 0(t8); \ 478 lsa t8, rix, rREFS, 2; \ 479 jalr zero, dst; \ 480 sw rd, 0(t8); \ 481 .set reorder 482#else 483#define SET_VREG_OBJECT_GOTO(rd, rix, dst) \ 484 .set noreorder; \ 485 GET_OPCODE_TARGET(dst); \ 486 .set noat; \ 487 sll AT, rix, 2; \ 488 addu t8, rFP, AT; \ 489 sw rd, 0(t8); \ 490 addu t8, rREFS, AT; \ 491 .set at; \ 492 jalr zero, dst; \ 493 sw rd, 0(t8); \ 494 .set reorder 495#endif 496 497/* Combination of the SET_VREG64 and GOTO_OPCODE functions to save 1 instruction */ 498#ifdef MIPS32REVGE6 499#define SET_VREG64_GOTO(rlo, rhi, rix, dst) \ 500 .set noreorder; \ 501 GET_OPCODE_TARGET(dst); \ 502 lsa t8, rix, rFP, 2; \ 503 sw rlo, 0(t8); \ 504 sw rhi, 4(t8); \ 505 lsa t8, rix, rREFS, 2; \ 506 sw zero, 0(t8); \ 507 jalr zero, dst; \ 508 sw zero, 4(t8); \ 509 .set reorder 510#else 511#define SET_VREG64_GOTO(rlo, rhi, rix, dst) \ 512 .set noreorder; \ 513 GET_OPCODE_TARGET(dst); \ 514 .set noat; \ 515 sll AT, rix, 2; \ 516 addu t8, rFP, AT; \ 517 sw rlo, 0(t8); \ 518 sw rhi, 4(t8); \ 519 addu t8, rREFS, AT; \ 520 .set at; \ 521 sw zero, 0(t8); \ 522 jalr zero, dst; \ 523 sw zero, 4(t8); \ 524 .set reorder 525#endif 526 527/* Combination of the SET_VREG_F and GOTO_OPCODE functions to save 1 instruction */ 528#ifdef MIPS32REVGE6 529#define SET_VREG_F_GOTO(rd, rix, dst) \ 530 .set noreorder; \ 531 GET_OPCODE_TARGET(dst); \ 532 lsa t8, rix, rFP, 2; \ 533 s.s rd, 0(t8); \ 534 lsa t8, rix, rREFS, 2; \ 535 jalr zero, dst; \ 536 sw zero, 0(t8); \ 537 .set reorder 538#else 539#define SET_VREG_F_GOTO(rd, rix, dst) \ 540 .set noreorder; \ 541 GET_OPCODE_TARGET(dst); \ 542 .set noat; \ 543 sll AT, rix, 2; \ 544 addu t8, rFP, AT; \ 545 s.s rd, 0(t8); \ 546 addu t8, rREFS, AT; \ 547 .set at; \ 548 jalr zero, dst; \ 549 sw zero, 0(t8); \ 550 .set reorder 551#endif 552 553/* Combination of the SET_VREG64_F and GOTO_OPCODE functions to save 1 instruction */ 554#ifdef MIPS32REVGE6 555#define SET_VREG64_F_GOTO(rlo, rhi, rix, dst) \ 556 .set noreorder; \ 557 GET_OPCODE_TARGET(dst); \ 558 lsa t8, rix, rFP, 2; \ 559 .set noat; \ 560 mfhc1 AT, rlo; \ 561 s.s rlo, 0(t8); \ 562 sw AT, 4(t8); \ 563 .set at; \ 564 lsa t8, rix, rREFS, 2; \ 565 sw zero, 0(t8); \ 566 jalr zero, dst; \ 567 sw zero, 4(t8); \ 568 .set reorder 569#elif defined(FPU64) 570#define SET_VREG64_F_GOTO(rlo, rhi, rix, dst) \ 571 .set noreorder; \ 572 GET_OPCODE_TARGET(dst); \ 573 .set noat; \ 574 sll AT, rix, 2; \ 575 addu t8, rREFS, AT; \ 576 sw zero, 0(t8); \ 577 sw zero, 4(t8); \ 578 addu t8, rFP, AT; \ 579 mfhc1 AT, rlo; \ 580 sw AT, 4(t8); \ 581 .set at; \ 582 jalr zero, dst; \ 583 s.s rlo, 0(t8); \ 584 .set reorder 585#else 586#define SET_VREG64_F_GOTO(rlo, rhi, rix, dst) \ 587 .set noreorder; \ 588 GET_OPCODE_TARGET(dst); \ 589 .set noat; \ 590 sll AT, rix, 2; \ 591 addu t8, rFP, AT; \ 592 s.s rlo, 0(t8); \ 593 s.s rhi, 4(t8); \ 594 addu t8, rREFS, AT; \ 595 .set at; \ 596 sw zero, 0(t8); \ 597 jalr zero, dst; \ 598 sw zero, 4(t8); \ 599 .set reorder 600#endif 601 602#define GET_OPA(rd) srl rd, rINST, 8 603#ifdef MIPS32REVGE2 604#define GET_OPA4(rd) ext rd, rINST, 8, 4 605#else 606#define GET_OPA4(rd) GET_OPA(rd); and rd, 0xf 607#endif 608#define GET_OPB(rd) srl rd, rINST, 12 609 610/* 611 * Form an Effective Address rd = rbase + roff<<shift; 612 * Uses reg AT on pre-R6. 613 */ 614#define EASN(rd, rbase, roff, shift) LSA(rd, roff, rbase, shift) 615 616#define EAS1(rd, rbase, roff) EASN(rd, rbase, roff, 1) 617#define EAS2(rd, rbase, roff) EASN(rd, rbase, roff, 2) 618#define EAS3(rd, rbase, roff) EASN(rd, rbase, roff, 3) 619#define EAS4(rd, rbase, roff) EASN(rd, rbase, roff, 4) 620 621#define LOAD_eas2(rd, rbase, roff) \ 622 .set noat; \ 623 EAS2(AT, rbase, roff); \ 624 lw rd, 0(AT); \ 625 .set at 626 627#define STORE_eas2(rd, rbase, roff) \ 628 .set noat; \ 629 EAS2(AT, rbase, roff); \ 630 sw rd, 0(AT); \ 631 .set at 632 633#define LOAD_RB_OFF(rd, rbase, off) lw rd, off(rbase) 634#define STORE_RB_OFF(rd, rbase, off) sw rd, off(rbase) 635 636#define STORE64_off(rlo, rhi, rbase, off) \ 637 sw rlo, off(rbase); \ 638 sw rhi, (off+4)(rbase) 639#define LOAD64_off(rlo, rhi, rbase, off) \ 640 lw rlo, off(rbase); \ 641 lw rhi, (off+4)(rbase) 642 643#define STORE64(rlo, rhi, rbase) STORE64_off(rlo, rhi, rbase, 0) 644#define LOAD64(rlo, rhi, rbase) LOAD64_off(rlo, rhi, rbase, 0) 645 646#ifdef FPU64 647#define STORE64_off_F(rlo, rhi, rbase, off) \ 648 s.s rlo, off(rbase); \ 649 .set noat; \ 650 mfhc1 AT, rlo; \ 651 sw AT, (off+4)(rbase); \ 652 .set at 653#define LOAD64_off_F(rlo, rhi, rbase, off) \ 654 l.s rlo, off(rbase); \ 655 .set noat; \ 656 lw AT, (off+4)(rbase); \ 657 mthc1 AT, rlo; \ 658 .set at 659#else 660#define STORE64_off_F(rlo, rhi, rbase, off) \ 661 s.s rlo, off(rbase); \ 662 s.s rhi, (off+4)(rbase) 663#define LOAD64_off_F(rlo, rhi, rbase, off) \ 664 l.s rlo, off(rbase); \ 665 l.s rhi, (off+4)(rbase) 666#endif 667 668#define STORE64_F(rlo, rhi, rbase) STORE64_off_F(rlo, rhi, rbase, 0) 669#define LOAD64_F(rlo, rhi, rbase) LOAD64_off_F(rlo, rhi, rbase, 0) 670 671 672#define LOAD_base_offMirrorArray_length(rd, rbase) LOAD_RB_OFF(rd, rbase, MIRROR_ARRAY_LENGTH_OFFSET) 673 674#define STACK_STORE(rd, off) sw rd, off(sp) 675#define STACK_LOAD(rd, off) lw rd, off(sp) 676#define CREATE_STACK(n) subu sp, sp, n 677#define DELETE_STACK(n) addu sp, sp, n 678 679#define LOAD_ADDR(dest, addr) la dest, addr 680#define LOAD_IMM(dest, imm) li dest, imm 681#define MOVE_REG(dest, src) move dest, src 682#define STACK_SIZE 128 683 684#define STACK_OFFSET_ARG04 16 685#define STACK_OFFSET_ARG05 20 686#define STACK_OFFSET_ARG06 24 687#define STACK_OFFSET_ARG07 28 688#define STACK_OFFSET_GP 84 689 690#define JAL(n) jal n 691#define BAL(n) bal n 692 693/* 694 * FP register usage restrictions: 695 * 1) We don't use the callee save FP registers so we don't have to save them. 696 * 2) We don't use the odd FP registers so we can share code with mips32r6. 697 */ 698#define STACK_STORE_FULL() CREATE_STACK(STACK_SIZE); \ 699 STACK_STORE(ra, 124); \ 700 STACK_STORE(s8, 120); \ 701 STACK_STORE(s0, 116); \ 702 STACK_STORE(s1, 112); \ 703 STACK_STORE(s2, 108); \ 704 STACK_STORE(s3, 104); \ 705 STACK_STORE(s4, 100); \ 706 STACK_STORE(s5, 96); \ 707 STACK_STORE(s6, 92); \ 708 STACK_STORE(s7, 88); 709 710#define STACK_LOAD_FULL() STACK_LOAD(gp, STACK_OFFSET_GP); \ 711 STACK_LOAD(s7, 88); \ 712 STACK_LOAD(s6, 92); \ 713 STACK_LOAD(s5, 96); \ 714 STACK_LOAD(s4, 100); \ 715 STACK_LOAD(s3, 104); \ 716 STACK_LOAD(s2, 108); \ 717 STACK_LOAD(s1, 112); \ 718 STACK_LOAD(s0, 116); \ 719 STACK_LOAD(s8, 120); \ 720 STACK_LOAD(ra, 124); \ 721 DELETE_STACK(STACK_SIZE) 722 723#define REFRESH_IBASE() \ 724 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) 725 726/* Constants for float/double_to_int/long conversions */ 727#define INT_MIN 0x80000000 728#define INT_MIN_AS_FLOAT 0xCF000000 729#define INT_MIN_AS_DOUBLE_HIGH 0xC1E00000 730#define LONG_MIN_HIGH 0x80000000 731#define LONG_MIN_AS_FLOAT 0xDF000000 732#define LONG_MIN_AS_DOUBLE_HIGH 0xC3E00000 733 734/* File: mips/entry.S */ 735/* 736 * Copyright (C) 2016 The Android Open Source Project 737 * 738 * Licensed under the Apache License, Version 2.0 (the "License"); 739 * you may not use this file except in compliance with the License. 740 * You may obtain a copy of the License at 741 * 742 * http://www.apache.org/licenses/LICENSE-2.0 743 * 744 * Unless required by applicable law or agreed to in writing, software 745 * distributed under the License is distributed on an "AS IS" BASIS, 746 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 747 * See the License for the specific language governing permissions and 748 * limitations under the License. 749 */ 750/* 751 * Interpreter entry point. 752 */ 753 754 .text 755 .align 2 756 .global ExecuteMterpImpl 757 .ent ExecuteMterpImpl 758 .frame sp, STACK_SIZE, ra 759/* 760 * On entry: 761 * a0 Thread* self 762 * a1 code_item 763 * a2 ShadowFrame 764 * a3 JValue* result_register 765 * 766 */ 767 768ExecuteMterpImpl: 769 .set noreorder 770 .cpload t9 771 .set reorder 772/* Save to the stack. Frame size = STACK_SIZE */ 773 STACK_STORE_FULL() 774/* This directive will make sure all subsequent jal restore gp at a known offset */ 775 .cprestore STACK_OFFSET_GP 776 777 /* Remember the return register */ 778 sw a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) 779 780 /* Remember the code_item */ 781 sw a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2) 782 783 /* set up "named" registers */ 784 move rSELF, a0 785 lw a0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) 786 addu rFP, a2, SHADOWFRAME_VREGS_OFFSET # point to vregs. 787 EAS2(rREFS, rFP, a0) # point to reference array in shadow frame 788 lw a0, SHADOWFRAME_DEX_PC_OFFSET(a2) # Get starting dex_pc 789 addu rPC, a1, CODEITEM_INSNS_OFFSET # Point to base of insns[] 790 EAS1(rPC, rPC, a0) # Create direct pointer to 1st dex opcode 791 792 EXPORT_PC() 793 794 /* Starting ibase */ 795 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) 796 797 /* Set up for backwards branches & osr profiling */ 798 lw a0, OFF_FP_METHOD(rFP) 799 addu a1, rFP, OFF_FP_SHADOWFRAME 800 JAL(MterpSetUpHotnessCountdown) # (method, shadow_frame) 801 move rPROFILE, v0 # Starting hotness countdown to rPROFILE 802 803 /* start executing the instruction at rPC */ 804 FETCH_INST() # load rINST from rPC 805 GET_INST_OPCODE(t0) # extract opcode from rINST 806 GOTO_OPCODE(t0) # jump to next instruction 807 /* NOTE: no fallthrough */ 808 809 810 .global artMterpAsmInstructionStart 811 .type artMterpAsmInstructionStart, %function 812artMterpAsmInstructionStart = .L_op_nop 813 .text 814 815/* ------------------------------ */ 816 .balign 128 817.L_op_nop: /* 0x00 */ 818/* File: mips/op_nop.S */ 819 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 820 GET_INST_OPCODE(t0) # extract opcode from rINST 821 GOTO_OPCODE(t0) # jump to next instruction 822 823/* ------------------------------ */ 824 .balign 128 825.L_op_move: /* 0x01 */ 826/* File: mips/op_move.S */ 827 /* for move, move-object, long-to-int */ 828 /* op vA, vB */ 829 GET_OPB(a1) # a1 <- B from 15:12 830 GET_OPA4(a0) # a0 <- A from 11:8 831 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 832 GET_VREG(a2, a1) # a2 <- fp[B] 833 GET_INST_OPCODE(t0) # t0 <- opcode from rINST 834 .if 0 835 SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[A] <- a2 836 .else 837 SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 838 .endif 839 840/* ------------------------------ */ 841 .balign 128 842.L_op_move_from16: /* 0x02 */ 843/* File: mips/op_move_from16.S */ 844 /* for: move/from16, move-object/from16 */ 845 /* op vAA, vBBBB */ 846 FETCH(a1, 1) # a1 <- BBBB 847 GET_OPA(a0) # a0 <- AA 848 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 849 GET_VREG(a2, a1) # a2 <- fp[BBBB] 850 GET_INST_OPCODE(t0) # extract opcode from rINST 851 .if 0 852 SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AA] <- a2 853 .else 854 SET_VREG_GOTO(a2, a0, t0) # fp[AA] <- a2 855 .endif 856 857/* ------------------------------ */ 858 .balign 128 859.L_op_move_16: /* 0x03 */ 860/* File: mips/op_move_16.S */ 861 /* for: move/16, move-object/16 */ 862 /* op vAAAA, vBBBB */ 863 FETCH(a1, 2) # a1 <- BBBB 864 FETCH(a0, 1) # a0 <- AAAA 865 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 866 GET_VREG(a2, a1) # a2 <- fp[BBBB] 867 GET_INST_OPCODE(t0) # extract opcode from rINST 868 .if 0 869 SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AAAA] <- a2 870 .else 871 SET_VREG_GOTO(a2, a0, t0) # fp[AAAA] <- a2 872 .endif 873 874/* ------------------------------ */ 875 .balign 128 876.L_op_move_wide: /* 0x04 */ 877/* File: mips/op_move_wide.S */ 878 /* move-wide vA, vB */ 879 /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ 880 GET_OPA4(a2) # a2 <- A(+) 881 GET_OPB(a3) # a3 <- B 882 EAS2(a3, rFP, a3) # a3 <- &fp[B] 883 LOAD64(a0, a1, a3) # a0/a1 <- fp[B] 884 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 885 GET_INST_OPCODE(t0) # extract opcode from rINST 886 SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 887 888/* ------------------------------ */ 889 .balign 128 890.L_op_move_wide_from16: /* 0x05 */ 891/* File: mips/op_move_wide_from16.S */ 892 /* move-wide/from16 vAA, vBBBB */ 893 /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ 894 FETCH(a3, 1) # a3 <- BBBB 895 GET_OPA(a2) # a2 <- AA 896 EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] 897 LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] 898 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 899 GET_INST_OPCODE(t0) # extract opcode from rINST 900 SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AA] <- a0/a1 901 902/* ------------------------------ */ 903 .balign 128 904.L_op_move_wide_16: /* 0x06 */ 905/* File: mips/op_move_wide_16.S */ 906 /* move-wide/16 vAAAA, vBBBB */ 907 /* NOTE: regs can overlap, e.g. "move v6, v7" or "move v7, v6" */ 908 FETCH(a3, 2) # a3 <- BBBB 909 FETCH(a2, 1) # a2 <- AAAA 910 EAS2(a3, rFP, a3) # a3 <- &fp[BBBB] 911 LOAD64(a0, a1, a3) # a0/a1 <- fp[BBBB] 912 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 913 GET_INST_OPCODE(t0) # extract opcode from rINST 914 SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AAAA] <- a0/a1 915 916/* ------------------------------ */ 917 .balign 128 918.L_op_move_object: /* 0x07 */ 919/* File: mips/op_move_object.S */ 920/* File: mips/op_move.S */ 921 /* for move, move-object, long-to-int */ 922 /* op vA, vB */ 923 GET_OPB(a1) # a1 <- B from 15:12 924 GET_OPA4(a0) # a0 <- A from 11:8 925 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 926 GET_VREG(a2, a1) # a2 <- fp[B] 927 GET_INST_OPCODE(t0) # t0 <- opcode from rINST 928 .if 1 929 SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[A] <- a2 930 .else 931 SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 932 .endif 933 934 935/* ------------------------------ */ 936 .balign 128 937.L_op_move_object_from16: /* 0x08 */ 938/* File: mips/op_move_object_from16.S */ 939/* File: mips/op_move_from16.S */ 940 /* for: move/from16, move-object/from16 */ 941 /* op vAA, vBBBB */ 942 FETCH(a1, 1) # a1 <- BBBB 943 GET_OPA(a0) # a0 <- AA 944 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 945 GET_VREG(a2, a1) # a2 <- fp[BBBB] 946 GET_INST_OPCODE(t0) # extract opcode from rINST 947 .if 1 948 SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AA] <- a2 949 .else 950 SET_VREG_GOTO(a2, a0, t0) # fp[AA] <- a2 951 .endif 952 953 954/* ------------------------------ */ 955 .balign 128 956.L_op_move_object_16: /* 0x09 */ 957/* File: mips/op_move_object_16.S */ 958/* File: mips/op_move_16.S */ 959 /* for: move/16, move-object/16 */ 960 /* op vAAAA, vBBBB */ 961 FETCH(a1, 2) # a1 <- BBBB 962 FETCH(a0, 1) # a0 <- AAAA 963 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 964 GET_VREG(a2, a1) # a2 <- fp[BBBB] 965 GET_INST_OPCODE(t0) # extract opcode from rINST 966 .if 1 967 SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[AAAA] <- a2 968 .else 969 SET_VREG_GOTO(a2, a0, t0) # fp[AAAA] <- a2 970 .endif 971 972 973/* ------------------------------ */ 974 .balign 128 975.L_op_move_result: /* 0x0a */ 976/* File: mips/op_move_result.S */ 977 /* for: move-result, move-result-object */ 978 /* op vAA */ 979 GET_OPA(a2) # a2 <- AA 980 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 981 lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 982 lw a0, 0(a0) # a0 <- result.i 983 GET_INST_OPCODE(t0) # extract opcode from rINST 984 .if 0 985 SET_VREG_OBJECT_GOTO(a0, a2, t0) # fp[AA] <- a0 986 .else 987 SET_VREG_GOTO(a0, a2, t0) # fp[AA] <- a0 988 .endif 989 990/* ------------------------------ */ 991 .balign 128 992.L_op_move_result_wide: /* 0x0b */ 993/* File: mips/op_move_result_wide.S */ 994 /* move-result-wide vAA */ 995 GET_OPA(a2) # a2 <- AA 996 lw a3, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 997 LOAD64(a0, a1, a3) # a0/a1 <- retval.j 998 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 999 GET_INST_OPCODE(t0) # extract opcode from rINST 1000 SET_VREG64_GOTO(a0, a1, a2, t0) # fp[AA] <- a0/a1 1001 1002/* ------------------------------ */ 1003 .balign 128 1004.L_op_move_result_object: /* 0x0c */ 1005/* File: mips/op_move_result_object.S */ 1006/* File: mips/op_move_result.S */ 1007 /* for: move-result, move-result-object */ 1008 /* op vAA */ 1009 GET_OPA(a2) # a2 <- AA 1010 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1011 lw a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 1012 lw a0, 0(a0) # a0 <- result.i 1013 GET_INST_OPCODE(t0) # extract opcode from rINST 1014 .if 1 1015 SET_VREG_OBJECT_GOTO(a0, a2, t0) # fp[AA] <- a0 1016 .else 1017 SET_VREG_GOTO(a0, a2, t0) # fp[AA] <- a0 1018 .endif 1019 1020 1021/* ------------------------------ */ 1022 .balign 128 1023.L_op_move_exception: /* 0x0d */ 1024/* File: mips/op_move_exception.S */ 1025 /* move-exception vAA */ 1026 GET_OPA(a2) # a2 <- AA 1027 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) # get exception obj 1028 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1029 GET_INST_OPCODE(t0) # extract opcode from rINST 1030 GET_OPCODE_TARGET(t0) 1031 SET_VREG_OBJECT(a3, a2) # fp[AA] <- exception obj 1032 sw zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception 1033 JR(t0) # jump to next instruction 1034 1035/* ------------------------------ */ 1036 .balign 128 1037.L_op_return_void: /* 0x0e */ 1038/* File: mips/op_return_void.S */ 1039 .extern MterpThreadFenceForConstructor 1040 JAL(MterpThreadFenceForConstructor) 1041 lw ra, THREAD_FLAGS_OFFSET(rSELF) 1042 move a0, rSELF 1043 and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 1044 beqz ra, 1f 1045 JAL(MterpSuspendCheck) # (self) 10461: 1047 move v0, zero 1048 move v1, zero 1049 b MterpReturn 1050 1051/* ------------------------------ */ 1052 .balign 128 1053.L_op_return: /* 0x0f */ 1054/* File: mips/op_return.S */ 1055 /* 1056 * Return a 32-bit value. 1057 * 1058 * for: return, return-object 1059 */ 1060 /* op vAA */ 1061 .extern MterpThreadFenceForConstructor 1062 JAL(MterpThreadFenceForConstructor) 1063 lw ra, THREAD_FLAGS_OFFSET(rSELF) 1064 move a0, rSELF 1065 and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 1066 beqz ra, 1f 1067 JAL(MterpSuspendCheck) # (self) 10681: 1069 GET_OPA(a2) # a2 <- AA 1070 GET_VREG(v0, a2) # v0 <- vAA 1071 move v1, zero 1072 b MterpReturn 1073 1074/* ------------------------------ */ 1075 .balign 128 1076.L_op_return_wide: /* 0x10 */ 1077/* File: mips/op_return_wide.S */ 1078 /* 1079 * Return a 64-bit value. 1080 */ 1081 /* return-wide vAA */ 1082 .extern MterpThreadFenceForConstructor 1083 JAL(MterpThreadFenceForConstructor) 1084 lw ra, THREAD_FLAGS_OFFSET(rSELF) 1085 move a0, rSELF 1086 and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 1087 beqz ra, 1f 1088 JAL(MterpSuspendCheck) # (self) 10891: 1090 GET_OPA(a2) # a2 <- AA 1091 EAS2(a2, rFP, a2) # a2 <- &fp[AA] 1092 LOAD64(v0, v1, a2) # v0/v1 <- vAA/vAA+1 1093 b MterpReturn 1094 1095/* ------------------------------ */ 1096 .balign 128 1097.L_op_return_object: /* 0x11 */ 1098/* File: mips/op_return_object.S */ 1099/* File: mips/op_return.S */ 1100 /* 1101 * Return a 32-bit value. 1102 * 1103 * for: return, return-object 1104 */ 1105 /* op vAA */ 1106 .extern MterpThreadFenceForConstructor 1107 JAL(MterpThreadFenceForConstructor) 1108 lw ra, THREAD_FLAGS_OFFSET(rSELF) 1109 move a0, rSELF 1110 and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 1111 beqz ra, 1f 1112 JAL(MterpSuspendCheck) # (self) 11131: 1114 GET_OPA(a2) # a2 <- AA 1115 GET_VREG(v0, a2) # v0 <- vAA 1116 move v1, zero 1117 b MterpReturn 1118 1119 1120/* ------------------------------ */ 1121 .balign 128 1122.L_op_const_4: /* 0x12 */ 1123/* File: mips/op_const_4.S */ 1124 /* const/4 vA, +B */ 1125 sll a1, rINST, 16 # a1 <- Bxxx0000 1126 GET_OPA(a0) # a0 <- A+ 1127 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1128 sra a1, a1, 28 # a1 <- sssssssB (sign-extended) 1129 and a0, a0, 15 1130 GET_INST_OPCODE(t0) # extract opcode from rINST 1131 SET_VREG_GOTO(a1, a0, t0) # fp[A] <- a1 1132 1133/* ------------------------------ */ 1134 .balign 128 1135.L_op_const_16: /* 0x13 */ 1136/* File: mips/op_const_16.S */ 1137 /* const/16 vAA, +BBBB */ 1138 FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) 1139 GET_OPA(a3) # a3 <- AA 1140 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1141 GET_INST_OPCODE(t0) # extract opcode from rINST 1142 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 1143 1144/* ------------------------------ */ 1145 .balign 128 1146.L_op_const: /* 0x14 */ 1147/* File: mips/op_const.S */ 1148 /* const vAA, +BBBBbbbb */ 1149 GET_OPA(a3) # a3 <- AA 1150 FETCH(a0, 1) # a0 <- bbbb (low) 1151 FETCH(a1, 2) # a1 <- BBBB (high) 1152 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 1153 INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb 1154 GET_INST_OPCODE(t0) # extract opcode from rINST 1155 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 1156 1157/* ------------------------------ */ 1158 .balign 128 1159.L_op_const_high16: /* 0x15 */ 1160/* File: mips/op_const_high16.S */ 1161 /* const/high16 vAA, +BBBB0000 */ 1162 FETCH(a0, 1) # a0 <- 0000BBBB (zero-extended) 1163 GET_OPA(a3) # a3 <- AA 1164 sll a0, a0, 16 # a0 <- BBBB0000 1165 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1166 GET_INST_OPCODE(t0) # extract opcode from rINST 1167 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0 1168 1169/* ------------------------------ */ 1170 .balign 128 1171.L_op_const_wide_16: /* 0x16 */ 1172/* File: mips/op_const_wide_16.S */ 1173 /* const-wide/16 vAA, +BBBB */ 1174 FETCH_S(a0, 1) # a0 <- ssssBBBB (sign-extended) 1175 GET_OPA(a3) # a3 <- AA 1176 sra a1, a0, 31 # a1 <- ssssssss 1177 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1178 GET_INST_OPCODE(t0) # extract opcode from rINST 1179 SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 1180 1181/* ------------------------------ */ 1182 .balign 128 1183.L_op_const_wide_32: /* 0x17 */ 1184/* File: mips/op_const_wide_32.S */ 1185 /* const-wide/32 vAA, +BBBBbbbb */ 1186 FETCH(a0, 1) # a0 <- 0000bbbb (low) 1187 GET_OPA(a3) # a3 <- AA 1188 FETCH_S(a2, 2) # a2 <- ssssBBBB (high) 1189 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 1190 INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb 1191 sra a1, a0, 31 # a1 <- ssssssss 1192 GET_INST_OPCODE(t0) # extract opcode from rINST 1193 SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 1194 1195/* ------------------------------ */ 1196 .balign 128 1197.L_op_const_wide: /* 0x18 */ 1198/* File: mips/op_const_wide.S */ 1199 /* const-wide vAA, +HHHHhhhhBBBBbbbb */ 1200 FETCH(a0, 1) # a0 <- bbbb (low) 1201 FETCH(a1, 2) # a1 <- BBBB (low middle) 1202 FETCH(a2, 3) # a2 <- hhhh (high middle) 1203 INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb (low word) 1204 FETCH(a3, 4) # a3 <- HHHH (high) 1205 GET_OPA(t1) # t1 <- AA 1206 INSERT_HIGH_HALF(a2, a3) # a2 <- HHHHhhhh (high word) 1207 FETCH_ADVANCE_INST(5) # advance rPC, load rINST 1208 GET_INST_OPCODE(t0) # extract opcode from rINST 1209 SET_VREG64_GOTO(a0, a2, t1, t0) # vAA/vAA+1 <- a0/a2 1210 1211/* ------------------------------ */ 1212 .balign 128 1213.L_op_const_wide_high16: /* 0x19 */ 1214/* File: mips/op_const_wide_high16.S */ 1215 /* const-wide/high16 vAA, +BBBB000000000000 */ 1216 FETCH(a1, 1) # a1 <- 0000BBBB (zero-extended) 1217 GET_OPA(a3) # a3 <- AA 1218 li a0, 0 # a0 <- 00000000 1219 sll a1, 16 # a1 <- BBBB0000 1220 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1221 GET_INST_OPCODE(t0) # extract opcode from rINST 1222 SET_VREG64_GOTO(a0, a1, a3, t0) # vAA/vAA+1 <- a0/a1 1223 1224/* ------------------------------ */ 1225 .balign 128 1226.L_op_const_string: /* 0x1a */ 1227/* File: mips/op_const_string.S */ 1228 /* const/string vAA, string@BBBB */ 1229 EXPORT_PC() 1230 FETCH(a0, 1) # a0 <- BBBB 1231 GET_OPA(a1) # a1 <- AA 1232 addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame 1233 move a3, rSELF 1234 JAL(MterpConstString) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) 1235 PREFETCH_INST(2) # load rINST 1236 bnez v0, MterpPossibleException 1237 ADVANCE(2) # advance rPC 1238 GET_INST_OPCODE(t0) # extract opcode from rINST 1239 GOTO_OPCODE(t0) # jump to next instruction 1240 1241/* ------------------------------ */ 1242 .balign 128 1243.L_op_const_string_jumbo: /* 0x1b */ 1244/* File: mips/op_const_string_jumbo.S */ 1245 /* const/string vAA, string@BBBBBBBB */ 1246 EXPORT_PC() 1247 FETCH(a0, 1) # a0 <- bbbb (low) 1248 FETCH(a2, 2) # a2 <- BBBB (high) 1249 GET_OPA(a1) # a1 <- AA 1250 INSERT_HIGH_HALF(a0, a2) # a0 <- BBBBbbbb 1251 addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame 1252 move a3, rSELF 1253 JAL(MterpConstString) # v0 <- Mterp(index, tgt_reg, shadow_frame, self) 1254 PREFETCH_INST(3) # load rINST 1255 bnez v0, MterpPossibleException 1256 ADVANCE(3) # advance rPC 1257 GET_INST_OPCODE(t0) # extract opcode from rINST 1258 GOTO_OPCODE(t0) # jump to next instruction 1259 1260/* ------------------------------ */ 1261 .balign 128 1262.L_op_const_class: /* 0x1c */ 1263/* File: mips/op_const_class.S */ 1264 /* const/class vAA, class@BBBB */ 1265 EXPORT_PC() 1266 FETCH(a0, 1) # a0 <- BBBB 1267 GET_OPA(a1) # a1 <- AA 1268 addu a2, rFP, OFF_FP_SHADOWFRAME # a2 <- shadow frame 1269 move a3, rSELF 1270 JAL(MterpConstClass) 1271 PREFETCH_INST(2) # load rINST 1272 bnez v0, MterpPossibleException 1273 ADVANCE(2) # advance rPC 1274 GET_INST_OPCODE(t0) # extract opcode from rINST 1275 GOTO_OPCODE(t0) # jump to next instruction 1276 1277/* ------------------------------ */ 1278 .balign 128 1279.L_op_monitor_enter: /* 0x1d */ 1280/* File: mips/op_monitor_enter.S */ 1281 /* 1282 * Synchronize on an object. 1283 */ 1284 /* monitor-enter vAA */ 1285 EXPORT_PC() 1286 GET_OPA(a2) # a2 <- AA 1287 GET_VREG(a0, a2) # a0 <- vAA (object) 1288 move a1, rSELF # a1 <- self 1289 JAL(artLockObjectFromCode) # v0 <- artLockObject(obj, self) 1290 bnez v0, MterpException 1291 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1292 GET_INST_OPCODE(t0) # extract opcode from rINST 1293 GOTO_OPCODE(t0) # jump to next instruction 1294 1295/* ------------------------------ */ 1296 .balign 128 1297.L_op_monitor_exit: /* 0x1e */ 1298/* File: mips/op_monitor_exit.S */ 1299 /* 1300 * Unlock an object. 1301 * 1302 * Exceptions that occur when unlocking a monitor need to appear as 1303 * if they happened at the following instruction. See the Dalvik 1304 * instruction spec. 1305 */ 1306 /* monitor-exit vAA */ 1307 EXPORT_PC() 1308 GET_OPA(a2) # a2 <- AA 1309 GET_VREG(a0, a2) # a0 <- vAA (object) 1310 move a1, rSELF # a1 <- self 1311 JAL(artUnlockObjectFromCode) # v0 <- artUnlockObject(obj, self) 1312 bnez v0, MterpException 1313 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1314 GET_INST_OPCODE(t0) # extract opcode from rINST 1315 GOTO_OPCODE(t0) # jump to next instruction 1316 1317/* ------------------------------ */ 1318 .balign 128 1319.L_op_check_cast: /* 0x1f */ 1320/* File: mips/op_check_cast.S */ 1321 /* 1322 * Check to see if a cast from one class to another is allowed. 1323 */ 1324 /* check-cast vAA, class@BBBB */ 1325 EXPORT_PC() 1326 FETCH(a0, 1) # a0 <- BBBB 1327 GET_OPA(a1) # a1 <- AA 1328 EAS2(a1, rFP, a1) # a1 <- &object 1329 lw a2, OFF_FP_METHOD(rFP) # a2 <- method 1330 move a3, rSELF # a3 <- self 1331 JAL(MterpCheckCast) # v0 <- CheckCast(index, &obj, method, self) 1332 PREFETCH_INST(2) 1333 bnez v0, MterpPossibleException 1334 ADVANCE(2) 1335 GET_INST_OPCODE(t0) # extract opcode from rINST 1336 GOTO_OPCODE(t0) # jump to next instruction 1337 1338/* ------------------------------ */ 1339 .balign 128 1340.L_op_instance_of: /* 0x20 */ 1341/* File: mips/op_instance_of.S */ 1342 /* 1343 * Check to see if an object reference is an instance of a class. 1344 * 1345 * Most common situation is a non-null object, being compared against 1346 * an already-resolved class. 1347 */ 1348 /* instance-of vA, vB, class@CCCC */ 1349 EXPORT_PC() 1350 FETCH(a0, 1) # a0 <- CCCC 1351 GET_OPB(a1) # a1 <- B 1352 EAS2(a1, rFP, a1) # a1 <- &object 1353 lw a2, OFF_FP_METHOD(rFP) # a2 <- method 1354 move a3, rSELF # a3 <- self 1355 GET_OPA4(rOBJ) # rOBJ <- A+ 1356 JAL(MterpInstanceOf) # v0 <- Mterp(index, &obj, method, self) 1357 lw a1, THREAD_EXCEPTION_OFFSET(rSELF) 1358 PREFETCH_INST(2) # load rINST 1359 bnez a1, MterpException 1360 ADVANCE(2) # advance rPC 1361 GET_INST_OPCODE(t0) # extract opcode from rINST 1362 SET_VREG_GOTO(v0, rOBJ, t0) # vA <- v0 1363 1364/* ------------------------------ */ 1365 .balign 128 1366.L_op_array_length: /* 0x21 */ 1367/* File: mips/op_array_length.S */ 1368 /* 1369 * Return the length of an array. 1370 */ 1371 /* array-length vA, vB */ 1372 GET_OPB(a1) # a1 <- B 1373 GET_OPA4(a2) # a2 <- A+ 1374 GET_VREG(a0, a1) # a0 <- vB (object ref) 1375 # is object null? 1376 beqz a0, common_errNullObject # yup, fail 1377 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 1378 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- array length 1379 GET_INST_OPCODE(t0) # extract opcode from rINST 1380 SET_VREG_GOTO(a3, a2, t0) # vA <- length 1381 1382/* ------------------------------ */ 1383 .balign 128 1384.L_op_new_instance: /* 0x22 */ 1385/* File: mips/op_new_instance.S */ 1386 /* 1387 * Create a new instance of a class. 1388 */ 1389 /* new-instance vAA, class@BBBB */ 1390 EXPORT_PC() 1391 addu a0, rFP, OFF_FP_SHADOWFRAME 1392 move a1, rSELF 1393 move a2, rINST 1394 JAL(MterpNewInstance) 1395 beqz v0, MterpPossibleException 1396 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1397 GET_INST_OPCODE(t0) # extract opcode from rINST 1398 GOTO_OPCODE(t0) # jump to next instruction 1399 1400/* ------------------------------ */ 1401 .balign 128 1402.L_op_new_array: /* 0x23 */ 1403/* File: mips/op_new_array.S */ 1404 /* 1405 * Allocate an array of objects, specified with the array class 1406 * and a count. 1407 * 1408 * The verifier guarantees that this is an array class, so we don't 1409 * check for it here. 1410 */ 1411 /* new-array vA, vB, class@CCCC */ 1412 EXPORT_PC() 1413 addu a0, rFP, OFF_FP_SHADOWFRAME 1414 move a1, rPC 1415 move a2, rINST 1416 move a3, rSELF 1417 JAL(MterpNewArray) 1418 beqz v0, MterpPossibleException 1419 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1420 GET_INST_OPCODE(t0) # extract opcode from rINST 1421 GOTO_OPCODE(t0) # jump to next instruction 1422 1423/* ------------------------------ */ 1424 .balign 128 1425.L_op_filled_new_array: /* 0x24 */ 1426/* File: mips/op_filled_new_array.S */ 1427 /* 1428 * Create a new array with elements filled from registers. 1429 * 1430 * for: filled-new-array, filled-new-array/range 1431 */ 1432 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1433 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1434 .extern MterpFilledNewArray 1435 EXPORT_PC() 1436 addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame 1437 move a1, rPC 1438 move a2, rSELF 1439 JAL(MterpFilledNewArray) # v0 <- helper(shadow_frame, pc, self) 1440 beqz v0, MterpPossibleException # has exception 1441 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 1442 GET_INST_OPCODE(t0) # extract opcode from rINST 1443 GOTO_OPCODE(t0) # jump to next instruction 1444 1445/* ------------------------------ */ 1446 .balign 128 1447.L_op_filled_new_array_range: /* 0x25 */ 1448/* File: mips/op_filled_new_array_range.S */ 1449/* File: mips/op_filled_new_array.S */ 1450 /* 1451 * Create a new array with elements filled from registers. 1452 * 1453 * for: filled-new-array, filled-new-array/range 1454 */ 1455 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 1456 /* op {vCCCC..v(CCCC+AA-1)}, type@BBBB */ 1457 .extern MterpFilledNewArrayRange 1458 EXPORT_PC() 1459 addu a0, rFP, OFF_FP_SHADOWFRAME # a0 <- shadow frame 1460 move a1, rPC 1461 move a2, rSELF 1462 JAL(MterpFilledNewArrayRange) # v0 <- helper(shadow_frame, pc, self) 1463 beqz v0, MterpPossibleException # has exception 1464 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 1465 GET_INST_OPCODE(t0) # extract opcode from rINST 1466 GOTO_OPCODE(t0) # jump to next instruction 1467 1468 1469/* ------------------------------ */ 1470 .balign 128 1471.L_op_fill_array_data: /* 0x26 */ 1472/* File: mips/op_fill_array_data.S */ 1473 /* fill-array-data vAA, +BBBBBBBB */ 1474 EXPORT_PC() 1475 FETCH(a1, 1) # a1 <- bbbb (lo) 1476 FETCH(a0, 2) # a0 <- BBBB (hi) 1477 GET_OPA(a3) # a3 <- AA 1478 INSERT_HIGH_HALF(a1, a0) # a1 <- BBBBbbbb 1479 GET_VREG(a0, a3) # a0 <- vAA (array object) 1480 EAS1(a1, rPC, a1) # a1 <- PC + BBBBbbbb*2 (array data off.) 1481 JAL(MterpFillArrayData) # v0 <- Mterp(obj, payload) 1482 beqz v0, MterpPossibleException # has exception 1483 FETCH_ADVANCE_INST(3) # advance rPC, load rINST 1484 GET_INST_OPCODE(t0) # extract opcode from rINST 1485 GOTO_OPCODE(t0) # jump to next instruction 1486 1487/* ------------------------------ */ 1488 .balign 128 1489.L_op_throw: /* 0x27 */ 1490/* File: mips/op_throw.S */ 1491 /* 1492 * Throw an exception object in the current thread. 1493 */ 1494 /* throw vAA */ 1495 EXPORT_PC() # exception handler can throw 1496 GET_OPA(a2) # a2 <- AA 1497 GET_VREG(a1, a2) # a1 <- vAA (exception object) 1498 # null object? 1499 beqz a1, common_errNullObject # yes, throw an NPE instead 1500 sw a1, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj 1501 b MterpException 1502 1503/* ------------------------------ */ 1504 .balign 128 1505.L_op_goto: /* 0x28 */ 1506/* File: mips/op_goto.S */ 1507 /* 1508 * Unconditional branch, 8-bit offset. 1509 * 1510 * The branch distance is a signed code-unit offset, which we need to 1511 * double to get a byte offset. 1512 */ 1513 /* goto +AA */ 1514 sll a0, rINST, 16 # a0 <- AAxx0000 1515 sra rINST, a0, 24 # rINST <- ssssssAA (sign-extended) 1516 b MterpCommonTakenBranchNoFlags 1517 1518/* ------------------------------ */ 1519 .balign 128 1520.L_op_goto_16: /* 0x29 */ 1521/* File: mips/op_goto_16.S */ 1522 /* 1523 * Unconditional branch, 16-bit offset. 1524 * 1525 * The branch distance is a signed code-unit offset, which we need to 1526 * double to get a byte offset. 1527 */ 1528 /* goto/16 +AAAA */ 1529 FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended) 1530 b MterpCommonTakenBranchNoFlags 1531 1532/* ------------------------------ */ 1533 .balign 128 1534.L_op_goto_32: /* 0x2a */ 1535/* File: mips/op_goto_32.S */ 1536 /* 1537 * Unconditional branch, 32-bit offset. 1538 * 1539 * The branch distance is a signed code-unit offset, which we need to 1540 * double to get a byte offset. 1541 * 1542 * Unlike most opcodes, this one is allowed to branch to itself, so 1543 * our "backward branch" test must be "<=0" instead of "<0". 1544 */ 1545 /* goto/32 +AAAAAAAA */ 1546 FETCH(rINST, 1) # rINST <- aaaa (lo) 1547 FETCH(a1, 2) # a1 <- AAAA (hi) 1548 INSERT_HIGH_HALF(rINST, a1) # rINST <- AAAAaaaa 1549 b MterpCommonTakenBranchNoFlags 1550 1551/* ------------------------------ */ 1552 .balign 128 1553.L_op_packed_switch: /* 0x2b */ 1554/* File: mips/op_packed_switch.S */ 1555 /* 1556 * Handle a packed-switch or sparse-switch instruction. In both cases 1557 * we decode it and hand it off to a helper function. 1558 * 1559 * We don't really expect backward branches in a switch statement, but 1560 * they're perfectly legal, so we check for them here. 1561 * 1562 * for: packed-switch, sparse-switch 1563 */ 1564 /* op vAA, +BBBB */ 1565 FETCH(a0, 1) # a0 <- bbbb (lo) 1566 FETCH(a1, 2) # a1 <- BBBB (hi) 1567 GET_OPA(a3) # a3 <- AA 1568 INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb 1569 GET_VREG(a1, a3) # a1 <- vAA 1570 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 1571 JAL(MterpDoPackedSwitch) # a0 <- code-unit branch offset 1572 move rINST, v0 1573 b MterpCommonTakenBranchNoFlags 1574 1575/* ------------------------------ */ 1576 .balign 128 1577.L_op_sparse_switch: /* 0x2c */ 1578/* File: mips/op_sparse_switch.S */ 1579/* File: mips/op_packed_switch.S */ 1580 /* 1581 * Handle a packed-switch or sparse-switch instruction. In both cases 1582 * we decode it and hand it off to a helper function. 1583 * 1584 * We don't really expect backward branches in a switch statement, but 1585 * they're perfectly legal, so we check for them here. 1586 * 1587 * for: packed-switch, sparse-switch 1588 */ 1589 /* op vAA, +BBBB */ 1590 FETCH(a0, 1) # a0 <- bbbb (lo) 1591 FETCH(a1, 2) # a1 <- BBBB (hi) 1592 GET_OPA(a3) # a3 <- AA 1593 INSERT_HIGH_HALF(a0, a1) # a0 <- BBBBbbbb 1594 GET_VREG(a1, a3) # a1 <- vAA 1595 EAS1(a0, rPC, a0) # a0 <- PC + BBBBbbbb*2 1596 JAL(MterpDoSparseSwitch) # a0 <- code-unit branch offset 1597 move rINST, v0 1598 b MterpCommonTakenBranchNoFlags 1599 1600 1601/* ------------------------------ */ 1602 .balign 128 1603.L_op_cmpl_float: /* 0x2d */ 1604/* File: mips/op_cmpl_float.S */ 1605 /* 1606 * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) 1607 * into the destination register based on the comparison results. 1608 * 1609 * for: cmpl-float, cmpg-float 1610 */ 1611 /* op vAA, vBB, vCC */ 1612 1613 FETCH(a0, 1) # a0 <- CCBB 1614 and a2, a0, 255 # a2 <- BB 1615 srl a3, a0, 8 1616 GET_VREG_F(ft0, a2) 1617 GET_VREG_F(ft1, a3) 1618#ifdef MIPS32REVGE6 1619 cmp.eq.s ft2, ft0, ft1 1620 li rTEMP, 0 1621 bc1nez ft2, 1f # done if vBB == vCC (ordered) 1622 .if 0 1623 cmp.lt.s ft2, ft0, ft1 1624 li rTEMP, -1 1625 bc1nez ft2, 1f # done if vBB < vCC (ordered) 1626 li rTEMP, 1 # vBB > vCC or unordered 1627 .else 1628 cmp.lt.s ft2, ft1, ft0 1629 li rTEMP, 1 1630 bc1nez ft2, 1f # done if vBB > vCC (ordered) 1631 li rTEMP, -1 # vBB < vCC or unordered 1632 .endif 1633#else 1634 c.eq.s fcc0, ft0, ft1 1635 li rTEMP, 0 1636 bc1t fcc0, 1f # done if vBB == vCC (ordered) 1637 .if 0 1638 c.olt.s fcc0, ft0, ft1 1639 li rTEMP, -1 1640 bc1t fcc0, 1f # done if vBB < vCC (ordered) 1641 li rTEMP, 1 # vBB > vCC or unordered 1642 .else 1643 c.olt.s fcc0, ft1, ft0 1644 li rTEMP, 1 1645 bc1t fcc0, 1f # done if vBB > vCC (ordered) 1646 li rTEMP, -1 # vBB < vCC or unordered 1647 .endif 1648#endif 16491: 1650 GET_OPA(rOBJ) 1651 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1652 GET_INST_OPCODE(t0) # extract opcode from rINST 1653 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 1654 1655/* ------------------------------ */ 1656 .balign 128 1657.L_op_cmpg_float: /* 0x2e */ 1658/* File: mips/op_cmpg_float.S */ 1659/* File: mips/op_cmpl_float.S */ 1660 /* 1661 * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) 1662 * into the destination register based on the comparison results. 1663 * 1664 * for: cmpl-float, cmpg-float 1665 */ 1666 /* op vAA, vBB, vCC */ 1667 1668 FETCH(a0, 1) # a0 <- CCBB 1669 and a2, a0, 255 # a2 <- BB 1670 srl a3, a0, 8 1671 GET_VREG_F(ft0, a2) 1672 GET_VREG_F(ft1, a3) 1673#ifdef MIPS32REVGE6 1674 cmp.eq.s ft2, ft0, ft1 1675 li rTEMP, 0 1676 bc1nez ft2, 1f # done if vBB == vCC (ordered) 1677 .if 1 1678 cmp.lt.s ft2, ft0, ft1 1679 li rTEMP, -1 1680 bc1nez ft2, 1f # done if vBB < vCC (ordered) 1681 li rTEMP, 1 # vBB > vCC or unordered 1682 .else 1683 cmp.lt.s ft2, ft1, ft0 1684 li rTEMP, 1 1685 bc1nez ft2, 1f # done if vBB > vCC (ordered) 1686 li rTEMP, -1 # vBB < vCC or unordered 1687 .endif 1688#else 1689 c.eq.s fcc0, ft0, ft1 1690 li rTEMP, 0 1691 bc1t fcc0, 1f # done if vBB == vCC (ordered) 1692 .if 1 1693 c.olt.s fcc0, ft0, ft1 1694 li rTEMP, -1 1695 bc1t fcc0, 1f # done if vBB < vCC (ordered) 1696 li rTEMP, 1 # vBB > vCC or unordered 1697 .else 1698 c.olt.s fcc0, ft1, ft0 1699 li rTEMP, 1 1700 bc1t fcc0, 1f # done if vBB > vCC (ordered) 1701 li rTEMP, -1 # vBB < vCC or unordered 1702 .endif 1703#endif 17041: 1705 GET_OPA(rOBJ) 1706 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1707 GET_INST_OPCODE(t0) # extract opcode from rINST 1708 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 1709 1710 1711/* ------------------------------ */ 1712 .balign 128 1713.L_op_cmpl_double: /* 0x2f */ 1714/* File: mips/op_cmpl_double.S */ 1715 /* 1716 * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) 1717 * into the destination register based on the comparison results. 1718 * 1719 * For: cmpl-double, cmpg-double 1720 */ 1721 /* op vAA, vBB, vCC */ 1722 1723 FETCH(a0, 1) # a0 <- CCBB 1724 and rOBJ, a0, 255 # rOBJ <- BB 1725 srl t0, a0, 8 # t0 <- CC 1726 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] 1727 EAS2(t0, rFP, t0) # t0 <- &fp[CC] 1728 LOAD64_F(ft0, ft0f, rOBJ) 1729 LOAD64_F(ft1, ft1f, t0) 1730#ifdef MIPS32REVGE6 1731 cmp.eq.d ft2, ft0, ft1 1732 li rTEMP, 0 1733 bc1nez ft2, 1f # done if vBB == vCC (ordered) 1734 .if 0 1735 cmp.lt.d ft2, ft0, ft1 1736 li rTEMP, -1 1737 bc1nez ft2, 1f # done if vBB < vCC (ordered) 1738 li rTEMP, 1 # vBB > vCC or unordered 1739 .else 1740 cmp.lt.d ft2, ft1, ft0 1741 li rTEMP, 1 1742 bc1nez ft2, 1f # done if vBB > vCC (ordered) 1743 li rTEMP, -1 # vBB < vCC or unordered 1744 .endif 1745#else 1746 c.eq.d fcc0, ft0, ft1 1747 li rTEMP, 0 1748 bc1t fcc0, 1f # done if vBB == vCC (ordered) 1749 .if 0 1750 c.olt.d fcc0, ft0, ft1 1751 li rTEMP, -1 1752 bc1t fcc0, 1f # done if vBB < vCC (ordered) 1753 li rTEMP, 1 # vBB > vCC or unordered 1754 .else 1755 c.olt.d fcc0, ft1, ft0 1756 li rTEMP, 1 1757 bc1t fcc0, 1f # done if vBB > vCC (ordered) 1758 li rTEMP, -1 # vBB < vCC or unordered 1759 .endif 1760#endif 17611: 1762 GET_OPA(rOBJ) 1763 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1764 GET_INST_OPCODE(t0) # extract opcode from rINST 1765 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 1766 1767/* ------------------------------ */ 1768 .balign 128 1769.L_op_cmpg_double: /* 0x30 */ 1770/* File: mips/op_cmpg_double.S */ 1771/* File: mips/op_cmpl_double.S */ 1772 /* 1773 * Compare two floating-point values. Puts 0(==), 1(>), or -1(<) 1774 * into the destination register based on the comparison results. 1775 * 1776 * For: cmpl-double, cmpg-double 1777 */ 1778 /* op vAA, vBB, vCC */ 1779 1780 FETCH(a0, 1) # a0 <- CCBB 1781 and rOBJ, a0, 255 # rOBJ <- BB 1782 srl t0, a0, 8 # t0 <- CC 1783 EAS2(rOBJ, rFP, rOBJ) # rOBJ <- &fp[BB] 1784 EAS2(t0, rFP, t0) # t0 <- &fp[CC] 1785 LOAD64_F(ft0, ft0f, rOBJ) 1786 LOAD64_F(ft1, ft1f, t0) 1787#ifdef MIPS32REVGE6 1788 cmp.eq.d ft2, ft0, ft1 1789 li rTEMP, 0 1790 bc1nez ft2, 1f # done if vBB == vCC (ordered) 1791 .if 1 1792 cmp.lt.d ft2, ft0, ft1 1793 li rTEMP, -1 1794 bc1nez ft2, 1f # done if vBB < vCC (ordered) 1795 li rTEMP, 1 # vBB > vCC or unordered 1796 .else 1797 cmp.lt.d ft2, ft1, ft0 1798 li rTEMP, 1 1799 bc1nez ft2, 1f # done if vBB > vCC (ordered) 1800 li rTEMP, -1 # vBB < vCC or unordered 1801 .endif 1802#else 1803 c.eq.d fcc0, ft0, ft1 1804 li rTEMP, 0 1805 bc1t fcc0, 1f # done if vBB == vCC (ordered) 1806 .if 1 1807 c.olt.d fcc0, ft0, ft1 1808 li rTEMP, -1 1809 bc1t fcc0, 1f # done if vBB < vCC (ordered) 1810 li rTEMP, 1 # vBB > vCC or unordered 1811 .else 1812 c.olt.d fcc0, ft1, ft0 1813 li rTEMP, 1 1814 bc1t fcc0, 1f # done if vBB > vCC (ordered) 1815 li rTEMP, -1 # vBB < vCC or unordered 1816 .endif 1817#endif 18181: 1819 GET_OPA(rOBJ) 1820 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1821 GET_INST_OPCODE(t0) # extract opcode from rINST 1822 SET_VREG_GOTO(rTEMP, rOBJ, t0) # vAA <- rTEMP 1823 1824 1825/* ------------------------------ */ 1826 .balign 128 1827.L_op_cmp_long: /* 0x31 */ 1828/* File: mips/op_cmp_long.S */ 1829 /* 1830 * Compare two 64-bit values 1831 * x = y return 0 1832 * x < y return -1 1833 * x > y return 1 1834 * 1835 * I think I can improve on the ARM code by the following observation 1836 * slt t0, x.hi, y.hi; # (x.hi < y.hi) ? 1:0 1837 * sgt t1, x.hi, y.hi; # (y.hi > x.hi) ? 1:0 1838 * subu v0, t0, t1 # v0= -1:1:0 for [ < > = ] 1839 */ 1840 /* cmp-long vAA, vBB, vCC */ 1841 FETCH(a0, 1) # a0 <- CCBB 1842 GET_OPA(rOBJ) # rOBJ <- AA 1843 and a2, a0, 255 # a2 <- BB 1844 srl a3, a0, 8 # a3 <- CC 1845 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 1846 EAS2(a3, rFP, a3) # a3 <- &fp[CC] 1847 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 1848 LOAD64(a2, a3, a3) # a2/a3 <- vCC/vCC+1 1849 1850 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1851 slt t0, a1, a3 # compare hi 1852 sgt t1, a1, a3 1853 subu v0, t1, t0 # v0 <- (-1, 1, 0) 1854 bnez v0, .Lop_cmp_long_finish 1855 # at this point x.hi==y.hi 1856 sltu t0, a0, a2 # compare lo 1857 sgtu t1, a0, a2 1858 subu v0, t1, t0 # v0 <- (-1, 1, 0) for [< > =] 1859 1860.Lop_cmp_long_finish: 1861 GET_INST_OPCODE(t0) # extract opcode from rINST 1862 SET_VREG_GOTO(v0, rOBJ, t0) # vAA <- v0 1863 1864/* ------------------------------ */ 1865 .balign 128 1866.L_op_if_eq: /* 0x32 */ 1867/* File: mips/op_if_eq.S */ 1868/* File: mips/bincmp.S */ 1869 /* 1870 * Generic two-operand compare-and-branch operation. Provide a "condition" 1871 * fragment that specifies the comparison to perform. 1872 * 1873 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1874 */ 1875 /* if-cmp vA, vB, +CCCC */ 1876 GET_OPA4(a0) # a0 <- A+ 1877 GET_OPB(a1) # a1 <- B 1878 GET_VREG(a3, a1) # a3 <- vB 1879 GET_VREG(a0, a0) # a0 <- vA 1880 FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1881 beq a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) 1882 li t0, JIT_CHECK_OSR 1883 beq rPROFILE, t0, .L_check_not_taken_osr 1884 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1885 GET_INST_OPCODE(t0) # extract opcode from rINST 1886 GOTO_OPCODE(t0) # jump to next instruction 1887 1888 1889/* ------------------------------ */ 1890 .balign 128 1891.L_op_if_ne: /* 0x33 */ 1892/* File: mips/op_if_ne.S */ 1893/* File: mips/bincmp.S */ 1894 /* 1895 * Generic two-operand compare-and-branch operation. Provide a "condition" 1896 * fragment that specifies the comparison to perform. 1897 * 1898 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1899 */ 1900 /* if-cmp vA, vB, +CCCC */ 1901 GET_OPA4(a0) # a0 <- A+ 1902 GET_OPB(a1) # a1 <- B 1903 GET_VREG(a3, a1) # a3 <- vB 1904 GET_VREG(a0, a0) # a0 <- vA 1905 FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1906 bne a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) 1907 li t0, JIT_CHECK_OSR 1908 beq rPROFILE, t0, .L_check_not_taken_osr 1909 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1910 GET_INST_OPCODE(t0) # extract opcode from rINST 1911 GOTO_OPCODE(t0) # jump to next instruction 1912 1913 1914/* ------------------------------ */ 1915 .balign 128 1916.L_op_if_lt: /* 0x34 */ 1917/* File: mips/op_if_lt.S */ 1918/* File: mips/bincmp.S */ 1919 /* 1920 * Generic two-operand compare-and-branch operation. Provide a "condition" 1921 * fragment that specifies the comparison to perform. 1922 * 1923 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1924 */ 1925 /* if-cmp vA, vB, +CCCC */ 1926 GET_OPA4(a0) # a0 <- A+ 1927 GET_OPB(a1) # a1 <- B 1928 GET_VREG(a3, a1) # a3 <- vB 1929 GET_VREG(a0, a0) # a0 <- vA 1930 FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1931 blt a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) 1932 li t0, JIT_CHECK_OSR 1933 beq rPROFILE, t0, .L_check_not_taken_osr 1934 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1935 GET_INST_OPCODE(t0) # extract opcode from rINST 1936 GOTO_OPCODE(t0) # jump to next instruction 1937 1938 1939/* ------------------------------ */ 1940 .balign 128 1941.L_op_if_ge: /* 0x35 */ 1942/* File: mips/op_if_ge.S */ 1943/* File: mips/bincmp.S */ 1944 /* 1945 * Generic two-operand compare-and-branch operation. Provide a "condition" 1946 * fragment that specifies the comparison to perform. 1947 * 1948 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1949 */ 1950 /* if-cmp vA, vB, +CCCC */ 1951 GET_OPA4(a0) # a0 <- A+ 1952 GET_OPB(a1) # a1 <- B 1953 GET_VREG(a3, a1) # a3 <- vB 1954 GET_VREG(a0, a0) # a0 <- vA 1955 FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1956 bge a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) 1957 li t0, JIT_CHECK_OSR 1958 beq rPROFILE, t0, .L_check_not_taken_osr 1959 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1960 GET_INST_OPCODE(t0) # extract opcode from rINST 1961 GOTO_OPCODE(t0) # jump to next instruction 1962 1963 1964/* ------------------------------ */ 1965 .balign 128 1966.L_op_if_gt: /* 0x36 */ 1967/* File: mips/op_if_gt.S */ 1968/* File: mips/bincmp.S */ 1969 /* 1970 * Generic two-operand compare-and-branch operation. Provide a "condition" 1971 * fragment that specifies the comparison to perform. 1972 * 1973 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1974 */ 1975 /* if-cmp vA, vB, +CCCC */ 1976 GET_OPA4(a0) # a0 <- A+ 1977 GET_OPB(a1) # a1 <- B 1978 GET_VREG(a3, a1) # a3 <- vB 1979 GET_VREG(a0, a0) # a0 <- vA 1980 FETCH_S(rINST, 1) # rINST<- branch offset, in code units 1981 bgt a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) 1982 li t0, JIT_CHECK_OSR 1983 beq rPROFILE, t0, .L_check_not_taken_osr 1984 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 1985 GET_INST_OPCODE(t0) # extract opcode from rINST 1986 GOTO_OPCODE(t0) # jump to next instruction 1987 1988 1989/* ------------------------------ */ 1990 .balign 128 1991.L_op_if_le: /* 0x37 */ 1992/* File: mips/op_if_le.S */ 1993/* File: mips/bincmp.S */ 1994 /* 1995 * Generic two-operand compare-and-branch operation. Provide a "condition" 1996 * fragment that specifies the comparison to perform. 1997 * 1998 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1999 */ 2000 /* if-cmp vA, vB, +CCCC */ 2001 GET_OPA4(a0) # a0 <- A+ 2002 GET_OPB(a1) # a1 <- B 2003 GET_VREG(a3, a1) # a3 <- vB 2004 GET_VREG(a0, a0) # a0 <- vA 2005 FETCH_S(rINST, 1) # rINST<- branch offset, in code units 2006 ble a0, a3, MterpCommonTakenBranchNoFlags # compare (vA, vB) 2007 li t0, JIT_CHECK_OSR 2008 beq rPROFILE, t0, .L_check_not_taken_osr 2009 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2010 GET_INST_OPCODE(t0) # extract opcode from rINST 2011 GOTO_OPCODE(t0) # jump to next instruction 2012 2013 2014/* ------------------------------ */ 2015 .balign 128 2016.L_op_if_eqz: /* 0x38 */ 2017/* File: mips/op_if_eqz.S */ 2018/* File: mips/zcmp.S */ 2019 /* 2020 * Generic one-operand compare-and-branch operation. Provide a "condition" 2021 * fragment that specifies the comparison to perform. 2022 * 2023 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2024 */ 2025 /* if-cmp vAA, +BBBB */ 2026 GET_OPA(a0) # a0 <- AA 2027 GET_VREG(a0, a0) # a0 <- vAA 2028 FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2029 beq a0, zero, MterpCommonTakenBranchNoFlags 2030 li t0, JIT_CHECK_OSR # possible OSR re-entry? 2031 beq rPROFILE, t0, .L_check_not_taken_osr 2032 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2033 GET_INST_OPCODE(t0) # extract opcode from rINST 2034 GOTO_OPCODE(t0) # jump to next instruction 2035 2036 2037/* ------------------------------ */ 2038 .balign 128 2039.L_op_if_nez: /* 0x39 */ 2040/* File: mips/op_if_nez.S */ 2041/* File: mips/zcmp.S */ 2042 /* 2043 * Generic one-operand compare-and-branch operation. Provide a "condition" 2044 * fragment that specifies the comparison to perform. 2045 * 2046 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2047 */ 2048 /* if-cmp vAA, +BBBB */ 2049 GET_OPA(a0) # a0 <- AA 2050 GET_VREG(a0, a0) # a0 <- vAA 2051 FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2052 bne a0, zero, MterpCommonTakenBranchNoFlags 2053 li t0, JIT_CHECK_OSR # possible OSR re-entry? 2054 beq rPROFILE, t0, .L_check_not_taken_osr 2055 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2056 GET_INST_OPCODE(t0) # extract opcode from rINST 2057 GOTO_OPCODE(t0) # jump to next instruction 2058 2059 2060/* ------------------------------ */ 2061 .balign 128 2062.L_op_if_ltz: /* 0x3a */ 2063/* File: mips/op_if_ltz.S */ 2064/* File: mips/zcmp.S */ 2065 /* 2066 * Generic one-operand compare-and-branch operation. Provide a "condition" 2067 * fragment that specifies the comparison to perform. 2068 * 2069 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2070 */ 2071 /* if-cmp vAA, +BBBB */ 2072 GET_OPA(a0) # a0 <- AA 2073 GET_VREG(a0, a0) # a0 <- vAA 2074 FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2075 blt a0, zero, MterpCommonTakenBranchNoFlags 2076 li t0, JIT_CHECK_OSR # possible OSR re-entry? 2077 beq rPROFILE, t0, .L_check_not_taken_osr 2078 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2079 GET_INST_OPCODE(t0) # extract opcode from rINST 2080 GOTO_OPCODE(t0) # jump to next instruction 2081 2082 2083/* ------------------------------ */ 2084 .balign 128 2085.L_op_if_gez: /* 0x3b */ 2086/* File: mips/op_if_gez.S */ 2087/* File: mips/zcmp.S */ 2088 /* 2089 * Generic one-operand compare-and-branch operation. Provide a "condition" 2090 * fragment that specifies the comparison to perform. 2091 * 2092 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2093 */ 2094 /* if-cmp vAA, +BBBB */ 2095 GET_OPA(a0) # a0 <- AA 2096 GET_VREG(a0, a0) # a0 <- vAA 2097 FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2098 bge a0, zero, MterpCommonTakenBranchNoFlags 2099 li t0, JIT_CHECK_OSR # possible OSR re-entry? 2100 beq rPROFILE, t0, .L_check_not_taken_osr 2101 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2102 GET_INST_OPCODE(t0) # extract opcode from rINST 2103 GOTO_OPCODE(t0) # jump to next instruction 2104 2105 2106/* ------------------------------ */ 2107 .balign 128 2108.L_op_if_gtz: /* 0x3c */ 2109/* File: mips/op_if_gtz.S */ 2110/* File: mips/zcmp.S */ 2111 /* 2112 * Generic one-operand compare-and-branch operation. Provide a "condition" 2113 * fragment that specifies the comparison to perform. 2114 * 2115 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2116 */ 2117 /* if-cmp vAA, +BBBB */ 2118 GET_OPA(a0) # a0 <- AA 2119 GET_VREG(a0, a0) # a0 <- vAA 2120 FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2121 bgt a0, zero, MterpCommonTakenBranchNoFlags 2122 li t0, JIT_CHECK_OSR # possible OSR re-entry? 2123 beq rPROFILE, t0, .L_check_not_taken_osr 2124 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2125 GET_INST_OPCODE(t0) # extract opcode from rINST 2126 GOTO_OPCODE(t0) # jump to next instruction 2127 2128 2129/* ------------------------------ */ 2130 .balign 128 2131.L_op_if_lez: /* 0x3d */ 2132/* File: mips/op_if_lez.S */ 2133/* File: mips/zcmp.S */ 2134 /* 2135 * Generic one-operand compare-and-branch operation. Provide a "condition" 2136 * fragment that specifies the comparison to perform. 2137 * 2138 * for: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 2139 */ 2140 /* if-cmp vAA, +BBBB */ 2141 GET_OPA(a0) # a0 <- AA 2142 GET_VREG(a0, a0) # a0 <- vAA 2143 FETCH_S(rINST, 1) # rINST <- branch offset, in code units 2144 ble a0, zero, MterpCommonTakenBranchNoFlags 2145 li t0, JIT_CHECK_OSR # possible OSR re-entry? 2146 beq rPROFILE, t0, .L_check_not_taken_osr 2147 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2148 GET_INST_OPCODE(t0) # extract opcode from rINST 2149 GOTO_OPCODE(t0) # jump to next instruction 2150 2151 2152/* ------------------------------ */ 2153 .balign 128 2154.L_op_unused_3e: /* 0x3e */ 2155/* File: mips/op_unused_3e.S */ 2156/* File: mips/unused.S */ 2157/* 2158 * Bail to reference interpreter to throw. 2159 */ 2160 b MterpFallback 2161 2162 2163/* ------------------------------ */ 2164 .balign 128 2165.L_op_unused_3f: /* 0x3f */ 2166/* File: mips/op_unused_3f.S */ 2167/* File: mips/unused.S */ 2168/* 2169 * Bail to reference interpreter to throw. 2170 */ 2171 b MterpFallback 2172 2173 2174/* ------------------------------ */ 2175 .balign 128 2176.L_op_unused_40: /* 0x40 */ 2177/* File: mips/op_unused_40.S */ 2178/* File: mips/unused.S */ 2179/* 2180 * Bail to reference interpreter to throw. 2181 */ 2182 b MterpFallback 2183 2184 2185/* ------------------------------ */ 2186 .balign 128 2187.L_op_unused_41: /* 0x41 */ 2188/* File: mips/op_unused_41.S */ 2189/* File: mips/unused.S */ 2190/* 2191 * Bail to reference interpreter to throw. 2192 */ 2193 b MterpFallback 2194 2195 2196/* ------------------------------ */ 2197 .balign 128 2198.L_op_unused_42: /* 0x42 */ 2199/* File: mips/op_unused_42.S */ 2200/* File: mips/unused.S */ 2201/* 2202 * Bail to reference interpreter to throw. 2203 */ 2204 b MterpFallback 2205 2206 2207/* ------------------------------ */ 2208 .balign 128 2209.L_op_unused_43: /* 0x43 */ 2210/* File: mips/op_unused_43.S */ 2211/* File: mips/unused.S */ 2212/* 2213 * Bail to reference interpreter to throw. 2214 */ 2215 b MterpFallback 2216 2217 2218/* ------------------------------ */ 2219 .balign 128 2220.L_op_aget: /* 0x44 */ 2221/* File: mips/op_aget.S */ 2222 /* 2223 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2224 * 2225 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2226 * instructions. We use a pair of FETCH_Bs instead. 2227 * 2228 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2229 * 2230 * NOTE: assumes data offset for arrays is the same for all non-wide types. 2231 * If this changes, specialize. 2232 */ 2233 /* op vAA, vBB, vCC */ 2234 FETCH_B(a2, 1, 0) # a2 <- BB 2235 GET_OPA(rOBJ) # rOBJ <- AA 2236 FETCH_B(a3, 1, 1) # a3 <- CC 2237 GET_VREG(a0, a2) # a0 <- vBB (array object) 2238 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2239 # null array object? 2240 beqz a0, common_errNullObject # yes, bail 2241 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2242 EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width 2243 # a1 >= a3; compare unsigned index 2244 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2245 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2246 lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2247 GET_INST_OPCODE(t0) # extract opcode from rINST 2248 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2249 2250/* ------------------------------ */ 2251 .balign 128 2252.L_op_aget_wide: /* 0x45 */ 2253/* File: mips/op_aget_wide.S */ 2254 /* 2255 * Array get, 64 bits. vAA <- vBB[vCC]. 2256 * 2257 * Arrays of long/double are 64-bit aligned. 2258 */ 2259 /* aget-wide vAA, vBB, vCC */ 2260 FETCH(a0, 1) # a0 <- CCBB 2261 GET_OPA(rOBJ) # rOBJ <- AA 2262 and a2, a0, 255 # a2 <- BB 2263 srl a3, a0, 8 # a3 <- CC 2264 GET_VREG(a0, a2) # a0 <- vBB (array object) 2265 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2266 # null array object? 2267 beqz a0, common_errNullObject # yes, bail 2268 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2269 EAS3(a0, a0, a1) # a0 <- arrayObj + index*width 2270 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2271 2272 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2273 LOAD64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) 2274 GET_INST_OPCODE(t0) # extract opcode from rINST 2275 SET_VREG64_GOTO(a2, a3, rOBJ, t0) # vAA/vAA+1 <- a2/a3 2276 2277/* ------------------------------ */ 2278 .balign 128 2279.L_op_aget_object: /* 0x46 */ 2280/* File: mips/op_aget_object.S */ 2281 /* 2282 * Array object get. vAA <- vBB[vCC]. 2283 * 2284 * for: aget-object 2285 */ 2286 /* op vAA, vBB, vCC */ 2287 FETCH_B(a2, 1, 0) # a2 <- BB 2288 GET_OPA(rOBJ) # rOBJ <- AA 2289 FETCH_B(a3, 1, 1) # a3 <- CC 2290 EXPORT_PC() 2291 GET_VREG(a0, a2) # a0 <- vBB (array object) 2292 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2293 JAL(artAGetObjectFromMterp) # v0 <- GetObj(array, index) 2294 lw a1, THREAD_EXCEPTION_OFFSET(rSELF) 2295 PREFETCH_INST(2) # load rINST 2296 bnez a1, MterpException 2297 ADVANCE(2) # advance rPC 2298 GET_INST_OPCODE(t0) # extract opcode from rINST 2299 SET_VREG_OBJECT_GOTO(v0, rOBJ, t0) # vAA <- v0 2300 2301/* ------------------------------ */ 2302 .balign 128 2303.L_op_aget_boolean: /* 0x47 */ 2304/* File: mips/op_aget_boolean.S */ 2305/* File: mips/op_aget.S */ 2306 /* 2307 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2308 * 2309 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2310 * instructions. We use a pair of FETCH_Bs instead. 2311 * 2312 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2313 * 2314 * NOTE: assumes data offset for arrays is the same for all non-wide types. 2315 * If this changes, specialize. 2316 */ 2317 /* op vAA, vBB, vCC */ 2318 FETCH_B(a2, 1, 0) # a2 <- BB 2319 GET_OPA(rOBJ) # rOBJ <- AA 2320 FETCH_B(a3, 1, 1) # a3 <- CC 2321 GET_VREG(a0, a2) # a0 <- vBB (array object) 2322 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2323 # null array object? 2324 beqz a0, common_errNullObject # yes, bail 2325 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2326 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2327 # a1 >= a3; compare unsigned index 2328 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2329 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2330 lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2331 GET_INST_OPCODE(t0) # extract opcode from rINST 2332 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2333 2334 2335/* ------------------------------ */ 2336 .balign 128 2337.L_op_aget_byte: /* 0x48 */ 2338/* File: mips/op_aget_byte.S */ 2339/* File: mips/op_aget.S */ 2340 /* 2341 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2342 * 2343 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2344 * instructions. We use a pair of FETCH_Bs instead. 2345 * 2346 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2347 * 2348 * NOTE: assumes data offset for arrays is the same for all non-wide types. 2349 * If this changes, specialize. 2350 */ 2351 /* op vAA, vBB, vCC */ 2352 FETCH_B(a2, 1, 0) # a2 <- BB 2353 GET_OPA(rOBJ) # rOBJ <- AA 2354 FETCH_B(a3, 1, 1) # a3 <- CC 2355 GET_VREG(a0, a2) # a0 <- vBB (array object) 2356 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2357 # null array object? 2358 beqz a0, common_errNullObject # yes, bail 2359 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2360 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2361 # a1 >= a3; compare unsigned index 2362 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2363 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2364 lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2365 GET_INST_OPCODE(t0) # extract opcode from rINST 2366 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2367 2368 2369/* ------------------------------ */ 2370 .balign 128 2371.L_op_aget_char: /* 0x49 */ 2372/* File: mips/op_aget_char.S */ 2373/* File: mips/op_aget.S */ 2374 /* 2375 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2376 * 2377 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2378 * instructions. We use a pair of FETCH_Bs instead. 2379 * 2380 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2381 * 2382 * NOTE: assumes data offset for arrays is the same for all non-wide types. 2383 * If this changes, specialize. 2384 */ 2385 /* op vAA, vBB, vCC */ 2386 FETCH_B(a2, 1, 0) # a2 <- BB 2387 GET_OPA(rOBJ) # rOBJ <- AA 2388 FETCH_B(a3, 1, 1) # a3 <- CC 2389 GET_VREG(a0, a2) # a0 <- vBB (array object) 2390 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2391 # null array object? 2392 beqz a0, common_errNullObject # yes, bail 2393 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2394 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2395 # a1 >= a3; compare unsigned index 2396 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2397 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2398 lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2399 GET_INST_OPCODE(t0) # extract opcode from rINST 2400 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2401 2402 2403/* ------------------------------ */ 2404 .balign 128 2405.L_op_aget_short: /* 0x4a */ 2406/* File: mips/op_aget_short.S */ 2407/* File: mips/op_aget.S */ 2408 /* 2409 * Array get, 32 bits or less. vAA <- vBB[vCC]. 2410 * 2411 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 2412 * instructions. We use a pair of FETCH_Bs instead. 2413 * 2414 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 2415 * 2416 * NOTE: assumes data offset for arrays is the same for all non-wide types. 2417 * If this changes, specialize. 2418 */ 2419 /* op vAA, vBB, vCC */ 2420 FETCH_B(a2, 1, 0) # a2 <- BB 2421 GET_OPA(rOBJ) # rOBJ <- AA 2422 FETCH_B(a3, 1, 1) # a3 <- CC 2423 GET_VREG(a0, a2) # a0 <- vBB (array object) 2424 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2425 # null array object? 2426 beqz a0, common_errNullObject # yes, bail 2427 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2428 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2429 # a1 >= a3; compare unsigned index 2430 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2431 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2432 lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 2433 GET_INST_OPCODE(t0) # extract opcode from rINST 2434 SET_VREG_GOTO(a2, rOBJ, t0) # vAA <- a2 2435 2436 2437/* ------------------------------ */ 2438 .balign 128 2439.L_op_aput: /* 0x4b */ 2440/* File: mips/op_aput.S */ 2441 2442 /* 2443 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2444 * 2445 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2446 * 2447 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2448 * If this changes, specialize. 2449 */ 2450 /* op vAA, vBB, vCC */ 2451 FETCH_B(a2, 1, 0) # a2 <- BB 2452 GET_OPA(rOBJ) # rOBJ <- AA 2453 FETCH_B(a3, 1, 1) # a3 <- CC 2454 GET_VREG(a0, a2) # a0 <- vBB (array object) 2455 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2456 # null array object? 2457 beqz a0, common_errNullObject # yes, bail 2458 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2459 EASN(a0, a0, a1, 2) # a0 <- arrayObj + index*width 2460 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2461 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2462 GET_VREG(a2, rOBJ) # a2 <- vAA 2463 GET_INST_OPCODE(t0) # extract opcode from rINST 2464 GET_OPCODE_TARGET(t0) 2465 sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2466 JR(t0) # jump to next instruction 2467 2468/* ------------------------------ */ 2469 .balign 128 2470.L_op_aput_wide: /* 0x4c */ 2471/* File: mips/op_aput_wide.S */ 2472 /* 2473 * Array put, 64 bits. vBB[vCC] <- vAA. 2474 */ 2475 /* aput-wide vAA, vBB, vCC */ 2476 FETCH(a0, 1) # a0 <- CCBB 2477 GET_OPA(t0) # t0 <- AA 2478 and a2, a0, 255 # a2 <- BB 2479 srl a3, a0, 8 # a3 <- CC 2480 GET_VREG(a0, a2) # a0 <- vBB (array object) 2481 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2482 # null array object? 2483 beqz a0, common_errNullObject # yes, bail 2484 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2485 EAS3(a0, a0, a1) # a0 <- arrayObj + index*width 2486 EAS2(rOBJ, rFP, t0) # rOBJ <- &fp[AA] 2487 # compare unsigned index, length 2488 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2489 2490 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2491 LOAD64(a2, a3, rOBJ) # a2/a3 <- vAA/vAA+1 2492 GET_INST_OPCODE(t0) # extract opcode from rINST 2493 GET_OPCODE_TARGET(t0) 2494 STORE64_off(a2, a3, a0, MIRROR_WIDE_ARRAY_DATA_OFFSET) # a2/a3 <- vBB[vCC] 2495 JR(t0) # jump to next instruction 2496 2497/* ------------------------------ */ 2498 .balign 128 2499.L_op_aput_object: /* 0x4d */ 2500/* File: mips/op_aput_object.S */ 2501 /* 2502 * Store an object into an array. vBB[vCC] <- vAA. 2503 * 2504 */ 2505 /* op vAA, vBB, vCC */ 2506 EXPORT_PC() 2507 addu a0, rFP, OFF_FP_SHADOWFRAME 2508 move a1, rPC 2509 move a2, rINST 2510 JAL(MterpAputObject) 2511 beqz v0, MterpPossibleException 2512 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2513 GET_INST_OPCODE(t0) # extract opcode from rINST 2514 GOTO_OPCODE(t0) # jump to next instruction 2515 2516/* ------------------------------ */ 2517 .balign 128 2518.L_op_aput_boolean: /* 0x4e */ 2519/* File: mips/op_aput_boolean.S */ 2520/* File: mips/op_aput.S */ 2521 2522 /* 2523 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2524 * 2525 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2526 * 2527 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2528 * If this changes, specialize. 2529 */ 2530 /* op vAA, vBB, vCC */ 2531 FETCH_B(a2, 1, 0) # a2 <- BB 2532 GET_OPA(rOBJ) # rOBJ <- AA 2533 FETCH_B(a3, 1, 1) # a3 <- CC 2534 GET_VREG(a0, a2) # a0 <- vBB (array object) 2535 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2536 # null array object? 2537 beqz a0, common_errNullObject # yes, bail 2538 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2539 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2540 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2541 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2542 GET_VREG(a2, rOBJ) # a2 <- vAA 2543 GET_INST_OPCODE(t0) # extract opcode from rINST 2544 GET_OPCODE_TARGET(t0) 2545 sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2546 JR(t0) # jump to next instruction 2547 2548 2549/* ------------------------------ */ 2550 .balign 128 2551.L_op_aput_byte: /* 0x4f */ 2552/* File: mips/op_aput_byte.S */ 2553/* File: mips/op_aput.S */ 2554 2555 /* 2556 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2557 * 2558 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2559 * 2560 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2561 * If this changes, specialize. 2562 */ 2563 /* op vAA, vBB, vCC */ 2564 FETCH_B(a2, 1, 0) # a2 <- BB 2565 GET_OPA(rOBJ) # rOBJ <- AA 2566 FETCH_B(a3, 1, 1) # a3 <- CC 2567 GET_VREG(a0, a2) # a0 <- vBB (array object) 2568 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2569 # null array object? 2570 beqz a0, common_errNullObject # yes, bail 2571 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2572 EASN(a0, a0, a1, 0) # a0 <- arrayObj + index*width 2573 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2574 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2575 GET_VREG(a2, rOBJ) # a2 <- vAA 2576 GET_INST_OPCODE(t0) # extract opcode from rINST 2577 GET_OPCODE_TARGET(t0) 2578 sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2579 JR(t0) # jump to next instruction 2580 2581 2582/* ------------------------------ */ 2583 .balign 128 2584.L_op_aput_char: /* 0x50 */ 2585/* File: mips/op_aput_char.S */ 2586/* File: mips/op_aput.S */ 2587 2588 /* 2589 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2590 * 2591 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2592 * 2593 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2594 * If this changes, specialize. 2595 */ 2596 /* op vAA, vBB, vCC */ 2597 FETCH_B(a2, 1, 0) # a2 <- BB 2598 GET_OPA(rOBJ) # rOBJ <- AA 2599 FETCH_B(a3, 1, 1) # a3 <- CC 2600 GET_VREG(a0, a2) # a0 <- vBB (array object) 2601 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2602 # null array object? 2603 beqz a0, common_errNullObject # yes, bail 2604 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2605 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2606 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2607 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2608 GET_VREG(a2, rOBJ) # a2 <- vAA 2609 GET_INST_OPCODE(t0) # extract opcode from rINST 2610 GET_OPCODE_TARGET(t0) 2611 sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2612 JR(t0) # jump to next instruction 2613 2614 2615/* ------------------------------ */ 2616 .balign 128 2617.L_op_aput_short: /* 0x51 */ 2618/* File: mips/op_aput_short.S */ 2619/* File: mips/op_aput.S */ 2620 2621 /* 2622 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2623 * 2624 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2625 * 2626 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2627 * If this changes, specialize. 2628 */ 2629 /* op vAA, vBB, vCC */ 2630 FETCH_B(a2, 1, 0) # a2 <- BB 2631 GET_OPA(rOBJ) # rOBJ <- AA 2632 FETCH_B(a3, 1, 1) # a3 <- CC 2633 GET_VREG(a0, a2) # a0 <- vBB (array object) 2634 GET_VREG(a1, a3) # a1 <- vCC (requested index) 2635 # null array object? 2636 beqz a0, common_errNullObject # yes, bail 2637 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length 2638 EASN(a0, a0, a1, 1) # a0 <- arrayObj + index*width 2639 bgeu a1, a3, common_errArrayIndex # index >= length, bail 2640 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2641 GET_VREG(a2, rOBJ) # a2 <- vAA 2642 GET_INST_OPCODE(t0) # extract opcode from rINST 2643 GET_OPCODE_TARGET(t0) 2644 sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2645 JR(t0) # jump to next instruction 2646 2647 2648/* ------------------------------ */ 2649 .balign 128 2650.L_op_iget: /* 0x52 */ 2651/* File: mips/op_iget.S */ 2652 /* 2653 * General instance field get. 2654 * 2655 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2656 */ 2657 /* op vA, vB, field@CCCC */ 2658 EXPORT_PC() 2659 FETCH(a0, 1) # a0 <- field ref CCCC 2660 GET_OPB(a1) # a1 <- B 2661 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2662 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2663 move a3, rSELF # a3 <- self 2664 JAL(artGet32InstanceFromCode) 2665 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2666 GET_OPA4(a2) # a2<- A+ 2667 PREFETCH_INST(2) # load rINST 2668 bnez a3, MterpPossibleException # bail out 2669 ADVANCE(2) # advance rPC 2670 GET_INST_OPCODE(t0) # extract opcode from rINST 2671 .if 0 2672 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 2673 .else 2674 SET_VREG_GOTO(v0, a2, t0) # fp[A] <- v0 2675 .endif 2676 2677/* ------------------------------ */ 2678 .balign 128 2679.L_op_iget_wide: /* 0x53 */ 2680/* File: mips/op_iget_wide.S */ 2681 /* 2682 * 64-bit instance field get. 2683 * 2684 * for: iget-wide 2685 */ 2686 /* op vA, vB, field@CCCC */ 2687 EXPORT_PC() 2688 FETCH(a0, 1) # a0 <- field byte offset 2689 GET_OPB(a1) # a1 <- B 2690 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2691 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2692 move a3, rSELF # a3 <- self 2693 JAL(artGet64InstanceFromCode) 2694 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2695 GET_OPA4(a2) # a2<- A+ 2696 PREFETCH_INST(2) # load rINST 2697 bnez a3, MterpException # bail out 2698 ADVANCE(2) # advance rPC 2699 GET_INST_OPCODE(t0) # extract opcode from rINST 2700 SET_VREG64_GOTO(v0, v1, a2, t0) # fp[A] <- v0/v1 2701 2702/* ------------------------------ */ 2703 .balign 128 2704.L_op_iget_object: /* 0x54 */ 2705/* File: mips/op_iget_object.S */ 2706/* File: mips/op_iget.S */ 2707 /* 2708 * General instance field get. 2709 * 2710 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2711 */ 2712 /* op vA, vB, field@CCCC */ 2713 EXPORT_PC() 2714 FETCH(a0, 1) # a0 <- field ref CCCC 2715 GET_OPB(a1) # a1 <- B 2716 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2717 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2718 move a3, rSELF # a3 <- self 2719 JAL(artGetObjInstanceFromCode) 2720 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2721 GET_OPA4(a2) # a2<- A+ 2722 PREFETCH_INST(2) # load rINST 2723 bnez a3, MterpPossibleException # bail out 2724 ADVANCE(2) # advance rPC 2725 GET_INST_OPCODE(t0) # extract opcode from rINST 2726 .if 1 2727 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 2728 .else 2729 SET_VREG_GOTO(v0, a2, t0) # fp[A] <- v0 2730 .endif 2731 2732 2733/* ------------------------------ */ 2734 .balign 128 2735.L_op_iget_boolean: /* 0x55 */ 2736/* File: mips/op_iget_boolean.S */ 2737/* File: mips/op_iget.S */ 2738 /* 2739 * General instance field get. 2740 * 2741 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2742 */ 2743 /* op vA, vB, field@CCCC */ 2744 EXPORT_PC() 2745 FETCH(a0, 1) # a0 <- field ref CCCC 2746 GET_OPB(a1) # a1 <- B 2747 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2748 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2749 move a3, rSELF # a3 <- self 2750 JAL(artGetBooleanInstanceFromCode) 2751 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2752 GET_OPA4(a2) # a2<- A+ 2753 PREFETCH_INST(2) # load rINST 2754 bnez a3, MterpPossibleException # bail out 2755 ADVANCE(2) # advance rPC 2756 GET_INST_OPCODE(t0) # extract opcode from rINST 2757 .if 0 2758 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 2759 .else 2760 SET_VREG_GOTO(v0, a2, t0) # fp[A] <- v0 2761 .endif 2762 2763 2764/* ------------------------------ */ 2765 .balign 128 2766.L_op_iget_byte: /* 0x56 */ 2767/* File: mips/op_iget_byte.S */ 2768/* File: mips/op_iget.S */ 2769 /* 2770 * General instance field get. 2771 * 2772 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2773 */ 2774 /* op vA, vB, field@CCCC */ 2775 EXPORT_PC() 2776 FETCH(a0, 1) # a0 <- field ref CCCC 2777 GET_OPB(a1) # a1 <- B 2778 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2779 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2780 move a3, rSELF # a3 <- self 2781 JAL(artGetByteInstanceFromCode) 2782 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2783 GET_OPA4(a2) # a2<- A+ 2784 PREFETCH_INST(2) # load rINST 2785 bnez a3, MterpPossibleException # bail out 2786 ADVANCE(2) # advance rPC 2787 GET_INST_OPCODE(t0) # extract opcode from rINST 2788 .if 0 2789 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 2790 .else 2791 SET_VREG_GOTO(v0, a2, t0) # fp[A] <- v0 2792 .endif 2793 2794 2795/* ------------------------------ */ 2796 .balign 128 2797.L_op_iget_char: /* 0x57 */ 2798/* File: mips/op_iget_char.S */ 2799/* File: mips/op_iget.S */ 2800 /* 2801 * General instance field get. 2802 * 2803 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2804 */ 2805 /* op vA, vB, field@CCCC */ 2806 EXPORT_PC() 2807 FETCH(a0, 1) # a0 <- field ref CCCC 2808 GET_OPB(a1) # a1 <- B 2809 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2810 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2811 move a3, rSELF # a3 <- self 2812 JAL(artGetCharInstanceFromCode) 2813 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2814 GET_OPA4(a2) # a2<- A+ 2815 PREFETCH_INST(2) # load rINST 2816 bnez a3, MterpPossibleException # bail out 2817 ADVANCE(2) # advance rPC 2818 GET_INST_OPCODE(t0) # extract opcode from rINST 2819 .if 0 2820 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 2821 .else 2822 SET_VREG_GOTO(v0, a2, t0) # fp[A] <- v0 2823 .endif 2824 2825 2826/* ------------------------------ */ 2827 .balign 128 2828.L_op_iget_short: /* 0x58 */ 2829/* File: mips/op_iget_short.S */ 2830/* File: mips/op_iget.S */ 2831 /* 2832 * General instance field get. 2833 * 2834 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2835 */ 2836 /* op vA, vB, field@CCCC */ 2837 EXPORT_PC() 2838 FETCH(a0, 1) # a0 <- field ref CCCC 2839 GET_OPB(a1) # a1 <- B 2840 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2841 lw a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2842 move a3, rSELF # a3 <- self 2843 JAL(artGetShortInstanceFromCode) 2844 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 2845 GET_OPA4(a2) # a2<- A+ 2846 PREFETCH_INST(2) # load rINST 2847 bnez a3, MterpPossibleException # bail out 2848 ADVANCE(2) # advance rPC 2849 GET_INST_OPCODE(t0) # extract opcode from rINST 2850 .if 0 2851 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 2852 .else 2853 SET_VREG_GOTO(v0, a2, t0) # fp[A] <- v0 2854 .endif 2855 2856 2857/* ------------------------------ */ 2858 .balign 128 2859.L_op_iput: /* 0x59 */ 2860/* File: mips/op_iput.S */ 2861 /* 2862 * General 32-bit instance field put. 2863 * 2864 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2865 */ 2866 /* op vA, vB, field@CCCC */ 2867 .extern artSet32InstanceFromMterp 2868 EXPORT_PC() 2869 FETCH(a0, 1) # a0 <- field ref CCCC 2870 GET_OPB(a1) # a1 <- B 2871 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2872 GET_OPA4(a2) # a2 <- A+ 2873 GET_VREG(a2, a2) # a2 <- fp[A] 2874 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2875 PREFETCH_INST(2) # load rINST 2876 JAL(artSet32InstanceFromMterp) 2877 bnez v0, MterpPossibleException # bail out 2878 ADVANCE(2) # advance rPC 2879 GET_INST_OPCODE(t0) # extract opcode from rINST 2880 GOTO_OPCODE(t0) # jump to next instruction 2881 2882/* ------------------------------ */ 2883 .balign 128 2884.L_op_iput_wide: /* 0x5a */ 2885/* File: mips/op_iput_wide.S */ 2886 /* iput-wide vA, vB, field@CCCC */ 2887 .extern artSet64InstanceFromMterp 2888 EXPORT_PC() 2889 FETCH(a0, 1) # a0 <- field ref CCCC 2890 GET_OPB(a1) # a1 <- B 2891 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2892 GET_OPA4(a2) # a2 <- A+ 2893 EAS2(a2, rFP, a2) # a2 <- &fp[A] 2894 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2895 PREFETCH_INST(2) # load rINST 2896 JAL(artSet64InstanceFromMterp) 2897 bnez v0, MterpPossibleException # bail out 2898 ADVANCE(2) # advance rPC 2899 GET_INST_OPCODE(t0) # extract opcode from rINST 2900 GOTO_OPCODE(t0) # jump to next instruction 2901 2902/* ------------------------------ */ 2903 .balign 128 2904.L_op_iput_object: /* 0x5b */ 2905/* File: mips/op_iput_object.S */ 2906 /* 2907 * 32-bit instance field put. 2908 * 2909 * for: iput-object, iput-object-volatile 2910 */ 2911 /* op vA, vB, field@CCCC */ 2912 EXPORT_PC() 2913 addu a0, rFP, OFF_FP_SHADOWFRAME 2914 move a1, rPC 2915 move a2, rINST 2916 move a3, rSELF 2917 JAL(MterpIputObject) 2918 beqz v0, MterpException 2919 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 2920 GET_INST_OPCODE(t0) # extract opcode from rINST 2921 GOTO_OPCODE(t0) # jump to next instruction 2922 2923/* ------------------------------ */ 2924 .balign 128 2925.L_op_iput_boolean: /* 0x5c */ 2926/* File: mips/op_iput_boolean.S */ 2927/* File: mips/op_iput.S */ 2928 /* 2929 * General 32-bit instance field put. 2930 * 2931 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2932 */ 2933 /* op vA, vB, field@CCCC */ 2934 .extern artSet8InstanceFromMterp 2935 EXPORT_PC() 2936 FETCH(a0, 1) # a0 <- field ref CCCC 2937 GET_OPB(a1) # a1 <- B 2938 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2939 GET_OPA4(a2) # a2 <- A+ 2940 GET_VREG(a2, a2) # a2 <- fp[A] 2941 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2942 PREFETCH_INST(2) # load rINST 2943 JAL(artSet8InstanceFromMterp) 2944 bnez v0, MterpPossibleException # bail out 2945 ADVANCE(2) # advance rPC 2946 GET_INST_OPCODE(t0) # extract opcode from rINST 2947 GOTO_OPCODE(t0) # jump to next instruction 2948 2949 2950/* ------------------------------ */ 2951 .balign 128 2952.L_op_iput_byte: /* 0x5d */ 2953/* File: mips/op_iput_byte.S */ 2954/* File: mips/op_iput.S */ 2955 /* 2956 * General 32-bit instance field put. 2957 * 2958 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2959 */ 2960 /* op vA, vB, field@CCCC */ 2961 .extern artSet8InstanceFromMterp 2962 EXPORT_PC() 2963 FETCH(a0, 1) # a0 <- field ref CCCC 2964 GET_OPB(a1) # a1 <- B 2965 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2966 GET_OPA4(a2) # a2 <- A+ 2967 GET_VREG(a2, a2) # a2 <- fp[A] 2968 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2969 PREFETCH_INST(2) # load rINST 2970 JAL(artSet8InstanceFromMterp) 2971 bnez v0, MterpPossibleException # bail out 2972 ADVANCE(2) # advance rPC 2973 GET_INST_OPCODE(t0) # extract opcode from rINST 2974 GOTO_OPCODE(t0) # jump to next instruction 2975 2976 2977/* ------------------------------ */ 2978 .balign 128 2979.L_op_iput_char: /* 0x5e */ 2980/* File: mips/op_iput_char.S */ 2981/* File: mips/op_iput.S */ 2982 /* 2983 * General 32-bit instance field put. 2984 * 2985 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2986 */ 2987 /* op vA, vB, field@CCCC */ 2988 .extern artSet16InstanceFromMterp 2989 EXPORT_PC() 2990 FETCH(a0, 1) # a0 <- field ref CCCC 2991 GET_OPB(a1) # a1 <- B 2992 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 2993 GET_OPA4(a2) # a2 <- A+ 2994 GET_VREG(a2, a2) # a2 <- fp[A] 2995 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2996 PREFETCH_INST(2) # load rINST 2997 JAL(artSet16InstanceFromMterp) 2998 bnez v0, MterpPossibleException # bail out 2999 ADVANCE(2) # advance rPC 3000 GET_INST_OPCODE(t0) # extract opcode from rINST 3001 GOTO_OPCODE(t0) # jump to next instruction 3002 3003 3004/* ------------------------------ */ 3005 .balign 128 3006.L_op_iput_short: /* 0x5f */ 3007/* File: mips/op_iput_short.S */ 3008/* File: mips/op_iput.S */ 3009 /* 3010 * General 32-bit instance field put. 3011 * 3012 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 3013 */ 3014 /* op vA, vB, field@CCCC */ 3015 .extern artSet16InstanceFromMterp 3016 EXPORT_PC() 3017 FETCH(a0, 1) # a0 <- field ref CCCC 3018 GET_OPB(a1) # a1 <- B 3019 GET_VREG(a1, a1) # a1 <- fp[B], the object pointer 3020 GET_OPA4(a2) # a2 <- A+ 3021 GET_VREG(a2, a2) # a2 <- fp[A] 3022 lw a3, OFF_FP_METHOD(rFP) # a3 <- referrer 3023 PREFETCH_INST(2) # load rINST 3024 JAL(artSet16InstanceFromMterp) 3025 bnez v0, MterpPossibleException # bail out 3026 ADVANCE(2) # advance rPC 3027 GET_INST_OPCODE(t0) # extract opcode from rINST 3028 GOTO_OPCODE(t0) # jump to next instruction 3029 3030 3031/* ------------------------------ */ 3032 .balign 128 3033.L_op_sget: /* 0x60 */ 3034/* File: mips/op_sget.S */ 3035 /* 3036 * General SGET handler. 3037 * 3038 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3039 */ 3040 /* op vAA, field@BBBB */ 3041 .extern MterpGet32Static 3042 EXPORT_PC() 3043 FETCH(a0, 1) # a0 <- field ref BBBB 3044 lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3045 move a2, rSELF # a2 <- self 3046 JAL(MterpGet32Static) 3047 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3048 GET_OPA(a2) # a2 <- AA 3049 PREFETCH_INST(2) 3050 bnez a3, MterpException # bail out 3051 ADVANCE(2) 3052 GET_INST_OPCODE(t0) # extract opcode from rINST 3053.if 0 3054 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[AA] <- v0 3055.else 3056 SET_VREG_GOTO(v0, a2, t0) # fp[AA] <- v0 3057.endif 3058 3059/* ------------------------------ */ 3060 .balign 128 3061.L_op_sget_wide: /* 0x61 */ 3062/* File: mips/op_sget_wide.S */ 3063 /* 3064 * 64-bit SGET handler. 3065 */ 3066 /* sget-wide vAA, field@BBBB */ 3067 .extern MterpGet64Static 3068 EXPORT_PC() 3069 FETCH(a0, 1) # a0 <- field ref BBBB 3070 lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3071 move a2, rSELF # a2 <- self 3072 JAL(MterpGet64Static) 3073 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3074 bnez a3, MterpException 3075 GET_OPA(a1) # a1 <- AA 3076 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 3077 GET_INST_OPCODE(t0) # extract opcode from rINST 3078 SET_VREG64_GOTO(v0, v1, a1, t0) # vAA/vAA+1 <- v0/v1 3079 3080/* ------------------------------ */ 3081 .balign 128 3082.L_op_sget_object: /* 0x62 */ 3083/* File: mips/op_sget_object.S */ 3084/* File: mips/op_sget.S */ 3085 /* 3086 * General SGET handler. 3087 * 3088 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3089 */ 3090 /* op vAA, field@BBBB */ 3091 .extern MterpGetObjStatic 3092 EXPORT_PC() 3093 FETCH(a0, 1) # a0 <- field ref BBBB 3094 lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3095 move a2, rSELF # a2 <- self 3096 JAL(MterpGetObjStatic) 3097 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3098 GET_OPA(a2) # a2 <- AA 3099 PREFETCH_INST(2) 3100 bnez a3, MterpException # bail out 3101 ADVANCE(2) 3102 GET_INST_OPCODE(t0) # extract opcode from rINST 3103.if 1 3104 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[AA] <- v0 3105.else 3106 SET_VREG_GOTO(v0, a2, t0) # fp[AA] <- v0 3107.endif 3108 3109 3110/* ------------------------------ */ 3111 .balign 128 3112.L_op_sget_boolean: /* 0x63 */ 3113/* File: mips/op_sget_boolean.S */ 3114/* File: mips/op_sget.S */ 3115 /* 3116 * General SGET handler. 3117 * 3118 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3119 */ 3120 /* op vAA, field@BBBB */ 3121 .extern MterpGetBooleanStatic 3122 EXPORT_PC() 3123 FETCH(a0, 1) # a0 <- field ref BBBB 3124 lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3125 move a2, rSELF # a2 <- self 3126 JAL(MterpGetBooleanStatic) 3127 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3128 GET_OPA(a2) # a2 <- AA 3129 PREFETCH_INST(2) 3130 bnez a3, MterpException # bail out 3131 ADVANCE(2) 3132 GET_INST_OPCODE(t0) # extract opcode from rINST 3133.if 0 3134 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[AA] <- v0 3135.else 3136 SET_VREG_GOTO(v0, a2, t0) # fp[AA] <- v0 3137.endif 3138 3139 3140/* ------------------------------ */ 3141 .balign 128 3142.L_op_sget_byte: /* 0x64 */ 3143/* File: mips/op_sget_byte.S */ 3144/* File: mips/op_sget.S */ 3145 /* 3146 * General SGET handler. 3147 * 3148 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3149 */ 3150 /* op vAA, field@BBBB */ 3151 .extern MterpGetByteStatic 3152 EXPORT_PC() 3153 FETCH(a0, 1) # a0 <- field ref BBBB 3154 lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3155 move a2, rSELF # a2 <- self 3156 JAL(MterpGetByteStatic) 3157 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3158 GET_OPA(a2) # a2 <- AA 3159 PREFETCH_INST(2) 3160 bnez a3, MterpException # bail out 3161 ADVANCE(2) 3162 GET_INST_OPCODE(t0) # extract opcode from rINST 3163.if 0 3164 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[AA] <- v0 3165.else 3166 SET_VREG_GOTO(v0, a2, t0) # fp[AA] <- v0 3167.endif 3168 3169 3170/* ------------------------------ */ 3171 .balign 128 3172.L_op_sget_char: /* 0x65 */ 3173/* File: mips/op_sget_char.S */ 3174/* File: mips/op_sget.S */ 3175 /* 3176 * General SGET handler. 3177 * 3178 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3179 */ 3180 /* op vAA, field@BBBB */ 3181 .extern MterpGetCharStatic 3182 EXPORT_PC() 3183 FETCH(a0, 1) # a0 <- field ref BBBB 3184 lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3185 move a2, rSELF # a2 <- self 3186 JAL(MterpGetCharStatic) 3187 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3188 GET_OPA(a2) # a2 <- AA 3189 PREFETCH_INST(2) 3190 bnez a3, MterpException # bail out 3191 ADVANCE(2) 3192 GET_INST_OPCODE(t0) # extract opcode from rINST 3193.if 0 3194 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[AA] <- v0 3195.else 3196 SET_VREG_GOTO(v0, a2, t0) # fp[AA] <- v0 3197.endif 3198 3199 3200/* ------------------------------ */ 3201 .balign 128 3202.L_op_sget_short: /* 0x66 */ 3203/* File: mips/op_sget_short.S */ 3204/* File: mips/op_sget.S */ 3205 /* 3206 * General SGET handler. 3207 * 3208 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 3209 */ 3210 /* op vAA, field@BBBB */ 3211 .extern MterpGetShortStatic 3212 EXPORT_PC() 3213 FETCH(a0, 1) # a0 <- field ref BBBB 3214 lw a1, OFF_FP_METHOD(rFP) # a1 <- method 3215 move a2, rSELF # a2 <- self 3216 JAL(MterpGetShortStatic) 3217 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 3218 GET_OPA(a2) # a2 <- AA 3219 PREFETCH_INST(2) 3220 bnez a3, MterpException # bail out 3221 ADVANCE(2) 3222 GET_INST_OPCODE(t0) # extract opcode from rINST 3223.if 0 3224 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[AA] <- v0 3225.else 3226 SET_VREG_GOTO(v0, a2, t0) # fp[AA] <- v0 3227.endif 3228 3229 3230/* ------------------------------ */ 3231 .balign 128 3232.L_op_sput: /* 0x67 */ 3233/* File: mips/op_sput.S */ 3234 /* 3235 * General SPUT handler. 3236 * 3237 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3238 */ 3239 /* op vAA, field@BBBB */ 3240 EXPORT_PC() 3241 FETCH(a0, 1) # a0 <- field ref BBBB 3242 GET_OPA(a3) # a3 <- AA 3243 GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer 3244 lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3245 move a3, rSELF # a3 <- self 3246 PREFETCH_INST(2) # load rINST 3247 JAL(MterpSet32Static) 3248 bnez v0, MterpException # bail out 3249 ADVANCE(2) # advance rPC 3250 GET_INST_OPCODE(t0) # extract opcode from rINST 3251 GOTO_OPCODE(t0) # jump to next instruction 3252 3253/* ------------------------------ */ 3254 .balign 128 3255.L_op_sput_wide: /* 0x68 */ 3256/* File: mips/op_sput_wide.S */ 3257 /* 3258 * 64-bit SPUT handler. 3259 */ 3260 /* sput-wide vAA, field@BBBB */ 3261 .extern MterpSet64Static 3262 EXPORT_PC() 3263 FETCH(a0, 1) # a0 <- field ref CCCC 3264 GET_OPA(a1) # a1 <- AA 3265 EAS2(a1, rFP, a1) # a1 <- &fp[AA] 3266 lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3267 move a3, rSELF # a3 <- self 3268 PREFETCH_INST(2) # load rINST 3269 JAL(MterpSet64Static) 3270 bnez v0, MterpException # bail out 3271 ADVANCE(2) # advance rPC 3272 GET_INST_OPCODE(t0) # extract opcode from rINST 3273 GOTO_OPCODE(t0) # jump to next instruction 3274 3275/* ------------------------------ */ 3276 .balign 128 3277.L_op_sput_object: /* 0x69 */ 3278/* File: mips/op_sput_object.S */ 3279 /* 3280 * General 32-bit SPUT handler. 3281 * 3282 * for: sput-object, 3283 */ 3284 /* op vAA, field@BBBB */ 3285 EXPORT_PC() 3286 addu a0, rFP, OFF_FP_SHADOWFRAME 3287 move a1, rPC 3288 move a2, rINST 3289 move a3, rSELF 3290 JAL(MterpSputObject) 3291 beqz v0, MterpException 3292 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 3293 GET_INST_OPCODE(t0) # extract opcode from rINST 3294 GOTO_OPCODE(t0) # jump to next instruction 3295 3296/* ------------------------------ */ 3297 .balign 128 3298.L_op_sput_boolean: /* 0x6a */ 3299/* File: mips/op_sput_boolean.S */ 3300/* File: mips/op_sput.S */ 3301 /* 3302 * General SPUT handler. 3303 * 3304 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3305 */ 3306 /* op vAA, field@BBBB */ 3307 EXPORT_PC() 3308 FETCH(a0, 1) # a0 <- field ref BBBB 3309 GET_OPA(a3) # a3 <- AA 3310 GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer 3311 lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3312 move a3, rSELF # a3 <- self 3313 PREFETCH_INST(2) # load rINST 3314 JAL(MterpSetBooleanStatic) 3315 bnez v0, MterpException # bail out 3316 ADVANCE(2) # advance rPC 3317 GET_INST_OPCODE(t0) # extract opcode from rINST 3318 GOTO_OPCODE(t0) # jump to next instruction 3319 3320 3321/* ------------------------------ */ 3322 .balign 128 3323.L_op_sput_byte: /* 0x6b */ 3324/* File: mips/op_sput_byte.S */ 3325/* File: mips/op_sput.S */ 3326 /* 3327 * General SPUT handler. 3328 * 3329 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3330 */ 3331 /* op vAA, field@BBBB */ 3332 EXPORT_PC() 3333 FETCH(a0, 1) # a0 <- field ref BBBB 3334 GET_OPA(a3) # a3 <- AA 3335 GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer 3336 lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3337 move a3, rSELF # a3 <- self 3338 PREFETCH_INST(2) # load rINST 3339 JAL(MterpSetByteStatic) 3340 bnez v0, MterpException # bail out 3341 ADVANCE(2) # advance rPC 3342 GET_INST_OPCODE(t0) # extract opcode from rINST 3343 GOTO_OPCODE(t0) # jump to next instruction 3344 3345 3346/* ------------------------------ */ 3347 .balign 128 3348.L_op_sput_char: /* 0x6c */ 3349/* File: mips/op_sput_char.S */ 3350/* File: mips/op_sput.S */ 3351 /* 3352 * General SPUT handler. 3353 * 3354 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3355 */ 3356 /* op vAA, field@BBBB */ 3357 EXPORT_PC() 3358 FETCH(a0, 1) # a0 <- field ref BBBB 3359 GET_OPA(a3) # a3 <- AA 3360 GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer 3361 lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3362 move a3, rSELF # a3 <- self 3363 PREFETCH_INST(2) # load rINST 3364 JAL(MterpSetCharStatic) 3365 bnez v0, MterpException # bail out 3366 ADVANCE(2) # advance rPC 3367 GET_INST_OPCODE(t0) # extract opcode from rINST 3368 GOTO_OPCODE(t0) # jump to next instruction 3369 3370 3371/* ------------------------------ */ 3372 .balign 128 3373.L_op_sput_short: /* 0x6d */ 3374/* File: mips/op_sput_short.S */ 3375/* File: mips/op_sput.S */ 3376 /* 3377 * General SPUT handler. 3378 * 3379 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 3380 */ 3381 /* op vAA, field@BBBB */ 3382 EXPORT_PC() 3383 FETCH(a0, 1) # a0 <- field ref BBBB 3384 GET_OPA(a3) # a3 <- AA 3385 GET_VREG(a1, a3) # a1 <- fp[AA], the object pointer 3386 lw a2, OFF_FP_METHOD(rFP) # a2 <- method 3387 move a3, rSELF # a3 <- self 3388 PREFETCH_INST(2) # load rINST 3389 JAL(MterpSetShortStatic) 3390 bnez v0, MterpException # bail out 3391 ADVANCE(2) # advance rPC 3392 GET_INST_OPCODE(t0) # extract opcode from rINST 3393 GOTO_OPCODE(t0) # jump to next instruction 3394 3395 3396/* ------------------------------ */ 3397 .balign 128 3398.L_op_invoke_virtual: /* 0x6e */ 3399/* File: mips/op_invoke_virtual.S */ 3400/* File: mips/invoke.S */ 3401 /* 3402 * Generic invoke handler wrapper. 3403 */ 3404 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3405 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3406 .extern MterpInvokeVirtual 3407 EXPORT_PC() 3408 move a0, rSELF 3409 addu a1, rFP, OFF_FP_SHADOWFRAME 3410 move a2, rPC 3411 move a3, rINST 3412 JAL(MterpInvokeVirtual) 3413 beqz v0, MterpException 3414 FETCH_ADVANCE_INST(3) 3415 JAL(MterpShouldSwitchInterpreters) 3416 bnez v0, MterpFallback 3417 GET_INST_OPCODE(t0) 3418 GOTO_OPCODE(t0) 3419 3420 3421/* ------------------------------ */ 3422 .balign 128 3423.L_op_invoke_super: /* 0x6f */ 3424/* File: mips/op_invoke_super.S */ 3425/* File: mips/invoke.S */ 3426 /* 3427 * Generic invoke handler wrapper. 3428 */ 3429 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3430 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3431 .extern MterpInvokeSuper 3432 EXPORT_PC() 3433 move a0, rSELF 3434 addu a1, rFP, OFF_FP_SHADOWFRAME 3435 move a2, rPC 3436 move a3, rINST 3437 JAL(MterpInvokeSuper) 3438 beqz v0, MterpException 3439 FETCH_ADVANCE_INST(3) 3440 JAL(MterpShouldSwitchInterpreters) 3441 bnez v0, MterpFallback 3442 GET_INST_OPCODE(t0) 3443 GOTO_OPCODE(t0) 3444 3445 3446/* ------------------------------ */ 3447 .balign 128 3448.L_op_invoke_direct: /* 0x70 */ 3449/* File: mips/op_invoke_direct.S */ 3450/* File: mips/invoke.S */ 3451 /* 3452 * Generic invoke handler wrapper. 3453 */ 3454 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3455 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3456 .extern MterpInvokeDirect 3457 EXPORT_PC() 3458 move a0, rSELF 3459 addu a1, rFP, OFF_FP_SHADOWFRAME 3460 move a2, rPC 3461 move a3, rINST 3462 JAL(MterpInvokeDirect) 3463 beqz v0, MterpException 3464 FETCH_ADVANCE_INST(3) 3465 JAL(MterpShouldSwitchInterpreters) 3466 bnez v0, MterpFallback 3467 GET_INST_OPCODE(t0) 3468 GOTO_OPCODE(t0) 3469 3470 3471/* ------------------------------ */ 3472 .balign 128 3473.L_op_invoke_static: /* 0x71 */ 3474/* File: mips/op_invoke_static.S */ 3475/* File: mips/invoke.S */ 3476 /* 3477 * Generic invoke handler wrapper. 3478 */ 3479 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3480 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3481 .extern MterpInvokeStatic 3482 EXPORT_PC() 3483 move a0, rSELF 3484 addu a1, rFP, OFF_FP_SHADOWFRAME 3485 move a2, rPC 3486 move a3, rINST 3487 JAL(MterpInvokeStatic) 3488 beqz v0, MterpException 3489 FETCH_ADVANCE_INST(3) 3490 JAL(MterpShouldSwitchInterpreters) 3491 bnez v0, MterpFallback 3492 GET_INST_OPCODE(t0) 3493 GOTO_OPCODE(t0) 3494 3495 3496/* ------------------------------ */ 3497 .balign 128 3498.L_op_invoke_interface: /* 0x72 */ 3499/* File: mips/op_invoke_interface.S */ 3500/* File: mips/invoke.S */ 3501 /* 3502 * Generic invoke handler wrapper. 3503 */ 3504 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3505 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3506 .extern MterpInvokeInterface 3507 EXPORT_PC() 3508 move a0, rSELF 3509 addu a1, rFP, OFF_FP_SHADOWFRAME 3510 move a2, rPC 3511 move a3, rINST 3512 JAL(MterpInvokeInterface) 3513 beqz v0, MterpException 3514 FETCH_ADVANCE_INST(3) 3515 JAL(MterpShouldSwitchInterpreters) 3516 bnez v0, MterpFallback 3517 GET_INST_OPCODE(t0) 3518 GOTO_OPCODE(t0) 3519 3520 3521/* ------------------------------ */ 3522 .balign 128 3523.L_op_return_void_no_barrier: /* 0x73 */ 3524/* File: mips/op_return_void_no_barrier.S */ 3525 lw ra, THREAD_FLAGS_OFFSET(rSELF) 3526 move a0, rSELF 3527 and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 3528 beqz ra, 1f 3529 JAL(MterpSuspendCheck) # (self) 35301: 3531 move v0, zero 3532 move v1, zero 3533 b MterpReturn 3534 3535/* ------------------------------ */ 3536 .balign 128 3537.L_op_invoke_virtual_range: /* 0x74 */ 3538/* File: mips/op_invoke_virtual_range.S */ 3539/* File: mips/invoke.S */ 3540 /* 3541 * Generic invoke handler wrapper. 3542 */ 3543 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3544 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3545 .extern MterpInvokeVirtualRange 3546 EXPORT_PC() 3547 move a0, rSELF 3548 addu a1, rFP, OFF_FP_SHADOWFRAME 3549 move a2, rPC 3550 move a3, rINST 3551 JAL(MterpInvokeVirtualRange) 3552 beqz v0, MterpException 3553 FETCH_ADVANCE_INST(3) 3554 JAL(MterpShouldSwitchInterpreters) 3555 bnez v0, MterpFallback 3556 GET_INST_OPCODE(t0) 3557 GOTO_OPCODE(t0) 3558 3559 3560/* ------------------------------ */ 3561 .balign 128 3562.L_op_invoke_super_range: /* 0x75 */ 3563/* File: mips/op_invoke_super_range.S */ 3564/* File: mips/invoke.S */ 3565 /* 3566 * Generic invoke handler wrapper. 3567 */ 3568 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3569 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3570 .extern MterpInvokeSuperRange 3571 EXPORT_PC() 3572 move a0, rSELF 3573 addu a1, rFP, OFF_FP_SHADOWFRAME 3574 move a2, rPC 3575 move a3, rINST 3576 JAL(MterpInvokeSuperRange) 3577 beqz v0, MterpException 3578 FETCH_ADVANCE_INST(3) 3579 JAL(MterpShouldSwitchInterpreters) 3580 bnez v0, MterpFallback 3581 GET_INST_OPCODE(t0) 3582 GOTO_OPCODE(t0) 3583 3584 3585/* ------------------------------ */ 3586 .balign 128 3587.L_op_invoke_direct_range: /* 0x76 */ 3588/* File: mips/op_invoke_direct_range.S */ 3589/* File: mips/invoke.S */ 3590 /* 3591 * Generic invoke handler wrapper. 3592 */ 3593 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3594 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3595 .extern MterpInvokeDirectRange 3596 EXPORT_PC() 3597 move a0, rSELF 3598 addu a1, rFP, OFF_FP_SHADOWFRAME 3599 move a2, rPC 3600 move a3, rINST 3601 JAL(MterpInvokeDirectRange) 3602 beqz v0, MterpException 3603 FETCH_ADVANCE_INST(3) 3604 JAL(MterpShouldSwitchInterpreters) 3605 bnez v0, MterpFallback 3606 GET_INST_OPCODE(t0) 3607 GOTO_OPCODE(t0) 3608 3609 3610/* ------------------------------ */ 3611 .balign 128 3612.L_op_invoke_static_range: /* 0x77 */ 3613/* File: mips/op_invoke_static_range.S */ 3614/* File: mips/invoke.S */ 3615 /* 3616 * Generic invoke handler wrapper. 3617 */ 3618 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3619 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3620 .extern MterpInvokeStaticRange 3621 EXPORT_PC() 3622 move a0, rSELF 3623 addu a1, rFP, OFF_FP_SHADOWFRAME 3624 move a2, rPC 3625 move a3, rINST 3626 JAL(MterpInvokeStaticRange) 3627 beqz v0, MterpException 3628 FETCH_ADVANCE_INST(3) 3629 JAL(MterpShouldSwitchInterpreters) 3630 bnez v0, MterpFallback 3631 GET_INST_OPCODE(t0) 3632 GOTO_OPCODE(t0) 3633 3634 3635/* ------------------------------ */ 3636 .balign 128 3637.L_op_invoke_interface_range: /* 0x78 */ 3638/* File: mips/op_invoke_interface_range.S */ 3639/* File: mips/invoke.S */ 3640 /* 3641 * Generic invoke handler wrapper. 3642 */ 3643 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3644 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3645 .extern MterpInvokeInterfaceRange 3646 EXPORT_PC() 3647 move a0, rSELF 3648 addu a1, rFP, OFF_FP_SHADOWFRAME 3649 move a2, rPC 3650 move a3, rINST 3651 JAL(MterpInvokeInterfaceRange) 3652 beqz v0, MterpException 3653 FETCH_ADVANCE_INST(3) 3654 JAL(MterpShouldSwitchInterpreters) 3655 bnez v0, MterpFallback 3656 GET_INST_OPCODE(t0) 3657 GOTO_OPCODE(t0) 3658 3659 3660/* ------------------------------ */ 3661 .balign 128 3662.L_op_unused_79: /* 0x79 */ 3663/* File: mips/op_unused_79.S */ 3664/* File: mips/unused.S */ 3665/* 3666 * Bail to reference interpreter to throw. 3667 */ 3668 b MterpFallback 3669 3670 3671/* ------------------------------ */ 3672 .balign 128 3673.L_op_unused_7a: /* 0x7a */ 3674/* File: mips/op_unused_7a.S */ 3675/* File: mips/unused.S */ 3676/* 3677 * Bail to reference interpreter to throw. 3678 */ 3679 b MterpFallback 3680 3681 3682/* ------------------------------ */ 3683 .balign 128 3684.L_op_neg_int: /* 0x7b */ 3685/* File: mips/op_neg_int.S */ 3686/* File: mips/unop.S */ 3687 /* 3688 * Generic 32-bit unary operation. Provide an "instr" line that 3689 * specifies an instruction that performs "result0 = op a0". 3690 * This could be a MIPS instruction or a function call. 3691 * 3692 * for: int-to-byte, int-to-char, int-to-short, 3693 * neg-int, not-int, neg-float 3694 */ 3695 /* unop vA, vB */ 3696 GET_OPB(a3) # a3 <- B 3697 GET_OPA4(t0) # t0 <- A+ 3698 GET_VREG(a0, a3) # a0 <- vB 3699 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3700 # optional op 3701 negu a0, a0 # a0 <- op, a0-a3 changed 3702 GET_INST_OPCODE(t1) # extract opcode from rINST 3703 SET_VREG_GOTO(a0, t0, t1) # vA <- result0 3704 3705 3706/* ------------------------------ */ 3707 .balign 128 3708.L_op_not_int: /* 0x7c */ 3709/* File: mips/op_not_int.S */ 3710/* File: mips/unop.S */ 3711 /* 3712 * Generic 32-bit unary operation. Provide an "instr" line that 3713 * specifies an instruction that performs "result0 = op a0". 3714 * This could be a MIPS instruction or a function call. 3715 * 3716 * for: int-to-byte, int-to-char, int-to-short, 3717 * neg-int, not-int, neg-float 3718 */ 3719 /* unop vA, vB */ 3720 GET_OPB(a3) # a3 <- B 3721 GET_OPA4(t0) # t0 <- A+ 3722 GET_VREG(a0, a3) # a0 <- vB 3723 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3724 # optional op 3725 not a0, a0 # a0 <- op, a0-a3 changed 3726 GET_INST_OPCODE(t1) # extract opcode from rINST 3727 SET_VREG_GOTO(a0, t0, t1) # vA <- result0 3728 3729 3730/* ------------------------------ */ 3731 .balign 128 3732.L_op_neg_long: /* 0x7d */ 3733/* File: mips/op_neg_long.S */ 3734/* File: mips/unopWide.S */ 3735 /* 3736 * Generic 64-bit unary operation. Provide an "instr" line that 3737 * specifies an instruction that performs "result0/result1 = op a0/a1". 3738 * This could be MIPS instruction or a function call. 3739 * 3740 * For: neg-long, not-long, neg-double, 3741 */ 3742 /* unop vA, vB */ 3743 GET_OPA4(rOBJ) # rOBJ <- A+ 3744 GET_OPB(a3) # a3 <- B 3745 EAS2(a3, rFP, a3) # a3 <- &fp[B] 3746 LOAD64(a0, a1, a3) # a0/a1 <- vA 3747 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3748 negu v0, a0 # optional op 3749 negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0 # a0/a1 <- op, a2-a3 changed 3750 GET_INST_OPCODE(t0) # extract opcode from rINST 3751 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- a0/a1 3752 3753 3754/* ------------------------------ */ 3755 .balign 128 3756.L_op_not_long: /* 0x7e */ 3757/* File: mips/op_not_long.S */ 3758/* File: mips/unopWide.S */ 3759 /* 3760 * Generic 64-bit unary operation. Provide an "instr" line that 3761 * specifies an instruction that performs "result0/result1 = op a0/a1". 3762 * This could be MIPS instruction or a function call. 3763 * 3764 * For: neg-long, not-long, neg-double, 3765 */ 3766 /* unop vA, vB */ 3767 GET_OPA4(rOBJ) # rOBJ <- A+ 3768 GET_OPB(a3) # a3 <- B 3769 EAS2(a3, rFP, a3) # a3 <- &fp[B] 3770 LOAD64(a0, a1, a3) # a0/a1 <- vA 3771 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3772 not a0, a0 # optional op 3773 not a1, a1 # a0/a1 <- op, a2-a3 changed 3774 GET_INST_OPCODE(t0) # extract opcode from rINST 3775 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 3776 3777 3778/* ------------------------------ */ 3779 .balign 128 3780.L_op_neg_float: /* 0x7f */ 3781/* File: mips/op_neg_float.S */ 3782/* File: mips/unop.S */ 3783 /* 3784 * Generic 32-bit unary operation. Provide an "instr" line that 3785 * specifies an instruction that performs "result0 = op a0". 3786 * This could be a MIPS instruction or a function call. 3787 * 3788 * for: int-to-byte, int-to-char, int-to-short, 3789 * neg-int, not-int, neg-float 3790 */ 3791 /* unop vA, vB */ 3792 GET_OPB(a3) # a3 <- B 3793 GET_OPA4(t0) # t0 <- A+ 3794 GET_VREG(a0, a3) # a0 <- vB 3795 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3796 # optional op 3797 addu a0, a0, 0x80000000 # a0 <- op, a0-a3 changed 3798 GET_INST_OPCODE(t1) # extract opcode from rINST 3799 SET_VREG_GOTO(a0, t0, t1) # vA <- result0 3800 3801 3802/* ------------------------------ */ 3803 .balign 128 3804.L_op_neg_double: /* 0x80 */ 3805/* File: mips/op_neg_double.S */ 3806/* File: mips/unopWide.S */ 3807 /* 3808 * Generic 64-bit unary operation. Provide an "instr" line that 3809 * specifies an instruction that performs "result0/result1 = op a0/a1". 3810 * This could be MIPS instruction or a function call. 3811 * 3812 * For: neg-long, not-long, neg-double, 3813 */ 3814 /* unop vA, vB */ 3815 GET_OPA4(rOBJ) # rOBJ <- A+ 3816 GET_OPB(a3) # a3 <- B 3817 EAS2(a3, rFP, a3) # a3 <- &fp[B] 3818 LOAD64(a0, a1, a3) # a0/a1 <- vA 3819 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3820 # optional op 3821 addu a1, a1, 0x80000000 # a0/a1 <- op, a2-a3 changed 3822 GET_INST_OPCODE(t0) # extract opcode from rINST 3823 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 3824 3825 3826/* ------------------------------ */ 3827 .balign 128 3828.L_op_int_to_long: /* 0x81 */ 3829/* File: mips/op_int_to_long.S */ 3830/* File: mips/unopWider.S */ 3831 /* 3832 * Generic 32bit-to-64bit unary operation. Provide an "instr" line 3833 * that specifies an instruction that performs "result0/result1 = op a0". 3834 * 3835 * For: int-to-long 3836 */ 3837 /* unop vA, vB */ 3838 GET_OPA4(rOBJ) # rOBJ <- A+ 3839 GET_OPB(a3) # a3 <- B 3840 GET_VREG(a0, a3) # a0 <- vB 3841 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3842 # optional op 3843 sra a1, a0, 31 # result <- op, a0-a3 changed 3844 GET_INST_OPCODE(t0) # extract opcode from rINST 3845 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 3846 3847 3848/* ------------------------------ */ 3849 .balign 128 3850.L_op_int_to_float: /* 0x82 */ 3851/* File: mips/op_int_to_float.S */ 3852/* File: mips/funop.S */ 3853 /* 3854 * Generic 32-bit floating-point unary operation. Provide an "instr" 3855 * line that specifies an instruction that performs "fv0 = op fa0". 3856 * This could be a MIPS instruction or a function call. 3857 * 3858 * for: int-to-float 3859 */ 3860 /* unop vA, vB */ 3861 GET_OPB(a3) # a3 <- B 3862 GET_OPA4(rOBJ) # rOBJ <- A+ 3863 GET_VREG_F(fa0, a3) 3864 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3865 cvt.s.w fv0, fa0 3866 GET_INST_OPCODE(t1) # extract opcode from rINST 3867 SET_VREG_F_GOTO(fv0, rOBJ, t1) # vA <- fv0 3868 3869 3870/* ------------------------------ */ 3871 .balign 128 3872.L_op_int_to_double: /* 0x83 */ 3873/* File: mips/op_int_to_double.S */ 3874/* File: mips/funopWider.S */ 3875 /* 3876 * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" 3877 * line that specifies an instruction that performs "fv0 = op fa0". 3878 * 3879 * For: int-to-double, float-to-double 3880 */ 3881 /* unop vA, vB */ 3882 GET_OPA4(rOBJ) # rOBJ <- A+ 3883 GET_OPB(a3) # a3 <- B 3884 GET_VREG_F(fa0, a3) 3885 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3886 cvt.d.w fv0, fa0 3887 GET_INST_OPCODE(t0) # extract opcode from rINST 3888 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 3889 3890 3891/* ------------------------------ */ 3892 .balign 128 3893.L_op_long_to_int: /* 0x84 */ 3894/* File: mips/op_long_to_int.S */ 3895/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3896/* File: mips/op_move.S */ 3897 /* for move, move-object, long-to-int */ 3898 /* op vA, vB */ 3899 GET_OPB(a1) # a1 <- B from 15:12 3900 GET_OPA4(a0) # a0 <- A from 11:8 3901 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3902 GET_VREG(a2, a1) # a2 <- fp[B] 3903 GET_INST_OPCODE(t0) # t0 <- opcode from rINST 3904 .if 0 3905 SET_VREG_OBJECT_GOTO(a2, a0, t0) # fp[A] <- a2 3906 .else 3907 SET_VREG_GOTO(a2, a0, t0) # fp[A] <- a2 3908 .endif 3909 3910 3911/* ------------------------------ */ 3912 .balign 128 3913.L_op_long_to_float: /* 0x85 */ 3914/* File: mips/op_long_to_float.S */ 3915 /* 3916 * long-to-float 3917 */ 3918 /* unop vA, vB */ 3919 GET_OPB(a3) # a3 <- B 3920 GET_OPA4(rOBJ) # rOBJ <- A+ 3921 EAS2(a3, rFP, a3) # a3 <- &fp[B] 3922 3923#ifdef MIPS32REVGE6 3924 LOAD64_F(fv0, fv0f, a3) 3925 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3926 cvt.s.l fv0, fv0 3927#else 3928 LOAD64(rARG0, rARG1, a3) 3929 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3930 JAL(__floatdisf) 3931#endif 3932 3933 GET_INST_OPCODE(t0) # extract opcode from rINST 3934 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 3935 3936/* ------------------------------ */ 3937 .balign 128 3938.L_op_long_to_double: /* 0x86 */ 3939/* File: mips/op_long_to_double.S */ 3940 /* 3941 * long-to-double 3942 */ 3943 /* unop vA, vB */ 3944 GET_OPA4(rOBJ) # rOBJ <- A+ 3945 GET_OPB(a3) # a3 <- B 3946 EAS2(a3, rFP, a3) # a3 <- &fp[B] 3947 3948#ifdef MIPS32REVGE6 3949 LOAD64_F(fv0, fv0f, a3) 3950 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3951 cvt.d.l fv0, fv0 3952#else 3953 LOAD64(rARG0, rARG1, a3) 3954 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3955 JAL(__floatdidf) # a0/a1 <- op, a2-a3 changed 3956#endif 3957 3958 GET_INST_OPCODE(t0) # extract opcode from rINST 3959 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- result 3960 3961/* ------------------------------ */ 3962 .balign 128 3963.L_op_float_to_int: /* 0x87 */ 3964/* File: mips/op_float_to_int.S */ 3965 /* 3966 * float-to-int 3967 * 3968 * We have to clip values to int min/max per the specification. The 3969 * expected common case is a "reasonable" value that converts directly 3970 * to modest integer. The EABI convert function isn't doing this for us. 3971 */ 3972 /* unop vA, vB */ 3973 GET_OPB(a3) # a3 <- B 3974 GET_OPA4(rOBJ) # rOBJ <- A+ 3975 GET_VREG_F(fa0, a3) 3976 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 3977 3978 li t0, INT_MIN_AS_FLOAT 3979 mtc1 t0, fa1 3980#ifdef MIPS32REVGE6 3981 /* 3982 * TODO: simplify this when the MIPS64R6 emulator 3983 * supports NAN2008=1. 3984 */ 3985 cmp.le.s ft0, fa1, fa0 3986 GET_INST_OPCODE(t1) # extract opcode from rINST 3987 bc1nez ft0, 1f # if INT_MIN <= vB, proceed to truncation 3988 cmp.eq.s ft0, fa0, fa0 3989 selnez.s fa0, fa1, ft0 # fa0 = ordered(vB) ? INT_MIN_AS_FLOAT : 0 3990#else 3991 c.ole.s fcc0, fa1, fa0 3992 GET_INST_OPCODE(t1) # extract opcode from rINST 3993 bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation 3994 c.eq.s fcc0, fa0, fa0 3995 mtc1 zero, fa0 3996 movt.s fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_FLOAT : 0 3997#endif 39981: 3999 trunc.w.s fa0, fa0 4000 SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result 4001 4002/* ------------------------------ */ 4003 .balign 128 4004.L_op_float_to_long: /* 0x88 */ 4005/* File: mips/op_float_to_long.S */ 4006 /* 4007 * float-to-long 4008 * 4009 * We have to clip values to long min/max per the specification. The 4010 * expected common case is a "reasonable" value that converts directly 4011 * to modest integer. The EABI convert function isn't doing this for us. 4012 */ 4013 /* unop vA, vB */ 4014 GET_OPA4(rOBJ) # rOBJ <- A+ 4015 GET_OPB(a3) # a3 <- B 4016 GET_VREG_F(fa0, a3) 4017 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4018 4019#ifdef MIPS32REVGE6 4020 /* 4021 * TODO: simplify this when the MIPS64R6 emulator 4022 * supports NAN2008=1. 4023 */ 4024 li t0, LONG_MIN_AS_FLOAT 4025 mtc1 t0, fa1 4026 cmp.le.s ft0, fa1, fa0 4027 GET_INST_OPCODE(t1) # extract opcode from rINST 4028 bc1nez ft0, 1f # if LONG_MIN <= vB, proceed to truncation 4029 cmp.eq.s ft0, fa0, fa0 4030 selnez.s fa0, fa1, ft0 # fa0 = ordered(vB) ? LONG_MIN_AS_FLOAT : 0 40311: 4032 trunc.l.s fa0, fa0 4033 SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result 4034#else 4035 c.eq.s fcc0, fa0, fa0 4036 li rRESULT0, 0 4037 li rRESULT1, 0 4038 bc1f fcc0, .Lop_float_to_long_get_opcode 4039 4040 li t0, LONG_MIN_AS_FLOAT 4041 mtc1 t0, fa1 4042 c.ole.s fcc0, fa0, fa1 4043 li rRESULT1, LONG_MIN_HIGH 4044 bc1t fcc0, .Lop_float_to_long_get_opcode 4045 4046 neg.s fa1, fa1 4047 c.ole.s fcc0, fa1, fa0 4048 nor rRESULT0, rRESULT0, zero 4049 nor rRESULT1, rRESULT1, zero 4050 bc1t fcc0, .Lop_float_to_long_get_opcode 4051 4052 JAL(__fixsfdi) 4053 GET_INST_OPCODE(t1) # extract opcode from rINST 4054 b .Lop_float_to_long_set_vreg 4055#endif 4056 4057/* ------------------------------ */ 4058 .balign 128 4059.L_op_float_to_double: /* 0x89 */ 4060/* File: mips/op_float_to_double.S */ 4061/* File: mips/funopWider.S */ 4062 /* 4063 * Generic 32bit-to-64bit floating-point unary operation. Provide an "instr" 4064 * line that specifies an instruction that performs "fv0 = op fa0". 4065 * 4066 * For: int-to-double, float-to-double 4067 */ 4068 /* unop vA, vB */ 4069 GET_OPA4(rOBJ) # rOBJ <- A+ 4070 GET_OPB(a3) # a3 <- B 4071 GET_VREG_F(fa0, a3) 4072 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4073 cvt.d.s fv0, fa0 4074 GET_INST_OPCODE(t0) # extract opcode from rINST 4075 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 4076 4077 4078/* ------------------------------ */ 4079 .balign 128 4080.L_op_double_to_int: /* 0x8a */ 4081/* File: mips/op_double_to_int.S */ 4082 /* 4083 * double-to-int 4084 * 4085 * We have to clip values to int min/max per the specification. The 4086 * expected common case is a "reasonable" value that converts directly 4087 * to modest integer. The EABI convert function isn't doing this for us. 4088 */ 4089 /* unop vA, vB */ 4090 GET_OPB(a3) # a3 <- B 4091 GET_OPA4(rOBJ) # rOBJ <- A+ 4092 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4093 LOAD64_F(fa0, fa0f, a3) 4094 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4095 4096 li t0, INT_MIN_AS_DOUBLE_HIGH 4097 mtc1 zero, fa1 4098 MOVE_TO_FPU_HIGH(t0, fa1, fa1f) 4099#ifdef MIPS32REVGE6 4100 /* 4101 * TODO: simplify this when the MIPS64R6 emulator 4102 * supports NAN2008=1. 4103 */ 4104 cmp.le.d ft0, fa1, fa0 4105 GET_INST_OPCODE(t1) # extract opcode from rINST 4106 bc1nez ft0, 1f # if INT_MIN <= vB, proceed to truncation 4107 cmp.eq.d ft0, fa0, fa0 4108 selnez.d fa0, fa1, ft0 # fa0 = ordered(vB) ? INT_MIN_AS_DOUBLE : 0 4109#else 4110 c.ole.d fcc0, fa1, fa0 4111 GET_INST_OPCODE(t1) # extract opcode from rINST 4112 bc1t fcc0, 1f # if INT_MIN <= vB, proceed to truncation 4113 c.eq.d fcc0, fa0, fa0 4114 mtc1 zero, fa0 4115 MOVE_TO_FPU_HIGH(zero, fa0, fa0f) 4116 movt.d fa0, fa1, fcc0 # fa0 = ordered(vB) ? INT_MIN_AS_DOUBLE : 0 4117#endif 41181: 4119 trunc.w.d fa0, fa0 4120 SET_VREG_F_GOTO(fa0, rOBJ, t1) # vA <- result 4121 4122/* ------------------------------ */ 4123 .balign 128 4124.L_op_double_to_long: /* 0x8b */ 4125/* File: mips/op_double_to_long.S */ 4126 /* 4127 * double-to-long 4128 * 4129 * We have to clip values to long min/max per the specification. The 4130 * expected common case is a "reasonable" value that converts directly 4131 * to modest integer. The EABI convert function isn't doing this for us. 4132 */ 4133 /* unop vA, vB */ 4134 GET_OPA4(rOBJ) # rOBJ <- A+ 4135 GET_OPB(a3) # a3 <- B 4136 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4137 LOAD64_F(fa0, fa0f, a3) 4138 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4139 4140#ifdef MIPS32REVGE6 4141 /* 4142 * TODO: simplify this when the MIPS64R6 emulator 4143 * supports NAN2008=1. 4144 */ 4145 li t0, LONG_MIN_AS_DOUBLE_HIGH 4146 mtc1 zero, fa1 4147 mthc1 t0, fa1 4148 cmp.le.d ft0, fa1, fa0 4149 GET_INST_OPCODE(t1) # extract opcode from rINST 4150 bc1nez ft0, 1f # if LONG_MIN <= vB, proceed to truncation 4151 cmp.eq.d ft0, fa0, fa0 4152 selnez.d fa0, fa1, ft0 # fa0 = ordered(vB) ? LONG_MIN_AS_DOUBLE : 0 41531: 4154 trunc.l.d fa0, fa0 4155 SET_VREG64_F_GOTO(fa0, fa0f, rOBJ, t1) # vA <- result 4156#else 4157 c.eq.d fcc0, fa0, fa0 4158 li rRESULT0, 0 4159 li rRESULT1, 0 4160 bc1f fcc0, .Lop_double_to_long_get_opcode 4161 4162 li t0, LONG_MIN_AS_DOUBLE_HIGH 4163 mtc1 zero, fa1 4164 MOVE_TO_FPU_HIGH(t0, fa1, fa1f) 4165 c.ole.d fcc0, fa0, fa1 4166 li rRESULT1, LONG_MIN_HIGH 4167 bc1t fcc0, .Lop_double_to_long_get_opcode 4168 4169 neg.d fa1, fa1 4170 c.ole.d fcc0, fa1, fa0 4171 nor rRESULT0, rRESULT0, zero 4172 nor rRESULT1, rRESULT1, zero 4173 bc1t fcc0, .Lop_double_to_long_get_opcode 4174 4175 JAL(__fixdfdi) 4176 GET_INST_OPCODE(t1) # extract opcode from rINST 4177 b .Lop_double_to_long_set_vreg 4178#endif 4179 4180/* ------------------------------ */ 4181 .balign 128 4182.L_op_double_to_float: /* 0x8c */ 4183/* File: mips/op_double_to_float.S */ 4184/* File: mips/unopNarrower.S */ 4185 /* 4186 * Generic 64bit-to-32bit floating-point unary operation. Provide an "instr" 4187 * line that specifies an instruction that performs "fv0 = op fa0". 4188 * 4189 * For: double-to-float 4190 */ 4191 /* unop vA, vB */ 4192 GET_OPB(a3) # a3 <- B 4193 GET_OPA4(rOBJ) # rOBJ <- A+ 4194 EAS2(a3, rFP, a3) # a3 <- &fp[B] 4195 LOAD64_F(fa0, fa0f, a3) 4196 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4197 cvt.s.d fv0, fa0 4198 GET_INST_OPCODE(t0) # extract opcode from rINST 4199 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- fv0 4200 4201 4202/* ------------------------------ */ 4203 .balign 128 4204.L_op_int_to_byte: /* 0x8d */ 4205/* File: mips/op_int_to_byte.S */ 4206/* File: mips/unop.S */ 4207 /* 4208 * Generic 32-bit unary operation. Provide an "instr" line that 4209 * specifies an instruction that performs "result0 = op a0". 4210 * This could be a MIPS instruction or a function call. 4211 * 4212 * for: int-to-byte, int-to-char, int-to-short, 4213 * neg-int, not-int, neg-float 4214 */ 4215 /* unop vA, vB */ 4216 GET_OPB(a3) # a3 <- B 4217 GET_OPA4(t0) # t0 <- A+ 4218 GET_VREG(a0, a3) # a0 <- vB 4219 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4220 # optional op 4221 SEB(a0, a0) # a0 <- op, a0-a3 changed 4222 GET_INST_OPCODE(t1) # extract opcode from rINST 4223 SET_VREG_GOTO(a0, t0, t1) # vA <- result0 4224 4225 4226/* ------------------------------ */ 4227 .balign 128 4228.L_op_int_to_char: /* 0x8e */ 4229/* File: mips/op_int_to_char.S */ 4230/* File: mips/unop.S */ 4231 /* 4232 * Generic 32-bit unary operation. Provide an "instr" line that 4233 * specifies an instruction that performs "result0 = op a0". 4234 * This could be a MIPS instruction or a function call. 4235 * 4236 * for: int-to-byte, int-to-char, int-to-short, 4237 * neg-int, not-int, neg-float 4238 */ 4239 /* unop vA, vB */ 4240 GET_OPB(a3) # a3 <- B 4241 GET_OPA4(t0) # t0 <- A+ 4242 GET_VREG(a0, a3) # a0 <- vB 4243 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4244 # optional op 4245 and a0, 0xffff # a0 <- op, a0-a3 changed 4246 GET_INST_OPCODE(t1) # extract opcode from rINST 4247 SET_VREG_GOTO(a0, t0, t1) # vA <- result0 4248 4249 4250/* ------------------------------ */ 4251 .balign 128 4252.L_op_int_to_short: /* 0x8f */ 4253/* File: mips/op_int_to_short.S */ 4254/* File: mips/unop.S */ 4255 /* 4256 * Generic 32-bit unary operation. Provide an "instr" line that 4257 * specifies an instruction that performs "result0 = op a0". 4258 * This could be a MIPS instruction or a function call. 4259 * 4260 * for: int-to-byte, int-to-char, int-to-short, 4261 * neg-int, not-int, neg-float 4262 */ 4263 /* unop vA, vB */ 4264 GET_OPB(a3) # a3 <- B 4265 GET_OPA4(t0) # t0 <- A+ 4266 GET_VREG(a0, a3) # a0 <- vB 4267 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 4268 # optional op 4269 SEH(a0, a0) # a0 <- op, a0-a3 changed 4270 GET_INST_OPCODE(t1) # extract opcode from rINST 4271 SET_VREG_GOTO(a0, t0, t1) # vA <- result0 4272 4273 4274/* ------------------------------ */ 4275 .balign 128 4276.L_op_add_int: /* 0x90 */ 4277/* File: mips/op_add_int.S */ 4278/* File: mips/binop.S */ 4279 /* 4280 * Generic 32-bit binary operation. Provide an "instr" line that 4281 * specifies an instruction that performs "result = a0 op a1". 4282 * This could be a MIPS instruction or a function call. (If the result 4283 * comes back in a register other than a0, you can override "result".) 4284 * 4285 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4286 * vCC (a1). Useful for integer division and modulus. Note that we 4287 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4288 * correctly. 4289 * 4290 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4291 * xor-int, shl-int, shr-int, ushr-int 4292 */ 4293 /* binop vAA, vBB, vCC */ 4294 FETCH(a0, 1) # a0 <- CCBB 4295 GET_OPA(rOBJ) # rOBJ <- AA 4296 srl a3, a0, 8 # a3 <- CC 4297 and a2, a0, 255 # a2 <- BB 4298 GET_VREG(a1, a3) # a1 <- vCC 4299 GET_VREG(a0, a2) # a0 <- vBB 4300 .if 0 4301 # is second operand zero? 4302 beqz a1, common_errDivideByZero 4303 .endif 4304 4305 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4306 # optional op 4307 addu a0, a0, a1 # a0 <- op, a0-a3 changed 4308 GET_INST_OPCODE(t0) # extract opcode from rINST 4309 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4310 4311 4312/* ------------------------------ */ 4313 .balign 128 4314.L_op_sub_int: /* 0x91 */ 4315/* File: mips/op_sub_int.S */ 4316/* File: mips/binop.S */ 4317 /* 4318 * Generic 32-bit binary operation. Provide an "instr" line that 4319 * specifies an instruction that performs "result = a0 op a1". 4320 * This could be a MIPS instruction or a function call. (If the result 4321 * comes back in a register other than a0, you can override "result".) 4322 * 4323 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4324 * vCC (a1). Useful for integer division and modulus. Note that we 4325 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4326 * correctly. 4327 * 4328 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4329 * xor-int, shl-int, shr-int, ushr-int 4330 */ 4331 /* binop vAA, vBB, vCC */ 4332 FETCH(a0, 1) # a0 <- CCBB 4333 GET_OPA(rOBJ) # rOBJ <- AA 4334 srl a3, a0, 8 # a3 <- CC 4335 and a2, a0, 255 # a2 <- BB 4336 GET_VREG(a1, a3) # a1 <- vCC 4337 GET_VREG(a0, a2) # a0 <- vBB 4338 .if 0 4339 # is second operand zero? 4340 beqz a1, common_errDivideByZero 4341 .endif 4342 4343 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4344 # optional op 4345 subu a0, a0, a1 # a0 <- op, a0-a3 changed 4346 GET_INST_OPCODE(t0) # extract opcode from rINST 4347 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4348 4349 4350/* ------------------------------ */ 4351 .balign 128 4352.L_op_mul_int: /* 0x92 */ 4353/* File: mips/op_mul_int.S */ 4354/* File: mips/binop.S */ 4355 /* 4356 * Generic 32-bit binary operation. Provide an "instr" line that 4357 * specifies an instruction that performs "result = a0 op a1". 4358 * This could be a MIPS instruction or a function call. (If the result 4359 * comes back in a register other than a0, you can override "result".) 4360 * 4361 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4362 * vCC (a1). Useful for integer division and modulus. Note that we 4363 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4364 * correctly. 4365 * 4366 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4367 * xor-int, shl-int, shr-int, ushr-int 4368 */ 4369 /* binop vAA, vBB, vCC */ 4370 FETCH(a0, 1) # a0 <- CCBB 4371 GET_OPA(rOBJ) # rOBJ <- AA 4372 srl a3, a0, 8 # a3 <- CC 4373 and a2, a0, 255 # a2 <- BB 4374 GET_VREG(a1, a3) # a1 <- vCC 4375 GET_VREG(a0, a2) # a0 <- vBB 4376 .if 0 4377 # is second operand zero? 4378 beqz a1, common_errDivideByZero 4379 .endif 4380 4381 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4382 # optional op 4383 mul a0, a0, a1 # a0 <- op, a0-a3 changed 4384 GET_INST_OPCODE(t0) # extract opcode from rINST 4385 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4386 4387 4388/* ------------------------------ */ 4389 .balign 128 4390.L_op_div_int: /* 0x93 */ 4391/* File: mips/op_div_int.S */ 4392#ifdef MIPS32REVGE6 4393/* File: mips/binop.S */ 4394 /* 4395 * Generic 32-bit binary operation. Provide an "instr" line that 4396 * specifies an instruction that performs "result = a0 op a1". 4397 * This could be a MIPS instruction or a function call. (If the result 4398 * comes back in a register other than a0, you can override "result".) 4399 * 4400 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4401 * vCC (a1). Useful for integer division and modulus. Note that we 4402 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4403 * correctly. 4404 * 4405 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4406 * xor-int, shl-int, shr-int, ushr-int 4407 */ 4408 /* binop vAA, vBB, vCC */ 4409 FETCH(a0, 1) # a0 <- CCBB 4410 GET_OPA(rOBJ) # rOBJ <- AA 4411 srl a3, a0, 8 # a3 <- CC 4412 and a2, a0, 255 # a2 <- BB 4413 GET_VREG(a1, a3) # a1 <- vCC 4414 GET_VREG(a0, a2) # a0 <- vBB 4415 .if 1 4416 # is second operand zero? 4417 beqz a1, common_errDivideByZero 4418 .endif 4419 4420 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4421 # optional op 4422 div a0, a0, a1 # a0 <- op, a0-a3 changed 4423 GET_INST_OPCODE(t0) # extract opcode from rINST 4424 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4425 4426#else 4427/* File: mips/binop.S */ 4428 /* 4429 * Generic 32-bit binary operation. Provide an "instr" line that 4430 * specifies an instruction that performs "result = a0 op a1". 4431 * This could be a MIPS instruction or a function call. (If the result 4432 * comes back in a register other than a0, you can override "result".) 4433 * 4434 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4435 * vCC (a1). Useful for integer division and modulus. Note that we 4436 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4437 * correctly. 4438 * 4439 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4440 * xor-int, shl-int, shr-int, ushr-int 4441 */ 4442 /* binop vAA, vBB, vCC */ 4443 FETCH(a0, 1) # a0 <- CCBB 4444 GET_OPA(rOBJ) # rOBJ <- AA 4445 srl a3, a0, 8 # a3 <- CC 4446 and a2, a0, 255 # a2 <- BB 4447 GET_VREG(a1, a3) # a1 <- vCC 4448 GET_VREG(a0, a2) # a0 <- vBB 4449 .if 1 4450 # is second operand zero? 4451 beqz a1, common_errDivideByZero 4452 .endif 4453 4454 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4455 div zero, a0, a1 # optional op 4456 mflo a0 # a0 <- op, a0-a3 changed 4457 GET_INST_OPCODE(t0) # extract opcode from rINST 4458 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4459 4460#endif 4461 4462/* ------------------------------ */ 4463 .balign 128 4464.L_op_rem_int: /* 0x94 */ 4465/* File: mips/op_rem_int.S */ 4466#ifdef MIPS32REVGE6 4467/* File: mips/binop.S */ 4468 /* 4469 * Generic 32-bit binary operation. Provide an "instr" line that 4470 * specifies an instruction that performs "result = a0 op a1". 4471 * This could be a MIPS instruction or a function call. (If the result 4472 * comes back in a register other than a0, you can override "result".) 4473 * 4474 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4475 * vCC (a1). Useful for integer division and modulus. Note that we 4476 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4477 * correctly. 4478 * 4479 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4480 * xor-int, shl-int, shr-int, ushr-int 4481 */ 4482 /* binop vAA, vBB, vCC */ 4483 FETCH(a0, 1) # a0 <- CCBB 4484 GET_OPA(rOBJ) # rOBJ <- AA 4485 srl a3, a0, 8 # a3 <- CC 4486 and a2, a0, 255 # a2 <- BB 4487 GET_VREG(a1, a3) # a1 <- vCC 4488 GET_VREG(a0, a2) # a0 <- vBB 4489 .if 1 4490 # is second operand zero? 4491 beqz a1, common_errDivideByZero 4492 .endif 4493 4494 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4495 # optional op 4496 mod a0, a0, a1 # a0 <- op, a0-a3 changed 4497 GET_INST_OPCODE(t0) # extract opcode from rINST 4498 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4499 4500#else 4501/* File: mips/binop.S */ 4502 /* 4503 * Generic 32-bit binary operation. Provide an "instr" line that 4504 * specifies an instruction that performs "result = a0 op a1". 4505 * This could be a MIPS instruction or a function call. (If the result 4506 * comes back in a register other than a0, you can override "result".) 4507 * 4508 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4509 * vCC (a1). Useful for integer division and modulus. Note that we 4510 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4511 * correctly. 4512 * 4513 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4514 * xor-int, shl-int, shr-int, ushr-int 4515 */ 4516 /* binop vAA, vBB, vCC */ 4517 FETCH(a0, 1) # a0 <- CCBB 4518 GET_OPA(rOBJ) # rOBJ <- AA 4519 srl a3, a0, 8 # a3 <- CC 4520 and a2, a0, 255 # a2 <- BB 4521 GET_VREG(a1, a3) # a1 <- vCC 4522 GET_VREG(a0, a2) # a0 <- vBB 4523 .if 1 4524 # is second operand zero? 4525 beqz a1, common_errDivideByZero 4526 .endif 4527 4528 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4529 div zero, a0, a1 # optional op 4530 mfhi a0 # a0 <- op, a0-a3 changed 4531 GET_INST_OPCODE(t0) # extract opcode from rINST 4532 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4533 4534#endif 4535 4536/* ------------------------------ */ 4537 .balign 128 4538.L_op_and_int: /* 0x95 */ 4539/* File: mips/op_and_int.S */ 4540/* File: mips/binop.S */ 4541 /* 4542 * Generic 32-bit binary operation. Provide an "instr" line that 4543 * specifies an instruction that performs "result = a0 op a1". 4544 * This could be a MIPS instruction or a function call. (If the result 4545 * comes back in a register other than a0, you can override "result".) 4546 * 4547 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4548 * vCC (a1). Useful for integer division and modulus. Note that we 4549 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4550 * correctly. 4551 * 4552 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4553 * xor-int, shl-int, shr-int, ushr-int 4554 */ 4555 /* binop vAA, vBB, vCC */ 4556 FETCH(a0, 1) # a0 <- CCBB 4557 GET_OPA(rOBJ) # rOBJ <- AA 4558 srl a3, a0, 8 # a3 <- CC 4559 and a2, a0, 255 # a2 <- BB 4560 GET_VREG(a1, a3) # a1 <- vCC 4561 GET_VREG(a0, a2) # a0 <- vBB 4562 .if 0 4563 # is second operand zero? 4564 beqz a1, common_errDivideByZero 4565 .endif 4566 4567 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4568 # optional op 4569 and a0, a0, a1 # a0 <- op, a0-a3 changed 4570 GET_INST_OPCODE(t0) # extract opcode from rINST 4571 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4572 4573 4574/* ------------------------------ */ 4575 .balign 128 4576.L_op_or_int: /* 0x96 */ 4577/* File: mips/op_or_int.S */ 4578/* File: mips/binop.S */ 4579 /* 4580 * Generic 32-bit binary operation. Provide an "instr" line that 4581 * specifies an instruction that performs "result = a0 op a1". 4582 * This could be a MIPS instruction or a function call. (If the result 4583 * comes back in a register other than a0, you can override "result".) 4584 * 4585 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4586 * vCC (a1). Useful for integer division and modulus. Note that we 4587 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4588 * correctly. 4589 * 4590 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4591 * xor-int, shl-int, shr-int, ushr-int 4592 */ 4593 /* binop vAA, vBB, vCC */ 4594 FETCH(a0, 1) # a0 <- CCBB 4595 GET_OPA(rOBJ) # rOBJ <- AA 4596 srl a3, a0, 8 # a3 <- CC 4597 and a2, a0, 255 # a2 <- BB 4598 GET_VREG(a1, a3) # a1 <- vCC 4599 GET_VREG(a0, a2) # a0 <- vBB 4600 .if 0 4601 # is second operand zero? 4602 beqz a1, common_errDivideByZero 4603 .endif 4604 4605 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4606 # optional op 4607 or a0, a0, a1 # a0 <- op, a0-a3 changed 4608 GET_INST_OPCODE(t0) # extract opcode from rINST 4609 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4610 4611 4612/* ------------------------------ */ 4613 .balign 128 4614.L_op_xor_int: /* 0x97 */ 4615/* File: mips/op_xor_int.S */ 4616/* File: mips/binop.S */ 4617 /* 4618 * Generic 32-bit binary operation. Provide an "instr" line that 4619 * specifies an instruction that performs "result = a0 op a1". 4620 * This could be a MIPS instruction or a function call. (If the result 4621 * comes back in a register other than a0, you can override "result".) 4622 * 4623 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4624 * vCC (a1). Useful for integer division and modulus. Note that we 4625 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4626 * correctly. 4627 * 4628 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4629 * xor-int, shl-int, shr-int, ushr-int 4630 */ 4631 /* binop vAA, vBB, vCC */ 4632 FETCH(a0, 1) # a0 <- CCBB 4633 GET_OPA(rOBJ) # rOBJ <- AA 4634 srl a3, a0, 8 # a3 <- CC 4635 and a2, a0, 255 # a2 <- BB 4636 GET_VREG(a1, a3) # a1 <- vCC 4637 GET_VREG(a0, a2) # a0 <- vBB 4638 .if 0 4639 # is second operand zero? 4640 beqz a1, common_errDivideByZero 4641 .endif 4642 4643 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4644 # optional op 4645 xor a0, a0, a1 # a0 <- op, a0-a3 changed 4646 GET_INST_OPCODE(t0) # extract opcode from rINST 4647 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4648 4649 4650/* ------------------------------ */ 4651 .balign 128 4652.L_op_shl_int: /* 0x98 */ 4653/* File: mips/op_shl_int.S */ 4654/* File: mips/binop.S */ 4655 /* 4656 * Generic 32-bit binary operation. Provide an "instr" line that 4657 * specifies an instruction that performs "result = a0 op a1". 4658 * This could be a MIPS instruction or a function call. (If the result 4659 * comes back in a register other than a0, you can override "result".) 4660 * 4661 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4662 * vCC (a1). Useful for integer division and modulus. Note that we 4663 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4664 * correctly. 4665 * 4666 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4667 * xor-int, shl-int, shr-int, ushr-int 4668 */ 4669 /* binop vAA, vBB, vCC */ 4670 FETCH(a0, 1) # a0 <- CCBB 4671 GET_OPA(rOBJ) # rOBJ <- AA 4672 srl a3, a0, 8 # a3 <- CC 4673 and a2, a0, 255 # a2 <- BB 4674 GET_VREG(a1, a3) # a1 <- vCC 4675 GET_VREG(a0, a2) # a0 <- vBB 4676 .if 0 4677 # is second operand zero? 4678 beqz a1, common_errDivideByZero 4679 .endif 4680 4681 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4682 # optional op 4683 sll a0, a0, a1 # a0 <- op, a0-a3 changed 4684 GET_INST_OPCODE(t0) # extract opcode from rINST 4685 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4686 4687 4688/* ------------------------------ */ 4689 .balign 128 4690.L_op_shr_int: /* 0x99 */ 4691/* File: mips/op_shr_int.S */ 4692/* File: mips/binop.S */ 4693 /* 4694 * Generic 32-bit binary operation. Provide an "instr" line that 4695 * specifies an instruction that performs "result = a0 op a1". 4696 * This could be a MIPS instruction or a function call. (If the result 4697 * comes back in a register other than a0, you can override "result".) 4698 * 4699 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4700 * vCC (a1). Useful for integer division and modulus. Note that we 4701 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4702 * correctly. 4703 * 4704 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4705 * xor-int, shl-int, shr-int, ushr-int 4706 */ 4707 /* binop vAA, vBB, vCC */ 4708 FETCH(a0, 1) # a0 <- CCBB 4709 GET_OPA(rOBJ) # rOBJ <- AA 4710 srl a3, a0, 8 # a3 <- CC 4711 and a2, a0, 255 # a2 <- BB 4712 GET_VREG(a1, a3) # a1 <- vCC 4713 GET_VREG(a0, a2) # a0 <- vBB 4714 .if 0 4715 # is second operand zero? 4716 beqz a1, common_errDivideByZero 4717 .endif 4718 4719 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4720 # optional op 4721 sra a0, a0, a1 # a0 <- op, a0-a3 changed 4722 GET_INST_OPCODE(t0) # extract opcode from rINST 4723 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4724 4725 4726/* ------------------------------ */ 4727 .balign 128 4728.L_op_ushr_int: /* 0x9a */ 4729/* File: mips/op_ushr_int.S */ 4730/* File: mips/binop.S */ 4731 /* 4732 * Generic 32-bit binary operation. Provide an "instr" line that 4733 * specifies an instruction that performs "result = a0 op a1". 4734 * This could be a MIPS instruction or a function call. (If the result 4735 * comes back in a register other than a0, you can override "result".) 4736 * 4737 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4738 * vCC (a1). Useful for integer division and modulus. Note that we 4739 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4740 * correctly. 4741 * 4742 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4743 * xor-int, shl-int, shr-int, ushr-int 4744 */ 4745 /* binop vAA, vBB, vCC */ 4746 FETCH(a0, 1) # a0 <- CCBB 4747 GET_OPA(rOBJ) # rOBJ <- AA 4748 srl a3, a0, 8 # a3 <- CC 4749 and a2, a0, 255 # a2 <- BB 4750 GET_VREG(a1, a3) # a1 <- vCC 4751 GET_VREG(a0, a2) # a0 <- vBB 4752 .if 0 4753 # is second operand zero? 4754 beqz a1, common_errDivideByZero 4755 .endif 4756 4757 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4758 # optional op 4759 srl a0, a0, a1 # a0 <- op, a0-a3 changed 4760 GET_INST_OPCODE(t0) # extract opcode from rINST 4761 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 4762 4763 4764/* ------------------------------ */ 4765 .balign 128 4766.L_op_add_long: /* 0x9b */ 4767/* File: mips/op_add_long.S */ 4768/* 4769 * The compiler generates the following sequence for 4770 * [v1 v0] = [a1 a0] + [a3 a2]; 4771 * addu v0,a2,a0 4772 * addu a1,a3,a1 4773 * sltu v1,v0,a2 4774 * addu v1,v1,a1 4775 */ 4776/* File: mips/binopWide.S */ 4777 /* 4778 * Generic 64-bit binary operation. Provide an "instr" line that 4779 * specifies an instruction that performs "result = a0-a1 op a2-a3". 4780 * This could be a MIPS instruction or a function call. (If the result 4781 * comes back in a register pair other than a0-a1, you can override "result".) 4782 * 4783 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4784 * vCC (a2-a3). Useful for integer division and modulus. 4785 * 4786 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4787 * xor-long 4788 * 4789 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4790 */ 4791 /* binop vAA, vBB, vCC */ 4792 FETCH(a0, 1) # a0 <- CCBB 4793 GET_OPA(rOBJ) # rOBJ <- AA 4794 and a2, a0, 255 # a2 <- BB 4795 srl a3, a0, 8 # a3 <- CC 4796 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 4797 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 4798 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 4799 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 4800 .if 0 4801 or t0, a2, a3 # second arg (a2-a3) is zero? 4802 beqz t0, common_errDivideByZero 4803 .endif 4804 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4805 4806 addu v0, a2, a0 # optional op 4807 addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed 4808 GET_INST_OPCODE(t0) # extract opcode from rINST 4809 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 4810 4811 4812/* ------------------------------ */ 4813 .balign 128 4814.L_op_sub_long: /* 0x9c */ 4815/* File: mips/op_sub_long.S */ 4816/* 4817 * For little endian the code sequence looks as follows: 4818 * subu v0,a0,a2 4819 * subu v1,a1,a3 4820 * sltu a0,a0,v0 4821 * subu v1,v1,a0 4822 */ 4823/* File: mips/binopWide.S */ 4824 /* 4825 * Generic 64-bit binary operation. Provide an "instr" line that 4826 * specifies an instruction that performs "result = a0-a1 op a2-a3". 4827 * This could be a MIPS instruction or a function call. (If the result 4828 * comes back in a register pair other than a0-a1, you can override "result".) 4829 * 4830 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4831 * vCC (a2-a3). Useful for integer division and modulus. 4832 * 4833 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4834 * xor-long 4835 * 4836 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4837 */ 4838 /* binop vAA, vBB, vCC */ 4839 FETCH(a0, 1) # a0 <- CCBB 4840 GET_OPA(rOBJ) # rOBJ <- AA 4841 and a2, a0, 255 # a2 <- BB 4842 srl a3, a0, 8 # a3 <- CC 4843 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 4844 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 4845 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 4846 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 4847 .if 0 4848 or t0, a2, a3 # second arg (a2-a3) is zero? 4849 beqz t0, common_errDivideByZero 4850 .endif 4851 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4852 4853 subu v0, a0, a2 # optional op 4854 subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed 4855 GET_INST_OPCODE(t0) # extract opcode from rINST 4856 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 4857 4858 4859/* ------------------------------ */ 4860 .balign 128 4861.L_op_mul_long: /* 0x9d */ 4862/* File: mips/op_mul_long.S */ 4863 /* 4864 * Signed 64-bit integer multiply. 4865 * a1 a0 4866 * x a3 a2 4867 * ------------- 4868 * a2a1 a2a0 4869 * a3a0 4870 * a3a1 (<= unused) 4871 * --------------- 4872 * v1 v0 4873 */ 4874 /* mul-long vAA, vBB, vCC */ 4875 FETCH(a0, 1) # a0 <- CCBB 4876 and t0, a0, 255 # a2 <- BB 4877 srl t1, a0, 8 # a3 <- CC 4878 EAS2(t0, rFP, t0) # t0 <- &fp[BB] 4879 LOAD64(a0, a1, t0) # a0/a1 <- vBB/vBB+1 4880 4881 EAS2(t1, rFP, t1) # t0 <- &fp[CC] 4882 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 4883 4884 mul v1, a3, a0 # v1= a3a0 4885#ifdef MIPS32REVGE6 4886 mulu v0, a2, a0 # v0= a2a0 4887 muhu t1, a2, a0 4888#else 4889 multu a2, a0 4890 mfhi t1 4891 mflo v0 # v0= a2a0 4892#endif 4893 mul t0, a2, a1 # t0= a2a1 4894 addu v1, v1, t1 # v1+= hi(a2a0) 4895 addu v1, v1, t0 # v1= a3a0 + a2a1; 4896 4897 GET_OPA(a0) # a0 <- AA 4898 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4899 b .Lop_mul_long_finish 4900 4901/* ------------------------------ */ 4902 .balign 128 4903.L_op_div_long: /* 0x9e */ 4904/* File: mips/op_div_long.S */ 4905/* File: mips/binopWide.S */ 4906 /* 4907 * Generic 64-bit binary operation. Provide an "instr" line that 4908 * specifies an instruction that performs "result = a0-a1 op a2-a3". 4909 * This could be a MIPS instruction or a function call. (If the result 4910 * comes back in a register pair other than a0-a1, you can override "result".) 4911 * 4912 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4913 * vCC (a2-a3). Useful for integer division and modulus. 4914 * 4915 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4916 * xor-long 4917 * 4918 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4919 */ 4920 /* binop vAA, vBB, vCC */ 4921 FETCH(a0, 1) # a0 <- CCBB 4922 GET_OPA(rOBJ) # rOBJ <- AA 4923 and a2, a0, 255 # a2 <- BB 4924 srl a3, a0, 8 # a3 <- CC 4925 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 4926 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 4927 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 4928 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 4929 .if 1 4930 or t0, a2, a3 # second arg (a2-a3) is zero? 4931 beqz t0, common_errDivideByZero 4932 .endif 4933 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4934 4935 # optional op 4936 JAL(__divdi3) # result <- op, a0-a3 changed 4937 GET_INST_OPCODE(t0) # extract opcode from rINST 4938 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 4939 4940 4941/* ------------------------------ */ 4942 .balign 128 4943.L_op_rem_long: /* 0x9f */ 4944/* File: mips/op_rem_long.S */ 4945/* File: mips/binopWide.S */ 4946 /* 4947 * Generic 64-bit binary operation. Provide an "instr" line that 4948 * specifies an instruction that performs "result = a0-a1 op a2-a3". 4949 * This could be a MIPS instruction or a function call. (If the result 4950 * comes back in a register pair other than a0-a1, you can override "result".) 4951 * 4952 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4953 * vCC (a2-a3). Useful for integer division and modulus. 4954 * 4955 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4956 * xor-long 4957 * 4958 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4959 */ 4960 /* binop vAA, vBB, vCC */ 4961 FETCH(a0, 1) # a0 <- CCBB 4962 GET_OPA(rOBJ) # rOBJ <- AA 4963 and a2, a0, 255 # a2 <- BB 4964 srl a3, a0, 8 # a3 <- CC 4965 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 4966 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 4967 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 4968 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 4969 .if 1 4970 or t0, a2, a3 # second arg (a2-a3) is zero? 4971 beqz t0, common_errDivideByZero 4972 .endif 4973 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 4974 4975 # optional op 4976 JAL(__moddi3) # result <- op, a0-a3 changed 4977 GET_INST_OPCODE(t0) # extract opcode from rINST 4978 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 4979 4980 4981/* ------------------------------ */ 4982 .balign 128 4983.L_op_and_long: /* 0xa0 */ 4984/* File: mips/op_and_long.S */ 4985/* File: mips/binopWide.S */ 4986 /* 4987 * Generic 64-bit binary operation. Provide an "instr" line that 4988 * specifies an instruction that performs "result = a0-a1 op a2-a3". 4989 * This could be a MIPS instruction or a function call. (If the result 4990 * comes back in a register pair other than a0-a1, you can override "result".) 4991 * 4992 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4993 * vCC (a2-a3). Useful for integer division and modulus. 4994 * 4995 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 4996 * xor-long 4997 * 4998 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 4999 */ 5000 /* binop vAA, vBB, vCC */ 5001 FETCH(a0, 1) # a0 <- CCBB 5002 GET_OPA(rOBJ) # rOBJ <- AA 5003 and a2, a0, 255 # a2 <- BB 5004 srl a3, a0, 8 # a3 <- CC 5005 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5006 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5007 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5008 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5009 .if 0 5010 or t0, a2, a3 # second arg (a2-a3) is zero? 5011 beqz t0, common_errDivideByZero 5012 .endif 5013 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5014 5015 and a0, a0, a2 # optional op 5016 and a1, a1, a3 # result <- op, a0-a3 changed 5017 GET_INST_OPCODE(t0) # extract opcode from rINST 5018 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 5019 5020 5021/* ------------------------------ */ 5022 .balign 128 5023.L_op_or_long: /* 0xa1 */ 5024/* File: mips/op_or_long.S */ 5025/* File: mips/binopWide.S */ 5026 /* 5027 * Generic 64-bit binary operation. Provide an "instr" line that 5028 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5029 * This could be a MIPS instruction or a function call. (If the result 5030 * comes back in a register pair other than a0-a1, you can override "result".) 5031 * 5032 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5033 * vCC (a2-a3). Useful for integer division and modulus. 5034 * 5035 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5036 * xor-long 5037 * 5038 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5039 */ 5040 /* binop vAA, vBB, vCC */ 5041 FETCH(a0, 1) # a0 <- CCBB 5042 GET_OPA(rOBJ) # rOBJ <- AA 5043 and a2, a0, 255 # a2 <- BB 5044 srl a3, a0, 8 # a3 <- CC 5045 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5046 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5047 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5048 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5049 .if 0 5050 or t0, a2, a3 # second arg (a2-a3) is zero? 5051 beqz t0, common_errDivideByZero 5052 .endif 5053 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5054 5055 or a0, a0, a2 # optional op 5056 or a1, a1, a3 # result <- op, a0-a3 changed 5057 GET_INST_OPCODE(t0) # extract opcode from rINST 5058 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 5059 5060 5061/* ------------------------------ */ 5062 .balign 128 5063.L_op_xor_long: /* 0xa2 */ 5064/* File: mips/op_xor_long.S */ 5065/* File: mips/binopWide.S */ 5066 /* 5067 * Generic 64-bit binary operation. Provide an "instr" line that 5068 * specifies an instruction that performs "result = a0-a1 op a2-a3". 5069 * This could be a MIPS instruction or a function call. (If the result 5070 * comes back in a register pair other than a0-a1, you can override "result".) 5071 * 5072 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5073 * vCC (a2-a3). Useful for integer division and modulus. 5074 * 5075 * for: add-long, sub-long, div-long, rem-long, and-long, or-long, 5076 * xor-long 5077 * 5078 * IMPORTANT: you may specify "chkzero" or "preinstr" but not both. 5079 */ 5080 /* binop vAA, vBB, vCC */ 5081 FETCH(a0, 1) # a0 <- CCBB 5082 GET_OPA(rOBJ) # rOBJ <- AA 5083 and a2, a0, 255 # a2 <- BB 5084 srl a3, a0, 8 # a3 <- CC 5085 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5086 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5087 LOAD64(a0, a1, a2) # a0/a1 <- vBB/vBB+1 5088 LOAD64(a2, a3, t1) # a2/a3 <- vCC/vCC+1 5089 .if 0 5090 or t0, a2, a3 # second arg (a2-a3) is zero? 5091 beqz t0, common_errDivideByZero 5092 .endif 5093 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5094 5095 xor a0, a0, a2 # optional op 5096 xor a1, a1, a3 # result <- op, a0-a3 changed 5097 GET_INST_OPCODE(t0) # extract opcode from rINST 5098 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vAA/vAA+1 <- a0/a1 5099 5100 5101/* ------------------------------ */ 5102 .balign 128 5103.L_op_shl_long: /* 0xa3 */ 5104/* File: mips/op_shl_long.S */ 5105 /* 5106 * Long integer shift. This is different from the generic 32/64-bit 5107 * binary operations because vAA/vBB are 64-bit but vCC (the shift 5108 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 5109 * 6 bits of the shift distance. 5110 */ 5111 /* shl-long vAA, vBB, vCC */ 5112 FETCH(a0, 1) # a0 <- CCBB 5113 GET_OPA(t2) # t2 <- AA 5114 and a3, a0, 255 # a3 <- BB 5115 srl a0, a0, 8 # a0 <- CC 5116 EAS2(a3, rFP, a3) # a3 <- &fp[BB] 5117 GET_VREG(a2, a0) # a2 <- vCC 5118 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 5119 5120 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5121 GET_INST_OPCODE(t0) # extract opcode from rINST 5122 5123 andi v1, a2, 0x20 # shift< shift & 0x20 5124 sll v0, a0, a2 # rlo<- alo << (shift&31) 5125 bnez v1, .Lop_shl_long_finish 5126 not v1, a2 # rhi<- 31-shift (shift is 5b) 5127 srl a0, 1 5128 srl a0, v1 # alo<- alo >> (32-(shift&31)) 5129 sll v1, a1, a2 # rhi<- ahi << (shift&31) 5130 or v1, a0 # rhi<- rhi | alo 5131 SET_VREG64_GOTO(v0, v1, t2, t0) # vAA/vAA+1 <- v0/v1 5132 5133/* ------------------------------ */ 5134 .balign 128 5135.L_op_shr_long: /* 0xa4 */ 5136/* File: mips/op_shr_long.S */ 5137 /* 5138 * Long integer shift. This is different from the generic 32/64-bit 5139 * binary operations because vAA/vBB are 64-bit but vCC (the shift 5140 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 5141 * 6 bits of the shift distance. 5142 */ 5143 /* shr-long vAA, vBB, vCC */ 5144 FETCH(a0, 1) # a0 <- CCBB 5145 GET_OPA(t3) # t3 <- AA 5146 and a3, a0, 255 # a3 <- BB 5147 srl a0, a0, 8 # a0 <- CC 5148 EAS2(a3, rFP, a3) # a3 <- &fp[BB] 5149 GET_VREG(a2, a0) # a2 <- vCC 5150 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 5151 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5152 GET_INST_OPCODE(t0) # extract opcode from rINST 5153 5154 andi v0, a2, 0x20 # shift & 0x20 5155 sra v1, a1, a2 # rhi<- ahi >> (shift&31) 5156 bnez v0, .Lop_shr_long_finish 5157 srl v0, a0, a2 # rlo<- alo >> (shift&31) 5158 not a0, a2 # alo<- 31-shift (shift is 5b) 5159 sll a1, 1 5160 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 5161 or v0, a1 # rlo<- rlo | ahi 5162 SET_VREG64_GOTO(v0, v1, t3, t0) # vAA/VAA+1 <- v0/v1 5163 5164/* ------------------------------ */ 5165 .balign 128 5166.L_op_ushr_long: /* 0xa5 */ 5167/* File: mips/op_ushr_long.S */ 5168 /* 5169 * Long integer shift. This is different from the generic 32/64-bit 5170 * binary operations because vAA/vBB are 64-bit but vCC (the shift 5171 * distance) is 32-bit. Also, Dalvik requires us to mask off the low 5172 * 6 bits of the shift distance. 5173 */ 5174 /* ushr-long vAA, vBB, vCC */ 5175 FETCH(a0, 1) # a0 <- CCBB 5176 GET_OPA(rOBJ) # rOBJ <- AA 5177 and a3, a0, 255 # a3 <- BB 5178 srl a0, a0, 8 # a0 <- CC 5179 EAS2(a3, rFP, a3) # a3 <- &fp[BB] 5180 GET_VREG(a2, a0) # a2 <- vCC 5181 LOAD64(a0, a1, a3) # a0/a1 <- vBB/vBB+1 5182 5183 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5184 GET_INST_OPCODE(t0) # extract opcode from rINST 5185 5186 andi v0, a2, 0x20 # shift & 0x20 5187 srl v1, a1, a2 # rhi<- ahi >> (shift&31) 5188 bnez v0, .Lop_ushr_long_finish 5189 srl v0, a0, a2 # rlo<- alo >> (shift&31) 5190 not a0, a2 # alo<- 31-n (shift is 5b) 5191 sll a1, 1 5192 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 5193 or v0, a1 # rlo<- rlo | ahi 5194 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vAA/vAA+1 <- v0/v1 5195 5196/* ------------------------------ */ 5197 .balign 128 5198.L_op_add_float: /* 0xa6 */ 5199/* File: mips/op_add_float.S */ 5200/* File: mips/fbinop.S */ 5201 /* 5202 * Generic 32-bit binary float operation. 5203 * 5204 * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp 5205 */ 5206 5207 /* binop vAA, vBB, vCC */ 5208 FETCH(a0, 1) # a0 <- CCBB 5209 GET_OPA(rOBJ) # rOBJ <- AA 5210 srl a3, a0, 8 # a3 <- CC 5211 and a2, a0, 255 # a2 <- BB 5212 GET_VREG_F(fa1, a3) # a1 <- vCC 5213 GET_VREG_F(fa0, a2) # a0 <- vBB 5214 5215 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5216 add.s fv0, fa0, fa1 # f0 = result 5217 GET_INST_OPCODE(t0) # extract opcode from rINST 5218 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 5219 5220 5221/* ------------------------------ */ 5222 .balign 128 5223.L_op_sub_float: /* 0xa7 */ 5224/* File: mips/op_sub_float.S */ 5225/* File: mips/fbinop.S */ 5226 /* 5227 * Generic 32-bit binary float operation. 5228 * 5229 * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp 5230 */ 5231 5232 /* binop vAA, vBB, vCC */ 5233 FETCH(a0, 1) # a0 <- CCBB 5234 GET_OPA(rOBJ) # rOBJ <- AA 5235 srl a3, a0, 8 # a3 <- CC 5236 and a2, a0, 255 # a2 <- BB 5237 GET_VREG_F(fa1, a3) # a1 <- vCC 5238 GET_VREG_F(fa0, a2) # a0 <- vBB 5239 5240 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5241 sub.s fv0, fa0, fa1 # f0 = result 5242 GET_INST_OPCODE(t0) # extract opcode from rINST 5243 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 5244 5245 5246/* ------------------------------ */ 5247 .balign 128 5248.L_op_mul_float: /* 0xa8 */ 5249/* File: mips/op_mul_float.S */ 5250/* File: mips/fbinop.S */ 5251 /* 5252 * Generic 32-bit binary float operation. 5253 * 5254 * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp 5255 */ 5256 5257 /* binop vAA, vBB, vCC */ 5258 FETCH(a0, 1) # a0 <- CCBB 5259 GET_OPA(rOBJ) # rOBJ <- AA 5260 srl a3, a0, 8 # a3 <- CC 5261 and a2, a0, 255 # a2 <- BB 5262 GET_VREG_F(fa1, a3) # a1 <- vCC 5263 GET_VREG_F(fa0, a2) # a0 <- vBB 5264 5265 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5266 mul.s fv0, fa0, fa1 # f0 = result 5267 GET_INST_OPCODE(t0) # extract opcode from rINST 5268 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 5269 5270 5271/* ------------------------------ */ 5272 .balign 128 5273.L_op_div_float: /* 0xa9 */ 5274/* File: mips/op_div_float.S */ 5275/* File: mips/fbinop.S */ 5276 /* 5277 * Generic 32-bit binary float operation. 5278 * 5279 * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp 5280 */ 5281 5282 /* binop vAA, vBB, vCC */ 5283 FETCH(a0, 1) # a0 <- CCBB 5284 GET_OPA(rOBJ) # rOBJ <- AA 5285 srl a3, a0, 8 # a3 <- CC 5286 and a2, a0, 255 # a2 <- BB 5287 GET_VREG_F(fa1, a3) # a1 <- vCC 5288 GET_VREG_F(fa0, a2) # a0 <- vBB 5289 5290 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5291 div.s fv0, fa0, fa1 # f0 = result 5292 GET_INST_OPCODE(t0) # extract opcode from rINST 5293 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 5294 5295 5296/* ------------------------------ */ 5297 .balign 128 5298.L_op_rem_float: /* 0xaa */ 5299/* File: mips/op_rem_float.S */ 5300/* File: mips/fbinop.S */ 5301 /* 5302 * Generic 32-bit binary float operation. 5303 * 5304 * For: add-fp, sub-fp, mul-fp, div-fp, rem-fp 5305 */ 5306 5307 /* binop vAA, vBB, vCC */ 5308 FETCH(a0, 1) # a0 <- CCBB 5309 GET_OPA(rOBJ) # rOBJ <- AA 5310 srl a3, a0, 8 # a3 <- CC 5311 and a2, a0, 255 # a2 <- BB 5312 GET_VREG_F(fa1, a3) # a1 <- vCC 5313 GET_VREG_F(fa0, a2) # a0 <- vBB 5314 5315 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5316 JAL(fmodf) # f0 = result 5317 GET_INST_OPCODE(t0) # extract opcode from rINST 5318 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vAA <- fv0 5319 5320 5321/* ------------------------------ */ 5322 .balign 128 5323.L_op_add_double: /* 0xab */ 5324/* File: mips/op_add_double.S */ 5325/* File: mips/fbinopWide.S */ 5326 /* 5327 * Generic 64-bit floating-point binary operation. Provide an "instr" 5328 * line that specifies an instruction that performs "fv0 = fa0 op fa1". 5329 * This could be an MIPS instruction or a function call. 5330 * 5331 * for: add-double, sub-double, mul-double, div-double, 5332 * rem-double 5333 * 5334 */ 5335 /* binop vAA, vBB, vCC */ 5336 FETCH(a0, 1) # a0 <- CCBB 5337 GET_OPA(rOBJ) # rOBJ <- AA 5338 and a2, a0, 255 # a2 <- BB 5339 srl a3, a0, 8 # a3 <- CC 5340 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5341 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5342 LOAD64_F(fa0, fa0f, a2) 5343 LOAD64_F(fa1, fa1f, t1) 5344 5345 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5346 add.d fv0, fa0, fa1 5347 GET_INST_OPCODE(t0) # extract opcode from rINST 5348 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 5349 5350 5351/* ------------------------------ */ 5352 .balign 128 5353.L_op_sub_double: /* 0xac */ 5354/* File: mips/op_sub_double.S */ 5355/* File: mips/fbinopWide.S */ 5356 /* 5357 * Generic 64-bit floating-point binary operation. Provide an "instr" 5358 * line that specifies an instruction that performs "fv0 = fa0 op fa1". 5359 * This could be an MIPS instruction or a function call. 5360 * 5361 * for: add-double, sub-double, mul-double, div-double, 5362 * rem-double 5363 * 5364 */ 5365 /* binop vAA, vBB, vCC */ 5366 FETCH(a0, 1) # a0 <- CCBB 5367 GET_OPA(rOBJ) # rOBJ <- AA 5368 and a2, a0, 255 # a2 <- BB 5369 srl a3, a0, 8 # a3 <- CC 5370 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5371 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5372 LOAD64_F(fa0, fa0f, a2) 5373 LOAD64_F(fa1, fa1f, t1) 5374 5375 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5376 sub.d fv0, fa0, fa1 5377 GET_INST_OPCODE(t0) # extract opcode from rINST 5378 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 5379 5380 5381/* ------------------------------ */ 5382 .balign 128 5383.L_op_mul_double: /* 0xad */ 5384/* File: mips/op_mul_double.S */ 5385/* File: mips/fbinopWide.S */ 5386 /* 5387 * Generic 64-bit floating-point binary operation. Provide an "instr" 5388 * line that specifies an instruction that performs "fv0 = fa0 op fa1". 5389 * This could be an MIPS instruction or a function call. 5390 * 5391 * for: add-double, sub-double, mul-double, div-double, 5392 * rem-double 5393 * 5394 */ 5395 /* binop vAA, vBB, vCC */ 5396 FETCH(a0, 1) # a0 <- CCBB 5397 GET_OPA(rOBJ) # rOBJ <- AA 5398 and a2, a0, 255 # a2 <- BB 5399 srl a3, a0, 8 # a3 <- CC 5400 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5401 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5402 LOAD64_F(fa0, fa0f, a2) 5403 LOAD64_F(fa1, fa1f, t1) 5404 5405 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5406 mul.d fv0, fa0, fa1 5407 GET_INST_OPCODE(t0) # extract opcode from rINST 5408 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 5409 5410 5411/* ------------------------------ */ 5412 .balign 128 5413.L_op_div_double: /* 0xae */ 5414/* File: mips/op_div_double.S */ 5415/* File: mips/fbinopWide.S */ 5416 /* 5417 * Generic 64-bit floating-point binary operation. Provide an "instr" 5418 * line that specifies an instruction that performs "fv0 = fa0 op fa1". 5419 * This could be an MIPS instruction or a function call. 5420 * 5421 * for: add-double, sub-double, mul-double, div-double, 5422 * rem-double 5423 * 5424 */ 5425 /* binop vAA, vBB, vCC */ 5426 FETCH(a0, 1) # a0 <- CCBB 5427 GET_OPA(rOBJ) # rOBJ <- AA 5428 and a2, a0, 255 # a2 <- BB 5429 srl a3, a0, 8 # a3 <- CC 5430 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5431 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5432 LOAD64_F(fa0, fa0f, a2) 5433 LOAD64_F(fa1, fa1f, t1) 5434 5435 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5436 div.d fv0, fa0, fa1 5437 GET_INST_OPCODE(t0) # extract opcode from rINST 5438 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 5439 5440 5441/* ------------------------------ */ 5442 .balign 128 5443.L_op_rem_double: /* 0xaf */ 5444/* File: mips/op_rem_double.S */ 5445/* File: mips/fbinopWide.S */ 5446 /* 5447 * Generic 64-bit floating-point binary operation. Provide an "instr" 5448 * line that specifies an instruction that performs "fv0 = fa0 op fa1". 5449 * This could be an MIPS instruction or a function call. 5450 * 5451 * for: add-double, sub-double, mul-double, div-double, 5452 * rem-double 5453 * 5454 */ 5455 /* binop vAA, vBB, vCC */ 5456 FETCH(a0, 1) # a0 <- CCBB 5457 GET_OPA(rOBJ) # rOBJ <- AA 5458 and a2, a0, 255 # a2 <- BB 5459 srl a3, a0, 8 # a3 <- CC 5460 EAS2(a2, rFP, a2) # a2 <- &fp[BB] 5461 EAS2(t1, rFP, a3) # a3 <- &fp[CC] 5462 LOAD64_F(fa0, fa0f, a2) 5463 LOAD64_F(fa1, fa1f, t1) 5464 5465 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 5466 JAL(fmod) 5467 GET_INST_OPCODE(t0) # extract opcode from rINST 5468 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vAA/vAA+1 <- fv0 5469 5470 5471/* ------------------------------ */ 5472 .balign 128 5473.L_op_add_int_2addr: /* 0xb0 */ 5474/* File: mips/op_add_int_2addr.S */ 5475/* File: mips/binop2addr.S */ 5476 /* 5477 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5478 * that specifies an instruction that performs "result = a0 op a1". 5479 * This could be an MIPS instruction or a function call. 5480 * 5481 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5482 * vCC (a1). Useful for integer division and modulus. 5483 * 5484 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5485 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5486 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5487 */ 5488 /* binop/2addr vA, vB */ 5489 GET_OPA4(rOBJ) # rOBJ <- A+ 5490 GET_OPB(a3) # a3 <- B 5491 GET_VREG(a0, rOBJ) # a0 <- vA 5492 GET_VREG(a1, a3) # a1 <- vB 5493 .if 0 5494 # is second operand zero? 5495 beqz a1, common_errDivideByZero 5496 .endif 5497 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5498 5499 # optional op 5500 addu a0, a0, a1 # a0 <- op, a0-a3 changed 5501 GET_INST_OPCODE(t0) # extract opcode from rINST 5502 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5503 5504 5505/* ------------------------------ */ 5506 .balign 128 5507.L_op_sub_int_2addr: /* 0xb1 */ 5508/* File: mips/op_sub_int_2addr.S */ 5509/* File: mips/binop2addr.S */ 5510 /* 5511 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5512 * that specifies an instruction that performs "result = a0 op a1". 5513 * This could be an MIPS instruction or a function call. 5514 * 5515 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5516 * vCC (a1). Useful for integer division and modulus. 5517 * 5518 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5519 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5520 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5521 */ 5522 /* binop/2addr vA, vB */ 5523 GET_OPA4(rOBJ) # rOBJ <- A+ 5524 GET_OPB(a3) # a3 <- B 5525 GET_VREG(a0, rOBJ) # a0 <- vA 5526 GET_VREG(a1, a3) # a1 <- vB 5527 .if 0 5528 # is second operand zero? 5529 beqz a1, common_errDivideByZero 5530 .endif 5531 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5532 5533 # optional op 5534 subu a0, a0, a1 # a0 <- op, a0-a3 changed 5535 GET_INST_OPCODE(t0) # extract opcode from rINST 5536 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5537 5538 5539/* ------------------------------ */ 5540 .balign 128 5541.L_op_mul_int_2addr: /* 0xb2 */ 5542/* File: mips/op_mul_int_2addr.S */ 5543/* File: mips/binop2addr.S */ 5544 /* 5545 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5546 * that specifies an instruction that performs "result = a0 op a1". 5547 * This could be an MIPS instruction or a function call. 5548 * 5549 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5550 * vCC (a1). Useful for integer division and modulus. 5551 * 5552 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5553 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5554 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5555 */ 5556 /* binop/2addr vA, vB */ 5557 GET_OPA4(rOBJ) # rOBJ <- A+ 5558 GET_OPB(a3) # a3 <- B 5559 GET_VREG(a0, rOBJ) # a0 <- vA 5560 GET_VREG(a1, a3) # a1 <- vB 5561 .if 0 5562 # is second operand zero? 5563 beqz a1, common_errDivideByZero 5564 .endif 5565 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5566 5567 # optional op 5568 mul a0, a0, a1 # a0 <- op, a0-a3 changed 5569 GET_INST_OPCODE(t0) # extract opcode from rINST 5570 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5571 5572 5573/* ------------------------------ */ 5574 .balign 128 5575.L_op_div_int_2addr: /* 0xb3 */ 5576/* File: mips/op_div_int_2addr.S */ 5577#ifdef MIPS32REVGE6 5578/* File: mips/binop2addr.S */ 5579 /* 5580 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5581 * that specifies an instruction that performs "result = a0 op a1". 5582 * This could be an MIPS instruction or a function call. 5583 * 5584 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5585 * vCC (a1). Useful for integer division and modulus. 5586 * 5587 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5588 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5589 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5590 */ 5591 /* binop/2addr vA, vB */ 5592 GET_OPA4(rOBJ) # rOBJ <- A+ 5593 GET_OPB(a3) # a3 <- B 5594 GET_VREG(a0, rOBJ) # a0 <- vA 5595 GET_VREG(a1, a3) # a1 <- vB 5596 .if 1 5597 # is second operand zero? 5598 beqz a1, common_errDivideByZero 5599 .endif 5600 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5601 5602 # optional op 5603 div a0, a0, a1 # a0 <- op, a0-a3 changed 5604 GET_INST_OPCODE(t0) # extract opcode from rINST 5605 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5606 5607#else 5608/* File: mips/binop2addr.S */ 5609 /* 5610 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5611 * that specifies an instruction that performs "result = a0 op a1". 5612 * This could be an MIPS instruction or a function call. 5613 * 5614 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5615 * vCC (a1). Useful for integer division and modulus. 5616 * 5617 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5618 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5619 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5620 */ 5621 /* binop/2addr vA, vB */ 5622 GET_OPA4(rOBJ) # rOBJ <- A+ 5623 GET_OPB(a3) # a3 <- B 5624 GET_VREG(a0, rOBJ) # a0 <- vA 5625 GET_VREG(a1, a3) # a1 <- vB 5626 .if 1 5627 # is second operand zero? 5628 beqz a1, common_errDivideByZero 5629 .endif 5630 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5631 5632 div zero, a0, a1 # optional op 5633 mflo a0 # a0 <- op, a0-a3 changed 5634 GET_INST_OPCODE(t0) # extract opcode from rINST 5635 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5636 5637#endif 5638 5639/* ------------------------------ */ 5640 .balign 128 5641.L_op_rem_int_2addr: /* 0xb4 */ 5642/* File: mips/op_rem_int_2addr.S */ 5643#ifdef MIPS32REVGE6 5644/* File: mips/binop2addr.S */ 5645 /* 5646 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5647 * that specifies an instruction that performs "result = a0 op a1". 5648 * This could be an MIPS instruction or a function call. 5649 * 5650 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5651 * vCC (a1). Useful for integer division and modulus. 5652 * 5653 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5654 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5655 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5656 */ 5657 /* binop/2addr vA, vB */ 5658 GET_OPA4(rOBJ) # rOBJ <- A+ 5659 GET_OPB(a3) # a3 <- B 5660 GET_VREG(a0, rOBJ) # a0 <- vA 5661 GET_VREG(a1, a3) # a1 <- vB 5662 .if 1 5663 # is second operand zero? 5664 beqz a1, common_errDivideByZero 5665 .endif 5666 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5667 5668 # optional op 5669 mod a0, a0, a1 # a0 <- op, a0-a3 changed 5670 GET_INST_OPCODE(t0) # extract opcode from rINST 5671 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5672 5673#else 5674/* File: mips/binop2addr.S */ 5675 /* 5676 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5677 * that specifies an instruction that performs "result = a0 op a1". 5678 * This could be an MIPS instruction or a function call. 5679 * 5680 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5681 * vCC (a1). Useful for integer division and modulus. 5682 * 5683 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5684 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5685 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5686 */ 5687 /* binop/2addr vA, vB */ 5688 GET_OPA4(rOBJ) # rOBJ <- A+ 5689 GET_OPB(a3) # a3 <- B 5690 GET_VREG(a0, rOBJ) # a0 <- vA 5691 GET_VREG(a1, a3) # a1 <- vB 5692 .if 1 5693 # is second operand zero? 5694 beqz a1, common_errDivideByZero 5695 .endif 5696 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5697 5698 div zero, a0, a1 # optional op 5699 mfhi a0 # a0 <- op, a0-a3 changed 5700 GET_INST_OPCODE(t0) # extract opcode from rINST 5701 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5702 5703#endif 5704 5705/* ------------------------------ */ 5706 .balign 128 5707.L_op_and_int_2addr: /* 0xb5 */ 5708/* File: mips/op_and_int_2addr.S */ 5709/* File: mips/binop2addr.S */ 5710 /* 5711 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5712 * that specifies an instruction that performs "result = a0 op a1". 5713 * This could be an MIPS instruction or a function call. 5714 * 5715 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5716 * vCC (a1). Useful for integer division and modulus. 5717 * 5718 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5719 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5720 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5721 */ 5722 /* binop/2addr vA, vB */ 5723 GET_OPA4(rOBJ) # rOBJ <- A+ 5724 GET_OPB(a3) # a3 <- B 5725 GET_VREG(a0, rOBJ) # a0 <- vA 5726 GET_VREG(a1, a3) # a1 <- vB 5727 .if 0 5728 # is second operand zero? 5729 beqz a1, common_errDivideByZero 5730 .endif 5731 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5732 5733 # optional op 5734 and a0, a0, a1 # a0 <- op, a0-a3 changed 5735 GET_INST_OPCODE(t0) # extract opcode from rINST 5736 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5737 5738 5739/* ------------------------------ */ 5740 .balign 128 5741.L_op_or_int_2addr: /* 0xb6 */ 5742/* File: mips/op_or_int_2addr.S */ 5743/* File: mips/binop2addr.S */ 5744 /* 5745 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5746 * that specifies an instruction that performs "result = a0 op a1". 5747 * This could be an MIPS instruction or a function call. 5748 * 5749 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5750 * vCC (a1). Useful for integer division and modulus. 5751 * 5752 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5753 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5754 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5755 */ 5756 /* binop/2addr vA, vB */ 5757 GET_OPA4(rOBJ) # rOBJ <- A+ 5758 GET_OPB(a3) # a3 <- B 5759 GET_VREG(a0, rOBJ) # a0 <- vA 5760 GET_VREG(a1, a3) # a1 <- vB 5761 .if 0 5762 # is second operand zero? 5763 beqz a1, common_errDivideByZero 5764 .endif 5765 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5766 5767 # optional op 5768 or a0, a0, a1 # a0 <- op, a0-a3 changed 5769 GET_INST_OPCODE(t0) # extract opcode from rINST 5770 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5771 5772 5773/* ------------------------------ */ 5774 .balign 128 5775.L_op_xor_int_2addr: /* 0xb7 */ 5776/* File: mips/op_xor_int_2addr.S */ 5777/* File: mips/binop2addr.S */ 5778 /* 5779 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5780 * that specifies an instruction that performs "result = a0 op a1". 5781 * This could be an MIPS instruction or a function call. 5782 * 5783 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5784 * vCC (a1). Useful for integer division and modulus. 5785 * 5786 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5787 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5788 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5789 */ 5790 /* binop/2addr vA, vB */ 5791 GET_OPA4(rOBJ) # rOBJ <- A+ 5792 GET_OPB(a3) # a3 <- B 5793 GET_VREG(a0, rOBJ) # a0 <- vA 5794 GET_VREG(a1, a3) # a1 <- vB 5795 .if 0 5796 # is second operand zero? 5797 beqz a1, common_errDivideByZero 5798 .endif 5799 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5800 5801 # optional op 5802 xor a0, a0, a1 # a0 <- op, a0-a3 changed 5803 GET_INST_OPCODE(t0) # extract opcode from rINST 5804 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5805 5806 5807/* ------------------------------ */ 5808 .balign 128 5809.L_op_shl_int_2addr: /* 0xb8 */ 5810/* File: mips/op_shl_int_2addr.S */ 5811/* File: mips/binop2addr.S */ 5812 /* 5813 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5814 * that specifies an instruction that performs "result = a0 op a1". 5815 * This could be an MIPS instruction or a function call. 5816 * 5817 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5818 * vCC (a1). Useful for integer division and modulus. 5819 * 5820 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5821 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5822 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5823 */ 5824 /* binop/2addr vA, vB */ 5825 GET_OPA4(rOBJ) # rOBJ <- A+ 5826 GET_OPB(a3) # a3 <- B 5827 GET_VREG(a0, rOBJ) # a0 <- vA 5828 GET_VREG(a1, a3) # a1 <- vB 5829 .if 0 5830 # is second operand zero? 5831 beqz a1, common_errDivideByZero 5832 .endif 5833 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5834 5835 # optional op 5836 sll a0, a0, a1 # a0 <- op, a0-a3 changed 5837 GET_INST_OPCODE(t0) # extract opcode from rINST 5838 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5839 5840 5841/* ------------------------------ */ 5842 .balign 128 5843.L_op_shr_int_2addr: /* 0xb9 */ 5844/* File: mips/op_shr_int_2addr.S */ 5845/* File: mips/binop2addr.S */ 5846 /* 5847 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5848 * that specifies an instruction that performs "result = a0 op a1". 5849 * This could be an MIPS instruction or a function call. 5850 * 5851 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5852 * vCC (a1). Useful for integer division and modulus. 5853 * 5854 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5855 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5856 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5857 */ 5858 /* binop/2addr vA, vB */ 5859 GET_OPA4(rOBJ) # rOBJ <- A+ 5860 GET_OPB(a3) # a3 <- B 5861 GET_VREG(a0, rOBJ) # a0 <- vA 5862 GET_VREG(a1, a3) # a1 <- vB 5863 .if 0 5864 # is second operand zero? 5865 beqz a1, common_errDivideByZero 5866 .endif 5867 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5868 5869 # optional op 5870 sra a0, a0, a1 # a0 <- op, a0-a3 changed 5871 GET_INST_OPCODE(t0) # extract opcode from rINST 5872 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5873 5874 5875/* ------------------------------ */ 5876 .balign 128 5877.L_op_ushr_int_2addr: /* 0xba */ 5878/* File: mips/op_ushr_int_2addr.S */ 5879/* File: mips/binop2addr.S */ 5880 /* 5881 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5882 * that specifies an instruction that performs "result = a0 op a1". 5883 * This could be an MIPS instruction or a function call. 5884 * 5885 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5886 * vCC (a1). Useful for integer division and modulus. 5887 * 5888 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5889 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5890 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5891 */ 5892 /* binop/2addr vA, vB */ 5893 GET_OPA4(rOBJ) # rOBJ <- A+ 5894 GET_OPB(a3) # a3 <- B 5895 GET_VREG(a0, rOBJ) # a0 <- vA 5896 GET_VREG(a1, a3) # a1 <- vB 5897 .if 0 5898 # is second operand zero? 5899 beqz a1, common_errDivideByZero 5900 .endif 5901 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5902 5903 # optional op 5904 srl a0, a0, a1 # a0 <- op, a0-a3 changed 5905 GET_INST_OPCODE(t0) # extract opcode from rINST 5906 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 5907 5908 5909/* ------------------------------ */ 5910 .balign 128 5911.L_op_add_long_2addr: /* 0xbb */ 5912/* File: mips/op_add_long_2addr.S */ 5913/* 5914 * See op_add_long.S for details 5915 */ 5916/* File: mips/binopWide2addr.S */ 5917 /* 5918 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5919 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 5920 * This could be a MIPS instruction or a function call. (If the result 5921 * comes back in a register pair other than a0-a1, you can override "result".) 5922 * 5923 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5924 * vB (a2-a3). Useful for integer division and modulus. 5925 * 5926 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5927 * and-long/2addr, or-long/2addr, xor-long/2addr 5928 */ 5929 /* binop/2addr vA, vB */ 5930 GET_OPA4(rOBJ) # rOBJ <- A+ 5931 GET_OPB(a1) # a1 <- B 5932 EAS2(a1, rFP, a1) # a1 <- &fp[B] 5933 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 5934 LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 5935 LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 5936 .if 0 5937 or t0, a2, a3 # second arg (a2-a3) is zero? 5938 beqz t0, common_errDivideByZero 5939 .endif 5940 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5941 5942 addu v0, a2, a0 # optional op 5943 addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1 # result <- op, a0-a3 changed 5944 GET_INST_OPCODE(t0) # extract opcode from rINST 5945 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 5946 5947 5948/* ------------------------------ */ 5949 .balign 128 5950.L_op_sub_long_2addr: /* 0xbc */ 5951/* File: mips/op_sub_long_2addr.S */ 5952/* 5953 * See op_sub_long.S for more details 5954 */ 5955/* File: mips/binopWide2addr.S */ 5956 /* 5957 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5958 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 5959 * This could be a MIPS instruction or a function call. (If the result 5960 * comes back in a register pair other than a0-a1, you can override "result".) 5961 * 5962 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5963 * vB (a2-a3). Useful for integer division and modulus. 5964 * 5965 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 5966 * and-long/2addr, or-long/2addr, xor-long/2addr 5967 */ 5968 /* binop/2addr vA, vB */ 5969 GET_OPA4(rOBJ) # rOBJ <- A+ 5970 GET_OPB(a1) # a1 <- B 5971 EAS2(a1, rFP, a1) # a1 <- &fp[B] 5972 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 5973 LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 5974 LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 5975 .if 0 5976 or t0, a2, a3 # second arg (a2-a3) is zero? 5977 beqz t0, common_errDivideByZero 5978 .endif 5979 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 5980 5981 subu v0, a0, a2 # optional op 5982 subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0 # result <- op, a0-a3 changed 5983 GET_INST_OPCODE(t0) # extract opcode from rINST 5984 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 5985 5986 5987/* ------------------------------ */ 5988 .balign 128 5989.L_op_mul_long_2addr: /* 0xbd */ 5990/* File: mips/op_mul_long_2addr.S */ 5991 /* 5992 * See op_mul_long.S for more details 5993 */ 5994 /* mul-long/2addr vA, vB */ 5995 GET_OPA4(rOBJ) # rOBJ <- A+ 5996 5997 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 5998 LOAD64(a0, a1, t0) # vAA.low / high 5999 6000 GET_OPB(t1) # t1 <- B 6001 EAS2(t1, rFP, t1) # t1 <- &fp[B] 6002 LOAD64(a2, a3, t1) # vBB.low / high 6003 6004 mul v1, a3, a0 # v1= a3a0 6005#ifdef MIPS32REVGE6 6006 mulu v0, a2, a0 # v0= a2a0 6007 muhu t1, a2, a0 6008#else 6009 multu a2, a0 6010 mfhi t1 6011 mflo v0 # v0= a2a0 6012 #endif 6013 mul t2, a2, a1 # t2= a2a1 6014 addu v1, v1, t1 # v1= a3a0 + hi(a2a0) 6015 addu v1, v1, t2 # v1= v1 + a2a1; 6016 6017 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6018 GET_INST_OPCODE(t1) # extract opcode from rINST 6019 SET_VREG64_GOTO(v0, v1, rOBJ, t1) # vA/vA+1 <- v0(low)/v1(high) 6020 6021/* ------------------------------ */ 6022 .balign 128 6023.L_op_div_long_2addr: /* 0xbe */ 6024/* File: mips/op_div_long_2addr.S */ 6025/* File: mips/binopWide2addr.S */ 6026 /* 6027 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6028 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6029 * This could be a MIPS instruction or a function call. (If the result 6030 * comes back in a register pair other than a0-a1, you can override "result".) 6031 * 6032 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6033 * vB (a2-a3). Useful for integer division and modulus. 6034 * 6035 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6036 * and-long/2addr, or-long/2addr, xor-long/2addr 6037 */ 6038 /* binop/2addr vA, vB */ 6039 GET_OPA4(rOBJ) # rOBJ <- A+ 6040 GET_OPB(a1) # a1 <- B 6041 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6042 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6043 LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 6044 LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 6045 .if 1 6046 or t0, a2, a3 # second arg (a2-a3) is zero? 6047 beqz t0, common_errDivideByZero 6048 .endif 6049 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6050 6051 # optional op 6052 JAL(__divdi3) # result <- op, a0-a3 changed 6053 GET_INST_OPCODE(t0) # extract opcode from rINST 6054 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 6055 6056 6057/* ------------------------------ */ 6058 .balign 128 6059.L_op_rem_long_2addr: /* 0xbf */ 6060/* File: mips/op_rem_long_2addr.S */ 6061/* File: mips/binopWide2addr.S */ 6062 /* 6063 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6064 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6065 * This could be a MIPS instruction or a function call. (If the result 6066 * comes back in a register pair other than a0-a1, you can override "result".) 6067 * 6068 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6069 * vB (a2-a3). Useful for integer division and modulus. 6070 * 6071 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6072 * and-long/2addr, or-long/2addr, xor-long/2addr 6073 */ 6074 /* binop/2addr vA, vB */ 6075 GET_OPA4(rOBJ) # rOBJ <- A+ 6076 GET_OPB(a1) # a1 <- B 6077 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6078 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6079 LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 6080 LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 6081 .if 1 6082 or t0, a2, a3 # second arg (a2-a3) is zero? 6083 beqz t0, common_errDivideByZero 6084 .endif 6085 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6086 6087 # optional op 6088 JAL(__moddi3) # result <- op, a0-a3 changed 6089 GET_INST_OPCODE(t0) # extract opcode from rINST 6090 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 6091 6092 6093/* ------------------------------ */ 6094 .balign 128 6095.L_op_and_long_2addr: /* 0xc0 */ 6096/* File: mips/op_and_long_2addr.S */ 6097/* File: mips/binopWide2addr.S */ 6098 /* 6099 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6100 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6101 * This could be a MIPS instruction or a function call. (If the result 6102 * comes back in a register pair other than a0-a1, you can override "result".) 6103 * 6104 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6105 * vB (a2-a3). Useful for integer division and modulus. 6106 * 6107 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6108 * and-long/2addr, or-long/2addr, xor-long/2addr 6109 */ 6110 /* binop/2addr vA, vB */ 6111 GET_OPA4(rOBJ) # rOBJ <- A+ 6112 GET_OPB(a1) # a1 <- B 6113 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6114 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6115 LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 6116 LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 6117 .if 0 6118 or t0, a2, a3 # second arg (a2-a3) is zero? 6119 beqz t0, common_errDivideByZero 6120 .endif 6121 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6122 6123 and a0, a0, a2 # optional op 6124 and a1, a1, a3 # result <- op, a0-a3 changed 6125 GET_INST_OPCODE(t0) # extract opcode from rINST 6126 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 6127 6128 6129/* ------------------------------ */ 6130 .balign 128 6131.L_op_or_long_2addr: /* 0xc1 */ 6132/* File: mips/op_or_long_2addr.S */ 6133/* File: mips/binopWide2addr.S */ 6134 /* 6135 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6136 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6137 * This could be a MIPS instruction or a function call. (If the result 6138 * comes back in a register pair other than a0-a1, you can override "result".) 6139 * 6140 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6141 * vB (a2-a3). Useful for integer division and modulus. 6142 * 6143 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6144 * and-long/2addr, or-long/2addr, xor-long/2addr 6145 */ 6146 /* binop/2addr vA, vB */ 6147 GET_OPA4(rOBJ) # rOBJ <- A+ 6148 GET_OPB(a1) # a1 <- B 6149 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6150 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6151 LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 6152 LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 6153 .if 0 6154 or t0, a2, a3 # second arg (a2-a3) is zero? 6155 beqz t0, common_errDivideByZero 6156 .endif 6157 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6158 6159 or a0, a0, a2 # optional op 6160 or a1, a1, a3 # result <- op, a0-a3 changed 6161 GET_INST_OPCODE(t0) # extract opcode from rINST 6162 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 6163 6164 6165/* ------------------------------ */ 6166 .balign 128 6167.L_op_xor_long_2addr: /* 0xc2 */ 6168/* File: mips/op_xor_long_2addr.S */ 6169/* File: mips/binopWide2addr.S */ 6170 /* 6171 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 6172 * that specifies an instruction that performs "result = a0-a1 op a2-a3". 6173 * This could be a MIPS instruction or a function call. (If the result 6174 * comes back in a register pair other than a0-a1, you can override "result".) 6175 * 6176 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6177 * vB (a2-a3). Useful for integer division and modulus. 6178 * 6179 * For: add-long/2addr, sub-long/2addr, div-long/2addr, rem-long/2addr, 6180 * and-long/2addr, or-long/2addr, xor-long/2addr 6181 */ 6182 /* binop/2addr vA, vB */ 6183 GET_OPA4(rOBJ) # rOBJ <- A+ 6184 GET_OPB(a1) # a1 <- B 6185 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6186 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6187 LOAD64(a2, a3, a1) # a2/a3 <- vB/vB+1 6188 LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 6189 .if 0 6190 or t0, a2, a3 # second arg (a2-a3) is zero? 6191 beqz t0, common_errDivideByZero 6192 .endif 6193 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6194 6195 xor a0, a0, a2 # optional op 6196 xor a1, a1, a3 # result <- op, a0-a3 changed 6197 GET_INST_OPCODE(t0) # extract opcode from rINST 6198 SET_VREG64_GOTO(a0, a1, rOBJ, t0) # vA/vA+1 <- a0/a1 6199 6200 6201/* ------------------------------ */ 6202 .balign 128 6203.L_op_shl_long_2addr: /* 0xc3 */ 6204/* File: mips/op_shl_long_2addr.S */ 6205 /* 6206 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6207 * 32-bit shift distance. 6208 */ 6209 /* shl-long/2addr vA, vB */ 6210 GET_OPA4(rOBJ) # rOBJ <- A+ 6211 GET_OPB(a3) # a3 <- B 6212 GET_VREG(a2, a3) # a2 <- vB 6213 EAS2(t2, rFP, rOBJ) # t2 <- &fp[A] 6214 LOAD64(a0, a1, t2) # a0/a1 <- vA/vA+1 6215 6216 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6217 GET_INST_OPCODE(t0) # extract opcode from rINST 6218 6219 andi v1, a2, 0x20 # shift< shift & 0x20 6220 sll v0, a0, a2 # rlo<- alo << (shift&31) 6221 bnez v1, .Lop_shl_long_2addr_finish 6222 not v1, a2 # rhi<- 31-shift (shift is 5b) 6223 srl a0, 1 6224 srl a0, v1 # alo<- alo >> (32-(shift&31)) 6225 sll v1, a1, a2 # rhi<- ahi << (shift&31) 6226 or v1, a0 # rhi<- rhi | alo 6227 SET_VREG64_GOTO(v0, v1, rOBJ, t0) # vA/vA+1 <- v0/v1 6228 6229/* ------------------------------ */ 6230 .balign 128 6231.L_op_shr_long_2addr: /* 0xc4 */ 6232/* File: mips/op_shr_long_2addr.S */ 6233 /* 6234 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6235 * 32-bit shift distance. 6236 */ 6237 /* shr-long/2addr vA, vB */ 6238 GET_OPA4(t2) # t2 <- A+ 6239 GET_OPB(a3) # a3 <- B 6240 GET_VREG(a2, a3) # a2 <- vB 6241 EAS2(t0, rFP, t2) # t0 <- &fp[A] 6242 LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 6243 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6244 GET_INST_OPCODE(t0) # extract opcode from rINST 6245 6246 andi v0, a2, 0x20 # shift & 0x20 6247 sra v1, a1, a2 # rhi<- ahi >> (shift&31) 6248 bnez v0, .Lop_shr_long_2addr_finish 6249 srl v0, a0, a2 # rlo<- alo >> (shift&31) 6250 not a0, a2 # alo<- 31-shift (shift is 5b) 6251 sll a1, 1 6252 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 6253 or v0, a1 # rlo<- rlo | ahi 6254 SET_VREG64_GOTO(v0, v1, t2, t0) # vA/vA+1 <- v0/v1 6255 6256/* ------------------------------ */ 6257 .balign 128 6258.L_op_ushr_long_2addr: /* 0xc5 */ 6259/* File: mips/op_ushr_long_2addr.S */ 6260 /* 6261 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 6262 * 32-bit shift distance. 6263 */ 6264 /* ushr-long/2addr vA, vB */ 6265 GET_OPA4(t3) # t3 <- A+ 6266 GET_OPB(a3) # a3 <- B 6267 GET_VREG(a2, a3) # a2 <- vB 6268 EAS2(t0, rFP, t3) # t0 <- &fp[A] 6269 LOAD64(a0, a1, t0) # a0/a1 <- vA/vA+1 6270 6271 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6272 GET_INST_OPCODE(t0) # extract opcode from rINST 6273 6274 andi v0, a2, 0x20 # shift & 0x20 6275 srl v1, a1, a2 # rhi<- ahi >> (shift&31) 6276 bnez v0, .Lop_ushr_long_2addr_finish 6277 srl v0, a0, a2 # rlo<- alo >> (shift&31) 6278 not a0, a2 # alo<- 31-n (shift is 5b) 6279 sll a1, 1 6280 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 6281 or v0, a1 # rlo<- rlo | ahi 6282 SET_VREG64_GOTO(v0, v1, t3, t0) # vA/vA+1 <- v0/v1 6283 6284/* ------------------------------ */ 6285 .balign 128 6286.L_op_add_float_2addr: /* 0xc6 */ 6287/* File: mips/op_add_float_2addr.S */ 6288/* File: mips/fbinop2addr.S */ 6289 /* 6290 * Generic 32-bit "/2addr" binary operation. Provide an "instr" 6291 * that specifies an instruction that performs "fv0 = fa0 op fa1". 6292 * This could be an MIPS instruction or a function call. 6293 * 6294 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 6295 * div-float/2addr, rem-float/2addr 6296 */ 6297 /* binop/2addr vA, vB */ 6298 GET_OPA4(rOBJ) # rOBJ <- A+ 6299 GET_OPB(a3) # a3 <- B 6300 GET_VREG_F(fa0, rOBJ) 6301 GET_VREG_F(fa1, a3) 6302 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6303 6304 add.s fv0, fa0, fa1 6305 GET_INST_OPCODE(t0) # extract opcode from rINST 6306 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result 6307 6308 6309/* ------------------------------ */ 6310 .balign 128 6311.L_op_sub_float_2addr: /* 0xc7 */ 6312/* File: mips/op_sub_float_2addr.S */ 6313/* File: mips/fbinop2addr.S */ 6314 /* 6315 * Generic 32-bit "/2addr" binary operation. Provide an "instr" 6316 * that specifies an instruction that performs "fv0 = fa0 op fa1". 6317 * This could be an MIPS instruction or a function call. 6318 * 6319 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 6320 * div-float/2addr, rem-float/2addr 6321 */ 6322 /* binop/2addr vA, vB */ 6323 GET_OPA4(rOBJ) # rOBJ <- A+ 6324 GET_OPB(a3) # a3 <- B 6325 GET_VREG_F(fa0, rOBJ) 6326 GET_VREG_F(fa1, a3) 6327 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6328 6329 sub.s fv0, fa0, fa1 6330 GET_INST_OPCODE(t0) # extract opcode from rINST 6331 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result 6332 6333 6334/* ------------------------------ */ 6335 .balign 128 6336.L_op_mul_float_2addr: /* 0xc8 */ 6337/* File: mips/op_mul_float_2addr.S */ 6338/* File: mips/fbinop2addr.S */ 6339 /* 6340 * Generic 32-bit "/2addr" binary operation. Provide an "instr" 6341 * that specifies an instruction that performs "fv0 = fa0 op fa1". 6342 * This could be an MIPS instruction or a function call. 6343 * 6344 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 6345 * div-float/2addr, rem-float/2addr 6346 */ 6347 /* binop/2addr vA, vB */ 6348 GET_OPA4(rOBJ) # rOBJ <- A+ 6349 GET_OPB(a3) # a3 <- B 6350 GET_VREG_F(fa0, rOBJ) 6351 GET_VREG_F(fa1, a3) 6352 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6353 6354 mul.s fv0, fa0, fa1 6355 GET_INST_OPCODE(t0) # extract opcode from rINST 6356 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result 6357 6358 6359/* ------------------------------ */ 6360 .balign 128 6361.L_op_div_float_2addr: /* 0xc9 */ 6362/* File: mips/op_div_float_2addr.S */ 6363/* File: mips/fbinop2addr.S */ 6364 /* 6365 * Generic 32-bit "/2addr" binary operation. Provide an "instr" 6366 * that specifies an instruction that performs "fv0 = fa0 op fa1". 6367 * This could be an MIPS instruction or a function call. 6368 * 6369 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 6370 * div-float/2addr, rem-float/2addr 6371 */ 6372 /* binop/2addr vA, vB */ 6373 GET_OPA4(rOBJ) # rOBJ <- A+ 6374 GET_OPB(a3) # a3 <- B 6375 GET_VREG_F(fa0, rOBJ) 6376 GET_VREG_F(fa1, a3) 6377 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6378 6379 div.s fv0, fa0, fa1 6380 GET_INST_OPCODE(t0) # extract opcode from rINST 6381 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result 6382 6383 6384/* ------------------------------ */ 6385 .balign 128 6386.L_op_rem_float_2addr: /* 0xca */ 6387/* File: mips/op_rem_float_2addr.S */ 6388/* File: mips/fbinop2addr.S */ 6389 /* 6390 * Generic 32-bit "/2addr" binary operation. Provide an "instr" 6391 * that specifies an instruction that performs "fv0 = fa0 op fa1". 6392 * This could be an MIPS instruction or a function call. 6393 * 6394 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, 6395 * div-float/2addr, rem-float/2addr 6396 */ 6397 /* binop/2addr vA, vB */ 6398 GET_OPA4(rOBJ) # rOBJ <- A+ 6399 GET_OPB(a3) # a3 <- B 6400 GET_VREG_F(fa0, rOBJ) 6401 GET_VREG_F(fa1, a3) 6402 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6403 6404 JAL(fmodf) 6405 GET_INST_OPCODE(t0) # extract opcode from rINST 6406 SET_VREG_F_GOTO(fv0, rOBJ, t0) # vA <- result 6407 6408 6409/* ------------------------------ */ 6410 .balign 128 6411.L_op_add_double_2addr: /* 0xcb */ 6412/* File: mips/op_add_double_2addr.S */ 6413/* File: mips/fbinopWide2addr.S */ 6414 /* 6415 * Generic 64-bit floating-point "/2addr" binary operation. 6416 * Provide an "instr" line that specifies an instruction that 6417 * performs "fv0 = fa0 op fa1". 6418 * This could be an MIPS instruction or a function call. 6419 * 6420 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6421 * div-double/2addr, rem-double/2addr 6422 */ 6423 /* binop/2addr vA, vB */ 6424 GET_OPA4(rOBJ) # rOBJ <- A+ 6425 GET_OPB(a1) # a1 <- B 6426 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6427 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6428 LOAD64_F(fa0, fa0f, t0) 6429 LOAD64_F(fa1, fa1f, a1) 6430 6431 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6432 add.d fv0, fa0, fa1 6433 GET_INST_OPCODE(t0) # extract opcode from rINST 6434 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 6435 6436 6437/* ------------------------------ */ 6438 .balign 128 6439.L_op_sub_double_2addr: /* 0xcc */ 6440/* File: mips/op_sub_double_2addr.S */ 6441/* File: mips/fbinopWide2addr.S */ 6442 /* 6443 * Generic 64-bit floating-point "/2addr" binary operation. 6444 * Provide an "instr" line that specifies an instruction that 6445 * performs "fv0 = fa0 op fa1". 6446 * This could be an MIPS instruction or a function call. 6447 * 6448 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6449 * div-double/2addr, rem-double/2addr 6450 */ 6451 /* binop/2addr vA, vB */ 6452 GET_OPA4(rOBJ) # rOBJ <- A+ 6453 GET_OPB(a1) # a1 <- B 6454 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6455 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6456 LOAD64_F(fa0, fa0f, t0) 6457 LOAD64_F(fa1, fa1f, a1) 6458 6459 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6460 sub.d fv0, fa0, fa1 6461 GET_INST_OPCODE(t0) # extract opcode from rINST 6462 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 6463 6464 6465/* ------------------------------ */ 6466 .balign 128 6467.L_op_mul_double_2addr: /* 0xcd */ 6468/* File: mips/op_mul_double_2addr.S */ 6469/* File: mips/fbinopWide2addr.S */ 6470 /* 6471 * Generic 64-bit floating-point "/2addr" binary operation. 6472 * Provide an "instr" line that specifies an instruction that 6473 * performs "fv0 = fa0 op fa1". 6474 * This could be an MIPS instruction or a function call. 6475 * 6476 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6477 * div-double/2addr, rem-double/2addr 6478 */ 6479 /* binop/2addr vA, vB */ 6480 GET_OPA4(rOBJ) # rOBJ <- A+ 6481 GET_OPB(a1) # a1 <- B 6482 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6483 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6484 LOAD64_F(fa0, fa0f, t0) 6485 LOAD64_F(fa1, fa1f, a1) 6486 6487 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6488 mul.d fv0, fa0, fa1 6489 GET_INST_OPCODE(t0) # extract opcode from rINST 6490 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 6491 6492 6493/* ------------------------------ */ 6494 .balign 128 6495.L_op_div_double_2addr: /* 0xce */ 6496/* File: mips/op_div_double_2addr.S */ 6497/* File: mips/fbinopWide2addr.S */ 6498 /* 6499 * Generic 64-bit floating-point "/2addr" binary operation. 6500 * Provide an "instr" line that specifies an instruction that 6501 * performs "fv0 = fa0 op fa1". 6502 * This could be an MIPS instruction or a function call. 6503 * 6504 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6505 * div-double/2addr, rem-double/2addr 6506 */ 6507 /* binop/2addr vA, vB */ 6508 GET_OPA4(rOBJ) # rOBJ <- A+ 6509 GET_OPB(a1) # a1 <- B 6510 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6511 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6512 LOAD64_F(fa0, fa0f, t0) 6513 LOAD64_F(fa1, fa1f, a1) 6514 6515 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6516 div.d fv0, fa0, fa1 6517 GET_INST_OPCODE(t0) # extract opcode from rINST 6518 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 6519 6520 6521/* ------------------------------ */ 6522 .balign 128 6523.L_op_rem_double_2addr: /* 0xcf */ 6524/* File: mips/op_rem_double_2addr.S */ 6525/* File: mips/fbinopWide2addr.S */ 6526 /* 6527 * Generic 64-bit floating-point "/2addr" binary operation. 6528 * Provide an "instr" line that specifies an instruction that 6529 * performs "fv0 = fa0 op fa1". 6530 * This could be an MIPS instruction or a function call. 6531 * 6532 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, 6533 * div-double/2addr, rem-double/2addr 6534 */ 6535 /* binop/2addr vA, vB */ 6536 GET_OPA4(rOBJ) # rOBJ <- A+ 6537 GET_OPB(a1) # a1 <- B 6538 EAS2(a1, rFP, a1) # a1 <- &fp[B] 6539 EAS2(t0, rFP, rOBJ) # t0 <- &fp[A] 6540 LOAD64_F(fa0, fa0f, t0) 6541 LOAD64_F(fa1, fa1f, a1) 6542 6543 FETCH_ADVANCE_INST(1) # advance rPC, load rINST 6544 JAL(fmod) 6545 GET_INST_OPCODE(t0) # extract opcode from rINST 6546 SET_VREG64_F_GOTO(fv0, fv0f, rOBJ, t0) # vA/vA+1 <- fv0 6547 6548 6549/* ------------------------------ */ 6550 .balign 128 6551.L_op_add_int_lit16: /* 0xd0 */ 6552/* File: mips/op_add_int_lit16.S */ 6553/* File: mips/binopLit16.S */ 6554 /* 6555 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6556 * that specifies an instruction that performs "result = a0 op a1". 6557 * This could be an MIPS instruction or a function call. (If the result 6558 * comes back in a register other than a0, you can override "result".) 6559 * 6560 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6561 * vCC (a1). Useful for integer division and modulus. 6562 * 6563 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6564 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6565 */ 6566 /* binop/lit16 vA, vB, +CCCC */ 6567 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6568 GET_OPB(a2) # a2 <- B 6569 GET_OPA4(rOBJ) # rOBJ <- A+ 6570 GET_VREG(a0, a2) # a0 <- vB 6571 .if 0 6572 # cmp a1, 0; is second operand zero? 6573 beqz a1, common_errDivideByZero 6574 .endif 6575 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6576 6577 # optional op 6578 addu a0, a0, a1 # a0 <- op, a0-a3 changed 6579 GET_INST_OPCODE(t0) # extract opcode from rINST 6580 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 6581 6582 6583/* ------------------------------ */ 6584 .balign 128 6585.L_op_rsub_int: /* 0xd1 */ 6586/* File: mips/op_rsub_int.S */ 6587/* this op is "rsub-int", but can be thought of as "rsub-int/lit16" */ 6588/* File: mips/binopLit16.S */ 6589 /* 6590 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6591 * that specifies an instruction that performs "result = a0 op a1". 6592 * This could be an MIPS instruction or a function call. (If the result 6593 * comes back in a register other than a0, you can override "result".) 6594 * 6595 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6596 * vCC (a1). Useful for integer division and modulus. 6597 * 6598 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6599 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6600 */ 6601 /* binop/lit16 vA, vB, +CCCC */ 6602 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6603 GET_OPB(a2) # a2 <- B 6604 GET_OPA4(rOBJ) # rOBJ <- A+ 6605 GET_VREG(a0, a2) # a0 <- vB 6606 .if 0 6607 # cmp a1, 0; is second operand zero? 6608 beqz a1, common_errDivideByZero 6609 .endif 6610 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6611 6612 # optional op 6613 subu a0, a1, a0 # a0 <- op, a0-a3 changed 6614 GET_INST_OPCODE(t0) # extract opcode from rINST 6615 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 6616 6617 6618/* ------------------------------ */ 6619 .balign 128 6620.L_op_mul_int_lit16: /* 0xd2 */ 6621/* File: mips/op_mul_int_lit16.S */ 6622/* File: mips/binopLit16.S */ 6623 /* 6624 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6625 * that specifies an instruction that performs "result = a0 op a1". 6626 * This could be an MIPS instruction or a function call. (If the result 6627 * comes back in a register other than a0, you can override "result".) 6628 * 6629 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6630 * vCC (a1). Useful for integer division and modulus. 6631 * 6632 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6633 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6634 */ 6635 /* binop/lit16 vA, vB, +CCCC */ 6636 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6637 GET_OPB(a2) # a2 <- B 6638 GET_OPA4(rOBJ) # rOBJ <- A+ 6639 GET_VREG(a0, a2) # a0 <- vB 6640 .if 0 6641 # cmp a1, 0; is second operand zero? 6642 beqz a1, common_errDivideByZero 6643 .endif 6644 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6645 6646 # optional op 6647 mul a0, a0, a1 # a0 <- op, a0-a3 changed 6648 GET_INST_OPCODE(t0) # extract opcode from rINST 6649 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 6650 6651 6652/* ------------------------------ */ 6653 .balign 128 6654.L_op_div_int_lit16: /* 0xd3 */ 6655/* File: mips/op_div_int_lit16.S */ 6656#ifdef MIPS32REVGE6 6657/* File: mips/binopLit16.S */ 6658 /* 6659 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6660 * that specifies an instruction that performs "result = a0 op a1". 6661 * This could be an MIPS instruction or a function call. (If the result 6662 * comes back in a register other than a0, you can override "result".) 6663 * 6664 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6665 * vCC (a1). Useful for integer division and modulus. 6666 * 6667 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6668 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6669 */ 6670 /* binop/lit16 vA, vB, +CCCC */ 6671 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6672 GET_OPB(a2) # a2 <- B 6673 GET_OPA4(rOBJ) # rOBJ <- A+ 6674 GET_VREG(a0, a2) # a0 <- vB 6675 .if 1 6676 # cmp a1, 0; is second operand zero? 6677 beqz a1, common_errDivideByZero 6678 .endif 6679 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6680 6681 # optional op 6682 div a0, a0, a1 # a0 <- op, a0-a3 changed 6683 GET_INST_OPCODE(t0) # extract opcode from rINST 6684 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 6685 6686#else 6687/* File: mips/binopLit16.S */ 6688 /* 6689 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6690 * that specifies an instruction that performs "result = a0 op a1". 6691 * This could be an MIPS instruction or a function call. (If the result 6692 * comes back in a register other than a0, you can override "result".) 6693 * 6694 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6695 * vCC (a1). Useful for integer division and modulus. 6696 * 6697 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6698 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6699 */ 6700 /* binop/lit16 vA, vB, +CCCC */ 6701 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6702 GET_OPB(a2) # a2 <- B 6703 GET_OPA4(rOBJ) # rOBJ <- A+ 6704 GET_VREG(a0, a2) # a0 <- vB 6705 .if 1 6706 # cmp a1, 0; is second operand zero? 6707 beqz a1, common_errDivideByZero 6708 .endif 6709 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6710 6711 div zero, a0, a1 # optional op 6712 mflo a0 # a0 <- op, a0-a3 changed 6713 GET_INST_OPCODE(t0) # extract opcode from rINST 6714 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 6715 6716#endif 6717 6718/* ------------------------------ */ 6719 .balign 128 6720.L_op_rem_int_lit16: /* 0xd4 */ 6721/* File: mips/op_rem_int_lit16.S */ 6722#ifdef MIPS32REVGE6 6723/* File: mips/binopLit16.S */ 6724 /* 6725 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6726 * that specifies an instruction that performs "result = a0 op a1". 6727 * This could be an MIPS instruction or a function call. (If the result 6728 * comes back in a register other than a0, you can override "result".) 6729 * 6730 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6731 * vCC (a1). Useful for integer division and modulus. 6732 * 6733 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6734 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6735 */ 6736 /* binop/lit16 vA, vB, +CCCC */ 6737 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6738 GET_OPB(a2) # a2 <- B 6739 GET_OPA4(rOBJ) # rOBJ <- A+ 6740 GET_VREG(a0, a2) # a0 <- vB 6741 .if 1 6742 # cmp a1, 0; is second operand zero? 6743 beqz a1, common_errDivideByZero 6744 .endif 6745 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6746 6747 # optional op 6748 mod a0, a0, a1 # a0 <- op, a0-a3 changed 6749 GET_INST_OPCODE(t0) # extract opcode from rINST 6750 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 6751 6752#else 6753/* File: mips/binopLit16.S */ 6754 /* 6755 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6756 * that specifies an instruction that performs "result = a0 op a1". 6757 * This could be an MIPS instruction or a function call. (If the result 6758 * comes back in a register other than a0, you can override "result".) 6759 * 6760 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6761 * vCC (a1). Useful for integer division and modulus. 6762 * 6763 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6764 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6765 */ 6766 /* binop/lit16 vA, vB, +CCCC */ 6767 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6768 GET_OPB(a2) # a2 <- B 6769 GET_OPA4(rOBJ) # rOBJ <- A+ 6770 GET_VREG(a0, a2) # a0 <- vB 6771 .if 1 6772 # cmp a1, 0; is second operand zero? 6773 beqz a1, common_errDivideByZero 6774 .endif 6775 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6776 6777 div zero, a0, a1 # optional op 6778 mfhi a0 # a0 <- op, a0-a3 changed 6779 GET_INST_OPCODE(t0) # extract opcode from rINST 6780 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 6781 6782#endif 6783 6784/* ------------------------------ */ 6785 .balign 128 6786.L_op_and_int_lit16: /* 0xd5 */ 6787/* File: mips/op_and_int_lit16.S */ 6788/* File: mips/binopLit16.S */ 6789 /* 6790 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6791 * that specifies an instruction that performs "result = a0 op a1". 6792 * This could be an MIPS instruction or a function call. (If the result 6793 * comes back in a register other than a0, you can override "result".) 6794 * 6795 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6796 * vCC (a1). Useful for integer division and modulus. 6797 * 6798 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6799 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6800 */ 6801 /* binop/lit16 vA, vB, +CCCC */ 6802 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6803 GET_OPB(a2) # a2 <- B 6804 GET_OPA4(rOBJ) # rOBJ <- A+ 6805 GET_VREG(a0, a2) # a0 <- vB 6806 .if 0 6807 # cmp a1, 0; is second operand zero? 6808 beqz a1, common_errDivideByZero 6809 .endif 6810 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6811 6812 # optional op 6813 and a0, a0, a1 # a0 <- op, a0-a3 changed 6814 GET_INST_OPCODE(t0) # extract opcode from rINST 6815 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 6816 6817 6818/* ------------------------------ */ 6819 .balign 128 6820.L_op_or_int_lit16: /* 0xd6 */ 6821/* File: mips/op_or_int_lit16.S */ 6822/* File: mips/binopLit16.S */ 6823 /* 6824 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6825 * that specifies an instruction that performs "result = a0 op a1". 6826 * This could be an MIPS instruction or a function call. (If the result 6827 * comes back in a register other than a0, you can override "result".) 6828 * 6829 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6830 * vCC (a1). Useful for integer division and modulus. 6831 * 6832 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6833 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6834 */ 6835 /* binop/lit16 vA, vB, +CCCC */ 6836 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6837 GET_OPB(a2) # a2 <- B 6838 GET_OPA4(rOBJ) # rOBJ <- A+ 6839 GET_VREG(a0, a2) # a0 <- vB 6840 .if 0 6841 # cmp a1, 0; is second operand zero? 6842 beqz a1, common_errDivideByZero 6843 .endif 6844 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6845 6846 # optional op 6847 or a0, a0, a1 # a0 <- op, a0-a3 changed 6848 GET_INST_OPCODE(t0) # extract opcode from rINST 6849 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 6850 6851 6852/* ------------------------------ */ 6853 .balign 128 6854.L_op_xor_int_lit16: /* 0xd7 */ 6855/* File: mips/op_xor_int_lit16.S */ 6856/* File: mips/binopLit16.S */ 6857 /* 6858 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6859 * that specifies an instruction that performs "result = a0 op a1". 6860 * This could be an MIPS instruction or a function call. (If the result 6861 * comes back in a register other than a0, you can override "result".) 6862 * 6863 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6864 * vCC (a1). Useful for integer division and modulus. 6865 * 6866 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6867 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6868 */ 6869 /* binop/lit16 vA, vB, +CCCC */ 6870 FETCH_S(a1, 1) # a1 <- ssssCCCC (sign-extended) 6871 GET_OPB(a2) # a2 <- B 6872 GET_OPA4(rOBJ) # rOBJ <- A+ 6873 GET_VREG(a0, a2) # a0 <- vB 6874 .if 0 6875 # cmp a1, 0; is second operand zero? 6876 beqz a1, common_errDivideByZero 6877 .endif 6878 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6879 6880 # optional op 6881 xor a0, a0, a1 # a0 <- op, a0-a3 changed 6882 GET_INST_OPCODE(t0) # extract opcode from rINST 6883 SET_VREG_GOTO(a0, rOBJ, t0) # vA <- a0 6884 6885 6886/* ------------------------------ */ 6887 .balign 128 6888.L_op_add_int_lit8: /* 0xd8 */ 6889/* File: mips/op_add_int_lit8.S */ 6890/* File: mips/binopLit8.S */ 6891 /* 6892 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6893 * that specifies an instruction that performs "result = a0 op a1". 6894 * This could be an MIPS instruction or a function call. (If the result 6895 * comes back in a register other than a0, you can override "result".) 6896 * 6897 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6898 * vCC (a1). Useful for integer division and modulus. 6899 * 6900 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6901 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6902 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6903 */ 6904 /* binop/lit8 vAA, vBB, +CC */ 6905 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 6906 GET_OPA(rOBJ) # rOBJ <- AA 6907 and a2, a3, 255 # a2 <- BB 6908 GET_VREG(a0, a2) # a0 <- vBB 6909 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 6910 .if 0 6911 # is second operand zero? 6912 beqz a1, common_errDivideByZero 6913 .endif 6914 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6915 6916 # optional op 6917 addu a0, a0, a1 # a0 <- op, a0-a3 changed 6918 GET_INST_OPCODE(t0) # extract opcode from rINST 6919 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6920 6921 6922/* ------------------------------ */ 6923 .balign 128 6924.L_op_rsub_int_lit8: /* 0xd9 */ 6925/* File: mips/op_rsub_int_lit8.S */ 6926/* File: mips/binopLit8.S */ 6927 /* 6928 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6929 * that specifies an instruction that performs "result = a0 op a1". 6930 * This could be an MIPS instruction or a function call. (If the result 6931 * comes back in a register other than a0, you can override "result".) 6932 * 6933 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6934 * vCC (a1). Useful for integer division and modulus. 6935 * 6936 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6937 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6938 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6939 */ 6940 /* binop/lit8 vAA, vBB, +CC */ 6941 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 6942 GET_OPA(rOBJ) # rOBJ <- AA 6943 and a2, a3, 255 # a2 <- BB 6944 GET_VREG(a0, a2) # a0 <- vBB 6945 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 6946 .if 0 6947 # is second operand zero? 6948 beqz a1, common_errDivideByZero 6949 .endif 6950 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6951 6952 # optional op 6953 subu a0, a1, a0 # a0 <- op, a0-a3 changed 6954 GET_INST_OPCODE(t0) # extract opcode from rINST 6955 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6956 6957 6958/* ------------------------------ */ 6959 .balign 128 6960.L_op_mul_int_lit8: /* 0xda */ 6961/* File: mips/op_mul_int_lit8.S */ 6962/* File: mips/binopLit8.S */ 6963 /* 6964 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6965 * that specifies an instruction that performs "result = a0 op a1". 6966 * This could be an MIPS instruction or a function call. (If the result 6967 * comes back in a register other than a0, you can override "result".) 6968 * 6969 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6970 * vCC (a1). Useful for integer division and modulus. 6971 * 6972 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6973 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6974 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6975 */ 6976 /* binop/lit8 vAA, vBB, +CC */ 6977 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 6978 GET_OPA(rOBJ) # rOBJ <- AA 6979 and a2, a3, 255 # a2 <- BB 6980 GET_VREG(a0, a2) # a0 <- vBB 6981 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 6982 .if 0 6983 # is second operand zero? 6984 beqz a1, common_errDivideByZero 6985 .endif 6986 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 6987 6988 # optional op 6989 mul a0, a0, a1 # a0 <- op, a0-a3 changed 6990 GET_INST_OPCODE(t0) # extract opcode from rINST 6991 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 6992 6993 6994/* ------------------------------ */ 6995 .balign 128 6996.L_op_div_int_lit8: /* 0xdb */ 6997/* File: mips/op_div_int_lit8.S */ 6998#ifdef MIPS32REVGE6 6999/* File: mips/binopLit8.S */ 7000 /* 7001 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7002 * that specifies an instruction that performs "result = a0 op a1". 7003 * This could be an MIPS instruction or a function call. (If the result 7004 * comes back in a register other than a0, you can override "result".) 7005 * 7006 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7007 * vCC (a1). Useful for integer division and modulus. 7008 * 7009 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7010 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7011 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7012 */ 7013 /* binop/lit8 vAA, vBB, +CC */ 7014 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7015 GET_OPA(rOBJ) # rOBJ <- AA 7016 and a2, a3, 255 # a2 <- BB 7017 GET_VREG(a0, a2) # a0 <- vBB 7018 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7019 .if 1 7020 # is second operand zero? 7021 beqz a1, common_errDivideByZero 7022 .endif 7023 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7024 7025 # optional op 7026 div a0, a0, a1 # a0 <- op, a0-a3 changed 7027 GET_INST_OPCODE(t0) # extract opcode from rINST 7028 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7029 7030#else 7031/* File: mips/binopLit8.S */ 7032 /* 7033 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7034 * that specifies an instruction that performs "result = a0 op a1". 7035 * This could be an MIPS instruction or a function call. (If the result 7036 * comes back in a register other than a0, you can override "result".) 7037 * 7038 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7039 * vCC (a1). Useful for integer division and modulus. 7040 * 7041 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7042 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7043 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7044 */ 7045 /* binop/lit8 vAA, vBB, +CC */ 7046 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7047 GET_OPA(rOBJ) # rOBJ <- AA 7048 and a2, a3, 255 # a2 <- BB 7049 GET_VREG(a0, a2) # a0 <- vBB 7050 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7051 .if 1 7052 # is second operand zero? 7053 beqz a1, common_errDivideByZero 7054 .endif 7055 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7056 7057 div zero, a0, a1 # optional op 7058 mflo a0 # a0 <- op, a0-a3 changed 7059 GET_INST_OPCODE(t0) # extract opcode from rINST 7060 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7061 7062#endif 7063 7064/* ------------------------------ */ 7065 .balign 128 7066.L_op_rem_int_lit8: /* 0xdc */ 7067/* File: mips/op_rem_int_lit8.S */ 7068#ifdef MIPS32REVGE6 7069/* File: mips/binopLit8.S */ 7070 /* 7071 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7072 * that specifies an instruction that performs "result = a0 op a1". 7073 * This could be an MIPS instruction or a function call. (If the result 7074 * comes back in a register other than a0, you can override "result".) 7075 * 7076 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7077 * vCC (a1). Useful for integer division and modulus. 7078 * 7079 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7080 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7081 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7082 */ 7083 /* binop/lit8 vAA, vBB, +CC */ 7084 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7085 GET_OPA(rOBJ) # rOBJ <- AA 7086 and a2, a3, 255 # a2 <- BB 7087 GET_VREG(a0, a2) # a0 <- vBB 7088 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7089 .if 1 7090 # is second operand zero? 7091 beqz a1, common_errDivideByZero 7092 .endif 7093 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7094 7095 # optional op 7096 mod a0, a0, a1 # a0 <- op, a0-a3 changed 7097 GET_INST_OPCODE(t0) # extract opcode from rINST 7098 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7099 7100#else 7101/* File: mips/binopLit8.S */ 7102 /* 7103 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7104 * that specifies an instruction that performs "result = a0 op a1". 7105 * This could be an MIPS instruction or a function call. (If the result 7106 * comes back in a register other than a0, you can override "result".) 7107 * 7108 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7109 * vCC (a1). Useful for integer division and modulus. 7110 * 7111 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7112 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7113 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7114 */ 7115 /* binop/lit8 vAA, vBB, +CC */ 7116 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7117 GET_OPA(rOBJ) # rOBJ <- AA 7118 and a2, a3, 255 # a2 <- BB 7119 GET_VREG(a0, a2) # a0 <- vBB 7120 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7121 .if 1 7122 # is second operand zero? 7123 beqz a1, common_errDivideByZero 7124 .endif 7125 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7126 7127 div zero, a0, a1 # optional op 7128 mfhi a0 # a0 <- op, a0-a3 changed 7129 GET_INST_OPCODE(t0) # extract opcode from rINST 7130 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7131 7132#endif 7133 7134/* ------------------------------ */ 7135 .balign 128 7136.L_op_and_int_lit8: /* 0xdd */ 7137/* File: mips/op_and_int_lit8.S */ 7138/* File: mips/binopLit8.S */ 7139 /* 7140 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7141 * that specifies an instruction that performs "result = a0 op a1". 7142 * This could be an MIPS instruction or a function call. (If the result 7143 * comes back in a register other than a0, you can override "result".) 7144 * 7145 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7146 * vCC (a1). Useful for integer division and modulus. 7147 * 7148 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7149 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7150 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7151 */ 7152 /* binop/lit8 vAA, vBB, +CC */ 7153 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7154 GET_OPA(rOBJ) # rOBJ <- AA 7155 and a2, a3, 255 # a2 <- BB 7156 GET_VREG(a0, a2) # a0 <- vBB 7157 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7158 .if 0 7159 # is second operand zero? 7160 beqz a1, common_errDivideByZero 7161 .endif 7162 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7163 7164 # optional op 7165 and a0, a0, a1 # a0 <- op, a0-a3 changed 7166 GET_INST_OPCODE(t0) # extract opcode from rINST 7167 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7168 7169 7170/* ------------------------------ */ 7171 .balign 128 7172.L_op_or_int_lit8: /* 0xde */ 7173/* File: mips/op_or_int_lit8.S */ 7174/* File: mips/binopLit8.S */ 7175 /* 7176 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7177 * that specifies an instruction that performs "result = a0 op a1". 7178 * This could be an MIPS instruction or a function call. (If the result 7179 * comes back in a register other than a0, you can override "result".) 7180 * 7181 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7182 * vCC (a1). Useful for integer division and modulus. 7183 * 7184 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7185 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7186 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7187 */ 7188 /* binop/lit8 vAA, vBB, +CC */ 7189 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7190 GET_OPA(rOBJ) # rOBJ <- AA 7191 and a2, a3, 255 # a2 <- BB 7192 GET_VREG(a0, a2) # a0 <- vBB 7193 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7194 .if 0 7195 # is second operand zero? 7196 beqz a1, common_errDivideByZero 7197 .endif 7198 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7199 7200 # optional op 7201 or a0, a0, a1 # a0 <- op, a0-a3 changed 7202 GET_INST_OPCODE(t0) # extract opcode from rINST 7203 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7204 7205 7206/* ------------------------------ */ 7207 .balign 128 7208.L_op_xor_int_lit8: /* 0xdf */ 7209/* File: mips/op_xor_int_lit8.S */ 7210/* File: mips/binopLit8.S */ 7211 /* 7212 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7213 * that specifies an instruction that performs "result = a0 op a1". 7214 * This could be an MIPS instruction or a function call. (If the result 7215 * comes back in a register other than a0, you can override "result".) 7216 * 7217 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7218 * vCC (a1). Useful for integer division and modulus. 7219 * 7220 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7221 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7222 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7223 */ 7224 /* binop/lit8 vAA, vBB, +CC */ 7225 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7226 GET_OPA(rOBJ) # rOBJ <- AA 7227 and a2, a3, 255 # a2 <- BB 7228 GET_VREG(a0, a2) # a0 <- vBB 7229 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7230 .if 0 7231 # is second operand zero? 7232 beqz a1, common_errDivideByZero 7233 .endif 7234 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7235 7236 # optional op 7237 xor a0, a0, a1 # a0 <- op, a0-a3 changed 7238 GET_INST_OPCODE(t0) # extract opcode from rINST 7239 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7240 7241 7242/* ------------------------------ */ 7243 .balign 128 7244.L_op_shl_int_lit8: /* 0xe0 */ 7245/* File: mips/op_shl_int_lit8.S */ 7246/* File: mips/binopLit8.S */ 7247 /* 7248 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7249 * that specifies an instruction that performs "result = a0 op a1". 7250 * This could be an MIPS instruction or a function call. (If the result 7251 * comes back in a register other than a0, you can override "result".) 7252 * 7253 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7254 * vCC (a1). Useful for integer division and modulus. 7255 * 7256 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7257 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7258 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7259 */ 7260 /* binop/lit8 vAA, vBB, +CC */ 7261 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7262 GET_OPA(rOBJ) # rOBJ <- AA 7263 and a2, a3, 255 # a2 <- BB 7264 GET_VREG(a0, a2) # a0 <- vBB 7265 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7266 .if 0 7267 # is second operand zero? 7268 beqz a1, common_errDivideByZero 7269 .endif 7270 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7271 7272 # optional op 7273 sll a0, a0, a1 # a0 <- op, a0-a3 changed 7274 GET_INST_OPCODE(t0) # extract opcode from rINST 7275 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7276 7277 7278/* ------------------------------ */ 7279 .balign 128 7280.L_op_shr_int_lit8: /* 0xe1 */ 7281/* File: mips/op_shr_int_lit8.S */ 7282/* File: mips/binopLit8.S */ 7283 /* 7284 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7285 * that specifies an instruction that performs "result = a0 op a1". 7286 * This could be an MIPS instruction or a function call. (If the result 7287 * comes back in a register other than a0, you can override "result".) 7288 * 7289 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7290 * vCC (a1). Useful for integer division and modulus. 7291 * 7292 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7293 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7294 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7295 */ 7296 /* binop/lit8 vAA, vBB, +CC */ 7297 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7298 GET_OPA(rOBJ) # rOBJ <- AA 7299 and a2, a3, 255 # a2 <- BB 7300 GET_VREG(a0, a2) # a0 <- vBB 7301 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7302 .if 0 7303 # is second operand zero? 7304 beqz a1, common_errDivideByZero 7305 .endif 7306 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7307 7308 # optional op 7309 sra a0, a0, a1 # a0 <- op, a0-a3 changed 7310 GET_INST_OPCODE(t0) # extract opcode from rINST 7311 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7312 7313 7314/* ------------------------------ */ 7315 .balign 128 7316.L_op_ushr_int_lit8: /* 0xe2 */ 7317/* File: mips/op_ushr_int_lit8.S */ 7318/* File: mips/binopLit8.S */ 7319 /* 7320 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 7321 * that specifies an instruction that performs "result = a0 op a1". 7322 * This could be an MIPS instruction or a function call. (If the result 7323 * comes back in a register other than a0, you can override "result".) 7324 * 7325 * If "chkzero" is set to 1, we perform a divide-by-zero check on 7326 * vCC (a1). Useful for integer division and modulus. 7327 * 7328 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 7329 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 7330 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 7331 */ 7332 /* binop/lit8 vAA, vBB, +CC */ 7333 FETCH_S(a3, 1) # a3 <- ssssCCBB (sign-extended for CC) 7334 GET_OPA(rOBJ) # rOBJ <- AA 7335 and a2, a3, 255 # a2 <- BB 7336 GET_VREG(a0, a2) # a0 <- vBB 7337 sra a1, a3, 8 # a1 <- ssssssCC (sign extended) 7338 .if 0 7339 # is second operand zero? 7340 beqz a1, common_errDivideByZero 7341 .endif 7342 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7343 7344 # optional op 7345 srl a0, a0, a1 # a0 <- op, a0-a3 changed 7346 GET_INST_OPCODE(t0) # extract opcode from rINST 7347 SET_VREG_GOTO(a0, rOBJ, t0) # vAA <- a0 7348 7349 7350/* ------------------------------ */ 7351 .balign 128 7352.L_op_iget_quick: /* 0xe3 */ 7353/* File: mips/op_iget_quick.S */ 7354 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7355 /* op vA, vB, offset@CCCC */ 7356 GET_OPB(a2) # a2 <- B 7357 GET_VREG(a3, a2) # a3 <- object we're operating on 7358 FETCH(a1, 1) # a1 <- field byte offset 7359 GET_OPA4(a2) # a2 <- A(+) 7360 # check object for null 7361 beqz a3, common_errNullObject # object was null 7362 addu t0, a3, a1 7363 lw a0, 0(t0) # a0 <- obj.field (8/16/32 bits) 7364 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7365 GET_INST_OPCODE(t0) # extract opcode from rINST 7366 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 7367 7368/* ------------------------------ */ 7369 .balign 128 7370.L_op_iget_wide_quick: /* 0xe4 */ 7371/* File: mips/op_iget_wide_quick.S */ 7372 /* iget-wide-quick vA, vB, offset@CCCC */ 7373 GET_OPB(a2) # a2 <- B 7374 GET_VREG(a3, a2) # a3 <- object we're operating on 7375 FETCH(a1, 1) # a1 <- field byte offset 7376 GET_OPA4(a2) # a2 <- A(+) 7377 # check object for null 7378 beqz a3, common_errNullObject # object was null 7379 addu t0, a3, a1 # t0 <- a3 + a1 7380 LOAD64(a0, a1, t0) # a0 <- obj.field (64 bits, aligned) 7381 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7382 GET_INST_OPCODE(t0) # extract opcode from rINST 7383 SET_VREG64_GOTO(a0, a1, a2, t0) # fp[A] <- a0/a1 7384 7385/* ------------------------------ */ 7386 .balign 128 7387.L_op_iget_object_quick: /* 0xe5 */ 7388/* File: mips/op_iget_object_quick.S */ 7389 /* For: iget-object-quick */ 7390 /* op vA, vB, offset@CCCC */ 7391 GET_OPB(a2) # a2 <- B 7392 FETCH(a1, 1) # a1 <- field byte offset 7393 EXPORT_PC() 7394 GET_VREG(a0, a2) # a0 <- object we're operating on 7395 JAL(artIGetObjectFromMterp) # v0 <- GetObj(obj, offset) 7396 lw a3, THREAD_EXCEPTION_OFFSET(rSELF) 7397 GET_OPA4(a2) # a2<- A+ 7398 PREFETCH_INST(2) # load rINST 7399 bnez a3, MterpPossibleException # bail out 7400 ADVANCE(2) # advance rPC 7401 GET_INST_OPCODE(t0) # extract opcode from rINST 7402 SET_VREG_OBJECT_GOTO(v0, a2, t0) # fp[A] <- v0 7403 7404/* ------------------------------ */ 7405 .balign 128 7406.L_op_iput_quick: /* 0xe6 */ 7407/* File: mips/op_iput_quick.S */ 7408 /* For: iput-quick, iput-object-quick */ 7409 /* op vA, vB, offset@CCCC */ 7410 GET_OPB(a2) # a2 <- B 7411 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 7412 FETCH(a1, 1) # a1 <- field byte offset 7413 GET_OPA4(a2) # a2 <- A(+) 7414 beqz a3, common_errNullObject # object was null 7415 GET_VREG(a0, a2) # a0 <- fp[A] 7416 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7417 addu t0, a3, a1 7418 GET_INST_OPCODE(t1) # extract opcode from rINST 7419 GET_OPCODE_TARGET(t1) 7420 sw a0, 0(t0) # obj.field (8/16/32 bits) <- a0 7421 JR(t1) # jump to next instruction 7422 7423/* ------------------------------ */ 7424 .balign 128 7425.L_op_iput_wide_quick: /* 0xe7 */ 7426/* File: mips/op_iput_wide_quick.S */ 7427 /* iput-wide-quick vA, vB, offset@CCCC */ 7428 GET_OPA4(a0) # a0 <- A(+) 7429 GET_OPB(a1) # a1 <- B 7430 GET_VREG(a2, a1) # a2 <- fp[B], the object pointer 7431 # check object for null 7432 beqz a2, common_errNullObject # object was null 7433 EAS2(a3, rFP, a0) # a3 <- &fp[A] 7434 LOAD64(a0, a1, a3) # a0/a1 <- fp[A] 7435 FETCH(a3, 1) # a3 <- field byte offset 7436 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7437 addu a2, a2, a3 # obj.field (64 bits, aligned) <- a0/a1 7438 GET_INST_OPCODE(t0) # extract opcode from rINST 7439 GET_OPCODE_TARGET(t0) 7440 STORE64(a0, a1, a2) # obj.field (64 bits, aligned) <- a0/a1 7441 JR(t0) # jump to next instruction 7442 7443/* ------------------------------ */ 7444 .balign 128 7445.L_op_iput_object_quick: /* 0xe8 */ 7446/* File: mips/op_iput_object_quick.S */ 7447 /* For: iput-object-quick */ 7448 /* op vA, vB, offset@CCCC */ 7449 EXPORT_PC() 7450 addu a0, rFP, OFF_FP_SHADOWFRAME 7451 move a1, rPC 7452 move a2, rINST 7453 JAL(MterpIputObjectQuick) 7454 beqz v0, MterpException 7455 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7456 GET_INST_OPCODE(t0) # extract opcode from rINST 7457 GOTO_OPCODE(t0) # jump to next instruction 7458 7459/* ------------------------------ */ 7460 .balign 128 7461.L_op_invoke_virtual_quick: /* 0xe9 */ 7462/* File: mips/op_invoke_virtual_quick.S */ 7463/* File: mips/invoke.S */ 7464 /* 7465 * Generic invoke handler wrapper. 7466 */ 7467 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7468 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7469 .extern MterpInvokeVirtualQuick 7470 EXPORT_PC() 7471 move a0, rSELF 7472 addu a1, rFP, OFF_FP_SHADOWFRAME 7473 move a2, rPC 7474 move a3, rINST 7475 JAL(MterpInvokeVirtualQuick) 7476 beqz v0, MterpException 7477 FETCH_ADVANCE_INST(3) 7478 JAL(MterpShouldSwitchInterpreters) 7479 bnez v0, MterpFallback 7480 GET_INST_OPCODE(t0) 7481 GOTO_OPCODE(t0) 7482 7483 7484/* ------------------------------ */ 7485 .balign 128 7486.L_op_invoke_virtual_range_quick: /* 0xea */ 7487/* File: mips/op_invoke_virtual_range_quick.S */ 7488/* File: mips/invoke.S */ 7489 /* 7490 * Generic invoke handler wrapper. 7491 */ 7492 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 7493 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 7494 .extern MterpInvokeVirtualQuickRange 7495 EXPORT_PC() 7496 move a0, rSELF 7497 addu a1, rFP, OFF_FP_SHADOWFRAME 7498 move a2, rPC 7499 move a3, rINST 7500 JAL(MterpInvokeVirtualQuickRange) 7501 beqz v0, MterpException 7502 FETCH_ADVANCE_INST(3) 7503 JAL(MterpShouldSwitchInterpreters) 7504 bnez v0, MterpFallback 7505 GET_INST_OPCODE(t0) 7506 GOTO_OPCODE(t0) 7507 7508 7509/* ------------------------------ */ 7510 .balign 128 7511.L_op_iput_boolean_quick: /* 0xeb */ 7512/* File: mips/op_iput_boolean_quick.S */ 7513/* File: mips/op_iput_quick.S */ 7514 /* For: iput-quick, iput-object-quick */ 7515 /* op vA, vB, offset@CCCC */ 7516 GET_OPB(a2) # a2 <- B 7517 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 7518 FETCH(a1, 1) # a1 <- field byte offset 7519 GET_OPA4(a2) # a2 <- A(+) 7520 beqz a3, common_errNullObject # object was null 7521 GET_VREG(a0, a2) # a0 <- fp[A] 7522 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7523 addu t0, a3, a1 7524 GET_INST_OPCODE(t1) # extract opcode from rINST 7525 GET_OPCODE_TARGET(t1) 7526 sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0 7527 JR(t1) # jump to next instruction 7528 7529 7530/* ------------------------------ */ 7531 .balign 128 7532.L_op_iput_byte_quick: /* 0xec */ 7533/* File: mips/op_iput_byte_quick.S */ 7534/* File: mips/op_iput_quick.S */ 7535 /* For: iput-quick, iput-object-quick */ 7536 /* op vA, vB, offset@CCCC */ 7537 GET_OPB(a2) # a2 <- B 7538 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 7539 FETCH(a1, 1) # a1 <- field byte offset 7540 GET_OPA4(a2) # a2 <- A(+) 7541 beqz a3, common_errNullObject # object was null 7542 GET_VREG(a0, a2) # a0 <- fp[A] 7543 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7544 addu t0, a3, a1 7545 GET_INST_OPCODE(t1) # extract opcode from rINST 7546 GET_OPCODE_TARGET(t1) 7547 sb a0, 0(t0) # obj.field (8/16/32 bits) <- a0 7548 JR(t1) # jump to next instruction 7549 7550 7551/* ------------------------------ */ 7552 .balign 128 7553.L_op_iput_char_quick: /* 0xed */ 7554/* File: mips/op_iput_char_quick.S */ 7555/* File: mips/op_iput_quick.S */ 7556 /* For: iput-quick, iput-object-quick */ 7557 /* op vA, vB, offset@CCCC */ 7558 GET_OPB(a2) # a2 <- B 7559 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 7560 FETCH(a1, 1) # a1 <- field byte offset 7561 GET_OPA4(a2) # a2 <- A(+) 7562 beqz a3, common_errNullObject # object was null 7563 GET_VREG(a0, a2) # a0 <- fp[A] 7564 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7565 addu t0, a3, a1 7566 GET_INST_OPCODE(t1) # extract opcode from rINST 7567 GET_OPCODE_TARGET(t1) 7568 sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0 7569 JR(t1) # jump to next instruction 7570 7571 7572/* ------------------------------ */ 7573 .balign 128 7574.L_op_iput_short_quick: /* 0xee */ 7575/* File: mips/op_iput_short_quick.S */ 7576/* File: mips/op_iput_quick.S */ 7577 /* For: iput-quick, iput-object-quick */ 7578 /* op vA, vB, offset@CCCC */ 7579 GET_OPB(a2) # a2 <- B 7580 GET_VREG(a3, a2) # a3 <- fp[B], the object pointer 7581 FETCH(a1, 1) # a1 <- field byte offset 7582 GET_OPA4(a2) # a2 <- A(+) 7583 beqz a3, common_errNullObject # object was null 7584 GET_VREG(a0, a2) # a0 <- fp[A] 7585 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7586 addu t0, a3, a1 7587 GET_INST_OPCODE(t1) # extract opcode from rINST 7588 GET_OPCODE_TARGET(t1) 7589 sh a0, 0(t0) # obj.field (8/16/32 bits) <- a0 7590 JR(t1) # jump to next instruction 7591 7592 7593/* ------------------------------ */ 7594 .balign 128 7595.L_op_iget_boolean_quick: /* 0xef */ 7596/* File: mips/op_iget_boolean_quick.S */ 7597/* File: mips/op_iget_quick.S */ 7598 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7599 /* op vA, vB, offset@CCCC */ 7600 GET_OPB(a2) # a2 <- B 7601 GET_VREG(a3, a2) # a3 <- object we're operating on 7602 FETCH(a1, 1) # a1 <- field byte offset 7603 GET_OPA4(a2) # a2 <- A(+) 7604 # check object for null 7605 beqz a3, common_errNullObject # object was null 7606 addu t0, a3, a1 7607 lbu a0, 0(t0) # a0 <- obj.field (8/16/32 bits) 7608 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7609 GET_INST_OPCODE(t0) # extract opcode from rINST 7610 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 7611 7612 7613/* ------------------------------ */ 7614 .balign 128 7615.L_op_iget_byte_quick: /* 0xf0 */ 7616/* File: mips/op_iget_byte_quick.S */ 7617/* File: mips/op_iget_quick.S */ 7618 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7619 /* op vA, vB, offset@CCCC */ 7620 GET_OPB(a2) # a2 <- B 7621 GET_VREG(a3, a2) # a3 <- object we're operating on 7622 FETCH(a1, 1) # a1 <- field byte offset 7623 GET_OPA4(a2) # a2 <- A(+) 7624 # check object for null 7625 beqz a3, common_errNullObject # object was null 7626 addu t0, a3, a1 7627 lb a0, 0(t0) # a0 <- obj.field (8/16/32 bits) 7628 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7629 GET_INST_OPCODE(t0) # extract opcode from rINST 7630 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 7631 7632 7633/* ------------------------------ */ 7634 .balign 128 7635.L_op_iget_char_quick: /* 0xf1 */ 7636/* File: mips/op_iget_char_quick.S */ 7637/* File: mips/op_iget_quick.S */ 7638 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7639 /* op vA, vB, offset@CCCC */ 7640 GET_OPB(a2) # a2 <- B 7641 GET_VREG(a3, a2) # a3 <- object we're operating on 7642 FETCH(a1, 1) # a1 <- field byte offset 7643 GET_OPA4(a2) # a2 <- A(+) 7644 # check object for null 7645 beqz a3, common_errNullObject # object was null 7646 addu t0, a3, a1 7647 lhu a0, 0(t0) # a0 <- obj.field (8/16/32 bits) 7648 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7649 GET_INST_OPCODE(t0) # extract opcode from rINST 7650 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 7651 7652 7653/* ------------------------------ */ 7654 .balign 128 7655.L_op_iget_short_quick: /* 0xf2 */ 7656/* File: mips/op_iget_short_quick.S */ 7657/* File: mips/op_iget_quick.S */ 7658 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 7659 /* op vA, vB, offset@CCCC */ 7660 GET_OPB(a2) # a2 <- B 7661 GET_VREG(a3, a2) # a3 <- object we're operating on 7662 FETCH(a1, 1) # a1 <- field byte offset 7663 GET_OPA4(a2) # a2 <- A(+) 7664 # check object for null 7665 beqz a3, common_errNullObject # object was null 7666 addu t0, a3, a1 7667 lh a0, 0(t0) # a0 <- obj.field (8/16/32 bits) 7668 FETCH_ADVANCE_INST(2) # advance rPC, load rINST 7669 GET_INST_OPCODE(t0) # extract opcode from rINST 7670 SET_VREG_GOTO(a0, a2, t0) # fp[A] <- a0 7671 7672 7673/* ------------------------------ */ 7674 .balign 128 7675.L_op_unused_f3: /* 0xf3 */ 7676/* File: mips/op_unused_f3.S */ 7677/* File: mips/unused.S */ 7678/* 7679 * Bail to reference interpreter to throw. 7680 */ 7681 b MterpFallback 7682 7683 7684/* ------------------------------ */ 7685 .balign 128 7686.L_op_unused_f4: /* 0xf4 */ 7687/* File: mips/op_unused_f4.S */ 7688/* File: mips/unused.S */ 7689/* 7690 * Bail to reference interpreter to throw. 7691 */ 7692 b MterpFallback 7693 7694 7695/* ------------------------------ */ 7696 .balign 128 7697.L_op_unused_f5: /* 0xf5 */ 7698/* File: mips/op_unused_f5.S */ 7699/* File: mips/unused.S */ 7700/* 7701 * Bail to reference interpreter to throw. 7702 */ 7703 b MterpFallback 7704 7705 7706/* ------------------------------ */ 7707 .balign 128 7708.L_op_unused_f6: /* 0xf6 */ 7709/* File: mips/op_unused_f6.S */ 7710/* File: mips/unused.S */ 7711/* 7712 * Bail to reference interpreter to throw. 7713 */ 7714 b MterpFallback 7715 7716 7717/* ------------------------------ */ 7718 .balign 128 7719.L_op_unused_f7: /* 0xf7 */ 7720/* File: mips/op_unused_f7.S */ 7721/* File: mips/unused.S */ 7722/* 7723 * Bail to reference interpreter to throw. 7724 */ 7725 b MterpFallback 7726 7727 7728/* ------------------------------ */ 7729 .balign 128 7730.L_op_unused_f8: /* 0xf8 */ 7731/* File: mips/op_unused_f8.S */ 7732/* File: mips/unused.S */ 7733/* 7734 * Bail to reference interpreter to throw. 7735 */ 7736 b MterpFallback 7737 7738 7739/* ------------------------------ */ 7740 .balign 128 7741.L_op_unused_f9: /* 0xf9 */ 7742/* File: mips/op_unused_f9.S */ 7743/* File: mips/unused.S */ 7744/* 7745 * Bail to reference interpreter to throw. 7746 */ 7747 b MterpFallback 7748 7749 7750/* ------------------------------ */ 7751 .balign 128 7752.L_op_invoke_polymorphic: /* 0xfa */ 7753/* Transfer stub to alternate interpreter */ 7754 b MterpFallback 7755 7756/* ------------------------------ */ 7757 .balign 128 7758.L_op_invoke_polymorphic_range: /* 0xfb */ 7759/* Transfer stub to alternate interpreter */ 7760 b MterpFallback 7761 7762/* ------------------------------ */ 7763 .balign 128 7764.L_op_invoke_custom: /* 0xfc */ 7765/* Transfer stub to alternate interpreter */ 7766 b MterpFallback 7767 7768/* ------------------------------ */ 7769 .balign 128 7770.L_op_invoke_custom_range: /* 0xfd */ 7771/* Transfer stub to alternate interpreter */ 7772 b MterpFallback 7773 7774/* ------------------------------ */ 7775 .balign 128 7776.L_op_unused_fe: /* 0xfe */ 7777/* File: mips/op_unused_fe.S */ 7778/* File: mips/unused.S */ 7779/* 7780 * Bail to reference interpreter to throw. 7781 */ 7782 b MterpFallback 7783 7784 7785/* ------------------------------ */ 7786 .balign 128 7787.L_op_unused_ff: /* 0xff */ 7788/* File: mips/op_unused_ff.S */ 7789/* File: mips/unused.S */ 7790/* 7791 * Bail to reference interpreter to throw. 7792 */ 7793 b MterpFallback 7794 7795 7796 .balign 128 7797 .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart 7798 .global artMterpAsmInstructionEnd 7799artMterpAsmInstructionEnd: 7800 7801/* 7802 * =========================================================================== 7803 * Sister implementations 7804 * =========================================================================== 7805 */ 7806 .global artMterpAsmSisterStart 7807 .type artMterpAsmSisterStart, %function 7808 .text 7809 .balign 4 7810artMterpAsmSisterStart: 7811 7812/* continuation for op_float_to_long */ 7813 7814#ifndef MIPS32REVGE6 7815.Lop_float_to_long_get_opcode: 7816 GET_INST_OPCODE(t1) # extract opcode from rINST 7817.Lop_float_to_long_set_vreg: 7818 SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 7819#endif 7820 7821/* continuation for op_double_to_long */ 7822 7823#ifndef MIPS32REVGE6 7824.Lop_double_to_long_get_opcode: 7825 GET_INST_OPCODE(t1) # extract opcode from rINST 7826.Lop_double_to_long_set_vreg: 7827 SET_VREG64_GOTO(rRESULT0, rRESULT1, rOBJ, t1) # vA/vA+1 <- v0/v1 7828#endif 7829 7830/* continuation for op_mul_long */ 7831 7832.Lop_mul_long_finish: 7833 GET_INST_OPCODE(t0) # extract opcode from rINST 7834 SET_VREG64_GOTO(v0, v1, a0, t0) # vAA/vAA+1 <- v0(low)/v1(high) 7835 7836/* continuation for op_shl_long */ 7837 7838.Lop_shl_long_finish: 7839 SET_VREG64_GOTO(zero, v0, t2, t0) # vAA/vAA+1 <- rlo/rhi 7840 7841/* continuation for op_shr_long */ 7842 7843.Lop_shr_long_finish: 7844 sra a3, a1, 31 # a3<- sign(ah) 7845 SET_VREG64_GOTO(v1, a3, t3, t0) # vAA/VAA+1 <- rlo/rhi 7846 7847/* continuation for op_ushr_long */ 7848 7849.Lop_ushr_long_finish: 7850 SET_VREG64_GOTO(v1, zero, rOBJ, t0) # vAA/vAA+1 <- rlo/rhi 7851 7852/* continuation for op_shl_long_2addr */ 7853 7854.Lop_shl_long_2addr_finish: 7855 SET_VREG64_GOTO(zero, v0, rOBJ, t0) # vA/vA+1 <- rlo/rhi 7856 7857/* continuation for op_shr_long_2addr */ 7858 7859.Lop_shr_long_2addr_finish: 7860 sra a3, a1, 31 # a3<- sign(ah) 7861 SET_VREG64_GOTO(v1, a3, t2, t0) # vA/vA+1 <- rlo/rhi 7862 7863/* continuation for op_ushr_long_2addr */ 7864 7865.Lop_ushr_long_2addr_finish: 7866 SET_VREG64_GOTO(v1, zero, t3, t0) # vA/vA+1 <- rlo/rhi 7867 7868 .size artMterpAsmSisterStart, .-artMterpAsmSisterStart 7869 .global artMterpAsmSisterEnd 7870artMterpAsmSisterEnd: 7871 7872 7873 .global artMterpAsmAltInstructionStart 7874 .type artMterpAsmAltInstructionStart, %function 7875 .text 7876 7877artMterpAsmAltInstructionStart = .L_ALT_op_nop 7878/* ------------------------------ */ 7879 .balign 128 7880.L_ALT_op_nop: /* 0x00 */ 7881/* File: mips/alt_stub.S */ 7882/* 7883 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7884 * any interesting requests and then jump to the real instruction 7885 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7886 */ 7887 .extern MterpCheckBefore 7888 la ra, artMterpAsmInstructionStart + (0 * 128) # Addr of primary handler 7889 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 7890 move a0, rSELF # arg0 7891 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 7892 move a2, rPC 7893 la t9, MterpCheckBefore 7894 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 7895 7896/* ------------------------------ */ 7897 .balign 128 7898.L_ALT_op_move: /* 0x01 */ 7899/* File: mips/alt_stub.S */ 7900/* 7901 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7902 * any interesting requests and then jump to the real instruction 7903 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7904 */ 7905 .extern MterpCheckBefore 7906 la ra, artMterpAsmInstructionStart + (1 * 128) # Addr of primary handler 7907 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 7908 move a0, rSELF # arg0 7909 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 7910 move a2, rPC 7911 la t9, MterpCheckBefore 7912 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 7913 7914/* ------------------------------ */ 7915 .balign 128 7916.L_ALT_op_move_from16: /* 0x02 */ 7917/* File: mips/alt_stub.S */ 7918/* 7919 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7920 * any interesting requests and then jump to the real instruction 7921 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7922 */ 7923 .extern MterpCheckBefore 7924 la ra, artMterpAsmInstructionStart + (2 * 128) # Addr of primary handler 7925 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 7926 move a0, rSELF # arg0 7927 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 7928 move a2, rPC 7929 la t9, MterpCheckBefore 7930 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 7931 7932/* ------------------------------ */ 7933 .balign 128 7934.L_ALT_op_move_16: /* 0x03 */ 7935/* File: mips/alt_stub.S */ 7936/* 7937 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7938 * any interesting requests and then jump to the real instruction 7939 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7940 */ 7941 .extern MterpCheckBefore 7942 la ra, artMterpAsmInstructionStart + (3 * 128) # Addr of primary handler 7943 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 7944 move a0, rSELF # arg0 7945 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 7946 move a2, rPC 7947 la t9, MterpCheckBefore 7948 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 7949 7950/* ------------------------------ */ 7951 .balign 128 7952.L_ALT_op_move_wide: /* 0x04 */ 7953/* File: mips/alt_stub.S */ 7954/* 7955 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7956 * any interesting requests and then jump to the real instruction 7957 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7958 */ 7959 .extern MterpCheckBefore 7960 la ra, artMterpAsmInstructionStart + (4 * 128) # Addr of primary handler 7961 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 7962 move a0, rSELF # arg0 7963 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 7964 move a2, rPC 7965 la t9, MterpCheckBefore 7966 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 7967 7968/* ------------------------------ */ 7969 .balign 128 7970.L_ALT_op_move_wide_from16: /* 0x05 */ 7971/* File: mips/alt_stub.S */ 7972/* 7973 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7974 * any interesting requests and then jump to the real instruction 7975 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7976 */ 7977 .extern MterpCheckBefore 7978 la ra, artMterpAsmInstructionStart + (5 * 128) # Addr of primary handler 7979 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 7980 move a0, rSELF # arg0 7981 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 7982 move a2, rPC 7983 la t9, MterpCheckBefore 7984 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 7985 7986/* ------------------------------ */ 7987 .balign 128 7988.L_ALT_op_move_wide_16: /* 0x06 */ 7989/* File: mips/alt_stub.S */ 7990/* 7991 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7992 * any interesting requests and then jump to the real instruction 7993 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7994 */ 7995 .extern MterpCheckBefore 7996 la ra, artMterpAsmInstructionStart + (6 * 128) # Addr of primary handler 7997 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 7998 move a0, rSELF # arg0 7999 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8000 move a2, rPC 8001 la t9, MterpCheckBefore 8002 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8003 8004/* ------------------------------ */ 8005 .balign 128 8006.L_ALT_op_move_object: /* 0x07 */ 8007/* File: mips/alt_stub.S */ 8008/* 8009 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8010 * any interesting requests and then jump to the real instruction 8011 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8012 */ 8013 .extern MterpCheckBefore 8014 la ra, artMterpAsmInstructionStart + (7 * 128) # Addr of primary handler 8015 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8016 move a0, rSELF # arg0 8017 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8018 move a2, rPC 8019 la t9, MterpCheckBefore 8020 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8021 8022/* ------------------------------ */ 8023 .balign 128 8024.L_ALT_op_move_object_from16: /* 0x08 */ 8025/* File: mips/alt_stub.S */ 8026/* 8027 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8028 * any interesting requests and then jump to the real instruction 8029 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8030 */ 8031 .extern MterpCheckBefore 8032 la ra, artMterpAsmInstructionStart + (8 * 128) # Addr of primary handler 8033 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8034 move a0, rSELF # arg0 8035 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8036 move a2, rPC 8037 la t9, MterpCheckBefore 8038 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8039 8040/* ------------------------------ */ 8041 .balign 128 8042.L_ALT_op_move_object_16: /* 0x09 */ 8043/* File: mips/alt_stub.S */ 8044/* 8045 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8046 * any interesting requests and then jump to the real instruction 8047 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8048 */ 8049 .extern MterpCheckBefore 8050 la ra, artMterpAsmInstructionStart + (9 * 128) # Addr of primary handler 8051 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8052 move a0, rSELF # arg0 8053 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8054 move a2, rPC 8055 la t9, MterpCheckBefore 8056 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8057 8058/* ------------------------------ */ 8059 .balign 128 8060.L_ALT_op_move_result: /* 0x0a */ 8061/* File: mips/alt_stub.S */ 8062/* 8063 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8064 * any interesting requests and then jump to the real instruction 8065 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8066 */ 8067 .extern MterpCheckBefore 8068 la ra, artMterpAsmInstructionStart + (10 * 128) # Addr of primary handler 8069 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8070 move a0, rSELF # arg0 8071 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8072 move a2, rPC 8073 la t9, MterpCheckBefore 8074 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8075 8076/* ------------------------------ */ 8077 .balign 128 8078.L_ALT_op_move_result_wide: /* 0x0b */ 8079/* File: mips/alt_stub.S */ 8080/* 8081 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8082 * any interesting requests and then jump to the real instruction 8083 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8084 */ 8085 .extern MterpCheckBefore 8086 la ra, artMterpAsmInstructionStart + (11 * 128) # Addr of primary handler 8087 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8088 move a0, rSELF # arg0 8089 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8090 move a2, rPC 8091 la t9, MterpCheckBefore 8092 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8093 8094/* ------------------------------ */ 8095 .balign 128 8096.L_ALT_op_move_result_object: /* 0x0c */ 8097/* File: mips/alt_stub.S */ 8098/* 8099 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8100 * any interesting requests and then jump to the real instruction 8101 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8102 */ 8103 .extern MterpCheckBefore 8104 la ra, artMterpAsmInstructionStart + (12 * 128) # Addr of primary handler 8105 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8106 move a0, rSELF # arg0 8107 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8108 move a2, rPC 8109 la t9, MterpCheckBefore 8110 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8111 8112/* ------------------------------ */ 8113 .balign 128 8114.L_ALT_op_move_exception: /* 0x0d */ 8115/* File: mips/alt_stub.S */ 8116/* 8117 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8118 * any interesting requests and then jump to the real instruction 8119 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8120 */ 8121 .extern MterpCheckBefore 8122 la ra, artMterpAsmInstructionStart + (13 * 128) # Addr of primary handler 8123 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8124 move a0, rSELF # arg0 8125 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8126 move a2, rPC 8127 la t9, MterpCheckBefore 8128 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8129 8130/* ------------------------------ */ 8131 .balign 128 8132.L_ALT_op_return_void: /* 0x0e */ 8133/* File: mips/alt_stub.S */ 8134/* 8135 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8136 * any interesting requests and then jump to the real instruction 8137 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8138 */ 8139 .extern MterpCheckBefore 8140 la ra, artMterpAsmInstructionStart + (14 * 128) # Addr of primary handler 8141 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8142 move a0, rSELF # arg0 8143 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8144 move a2, rPC 8145 la t9, MterpCheckBefore 8146 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8147 8148/* ------------------------------ */ 8149 .balign 128 8150.L_ALT_op_return: /* 0x0f */ 8151/* File: mips/alt_stub.S */ 8152/* 8153 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8154 * any interesting requests and then jump to the real instruction 8155 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8156 */ 8157 .extern MterpCheckBefore 8158 la ra, artMterpAsmInstructionStart + (15 * 128) # Addr of primary handler 8159 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8160 move a0, rSELF # arg0 8161 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8162 move a2, rPC 8163 la t9, MterpCheckBefore 8164 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8165 8166/* ------------------------------ */ 8167 .balign 128 8168.L_ALT_op_return_wide: /* 0x10 */ 8169/* File: mips/alt_stub.S */ 8170/* 8171 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8172 * any interesting requests and then jump to the real instruction 8173 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8174 */ 8175 .extern MterpCheckBefore 8176 la ra, artMterpAsmInstructionStart + (16 * 128) # Addr of primary handler 8177 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8178 move a0, rSELF # arg0 8179 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8180 move a2, rPC 8181 la t9, MterpCheckBefore 8182 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8183 8184/* ------------------------------ */ 8185 .balign 128 8186.L_ALT_op_return_object: /* 0x11 */ 8187/* File: mips/alt_stub.S */ 8188/* 8189 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8190 * any interesting requests and then jump to the real instruction 8191 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8192 */ 8193 .extern MterpCheckBefore 8194 la ra, artMterpAsmInstructionStart + (17 * 128) # Addr of primary handler 8195 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8196 move a0, rSELF # arg0 8197 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8198 move a2, rPC 8199 la t9, MterpCheckBefore 8200 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8201 8202/* ------------------------------ */ 8203 .balign 128 8204.L_ALT_op_const_4: /* 0x12 */ 8205/* File: mips/alt_stub.S */ 8206/* 8207 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8208 * any interesting requests and then jump to the real instruction 8209 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8210 */ 8211 .extern MterpCheckBefore 8212 la ra, artMterpAsmInstructionStart + (18 * 128) # Addr of primary handler 8213 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8214 move a0, rSELF # arg0 8215 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8216 move a2, rPC 8217 la t9, MterpCheckBefore 8218 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8219 8220/* ------------------------------ */ 8221 .balign 128 8222.L_ALT_op_const_16: /* 0x13 */ 8223/* File: mips/alt_stub.S */ 8224/* 8225 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8226 * any interesting requests and then jump to the real instruction 8227 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8228 */ 8229 .extern MterpCheckBefore 8230 la ra, artMterpAsmInstructionStart + (19 * 128) # Addr of primary handler 8231 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8232 move a0, rSELF # arg0 8233 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8234 move a2, rPC 8235 la t9, MterpCheckBefore 8236 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8237 8238/* ------------------------------ */ 8239 .balign 128 8240.L_ALT_op_const: /* 0x14 */ 8241/* File: mips/alt_stub.S */ 8242/* 8243 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8244 * any interesting requests and then jump to the real instruction 8245 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8246 */ 8247 .extern MterpCheckBefore 8248 la ra, artMterpAsmInstructionStart + (20 * 128) # Addr of primary handler 8249 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8250 move a0, rSELF # arg0 8251 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8252 move a2, rPC 8253 la t9, MterpCheckBefore 8254 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8255 8256/* ------------------------------ */ 8257 .balign 128 8258.L_ALT_op_const_high16: /* 0x15 */ 8259/* File: mips/alt_stub.S */ 8260/* 8261 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8262 * any interesting requests and then jump to the real instruction 8263 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8264 */ 8265 .extern MterpCheckBefore 8266 la ra, artMterpAsmInstructionStart + (21 * 128) # Addr of primary handler 8267 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8268 move a0, rSELF # arg0 8269 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8270 move a2, rPC 8271 la t9, MterpCheckBefore 8272 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8273 8274/* ------------------------------ */ 8275 .balign 128 8276.L_ALT_op_const_wide_16: /* 0x16 */ 8277/* File: mips/alt_stub.S */ 8278/* 8279 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8280 * any interesting requests and then jump to the real instruction 8281 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8282 */ 8283 .extern MterpCheckBefore 8284 la ra, artMterpAsmInstructionStart + (22 * 128) # Addr of primary handler 8285 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8286 move a0, rSELF # arg0 8287 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8288 move a2, rPC 8289 la t9, MterpCheckBefore 8290 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8291 8292/* ------------------------------ */ 8293 .balign 128 8294.L_ALT_op_const_wide_32: /* 0x17 */ 8295/* File: mips/alt_stub.S */ 8296/* 8297 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8298 * any interesting requests and then jump to the real instruction 8299 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8300 */ 8301 .extern MterpCheckBefore 8302 la ra, artMterpAsmInstructionStart + (23 * 128) # Addr of primary handler 8303 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8304 move a0, rSELF # arg0 8305 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8306 move a2, rPC 8307 la t9, MterpCheckBefore 8308 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8309 8310/* ------------------------------ */ 8311 .balign 128 8312.L_ALT_op_const_wide: /* 0x18 */ 8313/* File: mips/alt_stub.S */ 8314/* 8315 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8316 * any interesting requests and then jump to the real instruction 8317 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8318 */ 8319 .extern MterpCheckBefore 8320 la ra, artMterpAsmInstructionStart + (24 * 128) # Addr of primary handler 8321 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8322 move a0, rSELF # arg0 8323 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8324 move a2, rPC 8325 la t9, MterpCheckBefore 8326 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8327 8328/* ------------------------------ */ 8329 .balign 128 8330.L_ALT_op_const_wide_high16: /* 0x19 */ 8331/* File: mips/alt_stub.S */ 8332/* 8333 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8334 * any interesting requests and then jump to the real instruction 8335 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8336 */ 8337 .extern MterpCheckBefore 8338 la ra, artMterpAsmInstructionStart + (25 * 128) # Addr of primary handler 8339 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8340 move a0, rSELF # arg0 8341 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8342 move a2, rPC 8343 la t9, MterpCheckBefore 8344 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8345 8346/* ------------------------------ */ 8347 .balign 128 8348.L_ALT_op_const_string: /* 0x1a */ 8349/* File: mips/alt_stub.S */ 8350/* 8351 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8352 * any interesting requests and then jump to the real instruction 8353 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8354 */ 8355 .extern MterpCheckBefore 8356 la ra, artMterpAsmInstructionStart + (26 * 128) # Addr of primary handler 8357 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8358 move a0, rSELF # arg0 8359 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8360 move a2, rPC 8361 la t9, MterpCheckBefore 8362 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8363 8364/* ------------------------------ */ 8365 .balign 128 8366.L_ALT_op_const_string_jumbo: /* 0x1b */ 8367/* File: mips/alt_stub.S */ 8368/* 8369 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8370 * any interesting requests and then jump to the real instruction 8371 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8372 */ 8373 .extern MterpCheckBefore 8374 la ra, artMterpAsmInstructionStart + (27 * 128) # Addr of primary handler 8375 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8376 move a0, rSELF # arg0 8377 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8378 move a2, rPC 8379 la t9, MterpCheckBefore 8380 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8381 8382/* ------------------------------ */ 8383 .balign 128 8384.L_ALT_op_const_class: /* 0x1c */ 8385/* File: mips/alt_stub.S */ 8386/* 8387 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8388 * any interesting requests and then jump to the real instruction 8389 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8390 */ 8391 .extern MterpCheckBefore 8392 la ra, artMterpAsmInstructionStart + (28 * 128) # Addr of primary handler 8393 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8394 move a0, rSELF # arg0 8395 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8396 move a2, rPC 8397 la t9, MterpCheckBefore 8398 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8399 8400/* ------------------------------ */ 8401 .balign 128 8402.L_ALT_op_monitor_enter: /* 0x1d */ 8403/* File: mips/alt_stub.S */ 8404/* 8405 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8406 * any interesting requests and then jump to the real instruction 8407 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8408 */ 8409 .extern MterpCheckBefore 8410 la ra, artMterpAsmInstructionStart + (29 * 128) # Addr of primary handler 8411 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8412 move a0, rSELF # arg0 8413 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8414 move a2, rPC 8415 la t9, MterpCheckBefore 8416 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8417 8418/* ------------------------------ */ 8419 .balign 128 8420.L_ALT_op_monitor_exit: /* 0x1e */ 8421/* File: mips/alt_stub.S */ 8422/* 8423 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8424 * any interesting requests and then jump to the real instruction 8425 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8426 */ 8427 .extern MterpCheckBefore 8428 la ra, artMterpAsmInstructionStart + (30 * 128) # Addr of primary handler 8429 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8430 move a0, rSELF # arg0 8431 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8432 move a2, rPC 8433 la t9, MterpCheckBefore 8434 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8435 8436/* ------------------------------ */ 8437 .balign 128 8438.L_ALT_op_check_cast: /* 0x1f */ 8439/* File: mips/alt_stub.S */ 8440/* 8441 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8442 * any interesting requests and then jump to the real instruction 8443 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8444 */ 8445 .extern MterpCheckBefore 8446 la ra, artMterpAsmInstructionStart + (31 * 128) # Addr of primary handler 8447 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8448 move a0, rSELF # arg0 8449 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8450 move a2, rPC 8451 la t9, MterpCheckBefore 8452 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8453 8454/* ------------------------------ */ 8455 .balign 128 8456.L_ALT_op_instance_of: /* 0x20 */ 8457/* File: mips/alt_stub.S */ 8458/* 8459 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8460 * any interesting requests and then jump to the real instruction 8461 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8462 */ 8463 .extern MterpCheckBefore 8464 la ra, artMterpAsmInstructionStart + (32 * 128) # Addr of primary handler 8465 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8466 move a0, rSELF # arg0 8467 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8468 move a2, rPC 8469 la t9, MterpCheckBefore 8470 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8471 8472/* ------------------------------ */ 8473 .balign 128 8474.L_ALT_op_array_length: /* 0x21 */ 8475/* File: mips/alt_stub.S */ 8476/* 8477 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8478 * any interesting requests and then jump to the real instruction 8479 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8480 */ 8481 .extern MterpCheckBefore 8482 la ra, artMterpAsmInstructionStart + (33 * 128) # Addr of primary handler 8483 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8484 move a0, rSELF # arg0 8485 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8486 move a2, rPC 8487 la t9, MterpCheckBefore 8488 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8489 8490/* ------------------------------ */ 8491 .balign 128 8492.L_ALT_op_new_instance: /* 0x22 */ 8493/* File: mips/alt_stub.S */ 8494/* 8495 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8496 * any interesting requests and then jump to the real instruction 8497 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8498 */ 8499 .extern MterpCheckBefore 8500 la ra, artMterpAsmInstructionStart + (34 * 128) # Addr of primary handler 8501 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8502 move a0, rSELF # arg0 8503 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8504 move a2, rPC 8505 la t9, MterpCheckBefore 8506 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8507 8508/* ------------------------------ */ 8509 .balign 128 8510.L_ALT_op_new_array: /* 0x23 */ 8511/* File: mips/alt_stub.S */ 8512/* 8513 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8514 * any interesting requests and then jump to the real instruction 8515 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8516 */ 8517 .extern MterpCheckBefore 8518 la ra, artMterpAsmInstructionStart + (35 * 128) # Addr of primary handler 8519 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8520 move a0, rSELF # arg0 8521 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8522 move a2, rPC 8523 la t9, MterpCheckBefore 8524 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8525 8526/* ------------------------------ */ 8527 .balign 128 8528.L_ALT_op_filled_new_array: /* 0x24 */ 8529/* File: mips/alt_stub.S */ 8530/* 8531 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8532 * any interesting requests and then jump to the real instruction 8533 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8534 */ 8535 .extern MterpCheckBefore 8536 la ra, artMterpAsmInstructionStart + (36 * 128) # Addr of primary handler 8537 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8538 move a0, rSELF # arg0 8539 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8540 move a2, rPC 8541 la t9, MterpCheckBefore 8542 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8543 8544/* ------------------------------ */ 8545 .balign 128 8546.L_ALT_op_filled_new_array_range: /* 0x25 */ 8547/* File: mips/alt_stub.S */ 8548/* 8549 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8550 * any interesting requests and then jump to the real instruction 8551 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8552 */ 8553 .extern MterpCheckBefore 8554 la ra, artMterpAsmInstructionStart + (37 * 128) # Addr of primary handler 8555 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8556 move a0, rSELF # arg0 8557 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8558 move a2, rPC 8559 la t9, MterpCheckBefore 8560 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8561 8562/* ------------------------------ */ 8563 .balign 128 8564.L_ALT_op_fill_array_data: /* 0x26 */ 8565/* File: mips/alt_stub.S */ 8566/* 8567 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8568 * any interesting requests and then jump to the real instruction 8569 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8570 */ 8571 .extern MterpCheckBefore 8572 la ra, artMterpAsmInstructionStart + (38 * 128) # Addr of primary handler 8573 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8574 move a0, rSELF # arg0 8575 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8576 move a2, rPC 8577 la t9, MterpCheckBefore 8578 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8579 8580/* ------------------------------ */ 8581 .balign 128 8582.L_ALT_op_throw: /* 0x27 */ 8583/* File: mips/alt_stub.S */ 8584/* 8585 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8586 * any interesting requests and then jump to the real instruction 8587 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8588 */ 8589 .extern MterpCheckBefore 8590 la ra, artMterpAsmInstructionStart + (39 * 128) # Addr of primary handler 8591 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8592 move a0, rSELF # arg0 8593 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8594 move a2, rPC 8595 la t9, MterpCheckBefore 8596 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8597 8598/* ------------------------------ */ 8599 .balign 128 8600.L_ALT_op_goto: /* 0x28 */ 8601/* File: mips/alt_stub.S */ 8602/* 8603 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8604 * any interesting requests and then jump to the real instruction 8605 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8606 */ 8607 .extern MterpCheckBefore 8608 la ra, artMterpAsmInstructionStart + (40 * 128) # Addr of primary handler 8609 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8610 move a0, rSELF # arg0 8611 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8612 move a2, rPC 8613 la t9, MterpCheckBefore 8614 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8615 8616/* ------------------------------ */ 8617 .balign 128 8618.L_ALT_op_goto_16: /* 0x29 */ 8619/* File: mips/alt_stub.S */ 8620/* 8621 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8622 * any interesting requests and then jump to the real instruction 8623 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8624 */ 8625 .extern MterpCheckBefore 8626 la ra, artMterpAsmInstructionStart + (41 * 128) # Addr of primary handler 8627 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8628 move a0, rSELF # arg0 8629 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8630 move a2, rPC 8631 la t9, MterpCheckBefore 8632 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8633 8634/* ------------------------------ */ 8635 .balign 128 8636.L_ALT_op_goto_32: /* 0x2a */ 8637/* File: mips/alt_stub.S */ 8638/* 8639 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8640 * any interesting requests and then jump to the real instruction 8641 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8642 */ 8643 .extern MterpCheckBefore 8644 la ra, artMterpAsmInstructionStart + (42 * 128) # Addr of primary handler 8645 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8646 move a0, rSELF # arg0 8647 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8648 move a2, rPC 8649 la t9, MterpCheckBefore 8650 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8651 8652/* ------------------------------ */ 8653 .balign 128 8654.L_ALT_op_packed_switch: /* 0x2b */ 8655/* File: mips/alt_stub.S */ 8656/* 8657 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8658 * any interesting requests and then jump to the real instruction 8659 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8660 */ 8661 .extern MterpCheckBefore 8662 la ra, artMterpAsmInstructionStart + (43 * 128) # Addr of primary handler 8663 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8664 move a0, rSELF # arg0 8665 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8666 move a2, rPC 8667 la t9, MterpCheckBefore 8668 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8669 8670/* ------------------------------ */ 8671 .balign 128 8672.L_ALT_op_sparse_switch: /* 0x2c */ 8673/* File: mips/alt_stub.S */ 8674/* 8675 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8676 * any interesting requests and then jump to the real instruction 8677 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8678 */ 8679 .extern MterpCheckBefore 8680 la ra, artMterpAsmInstructionStart + (44 * 128) # Addr of primary handler 8681 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8682 move a0, rSELF # arg0 8683 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8684 move a2, rPC 8685 la t9, MterpCheckBefore 8686 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8687 8688/* ------------------------------ */ 8689 .balign 128 8690.L_ALT_op_cmpl_float: /* 0x2d */ 8691/* File: mips/alt_stub.S */ 8692/* 8693 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8694 * any interesting requests and then jump to the real instruction 8695 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8696 */ 8697 .extern MterpCheckBefore 8698 la ra, artMterpAsmInstructionStart + (45 * 128) # Addr of primary handler 8699 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8700 move a0, rSELF # arg0 8701 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8702 move a2, rPC 8703 la t9, MterpCheckBefore 8704 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8705 8706/* ------------------------------ */ 8707 .balign 128 8708.L_ALT_op_cmpg_float: /* 0x2e */ 8709/* File: mips/alt_stub.S */ 8710/* 8711 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8712 * any interesting requests and then jump to the real instruction 8713 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8714 */ 8715 .extern MterpCheckBefore 8716 la ra, artMterpAsmInstructionStart + (46 * 128) # Addr of primary handler 8717 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8718 move a0, rSELF # arg0 8719 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8720 move a2, rPC 8721 la t9, MterpCheckBefore 8722 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8723 8724/* ------------------------------ */ 8725 .balign 128 8726.L_ALT_op_cmpl_double: /* 0x2f */ 8727/* File: mips/alt_stub.S */ 8728/* 8729 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8730 * any interesting requests and then jump to the real instruction 8731 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8732 */ 8733 .extern MterpCheckBefore 8734 la ra, artMterpAsmInstructionStart + (47 * 128) # Addr of primary handler 8735 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8736 move a0, rSELF # arg0 8737 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8738 move a2, rPC 8739 la t9, MterpCheckBefore 8740 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8741 8742/* ------------------------------ */ 8743 .balign 128 8744.L_ALT_op_cmpg_double: /* 0x30 */ 8745/* File: mips/alt_stub.S */ 8746/* 8747 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8748 * any interesting requests and then jump to the real instruction 8749 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8750 */ 8751 .extern MterpCheckBefore 8752 la ra, artMterpAsmInstructionStart + (48 * 128) # Addr of primary handler 8753 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8754 move a0, rSELF # arg0 8755 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8756 move a2, rPC 8757 la t9, MterpCheckBefore 8758 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8759 8760/* ------------------------------ */ 8761 .balign 128 8762.L_ALT_op_cmp_long: /* 0x31 */ 8763/* File: mips/alt_stub.S */ 8764/* 8765 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8766 * any interesting requests and then jump to the real instruction 8767 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8768 */ 8769 .extern MterpCheckBefore 8770 la ra, artMterpAsmInstructionStart + (49 * 128) # Addr of primary handler 8771 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8772 move a0, rSELF # arg0 8773 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8774 move a2, rPC 8775 la t9, MterpCheckBefore 8776 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8777 8778/* ------------------------------ */ 8779 .balign 128 8780.L_ALT_op_if_eq: /* 0x32 */ 8781/* File: mips/alt_stub.S */ 8782/* 8783 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8784 * any interesting requests and then jump to the real instruction 8785 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8786 */ 8787 .extern MterpCheckBefore 8788 la ra, artMterpAsmInstructionStart + (50 * 128) # Addr of primary handler 8789 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8790 move a0, rSELF # arg0 8791 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8792 move a2, rPC 8793 la t9, MterpCheckBefore 8794 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8795 8796/* ------------------------------ */ 8797 .balign 128 8798.L_ALT_op_if_ne: /* 0x33 */ 8799/* File: mips/alt_stub.S */ 8800/* 8801 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8802 * any interesting requests and then jump to the real instruction 8803 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8804 */ 8805 .extern MterpCheckBefore 8806 la ra, artMterpAsmInstructionStart + (51 * 128) # Addr of primary handler 8807 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8808 move a0, rSELF # arg0 8809 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8810 move a2, rPC 8811 la t9, MterpCheckBefore 8812 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8813 8814/* ------------------------------ */ 8815 .balign 128 8816.L_ALT_op_if_lt: /* 0x34 */ 8817/* File: mips/alt_stub.S */ 8818/* 8819 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8820 * any interesting requests and then jump to the real instruction 8821 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8822 */ 8823 .extern MterpCheckBefore 8824 la ra, artMterpAsmInstructionStart + (52 * 128) # Addr of primary handler 8825 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8826 move a0, rSELF # arg0 8827 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8828 move a2, rPC 8829 la t9, MterpCheckBefore 8830 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8831 8832/* ------------------------------ */ 8833 .balign 128 8834.L_ALT_op_if_ge: /* 0x35 */ 8835/* File: mips/alt_stub.S */ 8836/* 8837 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8838 * any interesting requests and then jump to the real instruction 8839 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8840 */ 8841 .extern MterpCheckBefore 8842 la ra, artMterpAsmInstructionStart + (53 * 128) # Addr of primary handler 8843 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8844 move a0, rSELF # arg0 8845 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8846 move a2, rPC 8847 la t9, MterpCheckBefore 8848 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8849 8850/* ------------------------------ */ 8851 .balign 128 8852.L_ALT_op_if_gt: /* 0x36 */ 8853/* File: mips/alt_stub.S */ 8854/* 8855 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8856 * any interesting requests and then jump to the real instruction 8857 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8858 */ 8859 .extern MterpCheckBefore 8860 la ra, artMterpAsmInstructionStart + (54 * 128) # Addr of primary handler 8861 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8862 move a0, rSELF # arg0 8863 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8864 move a2, rPC 8865 la t9, MterpCheckBefore 8866 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8867 8868/* ------------------------------ */ 8869 .balign 128 8870.L_ALT_op_if_le: /* 0x37 */ 8871/* File: mips/alt_stub.S */ 8872/* 8873 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8874 * any interesting requests and then jump to the real instruction 8875 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8876 */ 8877 .extern MterpCheckBefore 8878 la ra, artMterpAsmInstructionStart + (55 * 128) # Addr of primary handler 8879 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8880 move a0, rSELF # arg0 8881 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8882 move a2, rPC 8883 la t9, MterpCheckBefore 8884 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8885 8886/* ------------------------------ */ 8887 .balign 128 8888.L_ALT_op_if_eqz: /* 0x38 */ 8889/* File: mips/alt_stub.S */ 8890/* 8891 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8892 * any interesting requests and then jump to the real instruction 8893 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8894 */ 8895 .extern MterpCheckBefore 8896 la ra, artMterpAsmInstructionStart + (56 * 128) # Addr of primary handler 8897 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8898 move a0, rSELF # arg0 8899 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8900 move a2, rPC 8901 la t9, MterpCheckBefore 8902 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8903 8904/* ------------------------------ */ 8905 .balign 128 8906.L_ALT_op_if_nez: /* 0x39 */ 8907/* File: mips/alt_stub.S */ 8908/* 8909 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8910 * any interesting requests and then jump to the real instruction 8911 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8912 */ 8913 .extern MterpCheckBefore 8914 la ra, artMterpAsmInstructionStart + (57 * 128) # Addr of primary handler 8915 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8916 move a0, rSELF # arg0 8917 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8918 move a2, rPC 8919 la t9, MterpCheckBefore 8920 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8921 8922/* ------------------------------ */ 8923 .balign 128 8924.L_ALT_op_if_ltz: /* 0x3a */ 8925/* File: mips/alt_stub.S */ 8926/* 8927 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8928 * any interesting requests and then jump to the real instruction 8929 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8930 */ 8931 .extern MterpCheckBefore 8932 la ra, artMterpAsmInstructionStart + (58 * 128) # Addr of primary handler 8933 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8934 move a0, rSELF # arg0 8935 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8936 move a2, rPC 8937 la t9, MterpCheckBefore 8938 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8939 8940/* ------------------------------ */ 8941 .balign 128 8942.L_ALT_op_if_gez: /* 0x3b */ 8943/* File: mips/alt_stub.S */ 8944/* 8945 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8946 * any interesting requests and then jump to the real instruction 8947 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8948 */ 8949 .extern MterpCheckBefore 8950 la ra, artMterpAsmInstructionStart + (59 * 128) # Addr of primary handler 8951 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8952 move a0, rSELF # arg0 8953 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8954 move a2, rPC 8955 la t9, MterpCheckBefore 8956 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8957 8958/* ------------------------------ */ 8959 .balign 128 8960.L_ALT_op_if_gtz: /* 0x3c */ 8961/* File: mips/alt_stub.S */ 8962/* 8963 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8964 * any interesting requests and then jump to the real instruction 8965 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8966 */ 8967 .extern MterpCheckBefore 8968 la ra, artMterpAsmInstructionStart + (60 * 128) # Addr of primary handler 8969 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8970 move a0, rSELF # arg0 8971 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8972 move a2, rPC 8973 la t9, MterpCheckBefore 8974 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8975 8976/* ------------------------------ */ 8977 .balign 128 8978.L_ALT_op_if_lez: /* 0x3d */ 8979/* File: mips/alt_stub.S */ 8980/* 8981 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8982 * any interesting requests and then jump to the real instruction 8983 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8984 */ 8985 .extern MterpCheckBefore 8986 la ra, artMterpAsmInstructionStart + (61 * 128) # Addr of primary handler 8987 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 8988 move a0, rSELF # arg0 8989 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 8990 move a2, rPC 8991 la t9, MterpCheckBefore 8992 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 8993 8994/* ------------------------------ */ 8995 .balign 128 8996.L_ALT_op_unused_3e: /* 0x3e */ 8997/* File: mips/alt_stub.S */ 8998/* 8999 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9000 * any interesting requests and then jump to the real instruction 9001 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9002 */ 9003 .extern MterpCheckBefore 9004 la ra, artMterpAsmInstructionStart + (62 * 128) # Addr of primary handler 9005 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9006 move a0, rSELF # arg0 9007 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9008 move a2, rPC 9009 la t9, MterpCheckBefore 9010 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9011 9012/* ------------------------------ */ 9013 .balign 128 9014.L_ALT_op_unused_3f: /* 0x3f */ 9015/* File: mips/alt_stub.S */ 9016/* 9017 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9018 * any interesting requests and then jump to the real instruction 9019 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9020 */ 9021 .extern MterpCheckBefore 9022 la ra, artMterpAsmInstructionStart + (63 * 128) # Addr of primary handler 9023 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9024 move a0, rSELF # arg0 9025 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9026 move a2, rPC 9027 la t9, MterpCheckBefore 9028 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9029 9030/* ------------------------------ */ 9031 .balign 128 9032.L_ALT_op_unused_40: /* 0x40 */ 9033/* File: mips/alt_stub.S */ 9034/* 9035 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9036 * any interesting requests and then jump to the real instruction 9037 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9038 */ 9039 .extern MterpCheckBefore 9040 la ra, artMterpAsmInstructionStart + (64 * 128) # Addr of primary handler 9041 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9042 move a0, rSELF # arg0 9043 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9044 move a2, rPC 9045 la t9, MterpCheckBefore 9046 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9047 9048/* ------------------------------ */ 9049 .balign 128 9050.L_ALT_op_unused_41: /* 0x41 */ 9051/* File: mips/alt_stub.S */ 9052/* 9053 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9054 * any interesting requests and then jump to the real instruction 9055 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9056 */ 9057 .extern MterpCheckBefore 9058 la ra, artMterpAsmInstructionStart + (65 * 128) # Addr of primary handler 9059 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9060 move a0, rSELF # arg0 9061 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9062 move a2, rPC 9063 la t9, MterpCheckBefore 9064 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9065 9066/* ------------------------------ */ 9067 .balign 128 9068.L_ALT_op_unused_42: /* 0x42 */ 9069/* File: mips/alt_stub.S */ 9070/* 9071 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9072 * any interesting requests and then jump to the real instruction 9073 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9074 */ 9075 .extern MterpCheckBefore 9076 la ra, artMterpAsmInstructionStart + (66 * 128) # Addr of primary handler 9077 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9078 move a0, rSELF # arg0 9079 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9080 move a2, rPC 9081 la t9, MterpCheckBefore 9082 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9083 9084/* ------------------------------ */ 9085 .balign 128 9086.L_ALT_op_unused_43: /* 0x43 */ 9087/* File: mips/alt_stub.S */ 9088/* 9089 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9090 * any interesting requests and then jump to the real instruction 9091 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9092 */ 9093 .extern MterpCheckBefore 9094 la ra, artMterpAsmInstructionStart + (67 * 128) # Addr of primary handler 9095 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9096 move a0, rSELF # arg0 9097 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9098 move a2, rPC 9099 la t9, MterpCheckBefore 9100 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9101 9102/* ------------------------------ */ 9103 .balign 128 9104.L_ALT_op_aget: /* 0x44 */ 9105/* File: mips/alt_stub.S */ 9106/* 9107 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9108 * any interesting requests and then jump to the real instruction 9109 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9110 */ 9111 .extern MterpCheckBefore 9112 la ra, artMterpAsmInstructionStart + (68 * 128) # Addr of primary handler 9113 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9114 move a0, rSELF # arg0 9115 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9116 move a2, rPC 9117 la t9, MterpCheckBefore 9118 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9119 9120/* ------------------------------ */ 9121 .balign 128 9122.L_ALT_op_aget_wide: /* 0x45 */ 9123/* File: mips/alt_stub.S */ 9124/* 9125 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9126 * any interesting requests and then jump to the real instruction 9127 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9128 */ 9129 .extern MterpCheckBefore 9130 la ra, artMterpAsmInstructionStart + (69 * 128) # Addr of primary handler 9131 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9132 move a0, rSELF # arg0 9133 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9134 move a2, rPC 9135 la t9, MterpCheckBefore 9136 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9137 9138/* ------------------------------ */ 9139 .balign 128 9140.L_ALT_op_aget_object: /* 0x46 */ 9141/* File: mips/alt_stub.S */ 9142/* 9143 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9144 * any interesting requests and then jump to the real instruction 9145 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9146 */ 9147 .extern MterpCheckBefore 9148 la ra, artMterpAsmInstructionStart + (70 * 128) # Addr of primary handler 9149 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9150 move a0, rSELF # arg0 9151 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9152 move a2, rPC 9153 la t9, MterpCheckBefore 9154 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9155 9156/* ------------------------------ */ 9157 .balign 128 9158.L_ALT_op_aget_boolean: /* 0x47 */ 9159/* File: mips/alt_stub.S */ 9160/* 9161 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9162 * any interesting requests and then jump to the real instruction 9163 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9164 */ 9165 .extern MterpCheckBefore 9166 la ra, artMterpAsmInstructionStart + (71 * 128) # Addr of primary handler 9167 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9168 move a0, rSELF # arg0 9169 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9170 move a2, rPC 9171 la t9, MterpCheckBefore 9172 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9173 9174/* ------------------------------ */ 9175 .balign 128 9176.L_ALT_op_aget_byte: /* 0x48 */ 9177/* File: mips/alt_stub.S */ 9178/* 9179 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9180 * any interesting requests and then jump to the real instruction 9181 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9182 */ 9183 .extern MterpCheckBefore 9184 la ra, artMterpAsmInstructionStart + (72 * 128) # Addr of primary handler 9185 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9186 move a0, rSELF # arg0 9187 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9188 move a2, rPC 9189 la t9, MterpCheckBefore 9190 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9191 9192/* ------------------------------ */ 9193 .balign 128 9194.L_ALT_op_aget_char: /* 0x49 */ 9195/* File: mips/alt_stub.S */ 9196/* 9197 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9198 * any interesting requests and then jump to the real instruction 9199 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9200 */ 9201 .extern MterpCheckBefore 9202 la ra, artMterpAsmInstructionStart + (73 * 128) # Addr of primary handler 9203 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9204 move a0, rSELF # arg0 9205 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9206 move a2, rPC 9207 la t9, MterpCheckBefore 9208 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9209 9210/* ------------------------------ */ 9211 .balign 128 9212.L_ALT_op_aget_short: /* 0x4a */ 9213/* File: mips/alt_stub.S */ 9214/* 9215 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9216 * any interesting requests and then jump to the real instruction 9217 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9218 */ 9219 .extern MterpCheckBefore 9220 la ra, artMterpAsmInstructionStart + (74 * 128) # Addr of primary handler 9221 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9222 move a0, rSELF # arg0 9223 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9224 move a2, rPC 9225 la t9, MterpCheckBefore 9226 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9227 9228/* ------------------------------ */ 9229 .balign 128 9230.L_ALT_op_aput: /* 0x4b */ 9231/* File: mips/alt_stub.S */ 9232/* 9233 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9234 * any interesting requests and then jump to the real instruction 9235 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9236 */ 9237 .extern MterpCheckBefore 9238 la ra, artMterpAsmInstructionStart + (75 * 128) # Addr of primary handler 9239 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9240 move a0, rSELF # arg0 9241 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9242 move a2, rPC 9243 la t9, MterpCheckBefore 9244 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9245 9246/* ------------------------------ */ 9247 .balign 128 9248.L_ALT_op_aput_wide: /* 0x4c */ 9249/* File: mips/alt_stub.S */ 9250/* 9251 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9252 * any interesting requests and then jump to the real instruction 9253 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9254 */ 9255 .extern MterpCheckBefore 9256 la ra, artMterpAsmInstructionStart + (76 * 128) # Addr of primary handler 9257 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9258 move a0, rSELF # arg0 9259 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9260 move a2, rPC 9261 la t9, MterpCheckBefore 9262 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9263 9264/* ------------------------------ */ 9265 .balign 128 9266.L_ALT_op_aput_object: /* 0x4d */ 9267/* File: mips/alt_stub.S */ 9268/* 9269 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9270 * any interesting requests and then jump to the real instruction 9271 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9272 */ 9273 .extern MterpCheckBefore 9274 la ra, artMterpAsmInstructionStart + (77 * 128) # Addr of primary handler 9275 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9276 move a0, rSELF # arg0 9277 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9278 move a2, rPC 9279 la t9, MterpCheckBefore 9280 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9281 9282/* ------------------------------ */ 9283 .balign 128 9284.L_ALT_op_aput_boolean: /* 0x4e */ 9285/* File: mips/alt_stub.S */ 9286/* 9287 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9288 * any interesting requests and then jump to the real instruction 9289 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9290 */ 9291 .extern MterpCheckBefore 9292 la ra, artMterpAsmInstructionStart + (78 * 128) # Addr of primary handler 9293 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9294 move a0, rSELF # arg0 9295 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9296 move a2, rPC 9297 la t9, MterpCheckBefore 9298 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9299 9300/* ------------------------------ */ 9301 .balign 128 9302.L_ALT_op_aput_byte: /* 0x4f */ 9303/* File: mips/alt_stub.S */ 9304/* 9305 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9306 * any interesting requests and then jump to the real instruction 9307 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9308 */ 9309 .extern MterpCheckBefore 9310 la ra, artMterpAsmInstructionStart + (79 * 128) # Addr of primary handler 9311 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9312 move a0, rSELF # arg0 9313 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9314 move a2, rPC 9315 la t9, MterpCheckBefore 9316 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9317 9318/* ------------------------------ */ 9319 .balign 128 9320.L_ALT_op_aput_char: /* 0x50 */ 9321/* File: mips/alt_stub.S */ 9322/* 9323 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9324 * any interesting requests and then jump to the real instruction 9325 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9326 */ 9327 .extern MterpCheckBefore 9328 la ra, artMterpAsmInstructionStart + (80 * 128) # Addr of primary handler 9329 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9330 move a0, rSELF # arg0 9331 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9332 move a2, rPC 9333 la t9, MterpCheckBefore 9334 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9335 9336/* ------------------------------ */ 9337 .balign 128 9338.L_ALT_op_aput_short: /* 0x51 */ 9339/* File: mips/alt_stub.S */ 9340/* 9341 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9342 * any interesting requests and then jump to the real instruction 9343 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9344 */ 9345 .extern MterpCheckBefore 9346 la ra, artMterpAsmInstructionStart + (81 * 128) # Addr of primary handler 9347 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9348 move a0, rSELF # arg0 9349 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9350 move a2, rPC 9351 la t9, MterpCheckBefore 9352 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9353 9354/* ------------------------------ */ 9355 .balign 128 9356.L_ALT_op_iget: /* 0x52 */ 9357/* File: mips/alt_stub.S */ 9358/* 9359 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9360 * any interesting requests and then jump to the real instruction 9361 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9362 */ 9363 .extern MterpCheckBefore 9364 la ra, artMterpAsmInstructionStart + (82 * 128) # Addr of primary handler 9365 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9366 move a0, rSELF # arg0 9367 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9368 move a2, rPC 9369 la t9, MterpCheckBefore 9370 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9371 9372/* ------------------------------ */ 9373 .balign 128 9374.L_ALT_op_iget_wide: /* 0x53 */ 9375/* File: mips/alt_stub.S */ 9376/* 9377 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9378 * any interesting requests and then jump to the real instruction 9379 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9380 */ 9381 .extern MterpCheckBefore 9382 la ra, artMterpAsmInstructionStart + (83 * 128) # Addr of primary handler 9383 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9384 move a0, rSELF # arg0 9385 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9386 move a2, rPC 9387 la t9, MterpCheckBefore 9388 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9389 9390/* ------------------------------ */ 9391 .balign 128 9392.L_ALT_op_iget_object: /* 0x54 */ 9393/* File: mips/alt_stub.S */ 9394/* 9395 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9396 * any interesting requests and then jump to the real instruction 9397 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9398 */ 9399 .extern MterpCheckBefore 9400 la ra, artMterpAsmInstructionStart + (84 * 128) # Addr of primary handler 9401 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9402 move a0, rSELF # arg0 9403 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9404 move a2, rPC 9405 la t9, MterpCheckBefore 9406 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9407 9408/* ------------------------------ */ 9409 .balign 128 9410.L_ALT_op_iget_boolean: /* 0x55 */ 9411/* File: mips/alt_stub.S */ 9412/* 9413 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9414 * any interesting requests and then jump to the real instruction 9415 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9416 */ 9417 .extern MterpCheckBefore 9418 la ra, artMterpAsmInstructionStart + (85 * 128) # Addr of primary handler 9419 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9420 move a0, rSELF # arg0 9421 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9422 move a2, rPC 9423 la t9, MterpCheckBefore 9424 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9425 9426/* ------------------------------ */ 9427 .balign 128 9428.L_ALT_op_iget_byte: /* 0x56 */ 9429/* File: mips/alt_stub.S */ 9430/* 9431 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9432 * any interesting requests and then jump to the real instruction 9433 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9434 */ 9435 .extern MterpCheckBefore 9436 la ra, artMterpAsmInstructionStart + (86 * 128) # Addr of primary handler 9437 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9438 move a0, rSELF # arg0 9439 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9440 move a2, rPC 9441 la t9, MterpCheckBefore 9442 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9443 9444/* ------------------------------ */ 9445 .balign 128 9446.L_ALT_op_iget_char: /* 0x57 */ 9447/* File: mips/alt_stub.S */ 9448/* 9449 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9450 * any interesting requests and then jump to the real instruction 9451 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9452 */ 9453 .extern MterpCheckBefore 9454 la ra, artMterpAsmInstructionStart + (87 * 128) # Addr of primary handler 9455 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9456 move a0, rSELF # arg0 9457 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9458 move a2, rPC 9459 la t9, MterpCheckBefore 9460 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9461 9462/* ------------------------------ */ 9463 .balign 128 9464.L_ALT_op_iget_short: /* 0x58 */ 9465/* File: mips/alt_stub.S */ 9466/* 9467 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9468 * any interesting requests and then jump to the real instruction 9469 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9470 */ 9471 .extern MterpCheckBefore 9472 la ra, artMterpAsmInstructionStart + (88 * 128) # Addr of primary handler 9473 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9474 move a0, rSELF # arg0 9475 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9476 move a2, rPC 9477 la t9, MterpCheckBefore 9478 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9479 9480/* ------------------------------ */ 9481 .balign 128 9482.L_ALT_op_iput: /* 0x59 */ 9483/* File: mips/alt_stub.S */ 9484/* 9485 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9486 * any interesting requests and then jump to the real instruction 9487 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9488 */ 9489 .extern MterpCheckBefore 9490 la ra, artMterpAsmInstructionStart + (89 * 128) # Addr of primary handler 9491 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9492 move a0, rSELF # arg0 9493 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9494 move a2, rPC 9495 la t9, MterpCheckBefore 9496 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9497 9498/* ------------------------------ */ 9499 .balign 128 9500.L_ALT_op_iput_wide: /* 0x5a */ 9501/* File: mips/alt_stub.S */ 9502/* 9503 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9504 * any interesting requests and then jump to the real instruction 9505 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9506 */ 9507 .extern MterpCheckBefore 9508 la ra, artMterpAsmInstructionStart + (90 * 128) # Addr of primary handler 9509 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9510 move a0, rSELF # arg0 9511 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9512 move a2, rPC 9513 la t9, MterpCheckBefore 9514 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9515 9516/* ------------------------------ */ 9517 .balign 128 9518.L_ALT_op_iput_object: /* 0x5b */ 9519/* File: mips/alt_stub.S */ 9520/* 9521 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9522 * any interesting requests and then jump to the real instruction 9523 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9524 */ 9525 .extern MterpCheckBefore 9526 la ra, artMterpAsmInstructionStart + (91 * 128) # Addr of primary handler 9527 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9528 move a0, rSELF # arg0 9529 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9530 move a2, rPC 9531 la t9, MterpCheckBefore 9532 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9533 9534/* ------------------------------ */ 9535 .balign 128 9536.L_ALT_op_iput_boolean: /* 0x5c */ 9537/* File: mips/alt_stub.S */ 9538/* 9539 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9540 * any interesting requests and then jump to the real instruction 9541 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9542 */ 9543 .extern MterpCheckBefore 9544 la ra, artMterpAsmInstructionStart + (92 * 128) # Addr of primary handler 9545 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9546 move a0, rSELF # arg0 9547 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9548 move a2, rPC 9549 la t9, MterpCheckBefore 9550 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9551 9552/* ------------------------------ */ 9553 .balign 128 9554.L_ALT_op_iput_byte: /* 0x5d */ 9555/* File: mips/alt_stub.S */ 9556/* 9557 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9558 * any interesting requests and then jump to the real instruction 9559 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9560 */ 9561 .extern MterpCheckBefore 9562 la ra, artMterpAsmInstructionStart + (93 * 128) # Addr of primary handler 9563 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9564 move a0, rSELF # arg0 9565 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9566 move a2, rPC 9567 la t9, MterpCheckBefore 9568 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9569 9570/* ------------------------------ */ 9571 .balign 128 9572.L_ALT_op_iput_char: /* 0x5e */ 9573/* File: mips/alt_stub.S */ 9574/* 9575 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9576 * any interesting requests and then jump to the real instruction 9577 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9578 */ 9579 .extern MterpCheckBefore 9580 la ra, artMterpAsmInstructionStart + (94 * 128) # Addr of primary handler 9581 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9582 move a0, rSELF # arg0 9583 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9584 move a2, rPC 9585 la t9, MterpCheckBefore 9586 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9587 9588/* ------------------------------ */ 9589 .balign 128 9590.L_ALT_op_iput_short: /* 0x5f */ 9591/* File: mips/alt_stub.S */ 9592/* 9593 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9594 * any interesting requests and then jump to the real instruction 9595 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9596 */ 9597 .extern MterpCheckBefore 9598 la ra, artMterpAsmInstructionStart + (95 * 128) # Addr of primary handler 9599 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9600 move a0, rSELF # arg0 9601 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9602 move a2, rPC 9603 la t9, MterpCheckBefore 9604 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9605 9606/* ------------------------------ */ 9607 .balign 128 9608.L_ALT_op_sget: /* 0x60 */ 9609/* File: mips/alt_stub.S */ 9610/* 9611 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9612 * any interesting requests and then jump to the real instruction 9613 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9614 */ 9615 .extern MterpCheckBefore 9616 la ra, artMterpAsmInstructionStart + (96 * 128) # Addr of primary handler 9617 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9618 move a0, rSELF # arg0 9619 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9620 move a2, rPC 9621 la t9, MterpCheckBefore 9622 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9623 9624/* ------------------------------ */ 9625 .balign 128 9626.L_ALT_op_sget_wide: /* 0x61 */ 9627/* File: mips/alt_stub.S */ 9628/* 9629 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9630 * any interesting requests and then jump to the real instruction 9631 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9632 */ 9633 .extern MterpCheckBefore 9634 la ra, artMterpAsmInstructionStart + (97 * 128) # Addr of primary handler 9635 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9636 move a0, rSELF # arg0 9637 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9638 move a2, rPC 9639 la t9, MterpCheckBefore 9640 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9641 9642/* ------------------------------ */ 9643 .balign 128 9644.L_ALT_op_sget_object: /* 0x62 */ 9645/* File: mips/alt_stub.S */ 9646/* 9647 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9648 * any interesting requests and then jump to the real instruction 9649 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9650 */ 9651 .extern MterpCheckBefore 9652 la ra, artMterpAsmInstructionStart + (98 * 128) # Addr of primary handler 9653 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9654 move a0, rSELF # arg0 9655 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9656 move a2, rPC 9657 la t9, MterpCheckBefore 9658 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9659 9660/* ------------------------------ */ 9661 .balign 128 9662.L_ALT_op_sget_boolean: /* 0x63 */ 9663/* File: mips/alt_stub.S */ 9664/* 9665 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9666 * any interesting requests and then jump to the real instruction 9667 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9668 */ 9669 .extern MterpCheckBefore 9670 la ra, artMterpAsmInstructionStart + (99 * 128) # Addr of primary handler 9671 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9672 move a0, rSELF # arg0 9673 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9674 move a2, rPC 9675 la t9, MterpCheckBefore 9676 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9677 9678/* ------------------------------ */ 9679 .balign 128 9680.L_ALT_op_sget_byte: /* 0x64 */ 9681/* File: mips/alt_stub.S */ 9682/* 9683 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9684 * any interesting requests and then jump to the real instruction 9685 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9686 */ 9687 .extern MterpCheckBefore 9688 la ra, artMterpAsmInstructionStart + (100 * 128) # Addr of primary handler 9689 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9690 move a0, rSELF # arg0 9691 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9692 move a2, rPC 9693 la t9, MterpCheckBefore 9694 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9695 9696/* ------------------------------ */ 9697 .balign 128 9698.L_ALT_op_sget_char: /* 0x65 */ 9699/* File: mips/alt_stub.S */ 9700/* 9701 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9702 * any interesting requests and then jump to the real instruction 9703 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9704 */ 9705 .extern MterpCheckBefore 9706 la ra, artMterpAsmInstructionStart + (101 * 128) # Addr of primary handler 9707 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9708 move a0, rSELF # arg0 9709 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9710 move a2, rPC 9711 la t9, MterpCheckBefore 9712 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9713 9714/* ------------------------------ */ 9715 .balign 128 9716.L_ALT_op_sget_short: /* 0x66 */ 9717/* File: mips/alt_stub.S */ 9718/* 9719 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9720 * any interesting requests and then jump to the real instruction 9721 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9722 */ 9723 .extern MterpCheckBefore 9724 la ra, artMterpAsmInstructionStart + (102 * 128) # Addr of primary handler 9725 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9726 move a0, rSELF # arg0 9727 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9728 move a2, rPC 9729 la t9, MterpCheckBefore 9730 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9731 9732/* ------------------------------ */ 9733 .balign 128 9734.L_ALT_op_sput: /* 0x67 */ 9735/* File: mips/alt_stub.S */ 9736/* 9737 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9738 * any interesting requests and then jump to the real instruction 9739 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9740 */ 9741 .extern MterpCheckBefore 9742 la ra, artMterpAsmInstructionStart + (103 * 128) # Addr of primary handler 9743 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9744 move a0, rSELF # arg0 9745 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9746 move a2, rPC 9747 la t9, MterpCheckBefore 9748 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9749 9750/* ------------------------------ */ 9751 .balign 128 9752.L_ALT_op_sput_wide: /* 0x68 */ 9753/* File: mips/alt_stub.S */ 9754/* 9755 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9756 * any interesting requests and then jump to the real instruction 9757 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9758 */ 9759 .extern MterpCheckBefore 9760 la ra, artMterpAsmInstructionStart + (104 * 128) # Addr of primary handler 9761 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9762 move a0, rSELF # arg0 9763 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9764 move a2, rPC 9765 la t9, MterpCheckBefore 9766 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9767 9768/* ------------------------------ */ 9769 .balign 128 9770.L_ALT_op_sput_object: /* 0x69 */ 9771/* File: mips/alt_stub.S */ 9772/* 9773 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9774 * any interesting requests and then jump to the real instruction 9775 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9776 */ 9777 .extern MterpCheckBefore 9778 la ra, artMterpAsmInstructionStart + (105 * 128) # Addr of primary handler 9779 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9780 move a0, rSELF # arg0 9781 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9782 move a2, rPC 9783 la t9, MterpCheckBefore 9784 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9785 9786/* ------------------------------ */ 9787 .balign 128 9788.L_ALT_op_sput_boolean: /* 0x6a */ 9789/* File: mips/alt_stub.S */ 9790/* 9791 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9792 * any interesting requests and then jump to the real instruction 9793 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9794 */ 9795 .extern MterpCheckBefore 9796 la ra, artMterpAsmInstructionStart + (106 * 128) # Addr of primary handler 9797 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9798 move a0, rSELF # arg0 9799 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9800 move a2, rPC 9801 la t9, MterpCheckBefore 9802 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9803 9804/* ------------------------------ */ 9805 .balign 128 9806.L_ALT_op_sput_byte: /* 0x6b */ 9807/* File: mips/alt_stub.S */ 9808/* 9809 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9810 * any interesting requests and then jump to the real instruction 9811 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9812 */ 9813 .extern MterpCheckBefore 9814 la ra, artMterpAsmInstructionStart + (107 * 128) # Addr of primary handler 9815 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9816 move a0, rSELF # arg0 9817 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9818 move a2, rPC 9819 la t9, MterpCheckBefore 9820 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9821 9822/* ------------------------------ */ 9823 .balign 128 9824.L_ALT_op_sput_char: /* 0x6c */ 9825/* File: mips/alt_stub.S */ 9826/* 9827 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9828 * any interesting requests and then jump to the real instruction 9829 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9830 */ 9831 .extern MterpCheckBefore 9832 la ra, artMterpAsmInstructionStart + (108 * 128) # Addr of primary handler 9833 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9834 move a0, rSELF # arg0 9835 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9836 move a2, rPC 9837 la t9, MterpCheckBefore 9838 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9839 9840/* ------------------------------ */ 9841 .balign 128 9842.L_ALT_op_sput_short: /* 0x6d */ 9843/* File: mips/alt_stub.S */ 9844/* 9845 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9846 * any interesting requests and then jump to the real instruction 9847 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9848 */ 9849 .extern MterpCheckBefore 9850 la ra, artMterpAsmInstructionStart + (109 * 128) # Addr of primary handler 9851 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9852 move a0, rSELF # arg0 9853 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9854 move a2, rPC 9855 la t9, MterpCheckBefore 9856 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9857 9858/* ------------------------------ */ 9859 .balign 128 9860.L_ALT_op_invoke_virtual: /* 0x6e */ 9861/* File: mips/alt_stub.S */ 9862/* 9863 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9864 * any interesting requests and then jump to the real instruction 9865 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9866 */ 9867 .extern MterpCheckBefore 9868 la ra, artMterpAsmInstructionStart + (110 * 128) # Addr of primary handler 9869 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9870 move a0, rSELF # arg0 9871 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9872 move a2, rPC 9873 la t9, MterpCheckBefore 9874 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9875 9876/* ------------------------------ */ 9877 .balign 128 9878.L_ALT_op_invoke_super: /* 0x6f */ 9879/* File: mips/alt_stub.S */ 9880/* 9881 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9882 * any interesting requests and then jump to the real instruction 9883 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9884 */ 9885 .extern MterpCheckBefore 9886 la ra, artMterpAsmInstructionStart + (111 * 128) # Addr of primary handler 9887 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9888 move a0, rSELF # arg0 9889 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9890 move a2, rPC 9891 la t9, MterpCheckBefore 9892 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9893 9894/* ------------------------------ */ 9895 .balign 128 9896.L_ALT_op_invoke_direct: /* 0x70 */ 9897/* File: mips/alt_stub.S */ 9898/* 9899 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9900 * any interesting requests and then jump to the real instruction 9901 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9902 */ 9903 .extern MterpCheckBefore 9904 la ra, artMterpAsmInstructionStart + (112 * 128) # Addr of primary handler 9905 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9906 move a0, rSELF # arg0 9907 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9908 move a2, rPC 9909 la t9, MterpCheckBefore 9910 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9911 9912/* ------------------------------ */ 9913 .balign 128 9914.L_ALT_op_invoke_static: /* 0x71 */ 9915/* File: mips/alt_stub.S */ 9916/* 9917 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9918 * any interesting requests and then jump to the real instruction 9919 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9920 */ 9921 .extern MterpCheckBefore 9922 la ra, artMterpAsmInstructionStart + (113 * 128) # Addr of primary handler 9923 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9924 move a0, rSELF # arg0 9925 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9926 move a2, rPC 9927 la t9, MterpCheckBefore 9928 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9929 9930/* ------------------------------ */ 9931 .balign 128 9932.L_ALT_op_invoke_interface: /* 0x72 */ 9933/* File: mips/alt_stub.S */ 9934/* 9935 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9936 * any interesting requests and then jump to the real instruction 9937 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9938 */ 9939 .extern MterpCheckBefore 9940 la ra, artMterpAsmInstructionStart + (114 * 128) # Addr of primary handler 9941 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9942 move a0, rSELF # arg0 9943 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9944 move a2, rPC 9945 la t9, MterpCheckBefore 9946 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9947 9948/* ------------------------------ */ 9949 .balign 128 9950.L_ALT_op_return_void_no_barrier: /* 0x73 */ 9951/* File: mips/alt_stub.S */ 9952/* 9953 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9954 * any interesting requests and then jump to the real instruction 9955 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9956 */ 9957 .extern MterpCheckBefore 9958 la ra, artMterpAsmInstructionStart + (115 * 128) # Addr of primary handler 9959 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9960 move a0, rSELF # arg0 9961 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9962 move a2, rPC 9963 la t9, MterpCheckBefore 9964 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9965 9966/* ------------------------------ */ 9967 .balign 128 9968.L_ALT_op_invoke_virtual_range: /* 0x74 */ 9969/* File: mips/alt_stub.S */ 9970/* 9971 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9972 * any interesting requests and then jump to the real instruction 9973 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9974 */ 9975 .extern MterpCheckBefore 9976 la ra, artMterpAsmInstructionStart + (116 * 128) # Addr of primary handler 9977 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9978 move a0, rSELF # arg0 9979 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9980 move a2, rPC 9981 la t9, MterpCheckBefore 9982 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 9983 9984/* ------------------------------ */ 9985 .balign 128 9986.L_ALT_op_invoke_super_range: /* 0x75 */ 9987/* File: mips/alt_stub.S */ 9988/* 9989 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9990 * any interesting requests and then jump to the real instruction 9991 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9992 */ 9993 .extern MterpCheckBefore 9994 la ra, artMterpAsmInstructionStart + (117 * 128) # Addr of primary handler 9995 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 9996 move a0, rSELF # arg0 9997 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 9998 move a2, rPC 9999 la t9, MterpCheckBefore 10000 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10001 10002/* ------------------------------ */ 10003 .balign 128 10004.L_ALT_op_invoke_direct_range: /* 0x76 */ 10005/* File: mips/alt_stub.S */ 10006/* 10007 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10008 * any interesting requests and then jump to the real instruction 10009 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10010 */ 10011 .extern MterpCheckBefore 10012 la ra, artMterpAsmInstructionStart + (118 * 128) # Addr of primary handler 10013 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10014 move a0, rSELF # arg0 10015 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10016 move a2, rPC 10017 la t9, MterpCheckBefore 10018 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10019 10020/* ------------------------------ */ 10021 .balign 128 10022.L_ALT_op_invoke_static_range: /* 0x77 */ 10023/* File: mips/alt_stub.S */ 10024/* 10025 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10026 * any interesting requests and then jump to the real instruction 10027 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10028 */ 10029 .extern MterpCheckBefore 10030 la ra, artMterpAsmInstructionStart + (119 * 128) # Addr of primary handler 10031 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10032 move a0, rSELF # arg0 10033 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10034 move a2, rPC 10035 la t9, MterpCheckBefore 10036 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10037 10038/* ------------------------------ */ 10039 .balign 128 10040.L_ALT_op_invoke_interface_range: /* 0x78 */ 10041/* File: mips/alt_stub.S */ 10042/* 10043 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10044 * any interesting requests and then jump to the real instruction 10045 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10046 */ 10047 .extern MterpCheckBefore 10048 la ra, artMterpAsmInstructionStart + (120 * 128) # Addr of primary handler 10049 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10050 move a0, rSELF # arg0 10051 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10052 move a2, rPC 10053 la t9, MterpCheckBefore 10054 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10055 10056/* ------------------------------ */ 10057 .balign 128 10058.L_ALT_op_unused_79: /* 0x79 */ 10059/* File: mips/alt_stub.S */ 10060/* 10061 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10062 * any interesting requests and then jump to the real instruction 10063 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10064 */ 10065 .extern MterpCheckBefore 10066 la ra, artMterpAsmInstructionStart + (121 * 128) # Addr of primary handler 10067 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10068 move a0, rSELF # arg0 10069 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10070 move a2, rPC 10071 la t9, MterpCheckBefore 10072 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10073 10074/* ------------------------------ */ 10075 .balign 128 10076.L_ALT_op_unused_7a: /* 0x7a */ 10077/* File: mips/alt_stub.S */ 10078/* 10079 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10080 * any interesting requests and then jump to the real instruction 10081 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10082 */ 10083 .extern MterpCheckBefore 10084 la ra, artMterpAsmInstructionStart + (122 * 128) # Addr of primary handler 10085 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10086 move a0, rSELF # arg0 10087 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10088 move a2, rPC 10089 la t9, MterpCheckBefore 10090 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10091 10092/* ------------------------------ */ 10093 .balign 128 10094.L_ALT_op_neg_int: /* 0x7b */ 10095/* File: mips/alt_stub.S */ 10096/* 10097 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10098 * any interesting requests and then jump to the real instruction 10099 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10100 */ 10101 .extern MterpCheckBefore 10102 la ra, artMterpAsmInstructionStart + (123 * 128) # Addr of primary handler 10103 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10104 move a0, rSELF # arg0 10105 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10106 move a2, rPC 10107 la t9, MterpCheckBefore 10108 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10109 10110/* ------------------------------ */ 10111 .balign 128 10112.L_ALT_op_not_int: /* 0x7c */ 10113/* File: mips/alt_stub.S */ 10114/* 10115 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10116 * any interesting requests and then jump to the real instruction 10117 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10118 */ 10119 .extern MterpCheckBefore 10120 la ra, artMterpAsmInstructionStart + (124 * 128) # Addr of primary handler 10121 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10122 move a0, rSELF # arg0 10123 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10124 move a2, rPC 10125 la t9, MterpCheckBefore 10126 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10127 10128/* ------------------------------ */ 10129 .balign 128 10130.L_ALT_op_neg_long: /* 0x7d */ 10131/* File: mips/alt_stub.S */ 10132/* 10133 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10134 * any interesting requests and then jump to the real instruction 10135 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10136 */ 10137 .extern MterpCheckBefore 10138 la ra, artMterpAsmInstructionStart + (125 * 128) # Addr of primary handler 10139 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10140 move a0, rSELF # arg0 10141 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10142 move a2, rPC 10143 la t9, MterpCheckBefore 10144 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10145 10146/* ------------------------------ */ 10147 .balign 128 10148.L_ALT_op_not_long: /* 0x7e */ 10149/* File: mips/alt_stub.S */ 10150/* 10151 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10152 * any interesting requests and then jump to the real instruction 10153 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10154 */ 10155 .extern MterpCheckBefore 10156 la ra, artMterpAsmInstructionStart + (126 * 128) # Addr of primary handler 10157 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10158 move a0, rSELF # arg0 10159 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10160 move a2, rPC 10161 la t9, MterpCheckBefore 10162 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10163 10164/* ------------------------------ */ 10165 .balign 128 10166.L_ALT_op_neg_float: /* 0x7f */ 10167/* File: mips/alt_stub.S */ 10168/* 10169 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10170 * any interesting requests and then jump to the real instruction 10171 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10172 */ 10173 .extern MterpCheckBefore 10174 la ra, artMterpAsmInstructionStart + (127 * 128) # Addr of primary handler 10175 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10176 move a0, rSELF # arg0 10177 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10178 move a2, rPC 10179 la t9, MterpCheckBefore 10180 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10181 10182/* ------------------------------ */ 10183 .balign 128 10184.L_ALT_op_neg_double: /* 0x80 */ 10185/* File: mips/alt_stub.S */ 10186/* 10187 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10188 * any interesting requests and then jump to the real instruction 10189 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10190 */ 10191 .extern MterpCheckBefore 10192 la ra, artMterpAsmInstructionStart + (128 * 128) # Addr of primary handler 10193 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10194 move a0, rSELF # arg0 10195 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10196 move a2, rPC 10197 la t9, MterpCheckBefore 10198 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10199 10200/* ------------------------------ */ 10201 .balign 128 10202.L_ALT_op_int_to_long: /* 0x81 */ 10203/* File: mips/alt_stub.S */ 10204/* 10205 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10206 * any interesting requests and then jump to the real instruction 10207 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10208 */ 10209 .extern MterpCheckBefore 10210 la ra, artMterpAsmInstructionStart + (129 * 128) # Addr of primary handler 10211 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10212 move a0, rSELF # arg0 10213 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10214 move a2, rPC 10215 la t9, MterpCheckBefore 10216 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10217 10218/* ------------------------------ */ 10219 .balign 128 10220.L_ALT_op_int_to_float: /* 0x82 */ 10221/* File: mips/alt_stub.S */ 10222/* 10223 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10224 * any interesting requests and then jump to the real instruction 10225 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10226 */ 10227 .extern MterpCheckBefore 10228 la ra, artMterpAsmInstructionStart + (130 * 128) # Addr of primary handler 10229 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10230 move a0, rSELF # arg0 10231 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10232 move a2, rPC 10233 la t9, MterpCheckBefore 10234 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10235 10236/* ------------------------------ */ 10237 .balign 128 10238.L_ALT_op_int_to_double: /* 0x83 */ 10239/* File: mips/alt_stub.S */ 10240/* 10241 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10242 * any interesting requests and then jump to the real instruction 10243 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10244 */ 10245 .extern MterpCheckBefore 10246 la ra, artMterpAsmInstructionStart + (131 * 128) # Addr of primary handler 10247 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10248 move a0, rSELF # arg0 10249 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10250 move a2, rPC 10251 la t9, MterpCheckBefore 10252 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10253 10254/* ------------------------------ */ 10255 .balign 128 10256.L_ALT_op_long_to_int: /* 0x84 */ 10257/* File: mips/alt_stub.S */ 10258/* 10259 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10260 * any interesting requests and then jump to the real instruction 10261 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10262 */ 10263 .extern MterpCheckBefore 10264 la ra, artMterpAsmInstructionStart + (132 * 128) # Addr of primary handler 10265 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10266 move a0, rSELF # arg0 10267 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10268 move a2, rPC 10269 la t9, MterpCheckBefore 10270 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10271 10272/* ------------------------------ */ 10273 .balign 128 10274.L_ALT_op_long_to_float: /* 0x85 */ 10275/* File: mips/alt_stub.S */ 10276/* 10277 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10278 * any interesting requests and then jump to the real instruction 10279 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10280 */ 10281 .extern MterpCheckBefore 10282 la ra, artMterpAsmInstructionStart + (133 * 128) # Addr of primary handler 10283 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10284 move a0, rSELF # arg0 10285 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10286 move a2, rPC 10287 la t9, MterpCheckBefore 10288 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10289 10290/* ------------------------------ */ 10291 .balign 128 10292.L_ALT_op_long_to_double: /* 0x86 */ 10293/* File: mips/alt_stub.S */ 10294/* 10295 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10296 * any interesting requests and then jump to the real instruction 10297 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10298 */ 10299 .extern MterpCheckBefore 10300 la ra, artMterpAsmInstructionStart + (134 * 128) # Addr of primary handler 10301 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10302 move a0, rSELF # arg0 10303 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10304 move a2, rPC 10305 la t9, MterpCheckBefore 10306 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10307 10308/* ------------------------------ */ 10309 .balign 128 10310.L_ALT_op_float_to_int: /* 0x87 */ 10311/* File: mips/alt_stub.S */ 10312/* 10313 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10314 * any interesting requests and then jump to the real instruction 10315 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10316 */ 10317 .extern MterpCheckBefore 10318 la ra, artMterpAsmInstructionStart + (135 * 128) # Addr of primary handler 10319 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10320 move a0, rSELF # arg0 10321 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10322 move a2, rPC 10323 la t9, MterpCheckBefore 10324 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10325 10326/* ------------------------------ */ 10327 .balign 128 10328.L_ALT_op_float_to_long: /* 0x88 */ 10329/* File: mips/alt_stub.S */ 10330/* 10331 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10332 * any interesting requests and then jump to the real instruction 10333 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10334 */ 10335 .extern MterpCheckBefore 10336 la ra, artMterpAsmInstructionStart + (136 * 128) # Addr of primary handler 10337 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10338 move a0, rSELF # arg0 10339 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10340 move a2, rPC 10341 la t9, MterpCheckBefore 10342 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10343 10344/* ------------------------------ */ 10345 .balign 128 10346.L_ALT_op_float_to_double: /* 0x89 */ 10347/* File: mips/alt_stub.S */ 10348/* 10349 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10350 * any interesting requests and then jump to the real instruction 10351 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10352 */ 10353 .extern MterpCheckBefore 10354 la ra, artMterpAsmInstructionStart + (137 * 128) # Addr of primary handler 10355 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10356 move a0, rSELF # arg0 10357 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10358 move a2, rPC 10359 la t9, MterpCheckBefore 10360 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10361 10362/* ------------------------------ */ 10363 .balign 128 10364.L_ALT_op_double_to_int: /* 0x8a */ 10365/* File: mips/alt_stub.S */ 10366/* 10367 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10368 * any interesting requests and then jump to the real instruction 10369 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10370 */ 10371 .extern MterpCheckBefore 10372 la ra, artMterpAsmInstructionStart + (138 * 128) # Addr of primary handler 10373 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10374 move a0, rSELF # arg0 10375 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10376 move a2, rPC 10377 la t9, MterpCheckBefore 10378 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10379 10380/* ------------------------------ */ 10381 .balign 128 10382.L_ALT_op_double_to_long: /* 0x8b */ 10383/* File: mips/alt_stub.S */ 10384/* 10385 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10386 * any interesting requests and then jump to the real instruction 10387 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10388 */ 10389 .extern MterpCheckBefore 10390 la ra, artMterpAsmInstructionStart + (139 * 128) # Addr of primary handler 10391 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10392 move a0, rSELF # arg0 10393 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10394 move a2, rPC 10395 la t9, MterpCheckBefore 10396 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10397 10398/* ------------------------------ */ 10399 .balign 128 10400.L_ALT_op_double_to_float: /* 0x8c */ 10401/* File: mips/alt_stub.S */ 10402/* 10403 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10404 * any interesting requests and then jump to the real instruction 10405 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10406 */ 10407 .extern MterpCheckBefore 10408 la ra, artMterpAsmInstructionStart + (140 * 128) # Addr of primary handler 10409 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10410 move a0, rSELF # arg0 10411 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10412 move a2, rPC 10413 la t9, MterpCheckBefore 10414 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10415 10416/* ------------------------------ */ 10417 .balign 128 10418.L_ALT_op_int_to_byte: /* 0x8d */ 10419/* File: mips/alt_stub.S */ 10420/* 10421 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10422 * any interesting requests and then jump to the real instruction 10423 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10424 */ 10425 .extern MterpCheckBefore 10426 la ra, artMterpAsmInstructionStart + (141 * 128) # Addr of primary handler 10427 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10428 move a0, rSELF # arg0 10429 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10430 move a2, rPC 10431 la t9, MterpCheckBefore 10432 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10433 10434/* ------------------------------ */ 10435 .balign 128 10436.L_ALT_op_int_to_char: /* 0x8e */ 10437/* File: mips/alt_stub.S */ 10438/* 10439 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10440 * any interesting requests and then jump to the real instruction 10441 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10442 */ 10443 .extern MterpCheckBefore 10444 la ra, artMterpAsmInstructionStart + (142 * 128) # Addr of primary handler 10445 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10446 move a0, rSELF # arg0 10447 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10448 move a2, rPC 10449 la t9, MterpCheckBefore 10450 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10451 10452/* ------------------------------ */ 10453 .balign 128 10454.L_ALT_op_int_to_short: /* 0x8f */ 10455/* File: mips/alt_stub.S */ 10456/* 10457 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10458 * any interesting requests and then jump to the real instruction 10459 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10460 */ 10461 .extern MterpCheckBefore 10462 la ra, artMterpAsmInstructionStart + (143 * 128) # Addr of primary handler 10463 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10464 move a0, rSELF # arg0 10465 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10466 move a2, rPC 10467 la t9, MterpCheckBefore 10468 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10469 10470/* ------------------------------ */ 10471 .balign 128 10472.L_ALT_op_add_int: /* 0x90 */ 10473/* File: mips/alt_stub.S */ 10474/* 10475 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10476 * any interesting requests and then jump to the real instruction 10477 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10478 */ 10479 .extern MterpCheckBefore 10480 la ra, artMterpAsmInstructionStart + (144 * 128) # Addr of primary handler 10481 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10482 move a0, rSELF # arg0 10483 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10484 move a2, rPC 10485 la t9, MterpCheckBefore 10486 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10487 10488/* ------------------------------ */ 10489 .balign 128 10490.L_ALT_op_sub_int: /* 0x91 */ 10491/* File: mips/alt_stub.S */ 10492/* 10493 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10494 * any interesting requests and then jump to the real instruction 10495 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10496 */ 10497 .extern MterpCheckBefore 10498 la ra, artMterpAsmInstructionStart + (145 * 128) # Addr of primary handler 10499 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10500 move a0, rSELF # arg0 10501 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10502 move a2, rPC 10503 la t9, MterpCheckBefore 10504 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10505 10506/* ------------------------------ */ 10507 .balign 128 10508.L_ALT_op_mul_int: /* 0x92 */ 10509/* File: mips/alt_stub.S */ 10510/* 10511 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10512 * any interesting requests and then jump to the real instruction 10513 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10514 */ 10515 .extern MterpCheckBefore 10516 la ra, artMterpAsmInstructionStart + (146 * 128) # Addr of primary handler 10517 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10518 move a0, rSELF # arg0 10519 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10520 move a2, rPC 10521 la t9, MterpCheckBefore 10522 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10523 10524/* ------------------------------ */ 10525 .balign 128 10526.L_ALT_op_div_int: /* 0x93 */ 10527/* File: mips/alt_stub.S */ 10528/* 10529 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10530 * any interesting requests and then jump to the real instruction 10531 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10532 */ 10533 .extern MterpCheckBefore 10534 la ra, artMterpAsmInstructionStart + (147 * 128) # Addr of primary handler 10535 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10536 move a0, rSELF # arg0 10537 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10538 move a2, rPC 10539 la t9, MterpCheckBefore 10540 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10541 10542/* ------------------------------ */ 10543 .balign 128 10544.L_ALT_op_rem_int: /* 0x94 */ 10545/* File: mips/alt_stub.S */ 10546/* 10547 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10548 * any interesting requests and then jump to the real instruction 10549 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10550 */ 10551 .extern MterpCheckBefore 10552 la ra, artMterpAsmInstructionStart + (148 * 128) # Addr of primary handler 10553 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10554 move a0, rSELF # arg0 10555 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10556 move a2, rPC 10557 la t9, MterpCheckBefore 10558 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10559 10560/* ------------------------------ */ 10561 .balign 128 10562.L_ALT_op_and_int: /* 0x95 */ 10563/* File: mips/alt_stub.S */ 10564/* 10565 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10566 * any interesting requests and then jump to the real instruction 10567 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10568 */ 10569 .extern MterpCheckBefore 10570 la ra, artMterpAsmInstructionStart + (149 * 128) # Addr of primary handler 10571 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10572 move a0, rSELF # arg0 10573 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10574 move a2, rPC 10575 la t9, MterpCheckBefore 10576 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10577 10578/* ------------------------------ */ 10579 .balign 128 10580.L_ALT_op_or_int: /* 0x96 */ 10581/* File: mips/alt_stub.S */ 10582/* 10583 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10584 * any interesting requests and then jump to the real instruction 10585 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10586 */ 10587 .extern MterpCheckBefore 10588 la ra, artMterpAsmInstructionStart + (150 * 128) # Addr of primary handler 10589 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10590 move a0, rSELF # arg0 10591 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10592 move a2, rPC 10593 la t9, MterpCheckBefore 10594 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10595 10596/* ------------------------------ */ 10597 .balign 128 10598.L_ALT_op_xor_int: /* 0x97 */ 10599/* File: mips/alt_stub.S */ 10600/* 10601 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10602 * any interesting requests and then jump to the real instruction 10603 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10604 */ 10605 .extern MterpCheckBefore 10606 la ra, artMterpAsmInstructionStart + (151 * 128) # Addr of primary handler 10607 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10608 move a0, rSELF # arg0 10609 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10610 move a2, rPC 10611 la t9, MterpCheckBefore 10612 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10613 10614/* ------------------------------ */ 10615 .balign 128 10616.L_ALT_op_shl_int: /* 0x98 */ 10617/* File: mips/alt_stub.S */ 10618/* 10619 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10620 * any interesting requests and then jump to the real instruction 10621 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10622 */ 10623 .extern MterpCheckBefore 10624 la ra, artMterpAsmInstructionStart + (152 * 128) # Addr of primary handler 10625 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10626 move a0, rSELF # arg0 10627 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10628 move a2, rPC 10629 la t9, MterpCheckBefore 10630 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10631 10632/* ------------------------------ */ 10633 .balign 128 10634.L_ALT_op_shr_int: /* 0x99 */ 10635/* File: mips/alt_stub.S */ 10636/* 10637 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10638 * any interesting requests and then jump to the real instruction 10639 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10640 */ 10641 .extern MterpCheckBefore 10642 la ra, artMterpAsmInstructionStart + (153 * 128) # Addr of primary handler 10643 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10644 move a0, rSELF # arg0 10645 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10646 move a2, rPC 10647 la t9, MterpCheckBefore 10648 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10649 10650/* ------------------------------ */ 10651 .balign 128 10652.L_ALT_op_ushr_int: /* 0x9a */ 10653/* File: mips/alt_stub.S */ 10654/* 10655 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10656 * any interesting requests and then jump to the real instruction 10657 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10658 */ 10659 .extern MterpCheckBefore 10660 la ra, artMterpAsmInstructionStart + (154 * 128) # Addr of primary handler 10661 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10662 move a0, rSELF # arg0 10663 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10664 move a2, rPC 10665 la t9, MterpCheckBefore 10666 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10667 10668/* ------------------------------ */ 10669 .balign 128 10670.L_ALT_op_add_long: /* 0x9b */ 10671/* File: mips/alt_stub.S */ 10672/* 10673 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10674 * any interesting requests and then jump to the real instruction 10675 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10676 */ 10677 .extern MterpCheckBefore 10678 la ra, artMterpAsmInstructionStart + (155 * 128) # Addr of primary handler 10679 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10680 move a0, rSELF # arg0 10681 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10682 move a2, rPC 10683 la t9, MterpCheckBefore 10684 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10685 10686/* ------------------------------ */ 10687 .balign 128 10688.L_ALT_op_sub_long: /* 0x9c */ 10689/* File: mips/alt_stub.S */ 10690/* 10691 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10692 * any interesting requests and then jump to the real instruction 10693 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10694 */ 10695 .extern MterpCheckBefore 10696 la ra, artMterpAsmInstructionStart + (156 * 128) # Addr of primary handler 10697 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10698 move a0, rSELF # arg0 10699 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10700 move a2, rPC 10701 la t9, MterpCheckBefore 10702 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10703 10704/* ------------------------------ */ 10705 .balign 128 10706.L_ALT_op_mul_long: /* 0x9d */ 10707/* File: mips/alt_stub.S */ 10708/* 10709 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10710 * any interesting requests and then jump to the real instruction 10711 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10712 */ 10713 .extern MterpCheckBefore 10714 la ra, artMterpAsmInstructionStart + (157 * 128) # Addr of primary handler 10715 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10716 move a0, rSELF # arg0 10717 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10718 move a2, rPC 10719 la t9, MterpCheckBefore 10720 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10721 10722/* ------------------------------ */ 10723 .balign 128 10724.L_ALT_op_div_long: /* 0x9e */ 10725/* File: mips/alt_stub.S */ 10726/* 10727 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10728 * any interesting requests and then jump to the real instruction 10729 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10730 */ 10731 .extern MterpCheckBefore 10732 la ra, artMterpAsmInstructionStart + (158 * 128) # Addr of primary handler 10733 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10734 move a0, rSELF # arg0 10735 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10736 move a2, rPC 10737 la t9, MterpCheckBefore 10738 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10739 10740/* ------------------------------ */ 10741 .balign 128 10742.L_ALT_op_rem_long: /* 0x9f */ 10743/* File: mips/alt_stub.S */ 10744/* 10745 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10746 * any interesting requests and then jump to the real instruction 10747 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10748 */ 10749 .extern MterpCheckBefore 10750 la ra, artMterpAsmInstructionStart + (159 * 128) # Addr of primary handler 10751 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10752 move a0, rSELF # arg0 10753 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10754 move a2, rPC 10755 la t9, MterpCheckBefore 10756 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10757 10758/* ------------------------------ */ 10759 .balign 128 10760.L_ALT_op_and_long: /* 0xa0 */ 10761/* File: mips/alt_stub.S */ 10762/* 10763 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10764 * any interesting requests and then jump to the real instruction 10765 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10766 */ 10767 .extern MterpCheckBefore 10768 la ra, artMterpAsmInstructionStart + (160 * 128) # Addr of primary handler 10769 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10770 move a0, rSELF # arg0 10771 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10772 move a2, rPC 10773 la t9, MterpCheckBefore 10774 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10775 10776/* ------------------------------ */ 10777 .balign 128 10778.L_ALT_op_or_long: /* 0xa1 */ 10779/* File: mips/alt_stub.S */ 10780/* 10781 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10782 * any interesting requests and then jump to the real instruction 10783 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10784 */ 10785 .extern MterpCheckBefore 10786 la ra, artMterpAsmInstructionStart + (161 * 128) # Addr of primary handler 10787 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10788 move a0, rSELF # arg0 10789 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10790 move a2, rPC 10791 la t9, MterpCheckBefore 10792 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10793 10794/* ------------------------------ */ 10795 .balign 128 10796.L_ALT_op_xor_long: /* 0xa2 */ 10797/* File: mips/alt_stub.S */ 10798/* 10799 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10800 * any interesting requests and then jump to the real instruction 10801 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10802 */ 10803 .extern MterpCheckBefore 10804 la ra, artMterpAsmInstructionStart + (162 * 128) # Addr of primary handler 10805 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10806 move a0, rSELF # arg0 10807 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10808 move a2, rPC 10809 la t9, MterpCheckBefore 10810 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10811 10812/* ------------------------------ */ 10813 .balign 128 10814.L_ALT_op_shl_long: /* 0xa3 */ 10815/* File: mips/alt_stub.S */ 10816/* 10817 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10818 * any interesting requests and then jump to the real instruction 10819 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10820 */ 10821 .extern MterpCheckBefore 10822 la ra, artMterpAsmInstructionStart + (163 * 128) # Addr of primary handler 10823 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10824 move a0, rSELF # arg0 10825 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10826 move a2, rPC 10827 la t9, MterpCheckBefore 10828 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10829 10830/* ------------------------------ */ 10831 .balign 128 10832.L_ALT_op_shr_long: /* 0xa4 */ 10833/* File: mips/alt_stub.S */ 10834/* 10835 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10836 * any interesting requests and then jump to the real instruction 10837 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10838 */ 10839 .extern MterpCheckBefore 10840 la ra, artMterpAsmInstructionStart + (164 * 128) # Addr of primary handler 10841 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10842 move a0, rSELF # arg0 10843 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10844 move a2, rPC 10845 la t9, MterpCheckBefore 10846 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10847 10848/* ------------------------------ */ 10849 .balign 128 10850.L_ALT_op_ushr_long: /* 0xa5 */ 10851/* File: mips/alt_stub.S */ 10852/* 10853 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10854 * any interesting requests and then jump to the real instruction 10855 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10856 */ 10857 .extern MterpCheckBefore 10858 la ra, artMterpAsmInstructionStart + (165 * 128) # Addr of primary handler 10859 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10860 move a0, rSELF # arg0 10861 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10862 move a2, rPC 10863 la t9, MterpCheckBefore 10864 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10865 10866/* ------------------------------ */ 10867 .balign 128 10868.L_ALT_op_add_float: /* 0xa6 */ 10869/* File: mips/alt_stub.S */ 10870/* 10871 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10872 * any interesting requests and then jump to the real instruction 10873 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10874 */ 10875 .extern MterpCheckBefore 10876 la ra, artMterpAsmInstructionStart + (166 * 128) # Addr of primary handler 10877 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10878 move a0, rSELF # arg0 10879 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10880 move a2, rPC 10881 la t9, MterpCheckBefore 10882 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10883 10884/* ------------------------------ */ 10885 .balign 128 10886.L_ALT_op_sub_float: /* 0xa7 */ 10887/* File: mips/alt_stub.S */ 10888/* 10889 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10890 * any interesting requests and then jump to the real instruction 10891 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10892 */ 10893 .extern MterpCheckBefore 10894 la ra, artMterpAsmInstructionStart + (167 * 128) # Addr of primary handler 10895 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10896 move a0, rSELF # arg0 10897 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10898 move a2, rPC 10899 la t9, MterpCheckBefore 10900 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10901 10902/* ------------------------------ */ 10903 .balign 128 10904.L_ALT_op_mul_float: /* 0xa8 */ 10905/* File: mips/alt_stub.S */ 10906/* 10907 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10908 * any interesting requests and then jump to the real instruction 10909 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10910 */ 10911 .extern MterpCheckBefore 10912 la ra, artMterpAsmInstructionStart + (168 * 128) # Addr of primary handler 10913 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10914 move a0, rSELF # arg0 10915 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10916 move a2, rPC 10917 la t9, MterpCheckBefore 10918 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10919 10920/* ------------------------------ */ 10921 .balign 128 10922.L_ALT_op_div_float: /* 0xa9 */ 10923/* File: mips/alt_stub.S */ 10924/* 10925 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10926 * any interesting requests and then jump to the real instruction 10927 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10928 */ 10929 .extern MterpCheckBefore 10930 la ra, artMterpAsmInstructionStart + (169 * 128) # Addr of primary handler 10931 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10932 move a0, rSELF # arg0 10933 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10934 move a2, rPC 10935 la t9, MterpCheckBefore 10936 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10937 10938/* ------------------------------ */ 10939 .balign 128 10940.L_ALT_op_rem_float: /* 0xaa */ 10941/* File: mips/alt_stub.S */ 10942/* 10943 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10944 * any interesting requests and then jump to the real instruction 10945 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10946 */ 10947 .extern MterpCheckBefore 10948 la ra, artMterpAsmInstructionStart + (170 * 128) # Addr of primary handler 10949 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10950 move a0, rSELF # arg0 10951 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10952 move a2, rPC 10953 la t9, MterpCheckBefore 10954 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10955 10956/* ------------------------------ */ 10957 .balign 128 10958.L_ALT_op_add_double: /* 0xab */ 10959/* File: mips/alt_stub.S */ 10960/* 10961 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10962 * any interesting requests and then jump to the real instruction 10963 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10964 */ 10965 .extern MterpCheckBefore 10966 la ra, artMterpAsmInstructionStart + (171 * 128) # Addr of primary handler 10967 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10968 move a0, rSELF # arg0 10969 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10970 move a2, rPC 10971 la t9, MterpCheckBefore 10972 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10973 10974/* ------------------------------ */ 10975 .balign 128 10976.L_ALT_op_sub_double: /* 0xac */ 10977/* File: mips/alt_stub.S */ 10978/* 10979 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10980 * any interesting requests and then jump to the real instruction 10981 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10982 */ 10983 .extern MterpCheckBefore 10984 la ra, artMterpAsmInstructionStart + (172 * 128) # Addr of primary handler 10985 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 10986 move a0, rSELF # arg0 10987 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 10988 move a2, rPC 10989 la t9, MterpCheckBefore 10990 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 10991 10992/* ------------------------------ */ 10993 .balign 128 10994.L_ALT_op_mul_double: /* 0xad */ 10995/* File: mips/alt_stub.S */ 10996/* 10997 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10998 * any interesting requests and then jump to the real instruction 10999 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11000 */ 11001 .extern MterpCheckBefore 11002 la ra, artMterpAsmInstructionStart + (173 * 128) # Addr of primary handler 11003 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11004 move a0, rSELF # arg0 11005 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11006 move a2, rPC 11007 la t9, MterpCheckBefore 11008 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11009 11010/* ------------------------------ */ 11011 .balign 128 11012.L_ALT_op_div_double: /* 0xae */ 11013/* File: mips/alt_stub.S */ 11014/* 11015 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11016 * any interesting requests and then jump to the real instruction 11017 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11018 */ 11019 .extern MterpCheckBefore 11020 la ra, artMterpAsmInstructionStart + (174 * 128) # Addr of primary handler 11021 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11022 move a0, rSELF # arg0 11023 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11024 move a2, rPC 11025 la t9, MterpCheckBefore 11026 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11027 11028/* ------------------------------ */ 11029 .balign 128 11030.L_ALT_op_rem_double: /* 0xaf */ 11031/* File: mips/alt_stub.S */ 11032/* 11033 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11034 * any interesting requests and then jump to the real instruction 11035 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11036 */ 11037 .extern MterpCheckBefore 11038 la ra, artMterpAsmInstructionStart + (175 * 128) # Addr of primary handler 11039 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11040 move a0, rSELF # arg0 11041 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11042 move a2, rPC 11043 la t9, MterpCheckBefore 11044 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11045 11046/* ------------------------------ */ 11047 .balign 128 11048.L_ALT_op_add_int_2addr: /* 0xb0 */ 11049/* File: mips/alt_stub.S */ 11050/* 11051 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11052 * any interesting requests and then jump to the real instruction 11053 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11054 */ 11055 .extern MterpCheckBefore 11056 la ra, artMterpAsmInstructionStart + (176 * 128) # Addr of primary handler 11057 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11058 move a0, rSELF # arg0 11059 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11060 move a2, rPC 11061 la t9, MterpCheckBefore 11062 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11063 11064/* ------------------------------ */ 11065 .balign 128 11066.L_ALT_op_sub_int_2addr: /* 0xb1 */ 11067/* File: mips/alt_stub.S */ 11068/* 11069 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11070 * any interesting requests and then jump to the real instruction 11071 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11072 */ 11073 .extern MterpCheckBefore 11074 la ra, artMterpAsmInstructionStart + (177 * 128) # Addr of primary handler 11075 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11076 move a0, rSELF # arg0 11077 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11078 move a2, rPC 11079 la t9, MterpCheckBefore 11080 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11081 11082/* ------------------------------ */ 11083 .balign 128 11084.L_ALT_op_mul_int_2addr: /* 0xb2 */ 11085/* File: mips/alt_stub.S */ 11086/* 11087 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11088 * any interesting requests and then jump to the real instruction 11089 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11090 */ 11091 .extern MterpCheckBefore 11092 la ra, artMterpAsmInstructionStart + (178 * 128) # Addr of primary handler 11093 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11094 move a0, rSELF # arg0 11095 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11096 move a2, rPC 11097 la t9, MterpCheckBefore 11098 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11099 11100/* ------------------------------ */ 11101 .balign 128 11102.L_ALT_op_div_int_2addr: /* 0xb3 */ 11103/* File: mips/alt_stub.S */ 11104/* 11105 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11106 * any interesting requests and then jump to the real instruction 11107 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11108 */ 11109 .extern MterpCheckBefore 11110 la ra, artMterpAsmInstructionStart + (179 * 128) # Addr of primary handler 11111 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11112 move a0, rSELF # arg0 11113 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11114 move a2, rPC 11115 la t9, MterpCheckBefore 11116 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11117 11118/* ------------------------------ */ 11119 .balign 128 11120.L_ALT_op_rem_int_2addr: /* 0xb4 */ 11121/* File: mips/alt_stub.S */ 11122/* 11123 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11124 * any interesting requests and then jump to the real instruction 11125 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11126 */ 11127 .extern MterpCheckBefore 11128 la ra, artMterpAsmInstructionStart + (180 * 128) # Addr of primary handler 11129 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11130 move a0, rSELF # arg0 11131 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11132 move a2, rPC 11133 la t9, MterpCheckBefore 11134 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11135 11136/* ------------------------------ */ 11137 .balign 128 11138.L_ALT_op_and_int_2addr: /* 0xb5 */ 11139/* File: mips/alt_stub.S */ 11140/* 11141 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11142 * any interesting requests and then jump to the real instruction 11143 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11144 */ 11145 .extern MterpCheckBefore 11146 la ra, artMterpAsmInstructionStart + (181 * 128) # Addr of primary handler 11147 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11148 move a0, rSELF # arg0 11149 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11150 move a2, rPC 11151 la t9, MterpCheckBefore 11152 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11153 11154/* ------------------------------ */ 11155 .balign 128 11156.L_ALT_op_or_int_2addr: /* 0xb6 */ 11157/* File: mips/alt_stub.S */ 11158/* 11159 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11160 * any interesting requests and then jump to the real instruction 11161 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11162 */ 11163 .extern MterpCheckBefore 11164 la ra, artMterpAsmInstructionStart + (182 * 128) # Addr of primary handler 11165 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11166 move a0, rSELF # arg0 11167 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11168 move a2, rPC 11169 la t9, MterpCheckBefore 11170 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11171 11172/* ------------------------------ */ 11173 .balign 128 11174.L_ALT_op_xor_int_2addr: /* 0xb7 */ 11175/* File: mips/alt_stub.S */ 11176/* 11177 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11178 * any interesting requests and then jump to the real instruction 11179 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11180 */ 11181 .extern MterpCheckBefore 11182 la ra, artMterpAsmInstructionStart + (183 * 128) # Addr of primary handler 11183 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11184 move a0, rSELF # arg0 11185 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11186 move a2, rPC 11187 la t9, MterpCheckBefore 11188 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11189 11190/* ------------------------------ */ 11191 .balign 128 11192.L_ALT_op_shl_int_2addr: /* 0xb8 */ 11193/* File: mips/alt_stub.S */ 11194/* 11195 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11196 * any interesting requests and then jump to the real instruction 11197 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11198 */ 11199 .extern MterpCheckBefore 11200 la ra, artMterpAsmInstructionStart + (184 * 128) # Addr of primary handler 11201 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11202 move a0, rSELF # arg0 11203 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11204 move a2, rPC 11205 la t9, MterpCheckBefore 11206 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11207 11208/* ------------------------------ */ 11209 .balign 128 11210.L_ALT_op_shr_int_2addr: /* 0xb9 */ 11211/* File: mips/alt_stub.S */ 11212/* 11213 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11214 * any interesting requests and then jump to the real instruction 11215 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11216 */ 11217 .extern MterpCheckBefore 11218 la ra, artMterpAsmInstructionStart + (185 * 128) # Addr of primary handler 11219 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11220 move a0, rSELF # arg0 11221 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11222 move a2, rPC 11223 la t9, MterpCheckBefore 11224 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11225 11226/* ------------------------------ */ 11227 .balign 128 11228.L_ALT_op_ushr_int_2addr: /* 0xba */ 11229/* File: mips/alt_stub.S */ 11230/* 11231 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11232 * any interesting requests and then jump to the real instruction 11233 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11234 */ 11235 .extern MterpCheckBefore 11236 la ra, artMterpAsmInstructionStart + (186 * 128) # Addr of primary handler 11237 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11238 move a0, rSELF # arg0 11239 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11240 move a2, rPC 11241 la t9, MterpCheckBefore 11242 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11243 11244/* ------------------------------ */ 11245 .balign 128 11246.L_ALT_op_add_long_2addr: /* 0xbb */ 11247/* File: mips/alt_stub.S */ 11248/* 11249 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11250 * any interesting requests and then jump to the real instruction 11251 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11252 */ 11253 .extern MterpCheckBefore 11254 la ra, artMterpAsmInstructionStart + (187 * 128) # Addr of primary handler 11255 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11256 move a0, rSELF # arg0 11257 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11258 move a2, rPC 11259 la t9, MterpCheckBefore 11260 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11261 11262/* ------------------------------ */ 11263 .balign 128 11264.L_ALT_op_sub_long_2addr: /* 0xbc */ 11265/* File: mips/alt_stub.S */ 11266/* 11267 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11268 * any interesting requests and then jump to the real instruction 11269 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11270 */ 11271 .extern MterpCheckBefore 11272 la ra, artMterpAsmInstructionStart + (188 * 128) # Addr of primary handler 11273 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11274 move a0, rSELF # arg0 11275 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11276 move a2, rPC 11277 la t9, MterpCheckBefore 11278 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11279 11280/* ------------------------------ */ 11281 .balign 128 11282.L_ALT_op_mul_long_2addr: /* 0xbd */ 11283/* File: mips/alt_stub.S */ 11284/* 11285 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11286 * any interesting requests and then jump to the real instruction 11287 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11288 */ 11289 .extern MterpCheckBefore 11290 la ra, artMterpAsmInstructionStart + (189 * 128) # Addr of primary handler 11291 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11292 move a0, rSELF # arg0 11293 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11294 move a2, rPC 11295 la t9, MterpCheckBefore 11296 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11297 11298/* ------------------------------ */ 11299 .balign 128 11300.L_ALT_op_div_long_2addr: /* 0xbe */ 11301/* File: mips/alt_stub.S */ 11302/* 11303 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11304 * any interesting requests and then jump to the real instruction 11305 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11306 */ 11307 .extern MterpCheckBefore 11308 la ra, artMterpAsmInstructionStart + (190 * 128) # Addr of primary handler 11309 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11310 move a0, rSELF # arg0 11311 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11312 move a2, rPC 11313 la t9, MterpCheckBefore 11314 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11315 11316/* ------------------------------ */ 11317 .balign 128 11318.L_ALT_op_rem_long_2addr: /* 0xbf */ 11319/* File: mips/alt_stub.S */ 11320/* 11321 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11322 * any interesting requests and then jump to the real instruction 11323 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11324 */ 11325 .extern MterpCheckBefore 11326 la ra, artMterpAsmInstructionStart + (191 * 128) # Addr of primary handler 11327 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11328 move a0, rSELF # arg0 11329 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11330 move a2, rPC 11331 la t9, MterpCheckBefore 11332 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11333 11334/* ------------------------------ */ 11335 .balign 128 11336.L_ALT_op_and_long_2addr: /* 0xc0 */ 11337/* File: mips/alt_stub.S */ 11338/* 11339 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11340 * any interesting requests and then jump to the real instruction 11341 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11342 */ 11343 .extern MterpCheckBefore 11344 la ra, artMterpAsmInstructionStart + (192 * 128) # Addr of primary handler 11345 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11346 move a0, rSELF # arg0 11347 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11348 move a2, rPC 11349 la t9, MterpCheckBefore 11350 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11351 11352/* ------------------------------ */ 11353 .balign 128 11354.L_ALT_op_or_long_2addr: /* 0xc1 */ 11355/* File: mips/alt_stub.S */ 11356/* 11357 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11358 * any interesting requests and then jump to the real instruction 11359 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11360 */ 11361 .extern MterpCheckBefore 11362 la ra, artMterpAsmInstructionStart + (193 * 128) # Addr of primary handler 11363 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11364 move a0, rSELF # arg0 11365 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11366 move a2, rPC 11367 la t9, MterpCheckBefore 11368 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11369 11370/* ------------------------------ */ 11371 .balign 128 11372.L_ALT_op_xor_long_2addr: /* 0xc2 */ 11373/* File: mips/alt_stub.S */ 11374/* 11375 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11376 * any interesting requests and then jump to the real instruction 11377 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11378 */ 11379 .extern MterpCheckBefore 11380 la ra, artMterpAsmInstructionStart + (194 * 128) # Addr of primary handler 11381 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11382 move a0, rSELF # arg0 11383 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11384 move a2, rPC 11385 la t9, MterpCheckBefore 11386 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11387 11388/* ------------------------------ */ 11389 .balign 128 11390.L_ALT_op_shl_long_2addr: /* 0xc3 */ 11391/* File: mips/alt_stub.S */ 11392/* 11393 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11394 * any interesting requests and then jump to the real instruction 11395 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11396 */ 11397 .extern MterpCheckBefore 11398 la ra, artMterpAsmInstructionStart + (195 * 128) # Addr of primary handler 11399 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11400 move a0, rSELF # arg0 11401 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11402 move a2, rPC 11403 la t9, MterpCheckBefore 11404 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11405 11406/* ------------------------------ */ 11407 .balign 128 11408.L_ALT_op_shr_long_2addr: /* 0xc4 */ 11409/* File: mips/alt_stub.S */ 11410/* 11411 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11412 * any interesting requests and then jump to the real instruction 11413 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11414 */ 11415 .extern MterpCheckBefore 11416 la ra, artMterpAsmInstructionStart + (196 * 128) # Addr of primary handler 11417 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11418 move a0, rSELF # arg0 11419 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11420 move a2, rPC 11421 la t9, MterpCheckBefore 11422 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11423 11424/* ------------------------------ */ 11425 .balign 128 11426.L_ALT_op_ushr_long_2addr: /* 0xc5 */ 11427/* File: mips/alt_stub.S */ 11428/* 11429 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11430 * any interesting requests and then jump to the real instruction 11431 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11432 */ 11433 .extern MterpCheckBefore 11434 la ra, artMterpAsmInstructionStart + (197 * 128) # Addr of primary handler 11435 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11436 move a0, rSELF # arg0 11437 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11438 move a2, rPC 11439 la t9, MterpCheckBefore 11440 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11441 11442/* ------------------------------ */ 11443 .balign 128 11444.L_ALT_op_add_float_2addr: /* 0xc6 */ 11445/* File: mips/alt_stub.S */ 11446/* 11447 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11448 * any interesting requests and then jump to the real instruction 11449 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11450 */ 11451 .extern MterpCheckBefore 11452 la ra, artMterpAsmInstructionStart + (198 * 128) # Addr of primary handler 11453 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11454 move a0, rSELF # arg0 11455 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11456 move a2, rPC 11457 la t9, MterpCheckBefore 11458 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11459 11460/* ------------------------------ */ 11461 .balign 128 11462.L_ALT_op_sub_float_2addr: /* 0xc7 */ 11463/* File: mips/alt_stub.S */ 11464/* 11465 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11466 * any interesting requests and then jump to the real instruction 11467 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11468 */ 11469 .extern MterpCheckBefore 11470 la ra, artMterpAsmInstructionStart + (199 * 128) # Addr of primary handler 11471 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11472 move a0, rSELF # arg0 11473 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11474 move a2, rPC 11475 la t9, MterpCheckBefore 11476 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11477 11478/* ------------------------------ */ 11479 .balign 128 11480.L_ALT_op_mul_float_2addr: /* 0xc8 */ 11481/* File: mips/alt_stub.S */ 11482/* 11483 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11484 * any interesting requests and then jump to the real instruction 11485 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11486 */ 11487 .extern MterpCheckBefore 11488 la ra, artMterpAsmInstructionStart + (200 * 128) # Addr of primary handler 11489 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11490 move a0, rSELF # arg0 11491 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11492 move a2, rPC 11493 la t9, MterpCheckBefore 11494 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11495 11496/* ------------------------------ */ 11497 .balign 128 11498.L_ALT_op_div_float_2addr: /* 0xc9 */ 11499/* File: mips/alt_stub.S */ 11500/* 11501 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11502 * any interesting requests and then jump to the real instruction 11503 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11504 */ 11505 .extern MterpCheckBefore 11506 la ra, artMterpAsmInstructionStart + (201 * 128) # Addr of primary handler 11507 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11508 move a0, rSELF # arg0 11509 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11510 move a2, rPC 11511 la t9, MterpCheckBefore 11512 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11513 11514/* ------------------------------ */ 11515 .balign 128 11516.L_ALT_op_rem_float_2addr: /* 0xca */ 11517/* File: mips/alt_stub.S */ 11518/* 11519 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11520 * any interesting requests and then jump to the real instruction 11521 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11522 */ 11523 .extern MterpCheckBefore 11524 la ra, artMterpAsmInstructionStart + (202 * 128) # Addr of primary handler 11525 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11526 move a0, rSELF # arg0 11527 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11528 move a2, rPC 11529 la t9, MterpCheckBefore 11530 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11531 11532/* ------------------------------ */ 11533 .balign 128 11534.L_ALT_op_add_double_2addr: /* 0xcb */ 11535/* File: mips/alt_stub.S */ 11536/* 11537 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11538 * any interesting requests and then jump to the real instruction 11539 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11540 */ 11541 .extern MterpCheckBefore 11542 la ra, artMterpAsmInstructionStart + (203 * 128) # Addr of primary handler 11543 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11544 move a0, rSELF # arg0 11545 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11546 move a2, rPC 11547 la t9, MterpCheckBefore 11548 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11549 11550/* ------------------------------ */ 11551 .balign 128 11552.L_ALT_op_sub_double_2addr: /* 0xcc */ 11553/* File: mips/alt_stub.S */ 11554/* 11555 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11556 * any interesting requests and then jump to the real instruction 11557 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11558 */ 11559 .extern MterpCheckBefore 11560 la ra, artMterpAsmInstructionStart + (204 * 128) # Addr of primary handler 11561 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11562 move a0, rSELF # arg0 11563 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11564 move a2, rPC 11565 la t9, MterpCheckBefore 11566 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11567 11568/* ------------------------------ */ 11569 .balign 128 11570.L_ALT_op_mul_double_2addr: /* 0xcd */ 11571/* File: mips/alt_stub.S */ 11572/* 11573 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11574 * any interesting requests and then jump to the real instruction 11575 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11576 */ 11577 .extern MterpCheckBefore 11578 la ra, artMterpAsmInstructionStart + (205 * 128) # Addr of primary handler 11579 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11580 move a0, rSELF # arg0 11581 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11582 move a2, rPC 11583 la t9, MterpCheckBefore 11584 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11585 11586/* ------------------------------ */ 11587 .balign 128 11588.L_ALT_op_div_double_2addr: /* 0xce */ 11589/* File: mips/alt_stub.S */ 11590/* 11591 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11592 * any interesting requests and then jump to the real instruction 11593 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11594 */ 11595 .extern MterpCheckBefore 11596 la ra, artMterpAsmInstructionStart + (206 * 128) # Addr of primary handler 11597 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11598 move a0, rSELF # arg0 11599 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11600 move a2, rPC 11601 la t9, MterpCheckBefore 11602 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11603 11604/* ------------------------------ */ 11605 .balign 128 11606.L_ALT_op_rem_double_2addr: /* 0xcf */ 11607/* File: mips/alt_stub.S */ 11608/* 11609 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11610 * any interesting requests and then jump to the real instruction 11611 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11612 */ 11613 .extern MterpCheckBefore 11614 la ra, artMterpAsmInstructionStart + (207 * 128) # Addr of primary handler 11615 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11616 move a0, rSELF # arg0 11617 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11618 move a2, rPC 11619 la t9, MterpCheckBefore 11620 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11621 11622/* ------------------------------ */ 11623 .balign 128 11624.L_ALT_op_add_int_lit16: /* 0xd0 */ 11625/* File: mips/alt_stub.S */ 11626/* 11627 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11628 * any interesting requests and then jump to the real instruction 11629 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11630 */ 11631 .extern MterpCheckBefore 11632 la ra, artMterpAsmInstructionStart + (208 * 128) # Addr of primary handler 11633 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11634 move a0, rSELF # arg0 11635 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11636 move a2, rPC 11637 la t9, MterpCheckBefore 11638 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11639 11640/* ------------------------------ */ 11641 .balign 128 11642.L_ALT_op_rsub_int: /* 0xd1 */ 11643/* File: mips/alt_stub.S */ 11644/* 11645 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11646 * any interesting requests and then jump to the real instruction 11647 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11648 */ 11649 .extern MterpCheckBefore 11650 la ra, artMterpAsmInstructionStart + (209 * 128) # Addr of primary handler 11651 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11652 move a0, rSELF # arg0 11653 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11654 move a2, rPC 11655 la t9, MterpCheckBefore 11656 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11657 11658/* ------------------------------ */ 11659 .balign 128 11660.L_ALT_op_mul_int_lit16: /* 0xd2 */ 11661/* File: mips/alt_stub.S */ 11662/* 11663 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11664 * any interesting requests and then jump to the real instruction 11665 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11666 */ 11667 .extern MterpCheckBefore 11668 la ra, artMterpAsmInstructionStart + (210 * 128) # Addr of primary handler 11669 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11670 move a0, rSELF # arg0 11671 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11672 move a2, rPC 11673 la t9, MterpCheckBefore 11674 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11675 11676/* ------------------------------ */ 11677 .balign 128 11678.L_ALT_op_div_int_lit16: /* 0xd3 */ 11679/* File: mips/alt_stub.S */ 11680/* 11681 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11682 * any interesting requests and then jump to the real instruction 11683 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11684 */ 11685 .extern MterpCheckBefore 11686 la ra, artMterpAsmInstructionStart + (211 * 128) # Addr of primary handler 11687 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11688 move a0, rSELF # arg0 11689 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11690 move a2, rPC 11691 la t9, MterpCheckBefore 11692 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11693 11694/* ------------------------------ */ 11695 .balign 128 11696.L_ALT_op_rem_int_lit16: /* 0xd4 */ 11697/* File: mips/alt_stub.S */ 11698/* 11699 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11700 * any interesting requests and then jump to the real instruction 11701 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11702 */ 11703 .extern MterpCheckBefore 11704 la ra, artMterpAsmInstructionStart + (212 * 128) # Addr of primary handler 11705 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11706 move a0, rSELF # arg0 11707 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11708 move a2, rPC 11709 la t9, MterpCheckBefore 11710 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11711 11712/* ------------------------------ */ 11713 .balign 128 11714.L_ALT_op_and_int_lit16: /* 0xd5 */ 11715/* File: mips/alt_stub.S */ 11716/* 11717 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11718 * any interesting requests and then jump to the real instruction 11719 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11720 */ 11721 .extern MterpCheckBefore 11722 la ra, artMterpAsmInstructionStart + (213 * 128) # Addr of primary handler 11723 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11724 move a0, rSELF # arg0 11725 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11726 move a2, rPC 11727 la t9, MterpCheckBefore 11728 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11729 11730/* ------------------------------ */ 11731 .balign 128 11732.L_ALT_op_or_int_lit16: /* 0xd6 */ 11733/* File: mips/alt_stub.S */ 11734/* 11735 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11736 * any interesting requests and then jump to the real instruction 11737 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11738 */ 11739 .extern MterpCheckBefore 11740 la ra, artMterpAsmInstructionStart + (214 * 128) # Addr of primary handler 11741 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11742 move a0, rSELF # arg0 11743 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11744 move a2, rPC 11745 la t9, MterpCheckBefore 11746 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11747 11748/* ------------------------------ */ 11749 .balign 128 11750.L_ALT_op_xor_int_lit16: /* 0xd7 */ 11751/* File: mips/alt_stub.S */ 11752/* 11753 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11754 * any interesting requests and then jump to the real instruction 11755 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11756 */ 11757 .extern MterpCheckBefore 11758 la ra, artMterpAsmInstructionStart + (215 * 128) # Addr of primary handler 11759 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11760 move a0, rSELF # arg0 11761 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11762 move a2, rPC 11763 la t9, MterpCheckBefore 11764 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11765 11766/* ------------------------------ */ 11767 .balign 128 11768.L_ALT_op_add_int_lit8: /* 0xd8 */ 11769/* File: mips/alt_stub.S */ 11770/* 11771 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11772 * any interesting requests and then jump to the real instruction 11773 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11774 */ 11775 .extern MterpCheckBefore 11776 la ra, artMterpAsmInstructionStart + (216 * 128) # Addr of primary handler 11777 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11778 move a0, rSELF # arg0 11779 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11780 move a2, rPC 11781 la t9, MterpCheckBefore 11782 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11783 11784/* ------------------------------ */ 11785 .balign 128 11786.L_ALT_op_rsub_int_lit8: /* 0xd9 */ 11787/* File: mips/alt_stub.S */ 11788/* 11789 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11790 * any interesting requests and then jump to the real instruction 11791 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11792 */ 11793 .extern MterpCheckBefore 11794 la ra, artMterpAsmInstructionStart + (217 * 128) # Addr of primary handler 11795 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11796 move a0, rSELF # arg0 11797 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11798 move a2, rPC 11799 la t9, MterpCheckBefore 11800 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11801 11802/* ------------------------------ */ 11803 .balign 128 11804.L_ALT_op_mul_int_lit8: /* 0xda */ 11805/* File: mips/alt_stub.S */ 11806/* 11807 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11808 * any interesting requests and then jump to the real instruction 11809 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11810 */ 11811 .extern MterpCheckBefore 11812 la ra, artMterpAsmInstructionStart + (218 * 128) # Addr of primary handler 11813 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11814 move a0, rSELF # arg0 11815 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11816 move a2, rPC 11817 la t9, MterpCheckBefore 11818 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11819 11820/* ------------------------------ */ 11821 .balign 128 11822.L_ALT_op_div_int_lit8: /* 0xdb */ 11823/* File: mips/alt_stub.S */ 11824/* 11825 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11826 * any interesting requests and then jump to the real instruction 11827 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11828 */ 11829 .extern MterpCheckBefore 11830 la ra, artMterpAsmInstructionStart + (219 * 128) # Addr of primary handler 11831 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11832 move a0, rSELF # arg0 11833 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11834 move a2, rPC 11835 la t9, MterpCheckBefore 11836 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11837 11838/* ------------------------------ */ 11839 .balign 128 11840.L_ALT_op_rem_int_lit8: /* 0xdc */ 11841/* File: mips/alt_stub.S */ 11842/* 11843 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11844 * any interesting requests and then jump to the real instruction 11845 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11846 */ 11847 .extern MterpCheckBefore 11848 la ra, artMterpAsmInstructionStart + (220 * 128) # Addr of primary handler 11849 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11850 move a0, rSELF # arg0 11851 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11852 move a2, rPC 11853 la t9, MterpCheckBefore 11854 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11855 11856/* ------------------------------ */ 11857 .balign 128 11858.L_ALT_op_and_int_lit8: /* 0xdd */ 11859/* File: mips/alt_stub.S */ 11860/* 11861 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11862 * any interesting requests and then jump to the real instruction 11863 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11864 */ 11865 .extern MterpCheckBefore 11866 la ra, artMterpAsmInstructionStart + (221 * 128) # Addr of primary handler 11867 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11868 move a0, rSELF # arg0 11869 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11870 move a2, rPC 11871 la t9, MterpCheckBefore 11872 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11873 11874/* ------------------------------ */ 11875 .balign 128 11876.L_ALT_op_or_int_lit8: /* 0xde */ 11877/* File: mips/alt_stub.S */ 11878/* 11879 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11880 * any interesting requests and then jump to the real instruction 11881 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11882 */ 11883 .extern MterpCheckBefore 11884 la ra, artMterpAsmInstructionStart + (222 * 128) # Addr of primary handler 11885 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11886 move a0, rSELF # arg0 11887 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11888 move a2, rPC 11889 la t9, MterpCheckBefore 11890 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11891 11892/* ------------------------------ */ 11893 .balign 128 11894.L_ALT_op_xor_int_lit8: /* 0xdf */ 11895/* File: mips/alt_stub.S */ 11896/* 11897 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11898 * any interesting requests and then jump to the real instruction 11899 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11900 */ 11901 .extern MterpCheckBefore 11902 la ra, artMterpAsmInstructionStart + (223 * 128) # Addr of primary handler 11903 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11904 move a0, rSELF # arg0 11905 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11906 move a2, rPC 11907 la t9, MterpCheckBefore 11908 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11909 11910/* ------------------------------ */ 11911 .balign 128 11912.L_ALT_op_shl_int_lit8: /* 0xe0 */ 11913/* File: mips/alt_stub.S */ 11914/* 11915 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11916 * any interesting requests and then jump to the real instruction 11917 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11918 */ 11919 .extern MterpCheckBefore 11920 la ra, artMterpAsmInstructionStart + (224 * 128) # Addr of primary handler 11921 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11922 move a0, rSELF # arg0 11923 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11924 move a2, rPC 11925 la t9, MterpCheckBefore 11926 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11927 11928/* ------------------------------ */ 11929 .balign 128 11930.L_ALT_op_shr_int_lit8: /* 0xe1 */ 11931/* File: mips/alt_stub.S */ 11932/* 11933 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11934 * any interesting requests and then jump to the real instruction 11935 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11936 */ 11937 .extern MterpCheckBefore 11938 la ra, artMterpAsmInstructionStart + (225 * 128) # Addr of primary handler 11939 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11940 move a0, rSELF # arg0 11941 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11942 move a2, rPC 11943 la t9, MterpCheckBefore 11944 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11945 11946/* ------------------------------ */ 11947 .balign 128 11948.L_ALT_op_ushr_int_lit8: /* 0xe2 */ 11949/* File: mips/alt_stub.S */ 11950/* 11951 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11952 * any interesting requests and then jump to the real instruction 11953 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11954 */ 11955 .extern MterpCheckBefore 11956 la ra, artMterpAsmInstructionStart + (226 * 128) # Addr of primary handler 11957 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11958 move a0, rSELF # arg0 11959 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11960 move a2, rPC 11961 la t9, MterpCheckBefore 11962 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11963 11964/* ------------------------------ */ 11965 .balign 128 11966.L_ALT_op_iget_quick: /* 0xe3 */ 11967/* File: mips/alt_stub.S */ 11968/* 11969 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11970 * any interesting requests and then jump to the real instruction 11971 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11972 */ 11973 .extern MterpCheckBefore 11974 la ra, artMterpAsmInstructionStart + (227 * 128) # Addr of primary handler 11975 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11976 move a0, rSELF # arg0 11977 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11978 move a2, rPC 11979 la t9, MterpCheckBefore 11980 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11981 11982/* ------------------------------ */ 11983 .balign 128 11984.L_ALT_op_iget_wide_quick: /* 0xe4 */ 11985/* File: mips/alt_stub.S */ 11986/* 11987 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11988 * any interesting requests and then jump to the real instruction 11989 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11990 */ 11991 .extern MterpCheckBefore 11992 la ra, artMterpAsmInstructionStart + (228 * 128) # Addr of primary handler 11993 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 11994 move a0, rSELF # arg0 11995 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 11996 move a2, rPC 11997 la t9, MterpCheckBefore 11998 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 11999 12000/* ------------------------------ */ 12001 .balign 128 12002.L_ALT_op_iget_object_quick: /* 0xe5 */ 12003/* File: mips/alt_stub.S */ 12004/* 12005 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12006 * any interesting requests and then jump to the real instruction 12007 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12008 */ 12009 .extern MterpCheckBefore 12010 la ra, artMterpAsmInstructionStart + (229 * 128) # Addr of primary handler 12011 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12012 move a0, rSELF # arg0 12013 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12014 move a2, rPC 12015 la t9, MterpCheckBefore 12016 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12017 12018/* ------------------------------ */ 12019 .balign 128 12020.L_ALT_op_iput_quick: /* 0xe6 */ 12021/* File: mips/alt_stub.S */ 12022/* 12023 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12024 * any interesting requests and then jump to the real instruction 12025 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12026 */ 12027 .extern MterpCheckBefore 12028 la ra, artMterpAsmInstructionStart + (230 * 128) # Addr of primary handler 12029 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12030 move a0, rSELF # arg0 12031 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12032 move a2, rPC 12033 la t9, MterpCheckBefore 12034 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12035 12036/* ------------------------------ */ 12037 .balign 128 12038.L_ALT_op_iput_wide_quick: /* 0xe7 */ 12039/* File: mips/alt_stub.S */ 12040/* 12041 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12042 * any interesting requests and then jump to the real instruction 12043 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12044 */ 12045 .extern MterpCheckBefore 12046 la ra, artMterpAsmInstructionStart + (231 * 128) # Addr of primary handler 12047 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12048 move a0, rSELF # arg0 12049 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12050 move a2, rPC 12051 la t9, MterpCheckBefore 12052 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12053 12054/* ------------------------------ */ 12055 .balign 128 12056.L_ALT_op_iput_object_quick: /* 0xe8 */ 12057/* File: mips/alt_stub.S */ 12058/* 12059 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12060 * any interesting requests and then jump to the real instruction 12061 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12062 */ 12063 .extern MterpCheckBefore 12064 la ra, artMterpAsmInstructionStart + (232 * 128) # Addr of primary handler 12065 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12066 move a0, rSELF # arg0 12067 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12068 move a2, rPC 12069 la t9, MterpCheckBefore 12070 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12071 12072/* ------------------------------ */ 12073 .balign 128 12074.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ 12075/* File: mips/alt_stub.S */ 12076/* 12077 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12078 * any interesting requests and then jump to the real instruction 12079 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12080 */ 12081 .extern MterpCheckBefore 12082 la ra, artMterpAsmInstructionStart + (233 * 128) # Addr of primary handler 12083 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12084 move a0, rSELF # arg0 12085 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12086 move a2, rPC 12087 la t9, MterpCheckBefore 12088 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12089 12090/* ------------------------------ */ 12091 .balign 128 12092.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ 12093/* File: mips/alt_stub.S */ 12094/* 12095 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12096 * any interesting requests and then jump to the real instruction 12097 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12098 */ 12099 .extern MterpCheckBefore 12100 la ra, artMterpAsmInstructionStart + (234 * 128) # Addr of primary handler 12101 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12102 move a0, rSELF # arg0 12103 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12104 move a2, rPC 12105 la t9, MterpCheckBefore 12106 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12107 12108/* ------------------------------ */ 12109 .balign 128 12110.L_ALT_op_iput_boolean_quick: /* 0xeb */ 12111/* File: mips/alt_stub.S */ 12112/* 12113 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12114 * any interesting requests and then jump to the real instruction 12115 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12116 */ 12117 .extern MterpCheckBefore 12118 la ra, artMterpAsmInstructionStart + (235 * 128) # Addr of primary handler 12119 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12120 move a0, rSELF # arg0 12121 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12122 move a2, rPC 12123 la t9, MterpCheckBefore 12124 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12125 12126/* ------------------------------ */ 12127 .balign 128 12128.L_ALT_op_iput_byte_quick: /* 0xec */ 12129/* File: mips/alt_stub.S */ 12130/* 12131 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12132 * any interesting requests and then jump to the real instruction 12133 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12134 */ 12135 .extern MterpCheckBefore 12136 la ra, artMterpAsmInstructionStart + (236 * 128) # Addr of primary handler 12137 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12138 move a0, rSELF # arg0 12139 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12140 move a2, rPC 12141 la t9, MterpCheckBefore 12142 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12143 12144/* ------------------------------ */ 12145 .balign 128 12146.L_ALT_op_iput_char_quick: /* 0xed */ 12147/* File: mips/alt_stub.S */ 12148/* 12149 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12150 * any interesting requests and then jump to the real instruction 12151 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12152 */ 12153 .extern MterpCheckBefore 12154 la ra, artMterpAsmInstructionStart + (237 * 128) # Addr of primary handler 12155 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12156 move a0, rSELF # arg0 12157 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12158 move a2, rPC 12159 la t9, MterpCheckBefore 12160 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12161 12162/* ------------------------------ */ 12163 .balign 128 12164.L_ALT_op_iput_short_quick: /* 0xee */ 12165/* File: mips/alt_stub.S */ 12166/* 12167 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12168 * any interesting requests and then jump to the real instruction 12169 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12170 */ 12171 .extern MterpCheckBefore 12172 la ra, artMterpAsmInstructionStart + (238 * 128) # Addr of primary handler 12173 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12174 move a0, rSELF # arg0 12175 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12176 move a2, rPC 12177 la t9, MterpCheckBefore 12178 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12179 12180/* ------------------------------ */ 12181 .balign 128 12182.L_ALT_op_iget_boolean_quick: /* 0xef */ 12183/* File: mips/alt_stub.S */ 12184/* 12185 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12186 * any interesting requests and then jump to the real instruction 12187 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12188 */ 12189 .extern MterpCheckBefore 12190 la ra, artMterpAsmInstructionStart + (239 * 128) # Addr of primary handler 12191 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12192 move a0, rSELF # arg0 12193 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12194 move a2, rPC 12195 la t9, MterpCheckBefore 12196 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12197 12198/* ------------------------------ */ 12199 .balign 128 12200.L_ALT_op_iget_byte_quick: /* 0xf0 */ 12201/* File: mips/alt_stub.S */ 12202/* 12203 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12204 * any interesting requests and then jump to the real instruction 12205 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12206 */ 12207 .extern MterpCheckBefore 12208 la ra, artMterpAsmInstructionStart + (240 * 128) # Addr of primary handler 12209 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12210 move a0, rSELF # arg0 12211 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12212 move a2, rPC 12213 la t9, MterpCheckBefore 12214 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12215 12216/* ------------------------------ */ 12217 .balign 128 12218.L_ALT_op_iget_char_quick: /* 0xf1 */ 12219/* File: mips/alt_stub.S */ 12220/* 12221 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12222 * any interesting requests and then jump to the real instruction 12223 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12224 */ 12225 .extern MterpCheckBefore 12226 la ra, artMterpAsmInstructionStart + (241 * 128) # Addr of primary handler 12227 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12228 move a0, rSELF # arg0 12229 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12230 move a2, rPC 12231 la t9, MterpCheckBefore 12232 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12233 12234/* ------------------------------ */ 12235 .balign 128 12236.L_ALT_op_iget_short_quick: /* 0xf2 */ 12237/* File: mips/alt_stub.S */ 12238/* 12239 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12240 * any interesting requests and then jump to the real instruction 12241 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12242 */ 12243 .extern MterpCheckBefore 12244 la ra, artMterpAsmInstructionStart + (242 * 128) # Addr of primary handler 12245 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12246 move a0, rSELF # arg0 12247 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12248 move a2, rPC 12249 la t9, MterpCheckBefore 12250 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12251 12252/* ------------------------------ */ 12253 .balign 128 12254.L_ALT_op_unused_f3: /* 0xf3 */ 12255/* File: mips/alt_stub.S */ 12256/* 12257 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12258 * any interesting requests and then jump to the real instruction 12259 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12260 */ 12261 .extern MterpCheckBefore 12262 la ra, artMterpAsmInstructionStart + (243 * 128) # Addr of primary handler 12263 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12264 move a0, rSELF # arg0 12265 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12266 move a2, rPC 12267 la t9, MterpCheckBefore 12268 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12269 12270/* ------------------------------ */ 12271 .balign 128 12272.L_ALT_op_unused_f4: /* 0xf4 */ 12273/* File: mips/alt_stub.S */ 12274/* 12275 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12276 * any interesting requests and then jump to the real instruction 12277 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12278 */ 12279 .extern MterpCheckBefore 12280 la ra, artMterpAsmInstructionStart + (244 * 128) # Addr of primary handler 12281 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12282 move a0, rSELF # arg0 12283 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12284 move a2, rPC 12285 la t9, MterpCheckBefore 12286 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12287 12288/* ------------------------------ */ 12289 .balign 128 12290.L_ALT_op_unused_f5: /* 0xf5 */ 12291/* File: mips/alt_stub.S */ 12292/* 12293 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12294 * any interesting requests and then jump to the real instruction 12295 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12296 */ 12297 .extern MterpCheckBefore 12298 la ra, artMterpAsmInstructionStart + (245 * 128) # Addr of primary handler 12299 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12300 move a0, rSELF # arg0 12301 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12302 move a2, rPC 12303 la t9, MterpCheckBefore 12304 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12305 12306/* ------------------------------ */ 12307 .balign 128 12308.L_ALT_op_unused_f6: /* 0xf6 */ 12309/* File: mips/alt_stub.S */ 12310/* 12311 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12312 * any interesting requests and then jump to the real instruction 12313 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12314 */ 12315 .extern MterpCheckBefore 12316 la ra, artMterpAsmInstructionStart + (246 * 128) # Addr of primary handler 12317 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12318 move a0, rSELF # arg0 12319 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12320 move a2, rPC 12321 la t9, MterpCheckBefore 12322 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12323 12324/* ------------------------------ */ 12325 .balign 128 12326.L_ALT_op_unused_f7: /* 0xf7 */ 12327/* File: mips/alt_stub.S */ 12328/* 12329 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12330 * any interesting requests and then jump to the real instruction 12331 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12332 */ 12333 .extern MterpCheckBefore 12334 la ra, artMterpAsmInstructionStart + (247 * 128) # Addr of primary handler 12335 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12336 move a0, rSELF # arg0 12337 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12338 move a2, rPC 12339 la t9, MterpCheckBefore 12340 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12341 12342/* ------------------------------ */ 12343 .balign 128 12344.L_ALT_op_unused_f8: /* 0xf8 */ 12345/* File: mips/alt_stub.S */ 12346/* 12347 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12348 * any interesting requests and then jump to the real instruction 12349 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12350 */ 12351 .extern MterpCheckBefore 12352 la ra, artMterpAsmInstructionStart + (248 * 128) # Addr of primary handler 12353 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12354 move a0, rSELF # arg0 12355 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12356 move a2, rPC 12357 la t9, MterpCheckBefore 12358 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12359 12360/* ------------------------------ */ 12361 .balign 128 12362.L_ALT_op_unused_f9: /* 0xf9 */ 12363/* File: mips/alt_stub.S */ 12364/* 12365 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12366 * any interesting requests and then jump to the real instruction 12367 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12368 */ 12369 .extern MterpCheckBefore 12370 la ra, artMterpAsmInstructionStart + (249 * 128) # Addr of primary handler 12371 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12372 move a0, rSELF # arg0 12373 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12374 move a2, rPC 12375 la t9, MterpCheckBefore 12376 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12377 12378/* ------------------------------ */ 12379 .balign 128 12380.L_ALT_op_invoke_polymorphic: /* 0xfa */ 12381/* File: mips/alt_stub.S */ 12382/* 12383 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12384 * any interesting requests and then jump to the real instruction 12385 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12386 */ 12387 .extern MterpCheckBefore 12388 la ra, artMterpAsmInstructionStart + (250 * 128) # Addr of primary handler 12389 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12390 move a0, rSELF # arg0 12391 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12392 move a2, rPC 12393 la t9, MterpCheckBefore 12394 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12395 12396/* ------------------------------ */ 12397 .balign 128 12398.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ 12399/* File: mips/alt_stub.S */ 12400/* 12401 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12402 * any interesting requests and then jump to the real instruction 12403 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12404 */ 12405 .extern MterpCheckBefore 12406 la ra, artMterpAsmInstructionStart + (251 * 128) # Addr of primary handler 12407 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12408 move a0, rSELF # arg0 12409 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12410 move a2, rPC 12411 la t9, MterpCheckBefore 12412 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12413 12414/* ------------------------------ */ 12415 .balign 128 12416.L_ALT_op_invoke_custom: /* 0xfc */ 12417/* File: mips/alt_stub.S */ 12418/* 12419 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12420 * any interesting requests and then jump to the real instruction 12421 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12422 */ 12423 .extern MterpCheckBefore 12424 la ra, artMterpAsmInstructionStart + (252 * 128) # Addr of primary handler 12425 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12426 move a0, rSELF # arg0 12427 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12428 move a2, rPC 12429 la t9, MterpCheckBefore 12430 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12431 12432/* ------------------------------ */ 12433 .balign 128 12434.L_ALT_op_invoke_custom_range: /* 0xfd */ 12435/* File: mips/alt_stub.S */ 12436/* 12437 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12438 * any interesting requests and then jump to the real instruction 12439 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12440 */ 12441 .extern MterpCheckBefore 12442 la ra, artMterpAsmInstructionStart + (253 * 128) # Addr of primary handler 12443 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12444 move a0, rSELF # arg0 12445 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12446 move a2, rPC 12447 la t9, MterpCheckBefore 12448 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12449 12450/* ------------------------------ */ 12451 .balign 128 12452.L_ALT_op_unused_fe: /* 0xfe */ 12453/* File: mips/alt_stub.S */ 12454/* 12455 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12456 * any interesting requests and then jump to the real instruction 12457 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12458 */ 12459 .extern MterpCheckBefore 12460 la ra, artMterpAsmInstructionStart + (254 * 128) # Addr of primary handler 12461 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12462 move a0, rSELF # arg0 12463 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12464 move a2, rPC 12465 la t9, MterpCheckBefore 12466 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12467 12468/* ------------------------------ */ 12469 .balign 128 12470.L_ALT_op_unused_ff: /* 0xff */ 12471/* File: mips/alt_stub.S */ 12472/* 12473 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12474 * any interesting requests and then jump to the real instruction 12475 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12476 */ 12477 .extern MterpCheckBefore 12478 la ra, artMterpAsmInstructionStart + (255 * 128) # Addr of primary handler 12479 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) # refresh IBASE 12480 move a0, rSELF # arg0 12481 addu a1, rFP, OFF_FP_SHADOWFRAME # arg1 12482 move a2, rPC 12483 la t9, MterpCheckBefore 12484 jalr zero, t9 # Tail call to Mterp(self, shadow_frame, dex_pc_ptr) 12485 12486 .balign 128 12487 .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart 12488 .global artMterpAsmAltInstructionEnd 12489artMterpAsmAltInstructionEnd: 12490/* File: mips/footer.S */ 12491/* 12492 * =========================================================================== 12493 * Common subroutines and data 12494 * =========================================================================== 12495 */ 12496 12497 .text 12498 .align 2 12499 12500/* 12501 * We've detected a condition that will result in an exception, but the exception 12502 * has not yet been thrown. Just bail out to the reference interpreter to deal with it. 12503 * TUNING: for consistency, we may want to just go ahead and handle these here. 12504 */ 12505common_errDivideByZero: 12506 EXPORT_PC() 12507#if MTERP_LOGGING 12508 move a0, rSELF 12509 addu a1, rFP, OFF_FP_SHADOWFRAME 12510 JAL(MterpLogDivideByZeroException) 12511#endif 12512 b MterpCommonFallback 12513 12514common_errArrayIndex: 12515 EXPORT_PC() 12516#if MTERP_LOGGING 12517 move a0, rSELF 12518 addu a1, rFP, OFF_FP_SHADOWFRAME 12519 JAL(MterpLogArrayIndexException) 12520#endif 12521 b MterpCommonFallback 12522 12523common_errNegativeArraySize: 12524 EXPORT_PC() 12525#if MTERP_LOGGING 12526 move a0, rSELF 12527 addu a1, rFP, OFF_FP_SHADOWFRAME 12528 JAL(MterpLogNegativeArraySizeException) 12529#endif 12530 b MterpCommonFallback 12531 12532common_errNoSuchMethod: 12533 EXPORT_PC() 12534#if MTERP_LOGGING 12535 move a0, rSELF 12536 addu a1, rFP, OFF_FP_SHADOWFRAME 12537 JAL(MterpLogNoSuchMethodException) 12538#endif 12539 b MterpCommonFallback 12540 12541common_errNullObject: 12542 EXPORT_PC() 12543#if MTERP_LOGGING 12544 move a0, rSELF 12545 addu a1, rFP, OFF_FP_SHADOWFRAME 12546 JAL(MterpLogNullObjectException) 12547#endif 12548 b MterpCommonFallback 12549 12550common_exceptionThrown: 12551 EXPORT_PC() 12552#if MTERP_LOGGING 12553 move a0, rSELF 12554 addu a1, rFP, OFF_FP_SHADOWFRAME 12555 JAL(MterpLogExceptionThrownException) 12556#endif 12557 b MterpCommonFallback 12558 12559MterpSuspendFallback: 12560 EXPORT_PC() 12561#if MTERP_LOGGING 12562 move a0, rSELF 12563 addu a1, rFP, OFF_FP_SHADOWFRAME 12564 lw a2, THREAD_FLAGS_OFFSET(rSELF) 12565 JAL(MterpLogSuspendFallback) 12566#endif 12567 b MterpCommonFallback 12568 12569/* 12570 * If we're here, something is out of the ordinary. If there is a pending 12571 * exception, handle it. Otherwise, roll back and retry with the reference 12572 * interpreter. 12573 */ 12574MterpPossibleException: 12575 lw a0, THREAD_EXCEPTION_OFFSET(rSELF) 12576 beqz a0, MterpFallback # If exception, fall back to reference interpreter. 12577 /* intentional fallthrough - handle pending exception. */ 12578/* 12579 * On return from a runtime helper routine, we've found a pending exception. 12580 * Can we handle it here - or need to bail out to caller? 12581 * 12582 */ 12583MterpException: 12584 move a0, rSELF 12585 addu a1, rFP, OFF_FP_SHADOWFRAME 12586 JAL(MterpHandleException) # (self, shadow_frame) 12587 beqz v0, MterpExceptionReturn # no local catch, back to caller. 12588 lw a0, OFF_FP_CODE_ITEM(rFP) 12589 lw a1, OFF_FP_DEX_PC(rFP) 12590 lw rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) 12591 addu rPC, a0, CODEITEM_INSNS_OFFSET 12592 sll a1, a1, 1 12593 addu rPC, rPC, a1 # generate new dex_pc_ptr 12594 /* Do we need to switch interpreters? */ 12595 JAL(MterpShouldSwitchInterpreters) 12596 bnez v0, MterpFallback 12597 /* resume execution at catch block */ 12598 EXPORT_PC() 12599 FETCH_INST() 12600 GET_INST_OPCODE(t0) 12601 GOTO_OPCODE(t0) 12602 /* NOTE: no fallthrough */ 12603 12604/* 12605 * Common handling for branches with support for Jit profiling. 12606 * On entry: 12607 * rINST <= signed offset 12608 * rPROFILE <= signed hotness countdown (expanded to 32 bits) 12609 * 12610 * We have quite a few different cases for branch profiling, OSR detection and 12611 * suspend check support here. 12612 * 12613 * Taken backward branches: 12614 * If profiling active, do hotness countdown and report if we hit zero. 12615 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 12616 * Is there a pending suspend request? If so, suspend. 12617 * 12618 * Taken forward branches and not-taken backward branches: 12619 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 12620 * 12621 * Our most common case is expected to be a taken backward branch with active jit profiling, 12622 * but no full OSR check and no pending suspend request. 12623 * Next most common case is not-taken branch with no full OSR check. 12624 */ 12625MterpCommonTakenBranchNoFlags: 12626 bgtz rINST, .L_forward_branch # don't add forward branches to hotness 12627/* 12628 * We need to subtract 1 from positive values and we should not see 0 here, 12629 * so we may use the result of the comparison with -1. 12630 */ 12631#if JIT_CHECK_OSR != -1 12632# error "JIT_CHECK_OSR must be -1." 12633#endif 12634 li t0, JIT_CHECK_OSR 12635 beq rPROFILE, t0, .L_osr_check 12636 blt rPROFILE, t0, .L_resume_backward_branch 12637 subu rPROFILE, 1 12638 beqz rPROFILE, .L_add_batch # counted down to zero - report 12639.L_resume_backward_branch: 12640 lw ra, THREAD_FLAGS_OFFSET(rSELF) 12641 REFRESH_IBASE() 12642 addu a2, rINST, rINST # a2<- byte offset 12643 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 12644 and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 12645 bnez ra, .L_suspend_request_pending 12646 GET_INST_OPCODE(t0) # extract opcode from rINST 12647 GOTO_OPCODE(t0) # jump to next instruction 12648 12649.L_suspend_request_pending: 12650 EXPORT_PC() 12651 move a0, rSELF 12652 JAL(MterpSuspendCheck) # (self) 12653 bnez v0, MterpFallback 12654 REFRESH_IBASE() # might have changed during suspend 12655 GET_INST_OPCODE(t0) # extract opcode from rINST 12656 GOTO_OPCODE(t0) # jump to next instruction 12657 12658.L_no_count_backwards: 12659 li t0, JIT_CHECK_OSR # check for possible OSR re-entry 12660 bne rPROFILE, t0, .L_resume_backward_branch 12661.L_osr_check: 12662 move a0, rSELF 12663 addu a1, rFP, OFF_FP_SHADOWFRAME 12664 move a2, rINST 12665 EXPORT_PC() 12666 JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) 12667 bnez v0, MterpOnStackReplacement 12668 b .L_resume_backward_branch 12669 12670.L_forward_branch: 12671 li t0, JIT_CHECK_OSR # check for possible OSR re-entry 12672 beq rPROFILE, t0, .L_check_osr_forward 12673.L_resume_forward_branch: 12674 add a2, rINST, rINST # a2<- byte offset 12675 FETCH_ADVANCE_INST_RB(a2) # update rPC, load rINST 12676 GET_INST_OPCODE(t0) # extract opcode from rINST 12677 GOTO_OPCODE(t0) # jump to next instruction 12678 12679.L_check_osr_forward: 12680 move a0, rSELF 12681 addu a1, rFP, OFF_FP_SHADOWFRAME 12682 move a2, rINST 12683 EXPORT_PC() 12684 JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) 12685 bnez v0, MterpOnStackReplacement 12686 b .L_resume_forward_branch 12687 12688.L_add_batch: 12689 addu a1, rFP, OFF_FP_SHADOWFRAME 12690 sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) 12691 lw a0, OFF_FP_METHOD(rFP) 12692 move a2, rSELF 12693 JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) 12694 move rPROFILE, v0 # restore new hotness countdown to rPROFILE 12695 b .L_no_count_backwards 12696 12697/* 12698 * Entered from the conditional branch handlers when OSR check request active on 12699 * not-taken path. All Dalvik not-taken conditional branch offsets are 2. 12700 */ 12701.L_check_not_taken_osr: 12702 move a0, rSELF 12703 addu a1, rFP, OFF_FP_SHADOWFRAME 12704 li a2, 2 12705 EXPORT_PC() 12706 JAL(MterpMaybeDoOnStackReplacement) # (self, shadow_frame, offset) 12707 bnez v0, MterpOnStackReplacement 12708 FETCH_ADVANCE_INST(2) 12709 GET_INST_OPCODE(t0) # extract opcode from rINST 12710 GOTO_OPCODE(t0) # jump to next instruction 12711 12712/* 12713 * On-stack replacement has happened, and now we've returned from the compiled method. 12714 */ 12715MterpOnStackReplacement: 12716#if MTERP_LOGGING 12717 move a0, rSELF 12718 addu a1, rFP, OFF_FP_SHADOWFRAME 12719 move a2, rINST 12720 JAL(MterpLogOSR) 12721#endif 12722 li v0, 1 # Signal normal return 12723 b MterpDone 12724 12725/* 12726 * Bail out to reference interpreter. 12727 */ 12728MterpFallback: 12729 EXPORT_PC() 12730#if MTERP_LOGGING 12731 move a0, rSELF 12732 addu a1, rFP, OFF_FP_SHADOWFRAME 12733 JAL(MterpLogFallback) 12734#endif 12735MterpCommonFallback: 12736 move v0, zero # signal retry with reference interpreter. 12737 b MterpDone 12738/* 12739 * We pushed some registers on the stack in ExecuteMterpImpl, then saved 12740 * SP and LR. Here we restore SP, restore the registers, and then restore 12741 * LR to PC. 12742 * 12743 * On entry: 12744 * uint32_t* rFP (should still be live, pointer to base of vregs) 12745 */ 12746MterpExceptionReturn: 12747 li v0, 1 # signal return to caller. 12748 b MterpDone 12749MterpReturn: 12750 lw a2, OFF_FP_RESULT_REGISTER(rFP) 12751 sw v0, 0(a2) 12752 sw v1, 4(a2) 12753 li v0, 1 # signal return to caller. 12754MterpDone: 12755/* 12756 * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're 12757 * checking for OSR. If greater than zero, we might have unreported hotness to register 12758 * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE 12759 * should only reach zero immediately after a hotness decrement, and is then reset to either 12760 * a negative special state or the new non-zero countdown value. 12761 */ 12762 blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. 12763 12764MterpProfileActive: 12765 move rINST, v0 # stash return value 12766 /* Report cached hotness counts */ 12767 lw a0, OFF_FP_METHOD(rFP) 12768 addu a1, rFP, OFF_FP_SHADOWFRAME 12769 move a2, rSELF 12770 sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) 12771 JAL(MterpAddHotnessBatch) # (method, shadow_frame, self) 12772 move v0, rINST # restore return value 12773 12774.L_pop_and_return: 12775/* Restore from the stack and return. Frame size = STACK_SIZE */ 12776 STACK_LOAD_FULL() 12777 jalr zero, ra 12778 12779 .end ExecuteMterpImpl 12780 12781