1/* 2 * This file was generated automatically by gen-mterp.py for 'mips64'. 3 * 4 * --> DO NOT EDIT <-- 5 */ 6 7/* File: mips64/header.S */ 8/* 9 * Copyright (C) 2016 The Android Open Source Project 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); 12 * you may not use this file except in compliance with the License. 13 * You may obtain a copy of the License at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an "AS IS" BASIS, 19 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 */ 23 24#include <machine/regdef.h> 25 26/* TODO: add the missing file and use its FP register definitions. */ 27/* #include <machine/fpregdef.h> */ 28/* FP register definitions */ 29#define f0 $f0 30#define f1 $f1 31#define f2 $f2 32#define f3 $f3 33#define f12 $f12 34#define f13 $f13 35 36/* 37 * It looks like the GNU assembler currently does not support the blec and bgtc 38 * idioms, which should translate into bgec and bltc respectively with swapped 39 * left and right register operands. 40 * TODO: remove these macros when the assembler is fixed. 41 */ 42.macro blec lreg, rreg, target 43 bgec \rreg, \lreg, \target 44.endm 45.macro bgtc lreg, rreg, target 46 bltc \rreg, \lreg, \target 47.endm 48 49/* 50Mterp and MIPS64 notes: 51 52The following registers have fixed assignments: 53 54 reg nick purpose 55 s0 rPC interpreted program counter, used for fetching instructions 56 s1 rFP interpreted frame pointer, used for accessing locals and args 57 s2 rSELF self (Thread) pointer 58 s3 rINST first 16-bit code unit of current instruction 59 s4 rIBASE interpreted instruction base pointer, used for computed goto 60 s5 rREFS base of object references in shadow frame (ideally, we'll get rid of this later). 61 s6 rPROFILE jit profile hotness countdown 62*/ 63 64/* During bringup, we'll use the shadow frame model instead of rFP */ 65/* single-purpose registers, given names for clarity */ 66#define rPC s0 67#define rFP s1 68#define rSELF s2 69#define rINST s3 70#define rIBASE s4 71#define rREFS s5 72#define rPROFILE s6 73 74/* 75 * This is a #include, not a %include, because we want the C pre-processor 76 * to expand the macros into assembler assignment statements. 77 */ 78#include "asm_support.h" 79 80/* 81 * Instead of holding a pointer to the shadow frame, we keep rFP at the base of the vregs. So, 82 * to access other shadow frame fields, we need to use a backwards offset. Define those here. 83 */ 84#define OFF_FP(a) (a - SHADOWFRAME_VREGS_OFFSET) 85#define OFF_FP_NUMBER_OF_VREGS OFF_FP(SHADOWFRAME_NUMBER_OF_VREGS_OFFSET) 86#define OFF_FP_DEX_PC OFF_FP(SHADOWFRAME_DEX_PC_OFFSET) 87#define OFF_FP_LINK OFF_FP(SHADOWFRAME_LINK_OFFSET) 88#define OFF_FP_METHOD OFF_FP(SHADOWFRAME_METHOD_OFFSET) 89#define OFF_FP_RESULT_REGISTER OFF_FP(SHADOWFRAME_RESULT_REGISTER_OFFSET) 90#define OFF_FP_DEX_PC_PTR OFF_FP(SHADOWFRAME_DEX_PC_PTR_OFFSET) 91#define OFF_FP_CODE_ITEM OFF_FP(SHADOWFRAME_CODE_ITEM_OFFSET) 92#define OFF_FP_SHADOWFRAME OFF_FP(0) 93 94#define MTERP_PROFILE_BRANCHES 1 95#define MTERP_LOGGING 0 96 97/* 98 * "export" the PC to dex_pc field in the shadow frame, f/b/o future exception objects. Must 99 * be done *before* something throws. 100 * 101 * It's okay to do this more than once. 102 * 103 * NOTE: the fast interpreter keeps track of dex pc as a direct pointer to the mapped 104 * dex byte codes. However, the rest of the runtime expects dex pc to be an instruction 105 * offset into the code_items_[] array. For effiency, we will "export" the 106 * current dex pc as a direct pointer using the EXPORT_PC macro, and rely on GetDexPC 107 * to convert to a dex pc when needed. 108 */ 109.macro EXPORT_PC 110 sd rPC, OFF_FP_DEX_PC_PTR(rFP) 111.endm 112 113/* 114 * Refresh handler table. 115 */ 116.macro REFRESH_IBASE 117 ld rIBASE, THREAD_CURRENT_IBASE_OFFSET(rSELF) 118.endm 119 120/* 121 * Fetch the next instruction from rPC into rINST. Does not advance rPC. 122 */ 123.macro FETCH_INST 124 lhu rINST, 0(rPC) 125.endm 126 127/* Advance rPC by some number of code units. */ 128.macro ADVANCE count 129 daddu rPC, rPC, (\count) * 2 130.endm 131 132/* 133 * Fetch the next instruction from an offset specified by _reg and advance xPC. 134 * xPC to point to the next instruction. "_reg" must specify the distance 135 * in bytes, *not* 16-bit code units, and may be a signed value. Must not set flags. 136 * 137 */ 138.macro FETCH_ADVANCE_INST_RB reg 139 daddu rPC, rPC, \reg 140 FETCH_INST 141.endm 142 143/* 144 * Fetch the next instruction from the specified offset. Advances rPC 145 * to point to the next instruction. 146 * 147 * This must come AFTER anything that can throw an exception, or the 148 * exception catch may miss. (This also implies that it must come after 149 * EXPORT_PC.) 150 */ 151.macro FETCH_ADVANCE_INST count 152 ADVANCE \count 153 FETCH_INST 154.endm 155 156/* 157 * Similar to FETCH_ADVANCE_INST, but does not update rPC. Used to load 158 * rINST ahead of possible exception point. Be sure to manually advance rPC 159 * later. 160 */ 161.macro PREFETCH_INST count 162 lhu rINST, ((\count) * 2)(rPC) 163.endm 164 165/* 166 * Put the instruction's opcode field into the specified register. 167 */ 168.macro GET_INST_OPCODE reg 169 and \reg, rINST, 255 170.endm 171 172/* 173 * Begin executing the opcode in _reg. 174 */ 175.macro GOTO_OPCODE reg 176 .set noat 177 sll AT, \reg, 7 178 daddu AT, rIBASE, AT 179 jic AT, 0 180 .set at 181.endm 182 183/* 184 * Get/set the 32-bit value from a Dalvik register. 185 * Note, GET_VREG does sign extension to 64 bits while 186 * GET_VREG_U does zero extension to 64 bits. 187 * One is useful for arithmetic while the other is 188 * useful for storing the result value as 64-bit. 189 */ 190.macro GET_VREG reg, vreg 191 .set noat 192 dlsa AT, \vreg, rFP, 2 193 lw \reg, 0(AT) 194 .set at 195.endm 196.macro GET_VREG_U reg, vreg 197 .set noat 198 dlsa AT, \vreg, rFP, 2 199 lwu \reg, 0(AT) 200 .set at 201.endm 202.macro GET_VREG_FLOAT reg, vreg 203 .set noat 204 dlsa AT, \vreg, rFP, 2 205 lwc1 \reg, 0(AT) 206 .set at 207.endm 208.macro SET_VREG reg, vreg 209 .set noat 210 dlsa AT, \vreg, rFP, 2 211 sw \reg, 0(AT) 212 dlsa AT, \vreg, rREFS, 2 213 sw zero, 0(AT) 214 .set at 215.endm 216.macro SET_VREG_OBJECT reg, vreg 217 .set noat 218 dlsa AT, \vreg, rFP, 2 219 sw \reg, 0(AT) 220 dlsa AT, \vreg, rREFS, 2 221 sw \reg, 0(AT) 222 .set at 223.endm 224.macro SET_VREG_FLOAT reg, vreg 225 .set noat 226 dlsa AT, \vreg, rFP, 2 227 swc1 \reg, 0(AT) 228 dlsa AT, \vreg, rREFS, 2 229 sw zero, 0(AT) 230 .set at 231.endm 232 233/* 234 * Get/set the 64-bit value from a Dalvik register. 235 * Avoid unaligned memory accesses. 236 * Note, SET_VREG_WIDE clobbers the register containing the value being stored. 237 * Note, SET_VREG_DOUBLE clobbers the register containing the Dalvik register number. 238 */ 239.macro GET_VREG_WIDE reg, vreg 240 .set noat 241 dlsa AT, \vreg, rFP, 2 242 lw \reg, 0(AT) 243 lw AT, 4(AT) 244 dinsu \reg, AT, 32, 32 245 .set at 246.endm 247.macro GET_VREG_DOUBLE reg, vreg 248 .set noat 249 dlsa AT, \vreg, rFP, 2 250 lwc1 \reg, 0(AT) 251 lw AT, 4(AT) 252 mthc1 AT, \reg 253 .set at 254.endm 255.macro SET_VREG_WIDE reg, vreg 256 .set noat 257 dlsa AT, \vreg, rFP, 2 258 sw \reg, 0(AT) 259 drotr32 \reg, \reg, 0 260 sw \reg, 4(AT) 261 dlsa AT, \vreg, rREFS, 2 262 sw zero, 0(AT) 263 sw zero, 4(AT) 264 .set at 265.endm 266.macro SET_VREG_DOUBLE reg, vreg 267 .set noat 268 dlsa AT, \vreg, rREFS, 2 269 sw zero, 0(AT) 270 sw zero, 4(AT) 271 dlsa AT, \vreg, rFP, 2 272 swc1 \reg, 0(AT) 273 mfhc1 \vreg, \reg 274 sw \vreg, 4(AT) 275 .set at 276.endm 277 278/* 279 * On-stack offsets for spilling/unspilling callee-saved registers 280 * and the frame size. 281 */ 282#define STACK_OFFSET_RA 0 283#define STACK_OFFSET_GP 8 284#define STACK_OFFSET_S0 16 285#define STACK_OFFSET_S1 24 286#define STACK_OFFSET_S2 32 287#define STACK_OFFSET_S3 40 288#define STACK_OFFSET_S4 48 289#define STACK_OFFSET_S5 56 290#define STACK_OFFSET_S6 64 291#define STACK_SIZE 80 /* needs 16 byte alignment */ 292 293/* Constants for float/double_to_int/long conversions */ 294#define INT_MIN 0x80000000 295#define INT_MIN_AS_FLOAT 0xCF000000 296#define INT_MIN_AS_DOUBLE 0xC1E0000000000000 297#define LONG_MIN 0x8000000000000000 298#define LONG_MIN_AS_FLOAT 0xDF000000 299#define LONG_MIN_AS_DOUBLE 0xC3E0000000000000 300 301/* File: mips64/entry.S */ 302/* 303 * Copyright (C) 2016 The Android Open Source Project 304 * 305 * Licensed under the Apache License, Version 2.0 (the "License"); 306 * you may not use this file except in compliance with the License. 307 * You may obtain a copy of the License at 308 * 309 * http://www.apache.org/licenses/LICENSE-2.0 310 * 311 * Unless required by applicable law or agreed to in writing, software 312 * distributed under the License is distributed on an "AS IS" BASIS, 313 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 314 * See the License for the specific language governing permissions and 315 * limitations under the License. 316 */ 317 318/* 319 * Interpreter entry point. 320 */ 321 322 .set reorder 323 324 .text 325 .global ExecuteMterpImpl 326 .type ExecuteMterpImpl, %function 327 .balign 16 328/* 329 * On entry: 330 * a0 Thread* self 331 * a1 code_item 332 * a2 ShadowFrame 333 * a3 JValue* result_register 334 * 335 */ 336ExecuteMterpImpl: 337 .cfi_startproc 338 .cpsetup t9, t8, ExecuteMterpImpl 339 340 .cfi_def_cfa sp, 0 341 daddu sp, sp, -STACK_SIZE 342 .cfi_adjust_cfa_offset STACK_SIZE 343 344 sd t8, STACK_OFFSET_GP(sp) 345 .cfi_rel_offset 28, STACK_OFFSET_GP 346 sd ra, STACK_OFFSET_RA(sp) 347 .cfi_rel_offset 31, STACK_OFFSET_RA 348 349 sd s0, STACK_OFFSET_S0(sp) 350 .cfi_rel_offset 16, STACK_OFFSET_S0 351 sd s1, STACK_OFFSET_S1(sp) 352 .cfi_rel_offset 17, STACK_OFFSET_S1 353 sd s2, STACK_OFFSET_S2(sp) 354 .cfi_rel_offset 18, STACK_OFFSET_S2 355 sd s3, STACK_OFFSET_S3(sp) 356 .cfi_rel_offset 19, STACK_OFFSET_S3 357 sd s4, STACK_OFFSET_S4(sp) 358 .cfi_rel_offset 20, STACK_OFFSET_S4 359 sd s5, STACK_OFFSET_S5(sp) 360 .cfi_rel_offset 21, STACK_OFFSET_S5 361 sd s6, STACK_OFFSET_S6(sp) 362 .cfi_rel_offset 22, STACK_OFFSET_S6 363 364 /* Remember the return register */ 365 sd a3, SHADOWFRAME_RESULT_REGISTER_OFFSET(a2) 366 367 /* Remember the code_item */ 368 sd a1, SHADOWFRAME_CODE_ITEM_OFFSET(a2) 369 370 /* set up "named" registers */ 371 move rSELF, a0 372 daddu rFP, a2, SHADOWFRAME_VREGS_OFFSET 373 lw v0, SHADOWFRAME_NUMBER_OF_VREGS_OFFSET(a2) 374 dlsa rREFS, v0, rFP, 2 375 daddu rPC, a1, CODEITEM_INSNS_OFFSET 376 lw v0, SHADOWFRAME_DEX_PC_OFFSET(a2) 377 dlsa rPC, v0, rPC, 1 378 EXPORT_PC 379 380 /* Starting ibase */ 381 REFRESH_IBASE 382 383 /* Set up for backwards branches & osr profiling */ 384 ld a0, OFF_FP_METHOD(rFP) 385 daddu a1, rFP, OFF_FP_SHADOWFRAME 386 jal MterpSetUpHotnessCountdown 387 move rPROFILE, v0 # Starting hotness countdown to rPROFILE 388 389 /* start executing the instruction at rPC */ 390 FETCH_INST 391 GET_INST_OPCODE v0 392 GOTO_OPCODE v0 393 394 /* NOTE: no fallthrough */ 395 396 397 .global artMterpAsmInstructionStart 398 .type artMterpAsmInstructionStart, %function 399artMterpAsmInstructionStart = .L_op_nop 400 .text 401 402/* ------------------------------ */ 403 .balign 128 404.L_op_nop: /* 0x00 */ 405/* File: mips64/op_nop.S */ 406 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 407 GET_INST_OPCODE v0 # extract opcode from rINST 408 GOTO_OPCODE v0 # jump to next instruction 409 410/* ------------------------------ */ 411 .balign 128 412.L_op_move: /* 0x01 */ 413/* File: mips64/op_move.S */ 414 /* for move, move-object, long-to-int */ 415 /* op vA, vB */ 416 ext a2, rINST, 8, 4 # a2 <- A 417 ext a3, rINST, 12, 4 # a3 <- B 418 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 419 GET_VREG a0, a3 # a0 <- vB 420 GET_INST_OPCODE v0 # extract opcode from rINST 421 .if 0 422 SET_VREG_OBJECT a0, a2 # vA <- vB 423 .else 424 SET_VREG a0, a2 # vA <- vB 425 .endif 426 GOTO_OPCODE v0 # jump to next instruction 427 428/* ------------------------------ */ 429 .balign 128 430.L_op_move_from16: /* 0x02 */ 431/* File: mips64/op_move_from16.S */ 432 /* for: move/from16, move-object/from16 */ 433 /* op vAA, vBBBB */ 434 lhu a3, 2(rPC) # a3 <- BBBB 435 srl a2, rINST, 8 # a2 <- AA 436 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 437 GET_VREG a0, a3 # a0 <- vBBBB 438 GET_INST_OPCODE v0 # extract opcode from rINST 439 .if 0 440 SET_VREG_OBJECT a0, a2 # vAA <- vBBBB 441 .else 442 SET_VREG a0, a2 # vAA <- vBBBB 443 .endif 444 GOTO_OPCODE v0 # jump to next instruction 445 446/* ------------------------------ */ 447 .balign 128 448.L_op_move_16: /* 0x03 */ 449/* File: mips64/op_move_16.S */ 450 /* for: move/16, move-object/16 */ 451 /* op vAAAA, vBBBB */ 452 lhu a3, 4(rPC) # a3 <- BBBB 453 lhu a2, 2(rPC) # a2 <- AAAA 454 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 455 GET_VREG a0, a3 # a0 <- vBBBB 456 GET_INST_OPCODE v0 # extract opcode from rINST 457 .if 0 458 SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB 459 .else 460 SET_VREG a0, a2 # vAAAA <- vBBBB 461 .endif 462 GOTO_OPCODE v0 # jump to next instruction 463 464/* ------------------------------ */ 465 .balign 128 466.L_op_move_wide: /* 0x04 */ 467/* File: mips64/op_move_wide.S */ 468 /* move-wide vA, vB */ 469 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 470 ext a3, rINST, 12, 4 # a3 <- B 471 ext a2, rINST, 8, 4 # a2 <- A 472 GET_VREG_WIDE a0, a3 # a0 <- vB 473 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 474 GET_INST_OPCODE v0 # extract opcode from rINST 475 SET_VREG_WIDE a0, a2 # vA <- vB 476 GOTO_OPCODE v0 # jump to next instruction 477 478/* ------------------------------ */ 479 .balign 128 480.L_op_move_wide_from16: /* 0x05 */ 481/* File: mips64/op_move_wide_from16.S */ 482 /* move-wide/from16 vAA, vBBBB */ 483 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 484 lhu a3, 2(rPC) # a3 <- BBBB 485 srl a2, rINST, 8 # a2 <- AA 486 GET_VREG_WIDE a0, a3 # a0 <- vBBBB 487 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 488 GET_INST_OPCODE v0 # extract opcode from rINST 489 SET_VREG_WIDE a0, a2 # vAA <- vBBBB 490 GOTO_OPCODE v0 # jump to next instruction 491 492/* ------------------------------ */ 493 .balign 128 494.L_op_move_wide_16: /* 0x06 */ 495/* File: mips64/op_move_wide_16.S */ 496 /* move-wide/16 vAAAA, vBBBB */ 497 /* NOTE: regs can overlap, e.g. "move v6,v7" or "move v7,v6" */ 498 lhu a3, 4(rPC) # a3 <- BBBB 499 lhu a2, 2(rPC) # a2 <- AAAA 500 GET_VREG_WIDE a0, a3 # a0 <- vBBBB 501 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 502 GET_INST_OPCODE v0 # extract opcode from rINST 503 SET_VREG_WIDE a0, a2 # vAAAA <- vBBBB 504 GOTO_OPCODE v0 # jump to next instruction 505 506/* ------------------------------ */ 507 .balign 128 508.L_op_move_object: /* 0x07 */ 509/* File: mips64/op_move_object.S */ 510/* File: mips64/op_move.S */ 511 /* for move, move-object, long-to-int */ 512 /* op vA, vB */ 513 ext a2, rINST, 8, 4 # a2 <- A 514 ext a3, rINST, 12, 4 # a3 <- B 515 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 516 GET_VREG a0, a3 # a0 <- vB 517 GET_INST_OPCODE v0 # extract opcode from rINST 518 .if 1 519 SET_VREG_OBJECT a0, a2 # vA <- vB 520 .else 521 SET_VREG a0, a2 # vA <- vB 522 .endif 523 GOTO_OPCODE v0 # jump to next instruction 524 525 526/* ------------------------------ */ 527 .balign 128 528.L_op_move_object_from16: /* 0x08 */ 529/* File: mips64/op_move_object_from16.S */ 530/* File: mips64/op_move_from16.S */ 531 /* for: move/from16, move-object/from16 */ 532 /* op vAA, vBBBB */ 533 lhu a3, 2(rPC) # a3 <- BBBB 534 srl a2, rINST, 8 # a2 <- AA 535 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 536 GET_VREG a0, a3 # a0 <- vBBBB 537 GET_INST_OPCODE v0 # extract opcode from rINST 538 .if 1 539 SET_VREG_OBJECT a0, a2 # vAA <- vBBBB 540 .else 541 SET_VREG a0, a2 # vAA <- vBBBB 542 .endif 543 GOTO_OPCODE v0 # jump to next instruction 544 545 546/* ------------------------------ */ 547 .balign 128 548.L_op_move_object_16: /* 0x09 */ 549/* File: mips64/op_move_object_16.S */ 550/* File: mips64/op_move_16.S */ 551 /* for: move/16, move-object/16 */ 552 /* op vAAAA, vBBBB */ 553 lhu a3, 4(rPC) # a3 <- BBBB 554 lhu a2, 2(rPC) # a2 <- AAAA 555 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 556 GET_VREG a0, a3 # a0 <- vBBBB 557 GET_INST_OPCODE v0 # extract opcode from rINST 558 .if 1 559 SET_VREG_OBJECT a0, a2 # vAAAA <- vBBBB 560 .else 561 SET_VREG a0, a2 # vAAAA <- vBBBB 562 .endif 563 GOTO_OPCODE v0 # jump to next instruction 564 565 566/* ------------------------------ */ 567 .balign 128 568.L_op_move_result: /* 0x0a */ 569/* File: mips64/op_move_result.S */ 570 /* for: move-result, move-result-object */ 571 /* op vAA */ 572 srl a2, rINST, 8 # a2 <- AA 573 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 574 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 575 lw a0, 0(a0) # a0 <- result.i 576 GET_INST_OPCODE v0 # extract opcode from rINST 577 .if 0 578 SET_VREG_OBJECT a0, a2 # vAA <- result 579 .else 580 SET_VREG a0, a2 # vAA <- result 581 .endif 582 GOTO_OPCODE v0 # jump to next instruction 583 584/* ------------------------------ */ 585 .balign 128 586.L_op_move_result_wide: /* 0x0b */ 587/* File: mips64/op_move_result_wide.S */ 588 /* for: move-result-wide */ 589 /* op vAA */ 590 srl a2, rINST, 8 # a2 <- AA 591 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 592 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 593 ld a0, 0(a0) # a0 <- result.j 594 GET_INST_OPCODE v0 # extract opcode from rINST 595 SET_VREG_WIDE a0, a2 # vAA <- result 596 GOTO_OPCODE v0 # jump to next instruction 597 598/* ------------------------------ */ 599 .balign 128 600.L_op_move_result_object: /* 0x0c */ 601/* File: mips64/op_move_result_object.S */ 602/* File: mips64/op_move_result.S */ 603 /* for: move-result, move-result-object */ 604 /* op vAA */ 605 srl a2, rINST, 8 # a2 <- AA 606 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 607 ld a0, OFF_FP_RESULT_REGISTER(rFP) # get pointer to result JType 608 lw a0, 0(a0) # a0 <- result.i 609 GET_INST_OPCODE v0 # extract opcode from rINST 610 .if 1 611 SET_VREG_OBJECT a0, a2 # vAA <- result 612 .else 613 SET_VREG a0, a2 # vAA <- result 614 .endif 615 GOTO_OPCODE v0 # jump to next instruction 616 617 618/* ------------------------------ */ 619 .balign 128 620.L_op_move_exception: /* 0x0d */ 621/* File: mips64/op_move_exception.S */ 622 /* move-exception vAA */ 623 srl a2, rINST, 8 # a2 <- AA 624 ld a0, THREAD_EXCEPTION_OFFSET(rSELF) # load exception obj 625 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 626 SET_VREG_OBJECT a0, a2 # vAA <- exception obj 627 GET_INST_OPCODE v0 # extract opcode from rINST 628 sd zero, THREAD_EXCEPTION_OFFSET(rSELF) # clear exception 629 GOTO_OPCODE v0 # jump to next instruction 630 631/* ------------------------------ */ 632 .balign 128 633.L_op_return_void: /* 0x0e */ 634/* File: mips64/op_return_void.S */ 635 .extern MterpThreadFenceForConstructor 636 .extern MterpSuspendCheck 637 jal MterpThreadFenceForConstructor 638 lw ra, THREAD_FLAGS_OFFSET(rSELF) 639 move a0, rSELF 640 and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 641 beqzc ra, 1f 642 jal MterpSuspendCheck # (self) 6431: 644 li a0, 0 645 b MterpReturn 646 647/* ------------------------------ */ 648 .balign 128 649.L_op_return: /* 0x0f */ 650/* File: mips64/op_return.S */ 651 /* 652 * Return a 32-bit value. 653 * 654 * for: return (sign-extend), return-object (zero-extend) 655 */ 656 /* op vAA */ 657 .extern MterpThreadFenceForConstructor 658 .extern MterpSuspendCheck 659 jal MterpThreadFenceForConstructor 660 lw ra, THREAD_FLAGS_OFFSET(rSELF) 661 move a0, rSELF 662 and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 663 beqzc ra, 1f 664 jal MterpSuspendCheck # (self) 6651: 666 srl a2, rINST, 8 # a2 <- AA 667 GET_VREG a0, a2 # a0 <- vAA 668 b MterpReturn 669 670/* ------------------------------ */ 671 .balign 128 672.L_op_return_wide: /* 0x10 */ 673/* File: mips64/op_return_wide.S */ 674 /* 675 * Return a 64-bit value. 676 */ 677 /* return-wide vAA */ 678 /* op vAA */ 679 .extern MterpThreadFenceForConstructor 680 .extern MterpSuspendCheck 681 jal MterpThreadFenceForConstructor 682 lw ra, THREAD_FLAGS_OFFSET(rSELF) 683 move a0, rSELF 684 and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 685 beqzc ra, 1f 686 jal MterpSuspendCheck # (self) 6871: 688 srl a2, rINST, 8 # a2 <- AA 689 GET_VREG_WIDE a0, a2 # a0 <- vAA 690 b MterpReturn 691 692/* ------------------------------ */ 693 .balign 128 694.L_op_return_object: /* 0x11 */ 695/* File: mips64/op_return_object.S */ 696/* File: mips64/op_return.S */ 697 /* 698 * Return a 32-bit value. 699 * 700 * for: return (sign-extend), return-object (zero-extend) 701 */ 702 /* op vAA */ 703 .extern MterpThreadFenceForConstructor 704 .extern MterpSuspendCheck 705 jal MterpThreadFenceForConstructor 706 lw ra, THREAD_FLAGS_OFFSET(rSELF) 707 move a0, rSELF 708 and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 709 beqzc ra, 1f 710 jal MterpSuspendCheck # (self) 7111: 712 srl a2, rINST, 8 # a2 <- AA 713 GET_VREG_U a0, a2 # a0 <- vAA 714 b MterpReturn 715 716 717/* ------------------------------ */ 718 .balign 128 719.L_op_const_4: /* 0x12 */ 720/* File: mips64/op_const_4.S */ 721 /* const/4 vA, #+B */ 722 ext a2, rINST, 8, 4 # a2 <- A 723 seh a0, rINST # sign extend B in rINST 724 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 725 sra a0, a0, 12 # shift B into its final position 726 GET_INST_OPCODE v0 # extract opcode from rINST 727 SET_VREG a0, a2 # vA <- +B 728 GOTO_OPCODE v0 # jump to next instruction 729 730/* ------------------------------ */ 731 .balign 128 732.L_op_const_16: /* 0x13 */ 733/* File: mips64/op_const_16.S */ 734 /* const/16 vAA, #+BBBB */ 735 srl a2, rINST, 8 # a2 <- AA 736 lh a0, 2(rPC) # a0 <- sign-extended BBBB 737 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 738 GET_INST_OPCODE v0 # extract opcode from rINST 739 SET_VREG a0, a2 # vAA <- +BBBB 740 GOTO_OPCODE v0 # jump to next instruction 741 742/* ------------------------------ */ 743 .balign 128 744.L_op_const: /* 0x14 */ 745/* File: mips64/op_const.S */ 746 /* const vAA, #+BBBBbbbb */ 747 srl a2, rINST, 8 # a2 <- AA 748 lh a0, 2(rPC) # a0 <- bbbb (low) 749 lh a1, 4(rPC) # a1 <- BBBB (high) 750 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 751 ins a0, a1, 16, 16 # a0 = BBBBbbbb 752 GET_INST_OPCODE v0 # extract opcode from rINST 753 SET_VREG a0, a2 # vAA <- +BBBBbbbb 754 GOTO_OPCODE v0 # jump to next instruction 755 756/* ------------------------------ */ 757 .balign 128 758.L_op_const_high16: /* 0x15 */ 759/* File: mips64/op_const_high16.S */ 760 /* const/high16 vAA, #+BBBB0000 */ 761 srl a2, rINST, 8 # a2 <- AA 762 lh a0, 2(rPC) # a0 <- BBBB 763 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 764 sll a0, a0, 16 # a0 <- BBBB0000 765 GET_INST_OPCODE v0 # extract opcode from rINST 766 SET_VREG a0, a2 # vAA <- +BBBB0000 767 GOTO_OPCODE v0 # jump to next instruction 768 769/* ------------------------------ */ 770 .balign 128 771.L_op_const_wide_16: /* 0x16 */ 772/* File: mips64/op_const_wide_16.S */ 773 /* const-wide/16 vAA, #+BBBB */ 774 srl a2, rINST, 8 # a2 <- AA 775 lh a0, 2(rPC) # a0 <- sign-extended BBBB 776 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 777 GET_INST_OPCODE v0 # extract opcode from rINST 778 SET_VREG_WIDE a0, a2 # vAA <- +BBBB 779 GOTO_OPCODE v0 # jump to next instruction 780 781/* ------------------------------ */ 782 .balign 128 783.L_op_const_wide_32: /* 0x17 */ 784/* File: mips64/op_const_wide_32.S */ 785 /* const-wide/32 vAA, #+BBBBbbbb */ 786 srl a2, rINST, 8 # a2 <- AA 787 lh a0, 2(rPC) # a0 <- bbbb (low) 788 lh a1, 4(rPC) # a1 <- BBBB (high) 789 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 790 ins a0, a1, 16, 16 # a0 = BBBBbbbb 791 GET_INST_OPCODE v0 # extract opcode from rINST 792 SET_VREG_WIDE a0, a2 # vAA <- +BBBBbbbb 793 GOTO_OPCODE v0 # jump to next instruction 794 795/* ------------------------------ */ 796 .balign 128 797.L_op_const_wide: /* 0x18 */ 798/* File: mips64/op_const_wide.S */ 799 /* const-wide vAA, #+HHHHhhhhBBBBbbbb */ 800 srl a4, rINST, 8 # a4 <- AA 801 lh a0, 2(rPC) # a0 <- bbbb (low) 802 lh a1, 4(rPC) # a1 <- BBBB (low middle) 803 lh a2, 6(rPC) # a2 <- hhhh (high middle) 804 lh a3, 8(rPC) # a3 <- HHHH (high) 805 FETCH_ADVANCE_INST 5 # advance rPC, load rINST 806 ins a0, a1, 16, 16 # a0 = BBBBbbbb 807 ins a2, a3, 16, 16 # a2 = HHHHhhhh 808 dinsu a0, a2, 32, 32 # a0 = HHHHhhhhBBBBbbbb 809 GET_INST_OPCODE v0 # extract opcode from rINST 810 SET_VREG_WIDE a0, a4 # vAA <- +HHHHhhhhBBBBbbbb 811 GOTO_OPCODE v0 # jump to next instruction 812 813/* ------------------------------ */ 814 .balign 128 815.L_op_const_wide_high16: /* 0x19 */ 816/* File: mips64/op_const_wide_high16.S */ 817 /* const-wide/high16 vAA, #+BBBB000000000000 */ 818 srl a2, rINST, 8 # a2 <- AA 819 lh a0, 2(rPC) # a0 <- BBBB 820 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 821 dsll32 a0, a0, 16 # a0 <- BBBB000000000000 822 GET_INST_OPCODE v0 # extract opcode from rINST 823 SET_VREG_WIDE a0, a2 # vAA <- +BBBB000000000000 824 GOTO_OPCODE v0 # jump to next instruction 825 826/* ------------------------------ */ 827 .balign 128 828.L_op_const_string: /* 0x1a */ 829/* File: mips64/op_const_string.S */ 830 /* const/string vAA, String//BBBB */ 831 .extern MterpConstString 832 EXPORT_PC 833 lhu a0, 2(rPC) # a0 <- BBBB 834 srl a1, rINST, 8 # a1 <- AA 835 daddu a2, rFP, OFF_FP_SHADOWFRAME 836 move a3, rSELF 837 jal MterpConstString # (index, tgt_reg, shadow_frame, self) 838 PREFETCH_INST 2 # load rINST 839 bnez v0, MterpPossibleException # let reference interpreter deal with it. 840 ADVANCE 2 # advance rPC 841 GET_INST_OPCODE v0 # extract opcode from rINST 842 GOTO_OPCODE v0 # jump to next instruction 843 844/* ------------------------------ */ 845 .balign 128 846.L_op_const_string_jumbo: /* 0x1b */ 847/* File: mips64/op_const_string_jumbo.S */ 848 /* const/string vAA, String//BBBBBBBB */ 849 .extern MterpConstString 850 EXPORT_PC 851 lh a0, 2(rPC) # a0 <- bbbb (low) 852 lh a4, 4(rPC) # a4 <- BBBB (high) 853 srl a1, rINST, 8 # a1 <- AA 854 ins a0, a4, 16, 16 # a0 <- BBBBbbbb 855 daddu a2, rFP, OFF_FP_SHADOWFRAME 856 move a3, rSELF 857 jal MterpConstString # (index, tgt_reg, shadow_frame, self) 858 PREFETCH_INST 3 # load rINST 859 bnez v0, MterpPossibleException # let reference interpreter deal with it. 860 ADVANCE 3 # advance rPC 861 GET_INST_OPCODE v0 # extract opcode from rINST 862 GOTO_OPCODE v0 # jump to next instruction 863 864/* ------------------------------ */ 865 .balign 128 866.L_op_const_class: /* 0x1c */ 867/* File: mips64/op_const_class.S */ 868 /* const/class vAA, Class//BBBB */ 869 .extern MterpConstClass 870 EXPORT_PC 871 lhu a0, 2(rPC) # a0 <- BBBB 872 srl a1, rINST, 8 # a1 <- AA 873 daddu a2, rFP, OFF_FP_SHADOWFRAME 874 move a3, rSELF 875 jal MterpConstClass # (index, tgt_reg, shadow_frame, self) 876 PREFETCH_INST 2 # load rINST 877 bnez v0, MterpPossibleException # let reference interpreter deal with it. 878 ADVANCE 2 # advance rPC 879 GET_INST_OPCODE v0 # extract opcode from rINST 880 GOTO_OPCODE v0 # jump to next instruction 881 882/* ------------------------------ */ 883 .balign 128 884.L_op_monitor_enter: /* 0x1d */ 885/* File: mips64/op_monitor_enter.S */ 886 /* 887 * Synchronize on an object. 888 */ 889 /* monitor-enter vAA */ 890 .extern artLockObjectFromCode 891 EXPORT_PC 892 srl a2, rINST, 8 # a2 <- AA 893 GET_VREG_U a0, a2 # a0 <- vAA (object) 894 move a1, rSELF # a1 <- self 895 jal artLockObjectFromCode 896 bnezc v0, MterpException 897 FETCH_ADVANCE_INST 1 898 GET_INST_OPCODE v0 # extract opcode from rINST 899 GOTO_OPCODE v0 # jump to next instruction 900 901/* ------------------------------ */ 902 .balign 128 903.L_op_monitor_exit: /* 0x1e */ 904/* File: mips64/op_monitor_exit.S */ 905 /* 906 * Unlock an object. 907 * 908 * Exceptions that occur when unlocking a monitor need to appear as 909 * if they happened at the following instruction. See the Dalvik 910 * instruction spec. 911 */ 912 /* monitor-exit vAA */ 913 .extern artUnlockObjectFromCode 914 EXPORT_PC 915 srl a2, rINST, 8 # a2 <- AA 916 GET_VREG_U a0, a2 # a0 <- vAA (object) 917 move a1, rSELF # a1 <- self 918 jal artUnlockObjectFromCode # v0 <- success for unlock(self, obj) 919 bnezc v0, MterpException 920 FETCH_ADVANCE_INST 1 # before throw: advance rPC, load rINST 921 GET_INST_OPCODE v0 # extract opcode from rINST 922 GOTO_OPCODE v0 # jump to next instruction 923 924/* ------------------------------ */ 925 .balign 128 926.L_op_check_cast: /* 0x1f */ 927/* File: mips64/op_check_cast.S */ 928 /* 929 * Check to see if a cast from one class to another is allowed. 930 */ 931 /* check-cast vAA, class//BBBB */ 932 .extern MterpCheckCast 933 EXPORT_PC 934 lhu a0, 2(rPC) # a0 <- BBBB 935 srl a1, rINST, 8 # a1 <- AA 936 dlsa a1, a1, rFP, 2 # a1 <- &object 937 ld a2, OFF_FP_METHOD(rFP) # a2 <- method 938 move a3, rSELF # a3 <- self 939 jal MterpCheckCast # (index, &obj, method, self) 940 PREFETCH_INST 2 941 bnez v0, MterpPossibleException 942 ADVANCE 2 943 GET_INST_OPCODE v0 # extract opcode from rINST 944 GOTO_OPCODE v0 # jump to next instruction 945 946/* ------------------------------ */ 947 .balign 128 948.L_op_instance_of: /* 0x20 */ 949/* File: mips64/op_instance_of.S */ 950 /* 951 * Check to see if an object reference is an instance of a class. 952 * 953 * Most common situation is a non-null object, being compared against 954 * an already-resolved class. 955 */ 956 /* instance-of vA, vB, class//CCCC */ 957 .extern MterpInstanceOf 958 EXPORT_PC 959 lhu a0, 2(rPC) # a0 <- CCCC 960 srl a1, rINST, 12 # a1 <- B 961 dlsa a1, a1, rFP, 2 # a1 <- &object 962 ld a2, OFF_FP_METHOD(rFP) # a2 <- method 963 move a3, rSELF # a3 <- self 964 jal MterpInstanceOf # (index, &obj, method, self) 965 ld a1, THREAD_EXCEPTION_OFFSET(rSELF) 966 ext a2, rINST, 8, 4 # a2 <- A 967 PREFETCH_INST 2 968 bnez a1, MterpException 969 ADVANCE 2 # advance rPC 970 SET_VREG v0, a2 # vA <- v0 971 GET_INST_OPCODE v0 # extract opcode from rINST 972 GOTO_OPCODE v0 # jump to next instruction 973 974/* ------------------------------ */ 975 .balign 128 976.L_op_array_length: /* 0x21 */ 977/* File: mips64/op_array_length.S */ 978 /* 979 * Return the length of an array. 980 */ 981 srl a1, rINST, 12 # a1 <- B 982 GET_VREG_U a0, a1 # a0 <- vB (object ref) 983 ext a2, rINST, 8, 4 # a2 <- A 984 beqz a0, common_errNullObject # yup, fail 985 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 986 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- array length 987 GET_INST_OPCODE v0 # extract opcode from rINST 988 SET_VREG a3, a2 # vB <- length 989 GOTO_OPCODE v0 # jump to next instruction 990 991/* ------------------------------ */ 992 .balign 128 993.L_op_new_instance: /* 0x22 */ 994/* File: mips64/op_new_instance.S */ 995 /* 996 * Create a new instance of a class. 997 */ 998 /* new-instance vAA, class//BBBB */ 999 .extern MterpNewInstance 1000 EXPORT_PC 1001 daddu a0, rFP, OFF_FP_SHADOWFRAME 1002 move a1, rSELF 1003 move a2, rINST 1004 jal MterpNewInstance # (shadow_frame, self, inst_data) 1005 beqzc v0, MterpPossibleException 1006 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1007 GET_INST_OPCODE v0 # extract opcode from rINST 1008 GOTO_OPCODE v0 # jump to next instruction 1009 1010/* ------------------------------ */ 1011 .balign 128 1012.L_op_new_array: /* 0x23 */ 1013/* File: mips64/op_new_array.S */ 1014 /* 1015 * Allocate an array of objects, specified with the array class 1016 * and a count. 1017 * 1018 * The verifier guarantees that this is an array class, so we don't 1019 * check for it here. 1020 */ 1021 /* new-array vA, vB, class//CCCC */ 1022 .extern MterpNewArray 1023 EXPORT_PC 1024 daddu a0, rFP, OFF_FP_SHADOWFRAME 1025 move a1, rPC 1026 move a2, rINST 1027 move a3, rSELF 1028 jal MterpNewArray 1029 beqzc v0, MterpPossibleException 1030 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1031 GET_INST_OPCODE v0 # extract opcode from rINST 1032 GOTO_OPCODE v0 # jump to next instruction 1033 1034/* ------------------------------ */ 1035 .balign 128 1036.L_op_filled_new_array: /* 0x24 */ 1037/* File: mips64/op_filled_new_array.S */ 1038 /* 1039 * Create a new array with elements filled from registers. 1040 * 1041 * for: filled-new-array, filled-new-array/range 1042 */ 1043 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ 1044 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ 1045 .extern MterpFilledNewArray 1046 EXPORT_PC 1047 daddu a0, rFP, OFF_FP_SHADOWFRAME 1048 move a1, rPC 1049 move a2, rSELF 1050 jal MterpFilledNewArray 1051 beqzc v0, MterpPossibleException 1052 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 1053 GET_INST_OPCODE v0 # extract opcode from rINST 1054 GOTO_OPCODE v0 # jump to next instruction 1055 1056/* ------------------------------ */ 1057 .balign 128 1058.L_op_filled_new_array_range: /* 0x25 */ 1059/* File: mips64/op_filled_new_array_range.S */ 1060/* File: mips64/op_filled_new_array.S */ 1061 /* 1062 * Create a new array with elements filled from registers. 1063 * 1064 * for: filled-new-array, filled-new-array/range 1065 */ 1066 /* op vB, {vD, vE, vF, vG, vA}, class//CCCC */ 1067 /* op {vCCCC..v(CCCC+AA-1)}, type//BBBB */ 1068 .extern MterpFilledNewArrayRange 1069 EXPORT_PC 1070 daddu a0, rFP, OFF_FP_SHADOWFRAME 1071 move a1, rPC 1072 move a2, rSELF 1073 jal MterpFilledNewArrayRange 1074 beqzc v0, MterpPossibleException 1075 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 1076 GET_INST_OPCODE v0 # extract opcode from rINST 1077 GOTO_OPCODE v0 # jump to next instruction 1078 1079 1080/* ------------------------------ */ 1081 .balign 128 1082.L_op_fill_array_data: /* 0x26 */ 1083/* File: mips64/op_fill_array_data.S */ 1084 /* fill-array-data vAA, +BBBBBBBB */ 1085 .extern MterpFillArrayData 1086 EXPORT_PC 1087 lh a1, 2(rPC) # a1 <- bbbb (lo) 1088 lh a0, 4(rPC) # a0 <- BBBB (hi) 1089 srl a3, rINST, 8 # a3 <- AA 1090 ins a1, a0, 16, 16 # a1 <- BBBBbbbb 1091 GET_VREG_U a0, a3 # a0 <- vAA (array object) 1092 dlsa a1, a1, rPC, 1 # a1 <- PC + BBBBbbbb*2 (array data off.) 1093 jal MterpFillArrayData # (obj, payload) 1094 beqzc v0, MterpPossibleException # exception? 1095 FETCH_ADVANCE_INST 3 # advance rPC, load rINST 1096 GET_INST_OPCODE v0 # extract opcode from rINST 1097 GOTO_OPCODE v0 # jump to next instruction 1098 1099/* ------------------------------ */ 1100 .balign 128 1101.L_op_throw: /* 0x27 */ 1102/* File: mips64/op_throw.S */ 1103 /* 1104 * Throw an exception object in the current thread. 1105 */ 1106 /* throw vAA */ 1107 EXPORT_PC 1108 srl a2, rINST, 8 # a2 <- AA 1109 GET_VREG_U a0, a2 # a0 <- vAA (exception object) 1110 beqzc a0, common_errNullObject 1111 sd a0, THREAD_EXCEPTION_OFFSET(rSELF) # thread->exception <- obj 1112 b MterpException 1113 1114/* ------------------------------ */ 1115 .balign 128 1116.L_op_goto: /* 0x28 */ 1117/* File: mips64/op_goto.S */ 1118 /* 1119 * Unconditional branch, 8-bit offset. 1120 * 1121 * The branch distance is a signed code-unit offset, which we need to 1122 * double to get a byte offset. 1123 */ 1124 /* goto +AA */ 1125 srl rINST, rINST, 8 1126 seb rINST, rINST # rINST <- offset (sign-extended AA) 1127 b MterpCommonTakenBranchNoFlags 1128 1129/* ------------------------------ */ 1130 .balign 128 1131.L_op_goto_16: /* 0x29 */ 1132/* File: mips64/op_goto_16.S */ 1133 /* 1134 * Unconditional branch, 16-bit offset. 1135 * 1136 * The branch distance is a signed code-unit offset, which we need to 1137 * double to get a byte offset. 1138 */ 1139 /* goto/16 +AAAA */ 1140 lh rINST, 2(rPC) # rINST <- offset (sign-extended AAAA) 1141 b MterpCommonTakenBranchNoFlags 1142 1143/* ------------------------------ */ 1144 .balign 128 1145.L_op_goto_32: /* 0x2a */ 1146/* File: mips64/op_goto_32.S */ 1147 /* 1148 * Unconditional branch, 32-bit offset. 1149 * 1150 * The branch distance is a signed code-unit offset, which we need to 1151 * double to get a byte offset. 1152 * 1153 * Unlike most opcodes, this one is allowed to branch to itself, so 1154 * our "backward branch" test must be "<=0" instead of "<0". 1155 */ 1156 /* goto/32 +AAAAAAAA */ 1157 lh rINST, 2(rPC) # rINST <- aaaa (low) 1158 lh a1, 4(rPC) # a1 <- AAAA (high) 1159 ins rINST, a1, 16, 16 # rINST <- offset (sign-extended AAAAaaaa) 1160 b MterpCommonTakenBranchNoFlags 1161 1162/* ------------------------------ */ 1163 .balign 128 1164.L_op_packed_switch: /* 0x2b */ 1165/* File: mips64/op_packed_switch.S */ 1166 /* 1167 * Handle a packed-switch or sparse-switch instruction. In both cases 1168 * we decode it and hand it off to a helper function. 1169 * 1170 * We don't really expect backward branches in a switch statement, but 1171 * they're perfectly legal, so we check for them here. 1172 * 1173 * for: packed-switch, sparse-switch 1174 */ 1175 /* op vAA, +BBBBBBBB */ 1176 .extern MterpDoPackedSwitch 1177 lh a0, 2(rPC) # a0 <- bbbb (lo) 1178 lh a1, 4(rPC) # a1 <- BBBB (hi) 1179 srl a3, rINST, 8 # a3 <- AA 1180 ins a0, a1, 16, 16 # a0 <- BBBBbbbb 1181 GET_VREG a1, a3 # a1 <- vAA 1182 dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 1183 jal MterpDoPackedSwitch # v0 <- code-unit branch offset 1184 move rINST, v0 1185 b MterpCommonTakenBranchNoFlags 1186 1187/* ------------------------------ */ 1188 .balign 128 1189.L_op_sparse_switch: /* 0x2c */ 1190/* File: mips64/op_sparse_switch.S */ 1191/* File: mips64/op_packed_switch.S */ 1192 /* 1193 * Handle a packed-switch or sparse-switch instruction. In both cases 1194 * we decode it and hand it off to a helper function. 1195 * 1196 * We don't really expect backward branches in a switch statement, but 1197 * they're perfectly legal, so we check for them here. 1198 * 1199 * for: packed-switch, sparse-switch 1200 */ 1201 /* op vAA, +BBBBBBBB */ 1202 .extern MterpDoSparseSwitch 1203 lh a0, 2(rPC) # a0 <- bbbb (lo) 1204 lh a1, 4(rPC) # a1 <- BBBB (hi) 1205 srl a3, rINST, 8 # a3 <- AA 1206 ins a0, a1, 16, 16 # a0 <- BBBBbbbb 1207 GET_VREG a1, a3 # a1 <- vAA 1208 dlsa a0, a0, rPC, 1 # a0 <- PC + BBBBbbbb*2 1209 jal MterpDoSparseSwitch # v0 <- code-unit branch offset 1210 move rINST, v0 1211 b MterpCommonTakenBranchNoFlags 1212 1213 1214/* ------------------------------ */ 1215 .balign 128 1216.L_op_cmpl_float: /* 0x2d */ 1217/* File: mips64/op_cmpl_float.S */ 1218/* File: mips64/fcmp.S */ 1219 /* 1220 * Compare two floating-point values. Puts 0, 1, or -1 into the 1221 * destination register based on the results of the comparison. 1222 * 1223 * For: cmpl-float, cmpg-float 1224 */ 1225 /* op vAA, vBB, vCC */ 1226 srl a4, rINST, 8 # a4 <- AA 1227 lbu a2, 2(rPC) # a2 <- BB 1228 lbu a3, 3(rPC) # a3 <- CC 1229 GET_VREG_FLOAT f0, a2 # f0 <- vBB 1230 GET_VREG_FLOAT f1, a3 # f1 <- vCC 1231 cmp.eq.s f2, f0, f1 1232 li a0, 0 1233 bc1nez f2, 1f # done if vBB == vCC (ordered) 1234 .if 0 1235 cmp.lt.s f2, f0, f1 1236 li a0, -1 1237 bc1nez f2, 1f # done if vBB < vCC (ordered) 1238 li a0, 1 # vBB > vCC or unordered 1239 .else 1240 cmp.lt.s f2, f1, f0 1241 li a0, 1 1242 bc1nez f2, 1f # done if vBB > vCC (ordered) 1243 li a0, -1 # vBB < vCC or unordered 1244 .endif 12451: 1246 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1247 GET_INST_OPCODE v0 # extract opcode from rINST 1248 SET_VREG a0, a4 # vAA <- a0 1249 GOTO_OPCODE v0 # jump to next instruction 1250 1251 1252/* ------------------------------ */ 1253 .balign 128 1254.L_op_cmpg_float: /* 0x2e */ 1255/* File: mips64/op_cmpg_float.S */ 1256/* File: mips64/fcmp.S */ 1257 /* 1258 * Compare two floating-point values. Puts 0, 1, or -1 into the 1259 * destination register based on the results of the comparison. 1260 * 1261 * For: cmpl-float, cmpg-float 1262 */ 1263 /* op vAA, vBB, vCC */ 1264 srl a4, rINST, 8 # a4 <- AA 1265 lbu a2, 2(rPC) # a2 <- BB 1266 lbu a3, 3(rPC) # a3 <- CC 1267 GET_VREG_FLOAT f0, a2 # f0 <- vBB 1268 GET_VREG_FLOAT f1, a3 # f1 <- vCC 1269 cmp.eq.s f2, f0, f1 1270 li a0, 0 1271 bc1nez f2, 1f # done if vBB == vCC (ordered) 1272 .if 1 1273 cmp.lt.s f2, f0, f1 1274 li a0, -1 1275 bc1nez f2, 1f # done if vBB < vCC (ordered) 1276 li a0, 1 # vBB > vCC or unordered 1277 .else 1278 cmp.lt.s f2, f1, f0 1279 li a0, 1 1280 bc1nez f2, 1f # done if vBB > vCC (ordered) 1281 li a0, -1 # vBB < vCC or unordered 1282 .endif 12831: 1284 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1285 GET_INST_OPCODE v0 # extract opcode from rINST 1286 SET_VREG a0, a4 # vAA <- a0 1287 GOTO_OPCODE v0 # jump to next instruction 1288 1289 1290/* ------------------------------ */ 1291 .balign 128 1292.L_op_cmpl_double: /* 0x2f */ 1293/* File: mips64/op_cmpl_double.S */ 1294/* File: mips64/fcmpWide.S */ 1295 /* 1296 * Compare two floating-point values. Puts 0, 1, or -1 into the 1297 * destination register based on the results of the comparison. 1298 * 1299 * For: cmpl-double, cmpg-double 1300 */ 1301 /* op vAA, vBB, vCC */ 1302 srl a4, rINST, 8 # a4 <- AA 1303 lbu a2, 2(rPC) # a2 <- BB 1304 lbu a3, 3(rPC) # a3 <- CC 1305 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 1306 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 1307 cmp.eq.d f2, f0, f1 1308 li a0, 0 1309 bc1nez f2, 1f # done if vBB == vCC (ordered) 1310 .if 0 1311 cmp.lt.d f2, f0, f1 1312 li a0, -1 1313 bc1nez f2, 1f # done if vBB < vCC (ordered) 1314 li a0, 1 # vBB > vCC or unordered 1315 .else 1316 cmp.lt.d f2, f1, f0 1317 li a0, 1 1318 bc1nez f2, 1f # done if vBB > vCC (ordered) 1319 li a0, -1 # vBB < vCC or unordered 1320 .endif 13211: 1322 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1323 GET_INST_OPCODE v0 # extract opcode from rINST 1324 SET_VREG a0, a4 # vAA <- a0 1325 GOTO_OPCODE v0 # jump to next instruction 1326 1327 1328/* ------------------------------ */ 1329 .balign 128 1330.L_op_cmpg_double: /* 0x30 */ 1331/* File: mips64/op_cmpg_double.S */ 1332/* File: mips64/fcmpWide.S */ 1333 /* 1334 * Compare two floating-point values. Puts 0, 1, or -1 into the 1335 * destination register based on the results of the comparison. 1336 * 1337 * For: cmpl-double, cmpg-double 1338 */ 1339 /* op vAA, vBB, vCC */ 1340 srl a4, rINST, 8 # a4 <- AA 1341 lbu a2, 2(rPC) # a2 <- BB 1342 lbu a3, 3(rPC) # a3 <- CC 1343 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 1344 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 1345 cmp.eq.d f2, f0, f1 1346 li a0, 0 1347 bc1nez f2, 1f # done if vBB == vCC (ordered) 1348 .if 1 1349 cmp.lt.d f2, f0, f1 1350 li a0, -1 1351 bc1nez f2, 1f # done if vBB < vCC (ordered) 1352 li a0, 1 # vBB > vCC or unordered 1353 .else 1354 cmp.lt.d f2, f1, f0 1355 li a0, 1 1356 bc1nez f2, 1f # done if vBB > vCC (ordered) 1357 li a0, -1 # vBB < vCC or unordered 1358 .endif 13591: 1360 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1361 GET_INST_OPCODE v0 # extract opcode from rINST 1362 SET_VREG a0, a4 # vAA <- a0 1363 GOTO_OPCODE v0 # jump to next instruction 1364 1365 1366/* ------------------------------ */ 1367 .balign 128 1368.L_op_cmp_long: /* 0x31 */ 1369/* File: mips64/op_cmp_long.S */ 1370 /* cmp-long vAA, vBB, vCC */ 1371 lbu a2, 2(rPC) # a2 <- BB 1372 lbu a3, 3(rPC) # a3 <- CC 1373 srl a4, rINST, 8 # a4 <- AA 1374 GET_VREG_WIDE a0, a2 # a0 <- vBB 1375 GET_VREG_WIDE a1, a3 # a1 <- vCC 1376 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1377 slt a2, a0, a1 1378 slt a0, a1, a0 1379 subu a0, a0, a2 1380 GET_INST_OPCODE v0 # extract opcode from rINST 1381 SET_VREG a0, a4 # vAA <- result 1382 GOTO_OPCODE v0 # jump to next instruction 1383 1384/* ------------------------------ */ 1385 .balign 128 1386.L_op_if_eq: /* 0x32 */ 1387/* File: mips64/op_if_eq.S */ 1388/* File: mips64/bincmp.S */ 1389 /* 1390 * Generic two-operand compare-and-branch operation. Provide a "condition" 1391 * fragment that specifies the comparison to perform, e.g. for 1392 * "if-le" you would use "le". 1393 * 1394 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1395 */ 1396 /* if-cmp vA, vB, +CCCC */ 1397 ext a2, rINST, 8, 4 # a2 <- A 1398 ext a3, rINST, 12, 4 # a3 <- B 1399 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1400 GET_VREG a0, a2 # a0 <- vA 1401 GET_VREG a1, a3 # a1 <- vB 1402 beqc a0, a1, MterpCommonTakenBranchNoFlags 1403 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1404 beqc rPROFILE, v0, .L_check_not_taken_osr 1405 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1406 GET_INST_OPCODE v0 # extract opcode from rINST 1407 GOTO_OPCODE v0 # jump to next instruction 1408 1409 1410/* ------------------------------ */ 1411 .balign 128 1412.L_op_if_ne: /* 0x33 */ 1413/* File: mips64/op_if_ne.S */ 1414/* File: mips64/bincmp.S */ 1415 /* 1416 * Generic two-operand compare-and-branch operation. Provide a "condition" 1417 * fragment that specifies the comparison to perform, e.g. for 1418 * "if-le" you would use "le". 1419 * 1420 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1421 */ 1422 /* if-cmp vA, vB, +CCCC */ 1423 ext a2, rINST, 8, 4 # a2 <- A 1424 ext a3, rINST, 12, 4 # a3 <- B 1425 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1426 GET_VREG a0, a2 # a0 <- vA 1427 GET_VREG a1, a3 # a1 <- vB 1428 bnec a0, a1, MterpCommonTakenBranchNoFlags 1429 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1430 beqc rPROFILE, v0, .L_check_not_taken_osr 1431 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1432 GET_INST_OPCODE v0 # extract opcode from rINST 1433 GOTO_OPCODE v0 # jump to next instruction 1434 1435 1436/* ------------------------------ */ 1437 .balign 128 1438.L_op_if_lt: /* 0x34 */ 1439/* File: mips64/op_if_lt.S */ 1440/* File: mips64/bincmp.S */ 1441 /* 1442 * Generic two-operand compare-and-branch operation. Provide a "condition" 1443 * fragment that specifies the comparison to perform, e.g. for 1444 * "if-le" you would use "le". 1445 * 1446 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1447 */ 1448 /* if-cmp vA, vB, +CCCC */ 1449 ext a2, rINST, 8, 4 # a2 <- A 1450 ext a3, rINST, 12, 4 # a3 <- B 1451 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1452 GET_VREG a0, a2 # a0 <- vA 1453 GET_VREG a1, a3 # a1 <- vB 1454 bltc a0, a1, MterpCommonTakenBranchNoFlags 1455 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1456 beqc rPROFILE, v0, .L_check_not_taken_osr 1457 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1458 GET_INST_OPCODE v0 # extract opcode from rINST 1459 GOTO_OPCODE v0 # jump to next instruction 1460 1461 1462/* ------------------------------ */ 1463 .balign 128 1464.L_op_if_ge: /* 0x35 */ 1465/* File: mips64/op_if_ge.S */ 1466/* File: mips64/bincmp.S */ 1467 /* 1468 * Generic two-operand compare-and-branch operation. Provide a "condition" 1469 * fragment that specifies the comparison to perform, e.g. for 1470 * "if-le" you would use "le". 1471 * 1472 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1473 */ 1474 /* if-cmp vA, vB, +CCCC */ 1475 ext a2, rINST, 8, 4 # a2 <- A 1476 ext a3, rINST, 12, 4 # a3 <- B 1477 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1478 GET_VREG a0, a2 # a0 <- vA 1479 GET_VREG a1, a3 # a1 <- vB 1480 bgec a0, a1, MterpCommonTakenBranchNoFlags 1481 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1482 beqc rPROFILE, v0, .L_check_not_taken_osr 1483 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1484 GET_INST_OPCODE v0 # extract opcode from rINST 1485 GOTO_OPCODE v0 # jump to next instruction 1486 1487 1488/* ------------------------------ */ 1489 .balign 128 1490.L_op_if_gt: /* 0x36 */ 1491/* File: mips64/op_if_gt.S */ 1492/* File: mips64/bincmp.S */ 1493 /* 1494 * Generic two-operand compare-and-branch operation. Provide a "condition" 1495 * fragment that specifies the comparison to perform, e.g. for 1496 * "if-le" you would use "le". 1497 * 1498 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1499 */ 1500 /* if-cmp vA, vB, +CCCC */ 1501 ext a2, rINST, 8, 4 # a2 <- A 1502 ext a3, rINST, 12, 4 # a3 <- B 1503 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1504 GET_VREG a0, a2 # a0 <- vA 1505 GET_VREG a1, a3 # a1 <- vB 1506 bgtc a0, a1, MterpCommonTakenBranchNoFlags 1507 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1508 beqc rPROFILE, v0, .L_check_not_taken_osr 1509 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1510 GET_INST_OPCODE v0 # extract opcode from rINST 1511 GOTO_OPCODE v0 # jump to next instruction 1512 1513 1514/* ------------------------------ */ 1515 .balign 128 1516.L_op_if_le: /* 0x37 */ 1517/* File: mips64/op_if_le.S */ 1518/* File: mips64/bincmp.S */ 1519 /* 1520 * Generic two-operand compare-and-branch operation. Provide a "condition" 1521 * fragment that specifies the comparison to perform, e.g. for 1522 * "if-le" you would use "le". 1523 * 1524 * For: if-eq, if-ne, if-lt, if-ge, if-gt, if-le 1525 */ 1526 /* if-cmp vA, vB, +CCCC */ 1527 ext a2, rINST, 8, 4 # a2 <- A 1528 ext a3, rINST, 12, 4 # a3 <- B 1529 lh rINST, 2(rPC) # rINST <- offset (sign-extended CCCC) 1530 GET_VREG a0, a2 # a0 <- vA 1531 GET_VREG a1, a3 # a1 <- vB 1532 blec a0, a1, MterpCommonTakenBranchNoFlags 1533 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1534 beqc rPROFILE, v0, .L_check_not_taken_osr 1535 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1536 GET_INST_OPCODE v0 # extract opcode from rINST 1537 GOTO_OPCODE v0 # jump to next instruction 1538 1539 1540/* ------------------------------ */ 1541 .balign 128 1542.L_op_if_eqz: /* 0x38 */ 1543/* File: mips64/op_if_eqz.S */ 1544/* File: mips64/zcmp.S */ 1545 /* 1546 * Generic one-operand compare-and-branch operation. Provide a "condition" 1547 * fragment that specifies the comparison to perform, e.g. for 1548 * "if-lez" you would use "le". 1549 * 1550 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1551 */ 1552 /* if-cmp vAA, +BBBB */ 1553 srl a2, rINST, 8 # a2 <- AA 1554 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1555 GET_VREG a0, a2 # a0 <- vAA 1556 beqzc a0, MterpCommonTakenBranchNoFlags 1557 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1558 beqc rPROFILE, v0, .L_check_not_taken_osr 1559 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1560 GET_INST_OPCODE v0 # extract opcode from rINST 1561 GOTO_OPCODE v0 # jump to next instruction 1562 1563 1564/* ------------------------------ */ 1565 .balign 128 1566.L_op_if_nez: /* 0x39 */ 1567/* File: mips64/op_if_nez.S */ 1568/* File: mips64/zcmp.S */ 1569 /* 1570 * Generic one-operand compare-and-branch operation. Provide a "condition" 1571 * fragment that specifies the comparison to perform, e.g. for 1572 * "if-lez" you would use "le". 1573 * 1574 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1575 */ 1576 /* if-cmp vAA, +BBBB */ 1577 srl a2, rINST, 8 # a2 <- AA 1578 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1579 GET_VREG a0, a2 # a0 <- vAA 1580 bnezc a0, MterpCommonTakenBranchNoFlags 1581 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1582 beqc rPROFILE, v0, .L_check_not_taken_osr 1583 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1584 GET_INST_OPCODE v0 # extract opcode from rINST 1585 GOTO_OPCODE v0 # jump to next instruction 1586 1587 1588/* ------------------------------ */ 1589 .balign 128 1590.L_op_if_ltz: /* 0x3a */ 1591/* File: mips64/op_if_ltz.S */ 1592/* File: mips64/zcmp.S */ 1593 /* 1594 * Generic one-operand compare-and-branch operation. Provide a "condition" 1595 * fragment that specifies the comparison to perform, e.g. for 1596 * "if-lez" you would use "le". 1597 * 1598 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1599 */ 1600 /* if-cmp vAA, +BBBB */ 1601 srl a2, rINST, 8 # a2 <- AA 1602 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1603 GET_VREG a0, a2 # a0 <- vAA 1604 bltzc a0, MterpCommonTakenBranchNoFlags 1605 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1606 beqc rPROFILE, v0, .L_check_not_taken_osr 1607 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1608 GET_INST_OPCODE v0 # extract opcode from rINST 1609 GOTO_OPCODE v0 # jump to next instruction 1610 1611 1612/* ------------------------------ */ 1613 .balign 128 1614.L_op_if_gez: /* 0x3b */ 1615/* File: mips64/op_if_gez.S */ 1616/* File: mips64/zcmp.S */ 1617 /* 1618 * Generic one-operand compare-and-branch operation. Provide a "condition" 1619 * fragment that specifies the comparison to perform, e.g. for 1620 * "if-lez" you would use "le". 1621 * 1622 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1623 */ 1624 /* if-cmp vAA, +BBBB */ 1625 srl a2, rINST, 8 # a2 <- AA 1626 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1627 GET_VREG a0, a2 # a0 <- vAA 1628 bgezc a0, MterpCommonTakenBranchNoFlags 1629 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1630 beqc rPROFILE, v0, .L_check_not_taken_osr 1631 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1632 GET_INST_OPCODE v0 # extract opcode from rINST 1633 GOTO_OPCODE v0 # jump to next instruction 1634 1635 1636/* ------------------------------ */ 1637 .balign 128 1638.L_op_if_gtz: /* 0x3c */ 1639/* File: mips64/op_if_gtz.S */ 1640/* File: mips64/zcmp.S */ 1641 /* 1642 * Generic one-operand compare-and-branch operation. Provide a "condition" 1643 * fragment that specifies the comparison to perform, e.g. for 1644 * "if-lez" you would use "le". 1645 * 1646 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1647 */ 1648 /* if-cmp vAA, +BBBB */ 1649 srl a2, rINST, 8 # a2 <- AA 1650 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1651 GET_VREG a0, a2 # a0 <- vAA 1652 bgtzc a0, MterpCommonTakenBranchNoFlags 1653 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1654 beqc rPROFILE, v0, .L_check_not_taken_osr 1655 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1656 GET_INST_OPCODE v0 # extract opcode from rINST 1657 GOTO_OPCODE v0 # jump to next instruction 1658 1659 1660/* ------------------------------ */ 1661 .balign 128 1662.L_op_if_lez: /* 0x3d */ 1663/* File: mips64/op_if_lez.S */ 1664/* File: mips64/zcmp.S */ 1665 /* 1666 * Generic one-operand compare-and-branch operation. Provide a "condition" 1667 * fragment that specifies the comparison to perform, e.g. for 1668 * "if-lez" you would use "le". 1669 * 1670 * For: if-eqz, if-nez, if-ltz, if-gez, if-gtz, if-lez 1671 */ 1672 /* if-cmp vAA, +BBBB */ 1673 srl a2, rINST, 8 # a2 <- AA 1674 lh rINST, 2(rPC) # rINST <- offset (sign-extended BBBB) 1675 GET_VREG a0, a2 # a0 <- vAA 1676 blezc a0, MterpCommonTakenBranchNoFlags 1677 li v0, JIT_CHECK_OSR # possible OSR re-entry? 1678 beqc rPROFILE, v0, .L_check_not_taken_osr 1679 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1680 GET_INST_OPCODE v0 # extract opcode from rINST 1681 GOTO_OPCODE v0 # jump to next instruction 1682 1683 1684/* ------------------------------ */ 1685 .balign 128 1686.L_op_unused_3e: /* 0x3e */ 1687/* File: mips64/op_unused_3e.S */ 1688/* File: mips64/unused.S */ 1689/* 1690 * Bail to reference interpreter to throw. 1691 */ 1692 b MterpFallback 1693 1694 1695/* ------------------------------ */ 1696 .balign 128 1697.L_op_unused_3f: /* 0x3f */ 1698/* File: mips64/op_unused_3f.S */ 1699/* File: mips64/unused.S */ 1700/* 1701 * Bail to reference interpreter to throw. 1702 */ 1703 b MterpFallback 1704 1705 1706/* ------------------------------ */ 1707 .balign 128 1708.L_op_unused_40: /* 0x40 */ 1709/* File: mips64/op_unused_40.S */ 1710/* File: mips64/unused.S */ 1711/* 1712 * Bail to reference interpreter to throw. 1713 */ 1714 b MterpFallback 1715 1716 1717/* ------------------------------ */ 1718 .balign 128 1719.L_op_unused_41: /* 0x41 */ 1720/* File: mips64/op_unused_41.S */ 1721/* File: mips64/unused.S */ 1722/* 1723 * Bail to reference interpreter to throw. 1724 */ 1725 b MterpFallback 1726 1727 1728/* ------------------------------ */ 1729 .balign 128 1730.L_op_unused_42: /* 0x42 */ 1731/* File: mips64/op_unused_42.S */ 1732/* File: mips64/unused.S */ 1733/* 1734 * Bail to reference interpreter to throw. 1735 */ 1736 b MterpFallback 1737 1738 1739/* ------------------------------ */ 1740 .balign 128 1741.L_op_unused_43: /* 0x43 */ 1742/* File: mips64/op_unused_43.S */ 1743/* File: mips64/unused.S */ 1744/* 1745 * Bail to reference interpreter to throw. 1746 */ 1747 b MterpFallback 1748 1749 1750/* ------------------------------ */ 1751 .balign 128 1752.L_op_aget: /* 0x44 */ 1753/* File: mips64/op_aget.S */ 1754 /* 1755 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1756 * 1757 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1758 * 1759 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1760 * If this changes, specialize. 1761 */ 1762 /* op vAA, vBB, vCC */ 1763 lbu a2, 2(rPC) # a2 <- BB 1764 lbu a3, 3(rPC) # a3 <- CC 1765 srl a4, rINST, 8 # a4 <- AA 1766 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1767 GET_VREG a1, a3 # a1 <- vCC (requested index) 1768 beqz a0, common_errNullObject # bail if null array object 1769 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1770 .if 2 1771 # [d]lsa does not support shift count of 0. 1772 dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width 1773 .else 1774 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1775 .endif 1776 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1777 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1778 lw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1779 GET_INST_OPCODE v0 # extract opcode from rINST 1780 SET_VREG a2, a4 # vAA <- a2 1781 GOTO_OPCODE v0 # jump to next instruction 1782 1783/* ------------------------------ */ 1784 .balign 128 1785.L_op_aget_wide: /* 0x45 */ 1786/* File: mips64/op_aget_wide.S */ 1787 /* 1788 * Array get, 64 bits. vAA <- vBB[vCC]. 1789 * 1790 */ 1791 /* aget-wide vAA, vBB, vCC */ 1792 lbu a2, 2(rPC) # a2 <- BB 1793 lbu a3, 3(rPC) # a3 <- CC 1794 srl a4, rINST, 8 # a4 <- AA 1795 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1796 GET_VREG a1, a3 # a1 <- vCC (requested index) 1797 beqz a0, common_errNullObject # bail if null array object 1798 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1799 dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width 1800 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1801 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1802 lw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) 1803 lw a3, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) 1804 dinsu a2, a3, 32, 32 # a2 <- vBB[vCC] 1805 GET_INST_OPCODE v0 # extract opcode from rINST 1806 SET_VREG_WIDE a2, a4 # vAA <- a2 1807 GOTO_OPCODE v0 # jump to next instruction 1808 1809/* ------------------------------ */ 1810 .balign 128 1811.L_op_aget_object: /* 0x46 */ 1812/* File: mips64/op_aget_object.S */ 1813 /* 1814 * Array object get. vAA <- vBB[vCC]. 1815 * 1816 * for: aget-object 1817 */ 1818 /* op vAA, vBB, vCC */ 1819 .extern artAGetObjectFromMterp 1820 lbu a2, 2(rPC) # a2 <- BB 1821 lbu a3, 3(rPC) # a3 <- CC 1822 EXPORT_PC 1823 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1824 GET_VREG a1, a3 # a1 <- vCC (requested index) 1825 jal artAGetObjectFromMterp # (array, index) 1826 ld a1, THREAD_EXCEPTION_OFFSET(rSELF) 1827 srl a4, rINST, 8 # a4 <- AA 1828 PREFETCH_INST 2 1829 bnez a1, MterpException 1830 SET_VREG_OBJECT v0, a4 # vAA <- v0 1831 ADVANCE 2 1832 GET_INST_OPCODE v0 # extract opcode from rINST 1833 GOTO_OPCODE v0 # jump to next instruction 1834 1835/* ------------------------------ */ 1836 .balign 128 1837.L_op_aget_boolean: /* 0x47 */ 1838/* File: mips64/op_aget_boolean.S */ 1839/* File: mips64/op_aget.S */ 1840 /* 1841 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1842 * 1843 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1844 * 1845 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1846 * If this changes, specialize. 1847 */ 1848 /* op vAA, vBB, vCC */ 1849 lbu a2, 2(rPC) # a2 <- BB 1850 lbu a3, 3(rPC) # a3 <- CC 1851 srl a4, rINST, 8 # a4 <- AA 1852 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1853 GET_VREG a1, a3 # a1 <- vCC (requested index) 1854 beqz a0, common_errNullObject # bail if null array object 1855 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1856 .if 0 1857 # [d]lsa does not support shift count of 0. 1858 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 1859 .else 1860 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1861 .endif 1862 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1863 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1864 lbu a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1865 GET_INST_OPCODE v0 # extract opcode from rINST 1866 SET_VREG a2, a4 # vAA <- a2 1867 GOTO_OPCODE v0 # jump to next instruction 1868 1869 1870/* ------------------------------ */ 1871 .balign 128 1872.L_op_aget_byte: /* 0x48 */ 1873/* File: mips64/op_aget_byte.S */ 1874/* File: mips64/op_aget.S */ 1875 /* 1876 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1877 * 1878 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1879 * 1880 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1881 * If this changes, specialize. 1882 */ 1883 /* op vAA, vBB, vCC */ 1884 lbu a2, 2(rPC) # a2 <- BB 1885 lbu a3, 3(rPC) # a3 <- CC 1886 srl a4, rINST, 8 # a4 <- AA 1887 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1888 GET_VREG a1, a3 # a1 <- vCC (requested index) 1889 beqz a0, common_errNullObject # bail if null array object 1890 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1891 .if 0 1892 # [d]lsa does not support shift count of 0. 1893 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 1894 .else 1895 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1896 .endif 1897 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1898 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1899 lb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1900 GET_INST_OPCODE v0 # extract opcode from rINST 1901 SET_VREG a2, a4 # vAA <- a2 1902 GOTO_OPCODE v0 # jump to next instruction 1903 1904 1905/* ------------------------------ */ 1906 .balign 128 1907.L_op_aget_char: /* 0x49 */ 1908/* File: mips64/op_aget_char.S */ 1909/* File: mips64/op_aget.S */ 1910 /* 1911 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1912 * 1913 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1914 * 1915 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1916 * If this changes, specialize. 1917 */ 1918 /* op vAA, vBB, vCC */ 1919 lbu a2, 2(rPC) # a2 <- BB 1920 lbu a3, 3(rPC) # a3 <- CC 1921 srl a4, rINST, 8 # a4 <- AA 1922 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1923 GET_VREG a1, a3 # a1 <- vCC (requested index) 1924 beqz a0, common_errNullObject # bail if null array object 1925 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1926 .if 1 1927 # [d]lsa does not support shift count of 0. 1928 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 1929 .else 1930 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1931 .endif 1932 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1933 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1934 lhu a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1935 GET_INST_OPCODE v0 # extract opcode from rINST 1936 SET_VREG a2, a4 # vAA <- a2 1937 GOTO_OPCODE v0 # jump to next instruction 1938 1939 1940/* ------------------------------ */ 1941 .balign 128 1942.L_op_aget_short: /* 0x4a */ 1943/* File: mips64/op_aget_short.S */ 1944/* File: mips64/op_aget.S */ 1945 /* 1946 * Array get, 32 bits or less. vAA <- vBB[vCC]. 1947 * 1948 * for: aget, aget-boolean, aget-byte, aget-char, aget-short 1949 * 1950 * NOTE: assumes data offset for arrays is the same for all non-wide types. 1951 * If this changes, specialize. 1952 */ 1953 /* op vAA, vBB, vCC */ 1954 lbu a2, 2(rPC) # a2 <- BB 1955 lbu a3, 3(rPC) # a3 <- CC 1956 srl a4, rINST, 8 # a4 <- AA 1957 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1958 GET_VREG a1, a3 # a1 <- vCC (requested index) 1959 beqz a0, common_errNullObject # bail if null array object 1960 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1961 .if 1 1962 # [d]lsa does not support shift count of 0. 1963 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 1964 .else 1965 daddu a0, a1, a0 # a0 <- arrayObj + index*width 1966 .endif 1967 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 1968 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 1969 lh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # a2 <- vBB[vCC] 1970 GET_INST_OPCODE v0 # extract opcode from rINST 1971 SET_VREG a2, a4 # vAA <- a2 1972 GOTO_OPCODE v0 # jump to next instruction 1973 1974 1975/* ------------------------------ */ 1976 .balign 128 1977.L_op_aput: /* 0x4b */ 1978/* File: mips64/op_aput.S */ 1979 /* 1980 * Array put, 32 bits or less. vBB[vCC] <- vAA. 1981 * 1982 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 1983 * 1984 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 1985 * If this changes, specialize. 1986 */ 1987 /* op vAA, vBB, vCC */ 1988 lbu a2, 2(rPC) # a2 <- BB 1989 lbu a3, 3(rPC) # a3 <- CC 1990 srl a4, rINST, 8 # a4 <- AA 1991 GET_VREG_U a0, a2 # a0 <- vBB (array object) 1992 GET_VREG a1, a3 # a1 <- vCC (requested index) 1993 beqz a0, common_errNullObject # bail if null array object 1994 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 1995 .if 2 1996 # [d]lsa does not support shift count of 0. 1997 dlsa a0, a1, a0, 2 # a0 <- arrayObj + index*width 1998 .else 1999 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2000 .endif 2001 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2002 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2003 GET_VREG a2, a4 # a2 <- vAA 2004 GET_INST_OPCODE v0 # extract opcode from rINST 2005 sw a2, MIRROR_INT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2006 GOTO_OPCODE v0 # jump to next instruction 2007 2008/* ------------------------------ */ 2009 .balign 128 2010.L_op_aput_wide: /* 0x4c */ 2011/* File: mips64/op_aput_wide.S */ 2012 /* 2013 * Array put, 64 bits. vBB[vCC] <- vAA. 2014 * 2015 */ 2016 /* aput-wide vAA, vBB, vCC */ 2017 lbu a2, 2(rPC) # a2 <- BB 2018 lbu a3, 3(rPC) # a3 <- CC 2019 srl a4, rINST, 8 # a4 <- AA 2020 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2021 GET_VREG a1, a3 # a1 <- vCC (requested index) 2022 beqz a0, common_errNullObject # bail if null array object 2023 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2024 dlsa a0, a1, a0, 3 # a0 <- arrayObj + index*width 2025 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2026 GET_VREG_WIDE a2, a4 # a2 <- vAA 2027 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2028 GET_INST_OPCODE v0 # extract opcode from rINST 2029 sw a2, MIRROR_WIDE_ARRAY_DATA_OFFSET(a0) 2030 dsrl32 a2, a2, 0 2031 sw a2, (MIRROR_WIDE_ARRAY_DATA_OFFSET+4)(a0) # vBB[vCC] <- a2 2032 GOTO_OPCODE v0 # jump to next instruction 2033 2034/* ------------------------------ */ 2035 .balign 128 2036.L_op_aput_object: /* 0x4d */ 2037/* File: mips64/op_aput_object.S */ 2038 /* 2039 * Store an object into an array. vBB[vCC] <- vAA. 2040 */ 2041 /* op vAA, vBB, vCC */ 2042 .extern MterpAputObject 2043 EXPORT_PC 2044 daddu a0, rFP, OFF_FP_SHADOWFRAME 2045 move a1, rPC 2046 move a2, rINST 2047 jal MterpAputObject 2048 beqzc v0, MterpPossibleException 2049 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2050 GET_INST_OPCODE v0 # extract opcode from rINST 2051 GOTO_OPCODE v0 # jump to next instruction 2052 2053/* ------------------------------ */ 2054 .balign 128 2055.L_op_aput_boolean: /* 0x4e */ 2056/* File: mips64/op_aput_boolean.S */ 2057/* File: mips64/op_aput.S */ 2058 /* 2059 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2060 * 2061 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2062 * 2063 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2064 * If this changes, specialize. 2065 */ 2066 /* op vAA, vBB, vCC */ 2067 lbu a2, 2(rPC) # a2 <- BB 2068 lbu a3, 3(rPC) # a3 <- CC 2069 srl a4, rINST, 8 # a4 <- AA 2070 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2071 GET_VREG a1, a3 # a1 <- vCC (requested index) 2072 beqz a0, common_errNullObject # bail if null array object 2073 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2074 .if 0 2075 # [d]lsa does not support shift count of 0. 2076 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 2077 .else 2078 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2079 .endif 2080 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2081 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2082 GET_VREG a2, a4 # a2 <- vAA 2083 GET_INST_OPCODE v0 # extract opcode from rINST 2084 sb a2, MIRROR_BOOLEAN_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2085 GOTO_OPCODE v0 # jump to next instruction 2086 2087 2088/* ------------------------------ */ 2089 .balign 128 2090.L_op_aput_byte: /* 0x4f */ 2091/* File: mips64/op_aput_byte.S */ 2092/* File: mips64/op_aput.S */ 2093 /* 2094 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2095 * 2096 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2097 * 2098 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2099 * If this changes, specialize. 2100 */ 2101 /* op vAA, vBB, vCC */ 2102 lbu a2, 2(rPC) # a2 <- BB 2103 lbu a3, 3(rPC) # a3 <- CC 2104 srl a4, rINST, 8 # a4 <- AA 2105 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2106 GET_VREG a1, a3 # a1 <- vCC (requested index) 2107 beqz a0, common_errNullObject # bail if null array object 2108 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2109 .if 0 2110 # [d]lsa does not support shift count of 0. 2111 dlsa a0, a1, a0, 0 # a0 <- arrayObj + index*width 2112 .else 2113 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2114 .endif 2115 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2116 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2117 GET_VREG a2, a4 # a2 <- vAA 2118 GET_INST_OPCODE v0 # extract opcode from rINST 2119 sb a2, MIRROR_BYTE_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2120 GOTO_OPCODE v0 # jump to next instruction 2121 2122 2123/* ------------------------------ */ 2124 .balign 128 2125.L_op_aput_char: /* 0x50 */ 2126/* File: mips64/op_aput_char.S */ 2127/* File: mips64/op_aput.S */ 2128 /* 2129 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2130 * 2131 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2132 * 2133 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2134 * If this changes, specialize. 2135 */ 2136 /* op vAA, vBB, vCC */ 2137 lbu a2, 2(rPC) # a2 <- BB 2138 lbu a3, 3(rPC) # a3 <- CC 2139 srl a4, rINST, 8 # a4 <- AA 2140 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2141 GET_VREG a1, a3 # a1 <- vCC (requested index) 2142 beqz a0, common_errNullObject # bail if null array object 2143 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2144 .if 1 2145 # [d]lsa does not support shift count of 0. 2146 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 2147 .else 2148 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2149 .endif 2150 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2151 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2152 GET_VREG a2, a4 # a2 <- vAA 2153 GET_INST_OPCODE v0 # extract opcode from rINST 2154 sh a2, MIRROR_CHAR_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2155 GOTO_OPCODE v0 # jump to next instruction 2156 2157 2158/* ------------------------------ */ 2159 .balign 128 2160.L_op_aput_short: /* 0x51 */ 2161/* File: mips64/op_aput_short.S */ 2162/* File: mips64/op_aput.S */ 2163 /* 2164 * Array put, 32 bits or less. vBB[vCC] <- vAA. 2165 * 2166 * for: aput, aput-boolean, aput-byte, aput-char, aput-short 2167 * 2168 * NOTE: this assumes data offset for arrays is the same for all non-wide types. 2169 * If this changes, specialize. 2170 */ 2171 /* op vAA, vBB, vCC */ 2172 lbu a2, 2(rPC) # a2 <- BB 2173 lbu a3, 3(rPC) # a3 <- CC 2174 srl a4, rINST, 8 # a4 <- AA 2175 GET_VREG_U a0, a2 # a0 <- vBB (array object) 2176 GET_VREG a1, a3 # a1 <- vCC (requested index) 2177 beqz a0, common_errNullObject # bail if null array object 2178 lw a3, MIRROR_ARRAY_LENGTH_OFFSET(a0) # a3 <- arrayObj->length 2179 .if 1 2180 # [d]lsa does not support shift count of 0. 2181 dlsa a0, a1, a0, 1 # a0 <- arrayObj + index*width 2182 .else 2183 daddu a0, a1, a0 # a0 <- arrayObj + index*width 2184 .endif 2185 bgeu a1, a3, common_errArrayIndex # unsigned compare: index >= length, bail 2186 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2187 GET_VREG a2, a4 # a2 <- vAA 2188 GET_INST_OPCODE v0 # extract opcode from rINST 2189 sh a2, MIRROR_SHORT_ARRAY_DATA_OFFSET(a0) # vBB[vCC] <- a2 2190 GOTO_OPCODE v0 # jump to next instruction 2191 2192 2193/* ------------------------------ */ 2194 .balign 128 2195.L_op_iget: /* 0x52 */ 2196/* File: mips64/op_iget.S */ 2197 /* 2198 * General instance field get. 2199 * 2200 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2201 */ 2202 .extern artGet32InstanceFromCode 2203 EXPORT_PC 2204 lhu a0, 2(rPC) # a0 <- field ref CCCC 2205 srl a1, rINST, 12 # a1 <- B 2206 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2207 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2208 move a3, rSELF # a3 <- self 2209 jal artGet32InstanceFromCode 2210 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2211 ext a2, rINST, 8, 4 # a2 <- A 2212 PREFETCH_INST 2 2213 bnez a3, MterpPossibleException # bail out 2214 .if 0 2215 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2216 .else 2217 SET_VREG v0, a2 # fp[A] <- v0 2218 .endif 2219 ADVANCE 2 2220 GET_INST_OPCODE v0 # extract opcode from rINST 2221 GOTO_OPCODE v0 # jump to next instruction 2222 2223/* ------------------------------ */ 2224 .balign 128 2225.L_op_iget_wide: /* 0x53 */ 2226/* File: mips64/op_iget_wide.S */ 2227 /* 2228 * 64-bit instance field get. 2229 * 2230 * for: iget-wide 2231 */ 2232 .extern artGet64InstanceFromCode 2233 EXPORT_PC 2234 lhu a0, 2(rPC) # a0 <- field ref CCCC 2235 srl a1, rINST, 12 # a1 <- B 2236 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2237 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2238 move a3, rSELF # a3 <- self 2239 jal artGet64InstanceFromCode 2240 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2241 ext a2, rINST, 8, 4 # a2 <- A 2242 PREFETCH_INST 2 2243 bnez a3, MterpPossibleException # bail out 2244 SET_VREG_WIDE v0, a2 # fp[A] <- v0 2245 ADVANCE 2 2246 GET_INST_OPCODE v0 # extract opcode from rINST 2247 GOTO_OPCODE v0 # jump to next instruction 2248 2249/* ------------------------------ */ 2250 .balign 128 2251.L_op_iget_object: /* 0x54 */ 2252/* File: mips64/op_iget_object.S */ 2253/* File: mips64/op_iget.S */ 2254 /* 2255 * General instance field get. 2256 * 2257 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2258 */ 2259 .extern artGetObjInstanceFromCode 2260 EXPORT_PC 2261 lhu a0, 2(rPC) # a0 <- field ref CCCC 2262 srl a1, rINST, 12 # a1 <- B 2263 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2264 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2265 move a3, rSELF # a3 <- self 2266 jal artGetObjInstanceFromCode 2267 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2268 ext a2, rINST, 8, 4 # a2 <- A 2269 PREFETCH_INST 2 2270 bnez a3, MterpPossibleException # bail out 2271 .if 1 2272 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2273 .else 2274 SET_VREG v0, a2 # fp[A] <- v0 2275 .endif 2276 ADVANCE 2 2277 GET_INST_OPCODE v0 # extract opcode from rINST 2278 GOTO_OPCODE v0 # jump to next instruction 2279 2280 2281/* ------------------------------ */ 2282 .balign 128 2283.L_op_iget_boolean: /* 0x55 */ 2284/* File: mips64/op_iget_boolean.S */ 2285/* File: mips64/op_iget.S */ 2286 /* 2287 * General instance field get. 2288 * 2289 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2290 */ 2291 .extern artGetBooleanInstanceFromCode 2292 EXPORT_PC 2293 lhu a0, 2(rPC) # a0 <- field ref CCCC 2294 srl a1, rINST, 12 # a1 <- B 2295 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2296 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2297 move a3, rSELF # a3 <- self 2298 jal artGetBooleanInstanceFromCode 2299 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2300 ext a2, rINST, 8, 4 # a2 <- A 2301 PREFETCH_INST 2 2302 bnez a3, MterpPossibleException # bail out 2303 .if 0 2304 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2305 .else 2306 SET_VREG v0, a2 # fp[A] <- v0 2307 .endif 2308 ADVANCE 2 2309 GET_INST_OPCODE v0 # extract opcode from rINST 2310 GOTO_OPCODE v0 # jump to next instruction 2311 2312 2313/* ------------------------------ */ 2314 .balign 128 2315.L_op_iget_byte: /* 0x56 */ 2316/* File: mips64/op_iget_byte.S */ 2317/* File: mips64/op_iget.S */ 2318 /* 2319 * General instance field get. 2320 * 2321 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2322 */ 2323 .extern artGetByteInstanceFromCode 2324 EXPORT_PC 2325 lhu a0, 2(rPC) # a0 <- field ref CCCC 2326 srl a1, rINST, 12 # a1 <- B 2327 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2328 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2329 move a3, rSELF # a3 <- self 2330 jal artGetByteInstanceFromCode 2331 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2332 ext a2, rINST, 8, 4 # a2 <- A 2333 PREFETCH_INST 2 2334 bnez a3, MterpPossibleException # bail out 2335 .if 0 2336 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2337 .else 2338 SET_VREG v0, a2 # fp[A] <- v0 2339 .endif 2340 ADVANCE 2 2341 GET_INST_OPCODE v0 # extract opcode from rINST 2342 GOTO_OPCODE v0 # jump to next instruction 2343 2344 2345/* ------------------------------ */ 2346 .balign 128 2347.L_op_iget_char: /* 0x57 */ 2348/* File: mips64/op_iget_char.S */ 2349/* File: mips64/op_iget.S */ 2350 /* 2351 * General instance field get. 2352 * 2353 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2354 */ 2355 .extern artGetCharInstanceFromCode 2356 EXPORT_PC 2357 lhu a0, 2(rPC) # a0 <- field ref CCCC 2358 srl a1, rINST, 12 # a1 <- B 2359 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2360 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2361 move a3, rSELF # a3 <- self 2362 jal artGetCharInstanceFromCode 2363 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2364 ext a2, rINST, 8, 4 # a2 <- A 2365 PREFETCH_INST 2 2366 bnez a3, MterpPossibleException # bail out 2367 .if 0 2368 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2369 .else 2370 SET_VREG v0, a2 # fp[A] <- v0 2371 .endif 2372 ADVANCE 2 2373 GET_INST_OPCODE v0 # extract opcode from rINST 2374 GOTO_OPCODE v0 # jump to next instruction 2375 2376 2377/* ------------------------------ */ 2378 .balign 128 2379.L_op_iget_short: /* 0x58 */ 2380/* File: mips64/op_iget_short.S */ 2381/* File: mips64/op_iget.S */ 2382 /* 2383 * General instance field get. 2384 * 2385 * for: iget, iget-object, iget-boolean, iget-byte, iget-char, iget-short 2386 */ 2387 .extern artGetShortInstanceFromCode 2388 EXPORT_PC 2389 lhu a0, 2(rPC) # a0 <- field ref CCCC 2390 srl a1, rINST, 12 # a1 <- B 2391 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2392 ld a2, OFF_FP_METHOD(rFP) # a2 <- referrer 2393 move a3, rSELF # a3 <- self 2394 jal artGetShortInstanceFromCode 2395 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2396 ext a2, rINST, 8, 4 # a2 <- A 2397 PREFETCH_INST 2 2398 bnez a3, MterpPossibleException # bail out 2399 .if 0 2400 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 2401 .else 2402 SET_VREG v0, a2 # fp[A] <- v0 2403 .endif 2404 ADVANCE 2 2405 GET_INST_OPCODE v0 # extract opcode from rINST 2406 GOTO_OPCODE v0 # jump to next instruction 2407 2408 2409/* ------------------------------ */ 2410 .balign 128 2411.L_op_iput: /* 0x59 */ 2412/* File: mips64/op_iput.S */ 2413 /* 2414 * General 32-bit instance field put. 2415 * 2416 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2417 */ 2418 /* op vA, vB, field//CCCC */ 2419 .extern artSet32InstanceFromMterp 2420 EXPORT_PC 2421 lhu a0, 2(rPC) # a0 <- field ref CCCC 2422 srl a1, rINST, 12 # a1 <- B 2423 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2424 ext a2, rINST, 8, 4 # a2 <- A 2425 GET_VREG a2, a2 # a2 <- fp[A] 2426 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2427 PREFETCH_INST 2 2428 jal artSet32InstanceFromMterp 2429 bnez v0, MterpPossibleException # bail out 2430 ADVANCE 2 2431 GET_INST_OPCODE v0 # extract opcode from rINST 2432 GOTO_OPCODE v0 # jump to next instruction 2433 2434/* ------------------------------ */ 2435 .balign 128 2436.L_op_iput_wide: /* 0x5a */ 2437/* File: mips64/op_iput_wide.S */ 2438 /* iput-wide vA, vB, field//CCCC */ 2439 .extern artSet64InstanceFromMterp 2440 EXPORT_PC 2441 lhu a0, 2(rPC) # a0 <- field ref CCCC 2442 srl a1, rINST, 12 # a1 <- B 2443 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2444 ext a2, rINST, 8, 4 # a2 <- A 2445 dlsa a2, a2, rFP, 2 # a2 <- &fp[A] 2446 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2447 PREFETCH_INST 2 2448 jal artSet64InstanceFromMterp 2449 bnez v0, MterpPossibleException # bail out 2450 ADVANCE 2 2451 GET_INST_OPCODE v0 # extract opcode from rINST 2452 GOTO_OPCODE v0 # jump to next instruction 2453 2454/* ------------------------------ */ 2455 .balign 128 2456.L_op_iput_object: /* 0x5b */ 2457/* File: mips64/op_iput_object.S */ 2458 .extern MterpIputObject 2459 EXPORT_PC 2460 daddu a0, rFP, OFF_FP_SHADOWFRAME 2461 move a1, rPC 2462 move a2, rINST 2463 move a3, rSELF 2464 jal MterpIputObject 2465 beqzc v0, MterpException 2466 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2467 GET_INST_OPCODE v0 # extract opcode from rINST 2468 GOTO_OPCODE v0 # jump to next instruction 2469 2470/* ------------------------------ */ 2471 .balign 128 2472.L_op_iput_boolean: /* 0x5c */ 2473/* File: mips64/op_iput_boolean.S */ 2474/* File: mips64/op_iput.S */ 2475 /* 2476 * General 32-bit instance field put. 2477 * 2478 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2479 */ 2480 /* op vA, vB, field//CCCC */ 2481 .extern artSet8InstanceFromMterp 2482 EXPORT_PC 2483 lhu a0, 2(rPC) # a0 <- field ref CCCC 2484 srl a1, rINST, 12 # a1 <- B 2485 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2486 ext a2, rINST, 8, 4 # a2 <- A 2487 GET_VREG a2, a2 # a2 <- fp[A] 2488 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2489 PREFETCH_INST 2 2490 jal artSet8InstanceFromMterp 2491 bnez v0, MterpPossibleException # bail out 2492 ADVANCE 2 2493 GET_INST_OPCODE v0 # extract opcode from rINST 2494 GOTO_OPCODE v0 # jump to next instruction 2495 2496 2497/* ------------------------------ */ 2498 .balign 128 2499.L_op_iput_byte: /* 0x5d */ 2500/* File: mips64/op_iput_byte.S */ 2501/* File: mips64/op_iput.S */ 2502 /* 2503 * General 32-bit instance field put. 2504 * 2505 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2506 */ 2507 /* op vA, vB, field//CCCC */ 2508 .extern artSet8InstanceFromMterp 2509 EXPORT_PC 2510 lhu a0, 2(rPC) # a0 <- field ref CCCC 2511 srl a1, rINST, 12 # a1 <- B 2512 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2513 ext a2, rINST, 8, 4 # a2 <- A 2514 GET_VREG a2, a2 # a2 <- fp[A] 2515 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2516 PREFETCH_INST 2 2517 jal artSet8InstanceFromMterp 2518 bnez v0, MterpPossibleException # bail out 2519 ADVANCE 2 2520 GET_INST_OPCODE v0 # extract opcode from rINST 2521 GOTO_OPCODE v0 # jump to next instruction 2522 2523 2524/* ------------------------------ */ 2525 .balign 128 2526.L_op_iput_char: /* 0x5e */ 2527/* File: mips64/op_iput_char.S */ 2528/* File: mips64/op_iput.S */ 2529 /* 2530 * General 32-bit instance field put. 2531 * 2532 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2533 */ 2534 /* op vA, vB, field//CCCC */ 2535 .extern artSet16InstanceFromMterp 2536 EXPORT_PC 2537 lhu a0, 2(rPC) # a0 <- field ref CCCC 2538 srl a1, rINST, 12 # a1 <- B 2539 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2540 ext a2, rINST, 8, 4 # a2 <- A 2541 GET_VREG a2, a2 # a2 <- fp[A] 2542 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2543 PREFETCH_INST 2 2544 jal artSet16InstanceFromMterp 2545 bnez v0, MterpPossibleException # bail out 2546 ADVANCE 2 2547 GET_INST_OPCODE v0 # extract opcode from rINST 2548 GOTO_OPCODE v0 # jump to next instruction 2549 2550 2551/* ------------------------------ */ 2552 .balign 128 2553.L_op_iput_short: /* 0x5f */ 2554/* File: mips64/op_iput_short.S */ 2555/* File: mips64/op_iput.S */ 2556 /* 2557 * General 32-bit instance field put. 2558 * 2559 * for: iput, iput-boolean, iput-byte, iput-char, iput-short 2560 */ 2561 /* op vA, vB, field//CCCC */ 2562 .extern artSet16InstanceFromMterp 2563 EXPORT_PC 2564 lhu a0, 2(rPC) # a0 <- field ref CCCC 2565 srl a1, rINST, 12 # a1 <- B 2566 GET_VREG_U a1, a1 # a1 <- fp[B], the object pointer 2567 ext a2, rINST, 8, 4 # a2 <- A 2568 GET_VREG a2, a2 # a2 <- fp[A] 2569 ld a3, OFF_FP_METHOD(rFP) # a3 <- referrer 2570 PREFETCH_INST 2 2571 jal artSet16InstanceFromMterp 2572 bnez v0, MterpPossibleException # bail out 2573 ADVANCE 2 2574 GET_INST_OPCODE v0 # extract opcode from rINST 2575 GOTO_OPCODE v0 # jump to next instruction 2576 2577 2578/* ------------------------------ */ 2579 .balign 128 2580.L_op_sget: /* 0x60 */ 2581/* File: mips64/op_sget.S */ 2582 /* 2583 * General SGET handler wrapper. 2584 * 2585 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2586 */ 2587 /* op vAA, field//BBBB */ 2588 .extern MterpGet32Static 2589 EXPORT_PC 2590 lhu a0, 2(rPC) # a0 <- field ref BBBB 2591 ld a1, OFF_FP_METHOD(rFP) 2592 move a2, rSELF 2593 jal MterpGet32Static 2594 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2595 srl a2, rINST, 8 # a2 <- AA 2596 2597 PREFETCH_INST 2 2598 bnez a3, MterpException # bail out 2599 .if 0 2600 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2601 .else 2602 SET_VREG v0, a2 # fp[AA] <- v0 2603 .endif 2604 ADVANCE 2 2605 GET_INST_OPCODE v0 # extract opcode from rINST 2606 GOTO_OPCODE v0 2607 2608/* ------------------------------ */ 2609 .balign 128 2610.L_op_sget_wide: /* 0x61 */ 2611/* File: mips64/op_sget_wide.S */ 2612 /* 2613 * SGET_WIDE handler wrapper. 2614 * 2615 */ 2616 /* sget-wide vAA, field//BBBB */ 2617 .extern MterpGet64Static 2618 EXPORT_PC 2619 lhu a0, 2(rPC) # a0 <- field ref BBBB 2620 ld a1, OFF_FP_METHOD(rFP) 2621 move a2, rSELF 2622 jal MterpGet64Static 2623 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2624 srl a4, rINST, 8 # a4 <- AA 2625 bnez a3, MterpException # bail out 2626 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2627 SET_VREG_WIDE v0, a4 2628 GET_INST_OPCODE v0 # extract opcode from rINST 2629 GOTO_OPCODE v0 # jump to next instruction 2630 2631/* ------------------------------ */ 2632 .balign 128 2633.L_op_sget_object: /* 0x62 */ 2634/* File: mips64/op_sget_object.S */ 2635/* File: mips64/op_sget.S */ 2636 /* 2637 * General SGET handler wrapper. 2638 * 2639 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2640 */ 2641 /* op vAA, field//BBBB */ 2642 .extern MterpGetObjStatic 2643 EXPORT_PC 2644 lhu a0, 2(rPC) # a0 <- field ref BBBB 2645 ld a1, OFF_FP_METHOD(rFP) 2646 move a2, rSELF 2647 jal MterpGetObjStatic 2648 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2649 srl a2, rINST, 8 # a2 <- AA 2650 2651 PREFETCH_INST 2 2652 bnez a3, MterpException # bail out 2653 .if 1 2654 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2655 .else 2656 SET_VREG v0, a2 # fp[AA] <- v0 2657 .endif 2658 ADVANCE 2 2659 GET_INST_OPCODE v0 # extract opcode from rINST 2660 GOTO_OPCODE v0 2661 2662 2663/* ------------------------------ */ 2664 .balign 128 2665.L_op_sget_boolean: /* 0x63 */ 2666/* File: mips64/op_sget_boolean.S */ 2667/* File: mips64/op_sget.S */ 2668 /* 2669 * General SGET handler wrapper. 2670 * 2671 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2672 */ 2673 /* op vAA, field//BBBB */ 2674 .extern MterpGetBooleanStatic 2675 EXPORT_PC 2676 lhu a0, 2(rPC) # a0 <- field ref BBBB 2677 ld a1, OFF_FP_METHOD(rFP) 2678 move a2, rSELF 2679 jal MterpGetBooleanStatic 2680 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2681 srl a2, rINST, 8 # a2 <- AA 2682 and v0, v0, 0xff 2683 PREFETCH_INST 2 2684 bnez a3, MterpException # bail out 2685 .if 0 2686 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2687 .else 2688 SET_VREG v0, a2 # fp[AA] <- v0 2689 .endif 2690 ADVANCE 2 2691 GET_INST_OPCODE v0 # extract opcode from rINST 2692 GOTO_OPCODE v0 2693 2694 2695/* ------------------------------ */ 2696 .balign 128 2697.L_op_sget_byte: /* 0x64 */ 2698/* File: mips64/op_sget_byte.S */ 2699/* File: mips64/op_sget.S */ 2700 /* 2701 * General SGET handler wrapper. 2702 * 2703 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2704 */ 2705 /* op vAA, field//BBBB */ 2706 .extern MterpGetByteStatic 2707 EXPORT_PC 2708 lhu a0, 2(rPC) # a0 <- field ref BBBB 2709 ld a1, OFF_FP_METHOD(rFP) 2710 move a2, rSELF 2711 jal MterpGetByteStatic 2712 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2713 srl a2, rINST, 8 # a2 <- AA 2714 seb v0, v0 2715 PREFETCH_INST 2 2716 bnez a3, MterpException # bail out 2717 .if 0 2718 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2719 .else 2720 SET_VREG v0, a2 # fp[AA] <- v0 2721 .endif 2722 ADVANCE 2 2723 GET_INST_OPCODE v0 # extract opcode from rINST 2724 GOTO_OPCODE v0 2725 2726 2727/* ------------------------------ */ 2728 .balign 128 2729.L_op_sget_char: /* 0x65 */ 2730/* File: mips64/op_sget_char.S */ 2731/* File: mips64/op_sget.S */ 2732 /* 2733 * General SGET handler wrapper. 2734 * 2735 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2736 */ 2737 /* op vAA, field//BBBB */ 2738 .extern MterpGetCharStatic 2739 EXPORT_PC 2740 lhu a0, 2(rPC) # a0 <- field ref BBBB 2741 ld a1, OFF_FP_METHOD(rFP) 2742 move a2, rSELF 2743 jal MterpGetCharStatic 2744 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2745 srl a2, rINST, 8 # a2 <- AA 2746 and v0, v0, 0xffff 2747 PREFETCH_INST 2 2748 bnez a3, MterpException # bail out 2749 .if 0 2750 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2751 .else 2752 SET_VREG v0, a2 # fp[AA] <- v0 2753 .endif 2754 ADVANCE 2 2755 GET_INST_OPCODE v0 # extract opcode from rINST 2756 GOTO_OPCODE v0 2757 2758 2759/* ------------------------------ */ 2760 .balign 128 2761.L_op_sget_short: /* 0x66 */ 2762/* File: mips64/op_sget_short.S */ 2763/* File: mips64/op_sget.S */ 2764 /* 2765 * General SGET handler wrapper. 2766 * 2767 * for: sget, sget-object, sget-boolean, sget-byte, sget-char, sget-short 2768 */ 2769 /* op vAA, field//BBBB */ 2770 .extern MterpGetShortStatic 2771 EXPORT_PC 2772 lhu a0, 2(rPC) # a0 <- field ref BBBB 2773 ld a1, OFF_FP_METHOD(rFP) 2774 move a2, rSELF 2775 jal MterpGetShortStatic 2776 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 2777 srl a2, rINST, 8 # a2 <- AA 2778 seh v0, v0 2779 PREFETCH_INST 2 2780 bnez a3, MterpException # bail out 2781 .if 0 2782 SET_VREG_OBJECT v0, a2 # fp[AA] <- v0 2783 .else 2784 SET_VREG v0, a2 # fp[AA] <- v0 2785 .endif 2786 ADVANCE 2 2787 GET_INST_OPCODE v0 # extract opcode from rINST 2788 GOTO_OPCODE v0 2789 2790 2791/* ------------------------------ */ 2792 .balign 128 2793.L_op_sput: /* 0x67 */ 2794/* File: mips64/op_sput.S */ 2795 /* 2796 * General SPUT handler wrapper. 2797 * 2798 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2799 */ 2800 /* op vAA, field//BBBB */ 2801 .extern MterpSet32Static 2802 EXPORT_PC 2803 lhu a0, 2(rPC) # a0 <- field ref BBBB 2804 srl a3, rINST, 8 # a3 <- AA 2805 GET_VREG a1, a3 # a1 <- fp[AA] 2806 ld a2, OFF_FP_METHOD(rFP) 2807 move a3, rSELF 2808 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2809 jal MterpSet32Static 2810 bnezc v0, MterpException # 0 on success 2811 ADVANCE 2 # Past exception point - now advance rPC 2812 GET_INST_OPCODE v0 # extract opcode from rINST 2813 GOTO_OPCODE v0 # jump to next instruction 2814 2815/* ------------------------------ */ 2816 .balign 128 2817.L_op_sput_wide: /* 0x68 */ 2818/* File: mips64/op_sput_wide.S */ 2819 /* 2820 * SPUT_WIDE handler wrapper. 2821 * 2822 */ 2823 /* sput-wide vAA, field//BBBB */ 2824 .extern MterpSet64Static 2825 EXPORT_PC 2826 lhu a0, 2(rPC) # a0 <- field ref BBBB 2827 srl a1, rINST, 8 # a2 <- AA 2828 dlsa a1, a1, rFP, 2 2829 ld a2, OFF_FP_METHOD(rFP) 2830 move a3, rSELF 2831 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2832 jal MterpSet64Static 2833 bnezc v0, MterpException # 0 on success, -1 on failure 2834 ADVANCE 2 # Past exception point - now advance rPC 2835 GET_INST_OPCODE v0 # extract opcode from rINST 2836 GOTO_OPCODE v0 # jump to next instruction 2837 2838/* ------------------------------ */ 2839 .balign 128 2840.L_op_sput_object: /* 0x69 */ 2841/* File: mips64/op_sput_object.S */ 2842 .extern MterpSputObject 2843 EXPORT_PC 2844 daddu a0, rFP, OFF_FP_SHADOWFRAME 2845 move a1, rPC 2846 move a2, rINST 2847 move a3, rSELF 2848 jal MterpSputObject 2849 beqzc v0, MterpException 2850 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 2851 GET_INST_OPCODE v0 # extract opcode from rINST 2852 GOTO_OPCODE v0 # jump to next instruction 2853 2854/* ------------------------------ */ 2855 .balign 128 2856.L_op_sput_boolean: /* 0x6a */ 2857/* File: mips64/op_sput_boolean.S */ 2858/* File: mips64/op_sput.S */ 2859 /* 2860 * General SPUT handler wrapper. 2861 * 2862 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2863 */ 2864 /* op vAA, field//BBBB */ 2865 .extern MterpSetBooleanStatic 2866 EXPORT_PC 2867 lhu a0, 2(rPC) # a0 <- field ref BBBB 2868 srl a3, rINST, 8 # a3 <- AA 2869 GET_VREG a1, a3 # a1 <- fp[AA] 2870 ld a2, OFF_FP_METHOD(rFP) 2871 move a3, rSELF 2872 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2873 jal MterpSetBooleanStatic 2874 bnezc v0, MterpException # 0 on success 2875 ADVANCE 2 # Past exception point - now advance rPC 2876 GET_INST_OPCODE v0 # extract opcode from rINST 2877 GOTO_OPCODE v0 # jump to next instruction 2878 2879 2880/* ------------------------------ */ 2881 .balign 128 2882.L_op_sput_byte: /* 0x6b */ 2883/* File: mips64/op_sput_byte.S */ 2884/* File: mips64/op_sput.S */ 2885 /* 2886 * General SPUT handler wrapper. 2887 * 2888 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2889 */ 2890 /* op vAA, field//BBBB */ 2891 .extern MterpSetByteStatic 2892 EXPORT_PC 2893 lhu a0, 2(rPC) # a0 <- field ref BBBB 2894 srl a3, rINST, 8 # a3 <- AA 2895 GET_VREG a1, a3 # a1 <- fp[AA] 2896 ld a2, OFF_FP_METHOD(rFP) 2897 move a3, rSELF 2898 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2899 jal MterpSetByteStatic 2900 bnezc v0, MterpException # 0 on success 2901 ADVANCE 2 # Past exception point - now advance rPC 2902 GET_INST_OPCODE v0 # extract opcode from rINST 2903 GOTO_OPCODE v0 # jump to next instruction 2904 2905 2906/* ------------------------------ */ 2907 .balign 128 2908.L_op_sput_char: /* 0x6c */ 2909/* File: mips64/op_sput_char.S */ 2910/* File: mips64/op_sput.S */ 2911 /* 2912 * General SPUT handler wrapper. 2913 * 2914 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2915 */ 2916 /* op vAA, field//BBBB */ 2917 .extern MterpSetCharStatic 2918 EXPORT_PC 2919 lhu a0, 2(rPC) # a0 <- field ref BBBB 2920 srl a3, rINST, 8 # a3 <- AA 2921 GET_VREG a1, a3 # a1 <- fp[AA] 2922 ld a2, OFF_FP_METHOD(rFP) 2923 move a3, rSELF 2924 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2925 jal MterpSetCharStatic 2926 bnezc v0, MterpException # 0 on success 2927 ADVANCE 2 # Past exception point - now advance rPC 2928 GET_INST_OPCODE v0 # extract opcode from rINST 2929 GOTO_OPCODE v0 # jump to next instruction 2930 2931 2932/* ------------------------------ */ 2933 .balign 128 2934.L_op_sput_short: /* 0x6d */ 2935/* File: mips64/op_sput_short.S */ 2936/* File: mips64/op_sput.S */ 2937 /* 2938 * General SPUT handler wrapper. 2939 * 2940 * for: sput, sput-boolean, sput-byte, sput-char, sput-short 2941 */ 2942 /* op vAA, field//BBBB */ 2943 .extern MterpSetShortStatic 2944 EXPORT_PC 2945 lhu a0, 2(rPC) # a0 <- field ref BBBB 2946 srl a3, rINST, 8 # a3 <- AA 2947 GET_VREG a1, a3 # a1 <- fp[AA] 2948 ld a2, OFF_FP_METHOD(rFP) 2949 move a3, rSELF 2950 PREFETCH_INST 2 # Get next inst, but don't advance rPC 2951 jal MterpSetShortStatic 2952 bnezc v0, MterpException # 0 on success 2953 ADVANCE 2 # Past exception point - now advance rPC 2954 GET_INST_OPCODE v0 # extract opcode from rINST 2955 GOTO_OPCODE v0 # jump to next instruction 2956 2957 2958/* ------------------------------ */ 2959 .balign 128 2960.L_op_invoke_virtual: /* 0x6e */ 2961/* File: mips64/op_invoke_virtual.S */ 2962/* File: mips64/invoke.S */ 2963 /* 2964 * Generic invoke handler wrapper. 2965 */ 2966 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2967 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2968 .extern MterpInvokeVirtual 2969 .extern MterpShouldSwitchInterpreters 2970 EXPORT_PC 2971 move a0, rSELF 2972 daddu a1, rFP, OFF_FP_SHADOWFRAME 2973 move a2, rPC 2974 move a3, rINST 2975 jal MterpInvokeVirtual 2976 beqzc v0, MterpException 2977 FETCH_ADVANCE_INST 3 2978 jal MterpShouldSwitchInterpreters 2979 bnezc v0, MterpFallback 2980 GET_INST_OPCODE v0 2981 GOTO_OPCODE v0 2982 2983 /* 2984 * Handle a virtual method call. 2985 * 2986 * for: invoke-virtual, invoke-virtual/range 2987 */ 2988 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 2989 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 2990 2991/* ------------------------------ */ 2992 .balign 128 2993.L_op_invoke_super: /* 0x6f */ 2994/* File: mips64/op_invoke_super.S */ 2995/* File: mips64/invoke.S */ 2996 /* 2997 * Generic invoke handler wrapper. 2998 */ 2999 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3000 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3001 .extern MterpInvokeSuper 3002 .extern MterpShouldSwitchInterpreters 3003 EXPORT_PC 3004 move a0, rSELF 3005 daddu a1, rFP, OFF_FP_SHADOWFRAME 3006 move a2, rPC 3007 move a3, rINST 3008 jal MterpInvokeSuper 3009 beqzc v0, MterpException 3010 FETCH_ADVANCE_INST 3 3011 jal MterpShouldSwitchInterpreters 3012 bnezc v0, MterpFallback 3013 GET_INST_OPCODE v0 3014 GOTO_OPCODE v0 3015 3016 /* 3017 * Handle a "super" method call. 3018 * 3019 * for: invoke-super, invoke-super/range 3020 */ 3021 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3022 /* op vAA, {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3023 3024/* ------------------------------ */ 3025 .balign 128 3026.L_op_invoke_direct: /* 0x70 */ 3027/* File: mips64/op_invoke_direct.S */ 3028/* File: mips64/invoke.S */ 3029 /* 3030 * Generic invoke handler wrapper. 3031 */ 3032 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3033 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3034 .extern MterpInvokeDirect 3035 .extern MterpShouldSwitchInterpreters 3036 EXPORT_PC 3037 move a0, rSELF 3038 daddu a1, rFP, OFF_FP_SHADOWFRAME 3039 move a2, rPC 3040 move a3, rINST 3041 jal MterpInvokeDirect 3042 beqzc v0, MterpException 3043 FETCH_ADVANCE_INST 3 3044 jal MterpShouldSwitchInterpreters 3045 bnezc v0, MterpFallback 3046 GET_INST_OPCODE v0 3047 GOTO_OPCODE v0 3048 3049 3050/* ------------------------------ */ 3051 .balign 128 3052.L_op_invoke_static: /* 0x71 */ 3053/* File: mips64/op_invoke_static.S */ 3054/* File: mips64/invoke.S */ 3055 /* 3056 * Generic invoke handler wrapper. 3057 */ 3058 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3059 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3060 .extern MterpInvokeStatic 3061 .extern MterpShouldSwitchInterpreters 3062 EXPORT_PC 3063 move a0, rSELF 3064 daddu a1, rFP, OFF_FP_SHADOWFRAME 3065 move a2, rPC 3066 move a3, rINST 3067 jal MterpInvokeStatic 3068 beqzc v0, MterpException 3069 FETCH_ADVANCE_INST 3 3070 jal MterpShouldSwitchInterpreters 3071 bnezc v0, MterpFallback 3072 GET_INST_OPCODE v0 3073 GOTO_OPCODE v0 3074 3075 3076/* ------------------------------ */ 3077 .balign 128 3078.L_op_invoke_interface: /* 0x72 */ 3079/* File: mips64/op_invoke_interface.S */ 3080/* File: mips64/invoke.S */ 3081 /* 3082 * Generic invoke handler wrapper. 3083 */ 3084 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3085 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3086 .extern MterpInvokeInterface 3087 .extern MterpShouldSwitchInterpreters 3088 EXPORT_PC 3089 move a0, rSELF 3090 daddu a1, rFP, OFF_FP_SHADOWFRAME 3091 move a2, rPC 3092 move a3, rINST 3093 jal MterpInvokeInterface 3094 beqzc v0, MterpException 3095 FETCH_ADVANCE_INST 3 3096 jal MterpShouldSwitchInterpreters 3097 bnezc v0, MterpFallback 3098 GET_INST_OPCODE v0 3099 GOTO_OPCODE v0 3100 3101 /* 3102 * Handle an interface method call. 3103 * 3104 * for: invoke-interface, invoke-interface/range 3105 */ 3106 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3107 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3108 3109/* ------------------------------ */ 3110 .balign 128 3111.L_op_return_void_no_barrier: /* 0x73 */ 3112/* File: mips64/op_return_void_no_barrier.S */ 3113 .extern MterpSuspendCheck 3114 lw ra, THREAD_FLAGS_OFFSET(rSELF) 3115 move a0, rSELF 3116 and ra, ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 3117 beqzc ra, 1f 3118 jal MterpSuspendCheck # (self) 31191: 3120 li a0, 0 3121 b MterpReturn 3122 3123/* ------------------------------ */ 3124 .balign 128 3125.L_op_invoke_virtual_range: /* 0x74 */ 3126/* File: mips64/op_invoke_virtual_range.S */ 3127/* File: mips64/invoke.S */ 3128 /* 3129 * Generic invoke handler wrapper. 3130 */ 3131 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3132 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3133 .extern MterpInvokeVirtualRange 3134 .extern MterpShouldSwitchInterpreters 3135 EXPORT_PC 3136 move a0, rSELF 3137 daddu a1, rFP, OFF_FP_SHADOWFRAME 3138 move a2, rPC 3139 move a3, rINST 3140 jal MterpInvokeVirtualRange 3141 beqzc v0, MterpException 3142 FETCH_ADVANCE_INST 3 3143 jal MterpShouldSwitchInterpreters 3144 bnezc v0, MterpFallback 3145 GET_INST_OPCODE v0 3146 GOTO_OPCODE v0 3147 3148 3149/* ------------------------------ */ 3150 .balign 128 3151.L_op_invoke_super_range: /* 0x75 */ 3152/* File: mips64/op_invoke_super_range.S */ 3153/* File: mips64/invoke.S */ 3154 /* 3155 * Generic invoke handler wrapper. 3156 */ 3157 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3158 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3159 .extern MterpInvokeSuperRange 3160 .extern MterpShouldSwitchInterpreters 3161 EXPORT_PC 3162 move a0, rSELF 3163 daddu a1, rFP, OFF_FP_SHADOWFRAME 3164 move a2, rPC 3165 move a3, rINST 3166 jal MterpInvokeSuperRange 3167 beqzc v0, MterpException 3168 FETCH_ADVANCE_INST 3 3169 jal MterpShouldSwitchInterpreters 3170 bnezc v0, MterpFallback 3171 GET_INST_OPCODE v0 3172 GOTO_OPCODE v0 3173 3174 3175/* ------------------------------ */ 3176 .balign 128 3177.L_op_invoke_direct_range: /* 0x76 */ 3178/* File: mips64/op_invoke_direct_range.S */ 3179/* File: mips64/invoke.S */ 3180 /* 3181 * Generic invoke handler wrapper. 3182 */ 3183 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3184 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3185 .extern MterpInvokeDirectRange 3186 .extern MterpShouldSwitchInterpreters 3187 EXPORT_PC 3188 move a0, rSELF 3189 daddu a1, rFP, OFF_FP_SHADOWFRAME 3190 move a2, rPC 3191 move a3, rINST 3192 jal MterpInvokeDirectRange 3193 beqzc v0, MterpException 3194 FETCH_ADVANCE_INST 3 3195 jal MterpShouldSwitchInterpreters 3196 bnezc v0, MterpFallback 3197 GET_INST_OPCODE v0 3198 GOTO_OPCODE v0 3199 3200 3201/* ------------------------------ */ 3202 .balign 128 3203.L_op_invoke_static_range: /* 0x77 */ 3204/* File: mips64/op_invoke_static_range.S */ 3205/* File: mips64/invoke.S */ 3206 /* 3207 * Generic invoke handler wrapper. 3208 */ 3209 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3210 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3211 .extern MterpInvokeStaticRange 3212 .extern MterpShouldSwitchInterpreters 3213 EXPORT_PC 3214 move a0, rSELF 3215 daddu a1, rFP, OFF_FP_SHADOWFRAME 3216 move a2, rPC 3217 move a3, rINST 3218 jal MterpInvokeStaticRange 3219 beqzc v0, MterpException 3220 FETCH_ADVANCE_INST 3 3221 jal MterpShouldSwitchInterpreters 3222 bnezc v0, MterpFallback 3223 GET_INST_OPCODE v0 3224 GOTO_OPCODE v0 3225 3226 3227/* ------------------------------ */ 3228 .balign 128 3229.L_op_invoke_interface_range: /* 0x78 */ 3230/* File: mips64/op_invoke_interface_range.S */ 3231/* File: mips64/invoke.S */ 3232 /* 3233 * Generic invoke handler wrapper. 3234 */ 3235 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 3236 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 3237 .extern MterpInvokeInterfaceRange 3238 .extern MterpShouldSwitchInterpreters 3239 EXPORT_PC 3240 move a0, rSELF 3241 daddu a1, rFP, OFF_FP_SHADOWFRAME 3242 move a2, rPC 3243 move a3, rINST 3244 jal MterpInvokeInterfaceRange 3245 beqzc v0, MterpException 3246 FETCH_ADVANCE_INST 3 3247 jal MterpShouldSwitchInterpreters 3248 bnezc v0, MterpFallback 3249 GET_INST_OPCODE v0 3250 GOTO_OPCODE v0 3251 3252 3253/* ------------------------------ */ 3254 .balign 128 3255.L_op_unused_79: /* 0x79 */ 3256/* File: mips64/op_unused_79.S */ 3257/* File: mips64/unused.S */ 3258/* 3259 * Bail to reference interpreter to throw. 3260 */ 3261 b MterpFallback 3262 3263 3264/* ------------------------------ */ 3265 .balign 128 3266.L_op_unused_7a: /* 0x7a */ 3267/* File: mips64/op_unused_7a.S */ 3268/* File: mips64/unused.S */ 3269/* 3270 * Bail to reference interpreter to throw. 3271 */ 3272 b MterpFallback 3273 3274 3275/* ------------------------------ */ 3276 .balign 128 3277.L_op_neg_int: /* 0x7b */ 3278/* File: mips64/op_neg_int.S */ 3279/* File: mips64/unop.S */ 3280 /* 3281 * Generic 32-bit unary operation. Provide an "instr" line that 3282 * specifies an instruction that performs "a0 = op a0". 3283 * 3284 * for: int-to-byte, int-to-char, int-to-short, 3285 * not-int, neg-int 3286 */ 3287 /* unop vA, vB */ 3288 ext a3, rINST, 12, 4 # a3 <- B 3289 GET_VREG a0, a3 # a0 <- vB 3290 ext a2, rINST, 8, 4 # a2 <- A 3291 # optional op 3292 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3293 subu a0, zero, a0 # a0 <- op, a0-a3 changed 3294 GET_INST_OPCODE v0 # extract opcode from rINST 3295 SET_VREG a0, a2 # vA <- a0 3296 GOTO_OPCODE v0 # jump to next instruction 3297 3298 3299/* ------------------------------ */ 3300 .balign 128 3301.L_op_not_int: /* 0x7c */ 3302/* File: mips64/op_not_int.S */ 3303/* File: mips64/unop.S */ 3304 /* 3305 * Generic 32-bit unary operation. Provide an "instr" line that 3306 * specifies an instruction that performs "a0 = op a0". 3307 * 3308 * for: int-to-byte, int-to-char, int-to-short, 3309 * not-int, neg-int 3310 */ 3311 /* unop vA, vB */ 3312 ext a3, rINST, 12, 4 # a3 <- B 3313 GET_VREG a0, a3 # a0 <- vB 3314 ext a2, rINST, 8, 4 # a2 <- A 3315 # optional op 3316 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3317 nor a0, zero, a0 # a0 <- op, a0-a3 changed 3318 GET_INST_OPCODE v0 # extract opcode from rINST 3319 SET_VREG a0, a2 # vA <- a0 3320 GOTO_OPCODE v0 # jump to next instruction 3321 3322 3323/* ------------------------------ */ 3324 .balign 128 3325.L_op_neg_long: /* 0x7d */ 3326/* File: mips64/op_neg_long.S */ 3327/* File: mips64/unopWide.S */ 3328 /* 3329 * Generic 64-bit unary operation. Provide an "instr" line that 3330 * specifies an instruction that performs "a0 = op a0". 3331 * 3332 * For: not-long, neg-long 3333 */ 3334 /* unop vA, vB */ 3335 ext a3, rINST, 12, 4 # a3 <- B 3336 GET_VREG_WIDE a0, a3 # a0 <- vB 3337 ext a2, rINST, 8, 4 # a2 <- A 3338 # optional op 3339 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3340 dsubu a0, zero, a0 # a0 <- op, a0-a3 changed 3341 GET_INST_OPCODE v0 # extract opcode from rINST 3342 SET_VREG_WIDE a0, a2 # vA <- a0 3343 GOTO_OPCODE v0 # jump to next instruction 3344 3345 3346/* ------------------------------ */ 3347 .balign 128 3348.L_op_not_long: /* 0x7e */ 3349/* File: mips64/op_not_long.S */ 3350/* File: mips64/unopWide.S */ 3351 /* 3352 * Generic 64-bit unary operation. Provide an "instr" line that 3353 * specifies an instruction that performs "a0 = op a0". 3354 * 3355 * For: not-long, neg-long 3356 */ 3357 /* unop vA, vB */ 3358 ext a3, rINST, 12, 4 # a3 <- B 3359 GET_VREG_WIDE a0, a3 # a0 <- vB 3360 ext a2, rINST, 8, 4 # a2 <- A 3361 # optional op 3362 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3363 nor a0, zero, a0 # a0 <- op, a0-a3 changed 3364 GET_INST_OPCODE v0 # extract opcode from rINST 3365 SET_VREG_WIDE a0, a2 # vA <- a0 3366 GOTO_OPCODE v0 # jump to next instruction 3367 3368 3369/* ------------------------------ */ 3370 .balign 128 3371.L_op_neg_float: /* 0x7f */ 3372/* File: mips64/op_neg_float.S */ 3373/* File: mips64/fcvtHeader.S */ 3374 /* 3375 * Loads a specified register from vB. Used primarily for conversions 3376 * from or to a floating-point type. 3377 * 3378 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3379 * store the result in vA and jump to the next instruction. 3380 * 3381 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3382 * float-to-int, float-to-long, float-to-double, double-to-int, 3383 * double-to-long, double-to-float, neg-float, neg-double. 3384 */ 3385 ext a1, rINST, 8, 4 # a1 <- A 3386 srl a2, rINST, 12 # a2 <- B 3387 GET_VREG_FLOAT f0, a2 3388 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3389 3390 neg.s f0, f0 3391/* File: mips64/fcvtFooter.S */ 3392 /* 3393 * Stores a specified register containing the result of conversion 3394 * from or to a floating-point type and jumps to the next instruction. 3395 * 3396 * Expects a1 to contain the destination Dalvik register number. 3397 * a1 is set up by fcvtHeader.S. 3398 * 3399 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3400 * float-to-int, float-to-long, float-to-double, double-to-int, 3401 * double-to-long, double-to-float, neg-float, neg-double. 3402 * 3403 * Note that this file can't be included after a break in other files 3404 * and in those files its contents appear as a copy. 3405 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3406 */ 3407 GET_INST_OPCODE v0 # extract opcode from rINST 3408 SET_VREG_FLOAT f0, a1 3409 GOTO_OPCODE v0 # jump to next instruction 3410 3411 3412/* ------------------------------ */ 3413 .balign 128 3414.L_op_neg_double: /* 0x80 */ 3415/* File: mips64/op_neg_double.S */ 3416/* File: mips64/fcvtHeader.S */ 3417 /* 3418 * Loads a specified register from vB. Used primarily for conversions 3419 * from or to a floating-point type. 3420 * 3421 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3422 * store the result in vA and jump to the next instruction. 3423 * 3424 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3425 * float-to-int, float-to-long, float-to-double, double-to-int, 3426 * double-to-long, double-to-float, neg-float, neg-double. 3427 */ 3428 ext a1, rINST, 8, 4 # a1 <- A 3429 srl a2, rINST, 12 # a2 <- B 3430 GET_VREG_DOUBLE f0, a2 3431 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3432 3433 neg.d f0, f0 3434/* File: mips64/fcvtFooter.S */ 3435 /* 3436 * Stores a specified register containing the result of conversion 3437 * from or to a floating-point type and jumps to the next instruction. 3438 * 3439 * Expects a1 to contain the destination Dalvik register number. 3440 * a1 is set up by fcvtHeader.S. 3441 * 3442 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3443 * float-to-int, float-to-long, float-to-double, double-to-int, 3444 * double-to-long, double-to-float, neg-float, neg-double. 3445 * 3446 * Note that this file can't be included after a break in other files 3447 * and in those files its contents appear as a copy. 3448 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3449 */ 3450 GET_INST_OPCODE v0 # extract opcode from rINST 3451 SET_VREG_DOUBLE f0, a1 3452 GOTO_OPCODE v0 # jump to next instruction 3453 3454 3455/* ------------------------------ */ 3456 .balign 128 3457.L_op_int_to_long: /* 0x81 */ 3458/* File: mips64/op_int_to_long.S */ 3459 /* int-to-long vA, vB */ 3460 ext a3, rINST, 12, 4 # a3 <- B 3461 GET_VREG a0, a3 # a0 <- vB (sign-extended to 64 bits) 3462 ext a2, rINST, 8, 4 # a2 <- A 3463 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3464 GET_INST_OPCODE v0 # extract opcode from rINST 3465 SET_VREG_WIDE a0, a2 # vA <- vB 3466 GOTO_OPCODE v0 # jump to next instruction 3467 3468/* ------------------------------ */ 3469 .balign 128 3470.L_op_int_to_float: /* 0x82 */ 3471/* File: mips64/op_int_to_float.S */ 3472 /* 3473 * Conversion from or to floating-point happens in a floating-point register. 3474 * Therefore we load the input and store the output into or from a 3475 * floating-point register irrespective of the type. 3476 */ 3477/* File: mips64/fcvtHeader.S */ 3478 /* 3479 * Loads a specified register from vB. Used primarily for conversions 3480 * from or to a floating-point type. 3481 * 3482 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3483 * store the result in vA and jump to the next instruction. 3484 * 3485 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3486 * float-to-int, float-to-long, float-to-double, double-to-int, 3487 * double-to-long, double-to-float, neg-float, neg-double. 3488 */ 3489 ext a1, rINST, 8, 4 # a1 <- A 3490 srl a2, rINST, 12 # a2 <- B 3491 GET_VREG_FLOAT f0, a2 3492 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3493 3494 cvt.s.w f0, f0 3495/* File: mips64/fcvtFooter.S */ 3496 /* 3497 * Stores a specified register containing the result of conversion 3498 * from or to a floating-point type and jumps to the next instruction. 3499 * 3500 * Expects a1 to contain the destination Dalvik register number. 3501 * a1 is set up by fcvtHeader.S. 3502 * 3503 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3504 * float-to-int, float-to-long, float-to-double, double-to-int, 3505 * double-to-long, double-to-float, neg-float, neg-double. 3506 * 3507 * Note that this file can't be included after a break in other files 3508 * and in those files its contents appear as a copy. 3509 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3510 */ 3511 GET_INST_OPCODE v0 # extract opcode from rINST 3512 SET_VREG_FLOAT f0, a1 3513 GOTO_OPCODE v0 # jump to next instruction 3514 3515 3516/* ------------------------------ */ 3517 .balign 128 3518.L_op_int_to_double: /* 0x83 */ 3519/* File: mips64/op_int_to_double.S */ 3520 /* 3521 * Conversion from or to floating-point happens in a floating-point register. 3522 * Therefore we load the input and store the output into or from a 3523 * floating-point register irrespective of the type. 3524 */ 3525/* File: mips64/fcvtHeader.S */ 3526 /* 3527 * Loads a specified register from vB. Used primarily for conversions 3528 * from or to a floating-point type. 3529 * 3530 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3531 * store the result in vA and jump to the next instruction. 3532 * 3533 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3534 * float-to-int, float-to-long, float-to-double, double-to-int, 3535 * double-to-long, double-to-float, neg-float, neg-double. 3536 */ 3537 ext a1, rINST, 8, 4 # a1 <- A 3538 srl a2, rINST, 12 # a2 <- B 3539 GET_VREG_FLOAT f0, a2 3540 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3541 3542 cvt.d.w f0, f0 3543/* File: mips64/fcvtFooter.S */ 3544 /* 3545 * Stores a specified register containing the result of conversion 3546 * from or to a floating-point type and jumps to the next instruction. 3547 * 3548 * Expects a1 to contain the destination Dalvik register number. 3549 * a1 is set up by fcvtHeader.S. 3550 * 3551 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3552 * float-to-int, float-to-long, float-to-double, double-to-int, 3553 * double-to-long, double-to-float, neg-float, neg-double. 3554 * 3555 * Note that this file can't be included after a break in other files 3556 * and in those files its contents appear as a copy. 3557 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3558 */ 3559 GET_INST_OPCODE v0 # extract opcode from rINST 3560 SET_VREG_DOUBLE f0, a1 3561 GOTO_OPCODE v0 # jump to next instruction 3562 3563 3564/* ------------------------------ */ 3565 .balign 128 3566.L_op_long_to_int: /* 0x84 */ 3567/* File: mips64/op_long_to_int.S */ 3568/* we ignore the high word, making this equivalent to a 32-bit reg move */ 3569/* File: mips64/op_move.S */ 3570 /* for move, move-object, long-to-int */ 3571 /* op vA, vB */ 3572 ext a2, rINST, 8, 4 # a2 <- A 3573 ext a3, rINST, 12, 4 # a3 <- B 3574 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3575 GET_VREG a0, a3 # a0 <- vB 3576 GET_INST_OPCODE v0 # extract opcode from rINST 3577 .if 0 3578 SET_VREG_OBJECT a0, a2 # vA <- vB 3579 .else 3580 SET_VREG a0, a2 # vA <- vB 3581 .endif 3582 GOTO_OPCODE v0 # jump to next instruction 3583 3584 3585/* ------------------------------ */ 3586 .balign 128 3587.L_op_long_to_float: /* 0x85 */ 3588/* File: mips64/op_long_to_float.S */ 3589 /* 3590 * Conversion from or to floating-point happens in a floating-point register. 3591 * Therefore we load the input and store the output into or from a 3592 * floating-point register irrespective of the type. 3593 */ 3594/* File: mips64/fcvtHeader.S */ 3595 /* 3596 * Loads a specified register from vB. Used primarily for conversions 3597 * from or to a floating-point type. 3598 * 3599 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3600 * store the result in vA and jump to the next instruction. 3601 * 3602 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3603 * float-to-int, float-to-long, float-to-double, double-to-int, 3604 * double-to-long, double-to-float, neg-float, neg-double. 3605 */ 3606 ext a1, rINST, 8, 4 # a1 <- A 3607 srl a2, rINST, 12 # a2 <- B 3608 GET_VREG_DOUBLE f0, a2 3609 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3610 3611 cvt.s.l f0, f0 3612/* File: mips64/fcvtFooter.S */ 3613 /* 3614 * Stores a specified register containing the result of conversion 3615 * from or to a floating-point type and jumps to the next instruction. 3616 * 3617 * Expects a1 to contain the destination Dalvik register number. 3618 * a1 is set up by fcvtHeader.S. 3619 * 3620 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3621 * float-to-int, float-to-long, float-to-double, double-to-int, 3622 * double-to-long, double-to-float, neg-float, neg-double. 3623 * 3624 * Note that this file can't be included after a break in other files 3625 * and in those files its contents appear as a copy. 3626 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3627 */ 3628 GET_INST_OPCODE v0 # extract opcode from rINST 3629 SET_VREG_FLOAT f0, a1 3630 GOTO_OPCODE v0 # jump to next instruction 3631 3632 3633/* ------------------------------ */ 3634 .balign 128 3635.L_op_long_to_double: /* 0x86 */ 3636/* File: mips64/op_long_to_double.S */ 3637 /* 3638 * Conversion from or to floating-point happens in a floating-point register. 3639 * Therefore we load the input and store the output into or from a 3640 * floating-point register irrespective of the type. 3641 */ 3642/* File: mips64/fcvtHeader.S */ 3643 /* 3644 * Loads a specified register from vB. Used primarily for conversions 3645 * from or to a floating-point type. 3646 * 3647 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3648 * store the result in vA and jump to the next instruction. 3649 * 3650 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3651 * float-to-int, float-to-long, float-to-double, double-to-int, 3652 * double-to-long, double-to-float, neg-float, neg-double. 3653 */ 3654 ext a1, rINST, 8, 4 # a1 <- A 3655 srl a2, rINST, 12 # a2 <- B 3656 GET_VREG_DOUBLE f0, a2 3657 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3658 3659 cvt.d.l f0, f0 3660/* File: mips64/fcvtFooter.S */ 3661 /* 3662 * Stores a specified register containing the result of conversion 3663 * from or to a floating-point type and jumps to the next instruction. 3664 * 3665 * Expects a1 to contain the destination Dalvik register number. 3666 * a1 is set up by fcvtHeader.S. 3667 * 3668 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3669 * float-to-int, float-to-long, float-to-double, double-to-int, 3670 * double-to-long, double-to-float, neg-float, neg-double. 3671 * 3672 * Note that this file can't be included after a break in other files 3673 * and in those files its contents appear as a copy. 3674 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3675 */ 3676 GET_INST_OPCODE v0 # extract opcode from rINST 3677 SET_VREG_DOUBLE f0, a1 3678 GOTO_OPCODE v0 # jump to next instruction 3679 3680 3681/* ------------------------------ */ 3682 .balign 128 3683.L_op_float_to_int: /* 0x87 */ 3684/* File: mips64/op_float_to_int.S */ 3685/* File: mips64/fcvtHeader.S */ 3686 /* 3687 * Loads a specified register from vB. Used primarily for conversions 3688 * from or to a floating-point type. 3689 * 3690 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3691 * store the result in vA and jump to the next instruction. 3692 * 3693 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3694 * float-to-int, float-to-long, float-to-double, double-to-int, 3695 * double-to-long, double-to-float, neg-float, neg-double. 3696 */ 3697 ext a1, rINST, 8, 4 # a1 <- A 3698 srl a2, rINST, 12 # a2 <- B 3699 GET_VREG_FLOAT f0, a2 3700 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3701 3702 /* 3703 * TODO: simplify this when the MIPS64R6 emulator 3704 * supports NAN2008=1. 3705 */ 3706 li t0, INT_MIN_AS_FLOAT 3707 mtc1 t0, f1 3708 cmp.le.s f1, f1, f0 3709 bc1nez f1, .Lop_float_to_int_trunc 3710 cmp.eq.s f1, f0, f0 3711 li t0, INT_MIN 3712 mfc1 t1, f1 3713 and t0, t0, t1 3714 b .Lop_float_to_int_done 3715 3716/* ------------------------------ */ 3717 .balign 128 3718.L_op_float_to_long: /* 0x88 */ 3719/* File: mips64/op_float_to_long.S */ 3720/* File: mips64/fcvtHeader.S */ 3721 /* 3722 * Loads a specified register from vB. Used primarily for conversions 3723 * from or to a floating-point type. 3724 * 3725 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3726 * store the result in vA and jump to the next instruction. 3727 * 3728 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3729 * float-to-int, float-to-long, float-to-double, double-to-int, 3730 * double-to-long, double-to-float, neg-float, neg-double. 3731 */ 3732 ext a1, rINST, 8, 4 # a1 <- A 3733 srl a2, rINST, 12 # a2 <- B 3734 GET_VREG_FLOAT f0, a2 3735 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3736 3737 /* 3738 * TODO: simplify this when the MIPS64R6 emulator 3739 * supports NAN2008=1. 3740 */ 3741 li t0, LONG_MIN_AS_FLOAT 3742 mtc1 t0, f1 3743 cmp.le.s f1, f1, f0 3744 bc1nez f1, .Lop_float_to_long_trunc 3745 cmp.eq.s f1, f0, f0 3746 dli t0, LONG_MIN 3747 mfc1 t1, f1 3748 and t0, t0, t1 3749 b .Lop_float_to_long_done 3750 3751/* ------------------------------ */ 3752 .balign 128 3753.L_op_float_to_double: /* 0x89 */ 3754/* File: mips64/op_float_to_double.S */ 3755 /* 3756 * Conversion from or to floating-point happens in a floating-point register. 3757 * Therefore we load the input and store the output into or from a 3758 * floating-point register irrespective of the type. 3759 */ 3760/* File: mips64/fcvtHeader.S */ 3761 /* 3762 * Loads a specified register from vB. Used primarily for conversions 3763 * from or to a floating-point type. 3764 * 3765 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3766 * store the result in vA and jump to the next instruction. 3767 * 3768 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3769 * float-to-int, float-to-long, float-to-double, double-to-int, 3770 * double-to-long, double-to-float, neg-float, neg-double. 3771 */ 3772 ext a1, rINST, 8, 4 # a1 <- A 3773 srl a2, rINST, 12 # a2 <- B 3774 GET_VREG_FLOAT f0, a2 3775 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3776 3777 cvt.d.s f0, f0 3778/* File: mips64/fcvtFooter.S */ 3779 /* 3780 * Stores a specified register containing the result of conversion 3781 * from or to a floating-point type and jumps to the next instruction. 3782 * 3783 * Expects a1 to contain the destination Dalvik register number. 3784 * a1 is set up by fcvtHeader.S. 3785 * 3786 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3787 * float-to-int, float-to-long, float-to-double, double-to-int, 3788 * double-to-long, double-to-float, neg-float, neg-double. 3789 * 3790 * Note that this file can't be included after a break in other files 3791 * and in those files its contents appear as a copy. 3792 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3793 */ 3794 GET_INST_OPCODE v0 # extract opcode from rINST 3795 SET_VREG_DOUBLE f0, a1 3796 GOTO_OPCODE v0 # jump to next instruction 3797 3798 3799/* ------------------------------ */ 3800 .balign 128 3801.L_op_double_to_int: /* 0x8a */ 3802/* File: mips64/op_double_to_int.S */ 3803/* File: mips64/fcvtHeader.S */ 3804 /* 3805 * Loads a specified register from vB. Used primarily for conversions 3806 * from or to a floating-point type. 3807 * 3808 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3809 * store the result in vA and jump to the next instruction. 3810 * 3811 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3812 * float-to-int, float-to-long, float-to-double, double-to-int, 3813 * double-to-long, double-to-float, neg-float, neg-double. 3814 */ 3815 ext a1, rINST, 8, 4 # a1 <- A 3816 srl a2, rINST, 12 # a2 <- B 3817 GET_VREG_DOUBLE f0, a2 3818 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3819 3820 /* 3821 * TODO: simplify this when the MIPS64R6 emulator 3822 * supports NAN2008=1. 3823 */ 3824 dli t0, INT_MIN_AS_DOUBLE 3825 dmtc1 t0, f1 3826 cmp.le.d f1, f1, f0 3827 bc1nez f1, .Lop_double_to_int_trunc 3828 cmp.eq.d f1, f0, f0 3829 li t0, INT_MIN 3830 mfc1 t1, f1 3831 and t0, t0, t1 3832 b .Lop_double_to_int_done 3833 3834/* ------------------------------ */ 3835 .balign 128 3836.L_op_double_to_long: /* 0x8b */ 3837/* File: mips64/op_double_to_long.S */ 3838/* File: mips64/fcvtHeader.S */ 3839 /* 3840 * Loads a specified register from vB. Used primarily for conversions 3841 * from or to a floating-point type. 3842 * 3843 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3844 * store the result in vA and jump to the next instruction. 3845 * 3846 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3847 * float-to-int, float-to-long, float-to-double, double-to-int, 3848 * double-to-long, double-to-float, neg-float, neg-double. 3849 */ 3850 ext a1, rINST, 8, 4 # a1 <- A 3851 srl a2, rINST, 12 # a2 <- B 3852 GET_VREG_DOUBLE f0, a2 3853 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3854 3855 /* 3856 * TODO: simplify this when the MIPS64R6 emulator 3857 * supports NAN2008=1. 3858 */ 3859 dli t0, LONG_MIN_AS_DOUBLE 3860 dmtc1 t0, f1 3861 cmp.le.d f1, f1, f0 3862 bc1nez f1, .Lop_double_to_long_trunc 3863 cmp.eq.d f1, f0, f0 3864 dli t0, LONG_MIN 3865 mfc1 t1, f1 3866 and t0, t0, t1 3867 b .Lop_double_to_long_done 3868 3869/* ------------------------------ */ 3870 .balign 128 3871.L_op_double_to_float: /* 0x8c */ 3872/* File: mips64/op_double_to_float.S */ 3873 /* 3874 * Conversion from or to floating-point happens in a floating-point register. 3875 * Therefore we load the input and store the output into or from a 3876 * floating-point register irrespective of the type. 3877 */ 3878/* File: mips64/fcvtHeader.S */ 3879 /* 3880 * Loads a specified register from vB. Used primarily for conversions 3881 * from or to a floating-point type. 3882 * 3883 * Sets up a1 = A and a2 = B. a2 is later used by fcvtFooter.S to 3884 * store the result in vA and jump to the next instruction. 3885 * 3886 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3887 * float-to-int, float-to-long, float-to-double, double-to-int, 3888 * double-to-long, double-to-float, neg-float, neg-double. 3889 */ 3890 ext a1, rINST, 8, 4 # a1 <- A 3891 srl a2, rINST, 12 # a2 <- B 3892 GET_VREG_DOUBLE f0, a2 3893 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3894 3895 cvt.s.d f0, f0 3896/* File: mips64/fcvtFooter.S */ 3897 /* 3898 * Stores a specified register containing the result of conversion 3899 * from or to a floating-point type and jumps to the next instruction. 3900 * 3901 * Expects a1 to contain the destination Dalvik register number. 3902 * a1 is set up by fcvtHeader.S. 3903 * 3904 * For: int-to-float, int-to-double, long-to-float, long-to-double, 3905 * float-to-int, float-to-long, float-to-double, double-to-int, 3906 * double-to-long, double-to-float, neg-float, neg-double. 3907 * 3908 * Note that this file can't be included after a break in other files 3909 * and in those files its contents appear as a copy. 3910 * See: float-to-int, float-to-long, double-to-int, double-to-long. 3911 */ 3912 GET_INST_OPCODE v0 # extract opcode from rINST 3913 SET_VREG_FLOAT f0, a1 3914 GOTO_OPCODE v0 # jump to next instruction 3915 3916 3917/* ------------------------------ */ 3918 .balign 128 3919.L_op_int_to_byte: /* 0x8d */ 3920/* File: mips64/op_int_to_byte.S */ 3921/* File: mips64/unop.S */ 3922 /* 3923 * Generic 32-bit unary operation. Provide an "instr" line that 3924 * specifies an instruction that performs "a0 = op a0". 3925 * 3926 * for: int-to-byte, int-to-char, int-to-short, 3927 * not-int, neg-int 3928 */ 3929 /* unop vA, vB */ 3930 ext a3, rINST, 12, 4 # a3 <- B 3931 GET_VREG a0, a3 # a0 <- vB 3932 ext a2, rINST, 8, 4 # a2 <- A 3933 # optional op 3934 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3935 seb a0, a0 # a0 <- op, a0-a3 changed 3936 GET_INST_OPCODE v0 # extract opcode from rINST 3937 SET_VREG a0, a2 # vA <- a0 3938 GOTO_OPCODE v0 # jump to next instruction 3939 3940 3941/* ------------------------------ */ 3942 .balign 128 3943.L_op_int_to_char: /* 0x8e */ 3944/* File: mips64/op_int_to_char.S */ 3945/* File: mips64/unop.S */ 3946 /* 3947 * Generic 32-bit unary operation. Provide an "instr" line that 3948 * specifies an instruction that performs "a0 = op a0". 3949 * 3950 * for: int-to-byte, int-to-char, int-to-short, 3951 * not-int, neg-int 3952 */ 3953 /* unop vA, vB */ 3954 ext a3, rINST, 12, 4 # a3 <- B 3955 GET_VREG a0, a3 # a0 <- vB 3956 ext a2, rINST, 8, 4 # a2 <- A 3957 # optional op 3958 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3959 and a0, a0, 0xffff # a0 <- op, a0-a3 changed 3960 GET_INST_OPCODE v0 # extract opcode from rINST 3961 SET_VREG a0, a2 # vA <- a0 3962 GOTO_OPCODE v0 # jump to next instruction 3963 3964 3965/* ------------------------------ */ 3966 .balign 128 3967.L_op_int_to_short: /* 0x8f */ 3968/* File: mips64/op_int_to_short.S */ 3969/* File: mips64/unop.S */ 3970 /* 3971 * Generic 32-bit unary operation. Provide an "instr" line that 3972 * specifies an instruction that performs "a0 = op a0". 3973 * 3974 * for: int-to-byte, int-to-char, int-to-short, 3975 * not-int, neg-int 3976 */ 3977 /* unop vA, vB */ 3978 ext a3, rINST, 12, 4 # a3 <- B 3979 GET_VREG a0, a3 # a0 <- vB 3980 ext a2, rINST, 8, 4 # a2 <- A 3981 # optional op 3982 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 3983 seh a0, a0 # a0 <- op, a0-a3 changed 3984 GET_INST_OPCODE v0 # extract opcode from rINST 3985 SET_VREG a0, a2 # vA <- a0 3986 GOTO_OPCODE v0 # jump to next instruction 3987 3988 3989/* ------------------------------ */ 3990 .balign 128 3991.L_op_add_int: /* 0x90 */ 3992/* File: mips64/op_add_int.S */ 3993/* File: mips64/binop.S */ 3994 /* 3995 * Generic 32-bit binary operation. Provide an "instr" line that 3996 * specifies an instruction that performs "result = a0 op a1". 3997 * This could be a MIPS instruction or a function call. (If the result 3998 * comes back in a register other than a0, you can override "result".) 3999 * 4000 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4001 * vCC (a1). Useful for integer division and modulus. Note that we 4002 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4003 * correctly. 4004 * 4005 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4006 * xor-int, shl-int, shr-int, ushr-int 4007 */ 4008 /* binop vAA, vBB, vCC */ 4009 srl a4, rINST, 8 # a4 <- AA 4010 lbu a2, 2(rPC) # a2 <- BB 4011 lbu a3, 3(rPC) # a3 <- CC 4012 GET_VREG a0, a2 # a0 <- vBB 4013 GET_VREG a1, a3 # a1 <- vCC 4014 .if 0 4015 beqz a1, common_errDivideByZero # is second operand zero? 4016 .endif 4017 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4018 # optional op 4019 addu a0, a0, a1 # a0 <- op, a0-a3 changed 4020 GET_INST_OPCODE v0 # extract opcode from rINST 4021 SET_VREG a0, a4 # vAA <- a0 4022 GOTO_OPCODE v0 # jump to next instruction 4023 4024 4025/* ------------------------------ */ 4026 .balign 128 4027.L_op_sub_int: /* 0x91 */ 4028/* File: mips64/op_sub_int.S */ 4029/* File: mips64/binop.S */ 4030 /* 4031 * Generic 32-bit binary operation. Provide an "instr" line that 4032 * specifies an instruction that performs "result = a0 op a1". 4033 * This could be a MIPS instruction or a function call. (If the result 4034 * comes back in a register other than a0, you can override "result".) 4035 * 4036 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4037 * vCC (a1). Useful for integer division and modulus. Note that we 4038 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4039 * correctly. 4040 * 4041 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4042 * xor-int, shl-int, shr-int, ushr-int 4043 */ 4044 /* binop vAA, vBB, vCC */ 4045 srl a4, rINST, 8 # a4 <- AA 4046 lbu a2, 2(rPC) # a2 <- BB 4047 lbu a3, 3(rPC) # a3 <- CC 4048 GET_VREG a0, a2 # a0 <- vBB 4049 GET_VREG a1, a3 # a1 <- vCC 4050 .if 0 4051 beqz a1, common_errDivideByZero # is second operand zero? 4052 .endif 4053 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4054 # optional op 4055 subu a0, a0, a1 # a0 <- op, a0-a3 changed 4056 GET_INST_OPCODE v0 # extract opcode from rINST 4057 SET_VREG a0, a4 # vAA <- a0 4058 GOTO_OPCODE v0 # jump to next instruction 4059 4060 4061/* ------------------------------ */ 4062 .balign 128 4063.L_op_mul_int: /* 0x92 */ 4064/* File: mips64/op_mul_int.S */ 4065/* File: mips64/binop.S */ 4066 /* 4067 * Generic 32-bit binary operation. Provide an "instr" line that 4068 * specifies an instruction that performs "result = a0 op a1". 4069 * This could be a MIPS instruction or a function call. (If the result 4070 * comes back in a register other than a0, you can override "result".) 4071 * 4072 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4073 * vCC (a1). Useful for integer division and modulus. Note that we 4074 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4075 * correctly. 4076 * 4077 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4078 * xor-int, shl-int, shr-int, ushr-int 4079 */ 4080 /* binop vAA, vBB, vCC */ 4081 srl a4, rINST, 8 # a4 <- AA 4082 lbu a2, 2(rPC) # a2 <- BB 4083 lbu a3, 3(rPC) # a3 <- CC 4084 GET_VREG a0, a2 # a0 <- vBB 4085 GET_VREG a1, a3 # a1 <- vCC 4086 .if 0 4087 beqz a1, common_errDivideByZero # is second operand zero? 4088 .endif 4089 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4090 # optional op 4091 mul a0, a0, a1 # a0 <- op, a0-a3 changed 4092 GET_INST_OPCODE v0 # extract opcode from rINST 4093 SET_VREG a0, a4 # vAA <- a0 4094 GOTO_OPCODE v0 # jump to next instruction 4095 4096 4097/* ------------------------------ */ 4098 .balign 128 4099.L_op_div_int: /* 0x93 */ 4100/* File: mips64/op_div_int.S */ 4101/* File: mips64/binop.S */ 4102 /* 4103 * Generic 32-bit binary operation. Provide an "instr" line that 4104 * specifies an instruction that performs "result = a0 op a1". 4105 * This could be a MIPS instruction or a function call. (If the result 4106 * comes back in a register other than a0, you can override "result".) 4107 * 4108 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4109 * vCC (a1). Useful for integer division and modulus. Note that we 4110 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4111 * correctly. 4112 * 4113 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4114 * xor-int, shl-int, shr-int, ushr-int 4115 */ 4116 /* binop vAA, vBB, vCC */ 4117 srl a4, rINST, 8 # a4 <- AA 4118 lbu a2, 2(rPC) # a2 <- BB 4119 lbu a3, 3(rPC) # a3 <- CC 4120 GET_VREG a0, a2 # a0 <- vBB 4121 GET_VREG a1, a3 # a1 <- vCC 4122 .if 1 4123 beqz a1, common_errDivideByZero # is second operand zero? 4124 .endif 4125 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4126 # optional op 4127 div a0, a0, a1 # a0 <- op, a0-a3 changed 4128 GET_INST_OPCODE v0 # extract opcode from rINST 4129 SET_VREG a0, a4 # vAA <- a0 4130 GOTO_OPCODE v0 # jump to next instruction 4131 4132 4133/* ------------------------------ */ 4134 .balign 128 4135.L_op_rem_int: /* 0x94 */ 4136/* File: mips64/op_rem_int.S */ 4137/* File: mips64/binop.S */ 4138 /* 4139 * Generic 32-bit binary operation. Provide an "instr" line that 4140 * specifies an instruction that performs "result = a0 op a1". 4141 * This could be a MIPS instruction or a function call. (If the result 4142 * comes back in a register other than a0, you can override "result".) 4143 * 4144 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4145 * vCC (a1). Useful for integer division and modulus. Note that we 4146 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4147 * correctly. 4148 * 4149 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4150 * xor-int, shl-int, shr-int, ushr-int 4151 */ 4152 /* binop vAA, vBB, vCC */ 4153 srl a4, rINST, 8 # a4 <- AA 4154 lbu a2, 2(rPC) # a2 <- BB 4155 lbu a3, 3(rPC) # a3 <- CC 4156 GET_VREG a0, a2 # a0 <- vBB 4157 GET_VREG a1, a3 # a1 <- vCC 4158 .if 1 4159 beqz a1, common_errDivideByZero # is second operand zero? 4160 .endif 4161 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4162 # optional op 4163 mod a0, a0, a1 # a0 <- op, a0-a3 changed 4164 GET_INST_OPCODE v0 # extract opcode from rINST 4165 SET_VREG a0, a4 # vAA <- a0 4166 GOTO_OPCODE v0 # jump to next instruction 4167 4168 4169/* ------------------------------ */ 4170 .balign 128 4171.L_op_and_int: /* 0x95 */ 4172/* File: mips64/op_and_int.S */ 4173/* File: mips64/binop.S */ 4174 /* 4175 * Generic 32-bit binary operation. Provide an "instr" line that 4176 * specifies an instruction that performs "result = a0 op a1". 4177 * This could be a MIPS instruction or a function call. (If the result 4178 * comes back in a register other than a0, you can override "result".) 4179 * 4180 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4181 * vCC (a1). Useful for integer division and modulus. Note that we 4182 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4183 * correctly. 4184 * 4185 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4186 * xor-int, shl-int, shr-int, ushr-int 4187 */ 4188 /* binop vAA, vBB, vCC */ 4189 srl a4, rINST, 8 # a4 <- AA 4190 lbu a2, 2(rPC) # a2 <- BB 4191 lbu a3, 3(rPC) # a3 <- CC 4192 GET_VREG a0, a2 # a0 <- vBB 4193 GET_VREG a1, a3 # a1 <- vCC 4194 .if 0 4195 beqz a1, common_errDivideByZero # is second operand zero? 4196 .endif 4197 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4198 # optional op 4199 and a0, a0, a1 # a0 <- op, a0-a3 changed 4200 GET_INST_OPCODE v0 # extract opcode from rINST 4201 SET_VREG a0, a4 # vAA <- a0 4202 GOTO_OPCODE v0 # jump to next instruction 4203 4204 4205/* ------------------------------ */ 4206 .balign 128 4207.L_op_or_int: /* 0x96 */ 4208/* File: mips64/op_or_int.S */ 4209/* File: mips64/binop.S */ 4210 /* 4211 * Generic 32-bit binary operation. Provide an "instr" line that 4212 * specifies an instruction that performs "result = a0 op a1". 4213 * This could be a MIPS instruction or a function call. (If the result 4214 * comes back in a register other than a0, you can override "result".) 4215 * 4216 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4217 * vCC (a1). Useful for integer division and modulus. Note that we 4218 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4219 * correctly. 4220 * 4221 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4222 * xor-int, shl-int, shr-int, ushr-int 4223 */ 4224 /* binop vAA, vBB, vCC */ 4225 srl a4, rINST, 8 # a4 <- AA 4226 lbu a2, 2(rPC) # a2 <- BB 4227 lbu a3, 3(rPC) # a3 <- CC 4228 GET_VREG a0, a2 # a0 <- vBB 4229 GET_VREG a1, a3 # a1 <- vCC 4230 .if 0 4231 beqz a1, common_errDivideByZero # is second operand zero? 4232 .endif 4233 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4234 # optional op 4235 or a0, a0, a1 # a0 <- op, a0-a3 changed 4236 GET_INST_OPCODE v0 # extract opcode from rINST 4237 SET_VREG a0, a4 # vAA <- a0 4238 GOTO_OPCODE v0 # jump to next instruction 4239 4240 4241/* ------------------------------ */ 4242 .balign 128 4243.L_op_xor_int: /* 0x97 */ 4244/* File: mips64/op_xor_int.S */ 4245/* File: mips64/binop.S */ 4246 /* 4247 * Generic 32-bit binary operation. Provide an "instr" line that 4248 * specifies an instruction that performs "result = a0 op a1". 4249 * This could be a MIPS instruction or a function call. (If the result 4250 * comes back in a register other than a0, you can override "result".) 4251 * 4252 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4253 * vCC (a1). Useful for integer division and modulus. Note that we 4254 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4255 * correctly. 4256 * 4257 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4258 * xor-int, shl-int, shr-int, ushr-int 4259 */ 4260 /* binop vAA, vBB, vCC */ 4261 srl a4, rINST, 8 # a4 <- AA 4262 lbu a2, 2(rPC) # a2 <- BB 4263 lbu a3, 3(rPC) # a3 <- CC 4264 GET_VREG a0, a2 # a0 <- vBB 4265 GET_VREG a1, a3 # a1 <- vCC 4266 .if 0 4267 beqz a1, common_errDivideByZero # is second operand zero? 4268 .endif 4269 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4270 # optional op 4271 xor a0, a0, a1 # a0 <- op, a0-a3 changed 4272 GET_INST_OPCODE v0 # extract opcode from rINST 4273 SET_VREG a0, a4 # vAA <- a0 4274 GOTO_OPCODE v0 # jump to next instruction 4275 4276 4277/* ------------------------------ */ 4278 .balign 128 4279.L_op_shl_int: /* 0x98 */ 4280/* File: mips64/op_shl_int.S */ 4281/* File: mips64/binop.S */ 4282 /* 4283 * Generic 32-bit binary operation. Provide an "instr" line that 4284 * specifies an instruction that performs "result = a0 op a1". 4285 * This could be a MIPS instruction or a function call. (If the result 4286 * comes back in a register other than a0, you can override "result".) 4287 * 4288 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4289 * vCC (a1). Useful for integer division and modulus. Note that we 4290 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4291 * correctly. 4292 * 4293 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4294 * xor-int, shl-int, shr-int, ushr-int 4295 */ 4296 /* binop vAA, vBB, vCC */ 4297 srl a4, rINST, 8 # a4 <- AA 4298 lbu a2, 2(rPC) # a2 <- BB 4299 lbu a3, 3(rPC) # a3 <- CC 4300 GET_VREG a0, a2 # a0 <- vBB 4301 GET_VREG a1, a3 # a1 <- vCC 4302 .if 0 4303 beqz a1, common_errDivideByZero # is second operand zero? 4304 .endif 4305 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4306 # optional op 4307 sll a0, a0, a1 # a0 <- op, a0-a3 changed 4308 GET_INST_OPCODE v0 # extract opcode from rINST 4309 SET_VREG a0, a4 # vAA <- a0 4310 GOTO_OPCODE v0 # jump to next instruction 4311 4312 4313/* ------------------------------ */ 4314 .balign 128 4315.L_op_shr_int: /* 0x99 */ 4316/* File: mips64/op_shr_int.S */ 4317/* File: mips64/binop.S */ 4318 /* 4319 * Generic 32-bit binary operation. Provide an "instr" line that 4320 * specifies an instruction that performs "result = a0 op a1". 4321 * This could be a MIPS instruction or a function call. (If the result 4322 * comes back in a register other than a0, you can override "result".) 4323 * 4324 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4325 * vCC (a1). Useful for integer division and modulus. Note that we 4326 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4327 * correctly. 4328 * 4329 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4330 * xor-int, shl-int, shr-int, ushr-int 4331 */ 4332 /* binop vAA, vBB, vCC */ 4333 srl a4, rINST, 8 # a4 <- AA 4334 lbu a2, 2(rPC) # a2 <- BB 4335 lbu a3, 3(rPC) # a3 <- CC 4336 GET_VREG a0, a2 # a0 <- vBB 4337 GET_VREG a1, a3 # a1 <- vCC 4338 .if 0 4339 beqz a1, common_errDivideByZero # is second operand zero? 4340 .endif 4341 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4342 # optional op 4343 sra a0, a0, a1 # a0 <- op, a0-a3 changed 4344 GET_INST_OPCODE v0 # extract opcode from rINST 4345 SET_VREG a0, a4 # vAA <- a0 4346 GOTO_OPCODE v0 # jump to next instruction 4347 4348 4349/* ------------------------------ */ 4350 .balign 128 4351.L_op_ushr_int: /* 0x9a */ 4352/* File: mips64/op_ushr_int.S */ 4353/* File: mips64/binop.S */ 4354 /* 4355 * Generic 32-bit binary operation. Provide an "instr" line that 4356 * specifies an instruction that performs "result = a0 op a1". 4357 * This could be a MIPS instruction or a function call. (If the result 4358 * comes back in a register other than a0, you can override "result".) 4359 * 4360 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4361 * vCC (a1). Useful for integer division and modulus. Note that we 4362 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 4363 * correctly. 4364 * 4365 * For: add-int, sub-int, mul-int, div-int, rem-int, and-int, or-int, 4366 * xor-int, shl-int, shr-int, ushr-int 4367 */ 4368 /* binop vAA, vBB, vCC */ 4369 srl a4, rINST, 8 # a4 <- AA 4370 lbu a2, 2(rPC) # a2 <- BB 4371 lbu a3, 3(rPC) # a3 <- CC 4372 GET_VREG a0, a2 # a0 <- vBB 4373 GET_VREG a1, a3 # a1 <- vCC 4374 .if 0 4375 beqz a1, common_errDivideByZero # is second operand zero? 4376 .endif 4377 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4378 # optional op 4379 srl a0, a0, a1 # a0 <- op, a0-a3 changed 4380 GET_INST_OPCODE v0 # extract opcode from rINST 4381 SET_VREG a0, a4 # vAA <- a0 4382 GOTO_OPCODE v0 # jump to next instruction 4383 4384 4385/* ------------------------------ */ 4386 .balign 128 4387.L_op_add_long: /* 0x9b */ 4388/* File: mips64/op_add_long.S */ 4389/* File: mips64/binopWide.S */ 4390 /* 4391 * Generic 64-bit binary operation. Provide an "instr" line that 4392 * specifies an instruction that performs "result = a0 op a1". 4393 * This could be a MIPS instruction or a function call. (If the result 4394 * comes back in a register other than a0, you can override "result".) 4395 * 4396 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4397 * vCC (a1). Useful for integer division and modulus. Note that we 4398 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4399 * correctly. 4400 * 4401 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4402 * xor-long, shl-long, shr-long, ushr-long 4403 */ 4404 /* binop vAA, vBB, vCC */ 4405 srl a4, rINST, 8 # a4 <- AA 4406 lbu a2, 2(rPC) # a2 <- BB 4407 lbu a3, 3(rPC) # a3 <- CC 4408 GET_VREG_WIDE a0, a2 # a0 <- vBB 4409 GET_VREG_WIDE a1, a3 # a1 <- vCC 4410 .if 0 4411 beqz a1, common_errDivideByZero # is second operand zero? 4412 .endif 4413 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4414 # optional op 4415 daddu a0, a0, a1 # a0 <- op, a0-a3 changed 4416 GET_INST_OPCODE v0 # extract opcode from rINST 4417 SET_VREG_WIDE a0, a4 # vAA <- a0 4418 GOTO_OPCODE v0 # jump to next instruction 4419 4420 4421/* ------------------------------ */ 4422 .balign 128 4423.L_op_sub_long: /* 0x9c */ 4424/* File: mips64/op_sub_long.S */ 4425/* File: mips64/binopWide.S */ 4426 /* 4427 * Generic 64-bit binary operation. Provide an "instr" line that 4428 * specifies an instruction that performs "result = a0 op a1". 4429 * This could be a MIPS instruction or a function call. (If the result 4430 * comes back in a register other than a0, you can override "result".) 4431 * 4432 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4433 * vCC (a1). Useful for integer division and modulus. Note that we 4434 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4435 * correctly. 4436 * 4437 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4438 * xor-long, shl-long, shr-long, ushr-long 4439 */ 4440 /* binop vAA, vBB, vCC */ 4441 srl a4, rINST, 8 # a4 <- AA 4442 lbu a2, 2(rPC) # a2 <- BB 4443 lbu a3, 3(rPC) # a3 <- CC 4444 GET_VREG_WIDE a0, a2 # a0 <- vBB 4445 GET_VREG_WIDE a1, a3 # a1 <- vCC 4446 .if 0 4447 beqz a1, common_errDivideByZero # is second operand zero? 4448 .endif 4449 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4450 # optional op 4451 dsubu a0, a0, a1 # a0 <- op, a0-a3 changed 4452 GET_INST_OPCODE v0 # extract opcode from rINST 4453 SET_VREG_WIDE a0, a4 # vAA <- a0 4454 GOTO_OPCODE v0 # jump to next instruction 4455 4456 4457/* ------------------------------ */ 4458 .balign 128 4459.L_op_mul_long: /* 0x9d */ 4460/* File: mips64/op_mul_long.S */ 4461/* File: mips64/binopWide.S */ 4462 /* 4463 * Generic 64-bit binary operation. Provide an "instr" line that 4464 * specifies an instruction that performs "result = a0 op a1". 4465 * This could be a MIPS instruction or a function call. (If the result 4466 * comes back in a register other than a0, you can override "result".) 4467 * 4468 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4469 * vCC (a1). Useful for integer division and modulus. Note that we 4470 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4471 * correctly. 4472 * 4473 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4474 * xor-long, shl-long, shr-long, ushr-long 4475 */ 4476 /* binop vAA, vBB, vCC */ 4477 srl a4, rINST, 8 # a4 <- AA 4478 lbu a2, 2(rPC) # a2 <- BB 4479 lbu a3, 3(rPC) # a3 <- CC 4480 GET_VREG_WIDE a0, a2 # a0 <- vBB 4481 GET_VREG_WIDE a1, a3 # a1 <- vCC 4482 .if 0 4483 beqz a1, common_errDivideByZero # is second operand zero? 4484 .endif 4485 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4486 # optional op 4487 dmul a0, a0, a1 # a0 <- op, a0-a3 changed 4488 GET_INST_OPCODE v0 # extract opcode from rINST 4489 SET_VREG_WIDE a0, a4 # vAA <- a0 4490 GOTO_OPCODE v0 # jump to next instruction 4491 4492 4493/* ------------------------------ */ 4494 .balign 128 4495.L_op_div_long: /* 0x9e */ 4496/* File: mips64/op_div_long.S */ 4497/* File: mips64/binopWide.S */ 4498 /* 4499 * Generic 64-bit binary operation. Provide an "instr" line that 4500 * specifies an instruction that performs "result = a0 op a1". 4501 * This could be a MIPS instruction or a function call. (If the result 4502 * comes back in a register other than a0, you can override "result".) 4503 * 4504 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4505 * vCC (a1). Useful for integer division and modulus. Note that we 4506 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4507 * correctly. 4508 * 4509 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4510 * xor-long, shl-long, shr-long, ushr-long 4511 */ 4512 /* binop vAA, vBB, vCC */ 4513 srl a4, rINST, 8 # a4 <- AA 4514 lbu a2, 2(rPC) # a2 <- BB 4515 lbu a3, 3(rPC) # a3 <- CC 4516 GET_VREG_WIDE a0, a2 # a0 <- vBB 4517 GET_VREG_WIDE a1, a3 # a1 <- vCC 4518 .if 1 4519 beqz a1, common_errDivideByZero # is second operand zero? 4520 .endif 4521 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4522 # optional op 4523 ddiv a0, a0, a1 # a0 <- op, a0-a3 changed 4524 GET_INST_OPCODE v0 # extract opcode from rINST 4525 SET_VREG_WIDE a0, a4 # vAA <- a0 4526 GOTO_OPCODE v0 # jump to next instruction 4527 4528 4529/* ------------------------------ */ 4530 .balign 128 4531.L_op_rem_long: /* 0x9f */ 4532/* File: mips64/op_rem_long.S */ 4533/* File: mips64/binopWide.S */ 4534 /* 4535 * Generic 64-bit binary operation. Provide an "instr" line that 4536 * specifies an instruction that performs "result = a0 op a1". 4537 * This could be a MIPS instruction or a function call. (If the result 4538 * comes back in a register other than a0, you can override "result".) 4539 * 4540 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4541 * vCC (a1). Useful for integer division and modulus. Note that we 4542 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4543 * correctly. 4544 * 4545 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4546 * xor-long, shl-long, shr-long, ushr-long 4547 */ 4548 /* binop vAA, vBB, vCC */ 4549 srl a4, rINST, 8 # a4 <- AA 4550 lbu a2, 2(rPC) # a2 <- BB 4551 lbu a3, 3(rPC) # a3 <- CC 4552 GET_VREG_WIDE a0, a2 # a0 <- vBB 4553 GET_VREG_WIDE a1, a3 # a1 <- vCC 4554 .if 1 4555 beqz a1, common_errDivideByZero # is second operand zero? 4556 .endif 4557 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4558 # optional op 4559 dmod a0, a0, a1 # a0 <- op, a0-a3 changed 4560 GET_INST_OPCODE v0 # extract opcode from rINST 4561 SET_VREG_WIDE a0, a4 # vAA <- a0 4562 GOTO_OPCODE v0 # jump to next instruction 4563 4564 4565/* ------------------------------ */ 4566 .balign 128 4567.L_op_and_long: /* 0xa0 */ 4568/* File: mips64/op_and_long.S */ 4569/* File: mips64/binopWide.S */ 4570 /* 4571 * Generic 64-bit binary operation. Provide an "instr" line that 4572 * specifies an instruction that performs "result = a0 op a1". 4573 * This could be a MIPS instruction or a function call. (If the result 4574 * comes back in a register other than a0, you can override "result".) 4575 * 4576 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4577 * vCC (a1). Useful for integer division and modulus. Note that we 4578 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4579 * correctly. 4580 * 4581 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4582 * xor-long, shl-long, shr-long, ushr-long 4583 */ 4584 /* binop vAA, vBB, vCC */ 4585 srl a4, rINST, 8 # a4 <- AA 4586 lbu a2, 2(rPC) # a2 <- BB 4587 lbu a3, 3(rPC) # a3 <- CC 4588 GET_VREG_WIDE a0, a2 # a0 <- vBB 4589 GET_VREG_WIDE a1, a3 # a1 <- vCC 4590 .if 0 4591 beqz a1, common_errDivideByZero # is second operand zero? 4592 .endif 4593 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4594 # optional op 4595 and a0, a0, a1 # a0 <- op, a0-a3 changed 4596 GET_INST_OPCODE v0 # extract opcode from rINST 4597 SET_VREG_WIDE a0, a4 # vAA <- a0 4598 GOTO_OPCODE v0 # jump to next instruction 4599 4600 4601/* ------------------------------ */ 4602 .balign 128 4603.L_op_or_long: /* 0xa1 */ 4604/* File: mips64/op_or_long.S */ 4605/* File: mips64/binopWide.S */ 4606 /* 4607 * Generic 64-bit binary operation. Provide an "instr" line that 4608 * specifies an instruction that performs "result = a0 op a1". 4609 * This could be a MIPS instruction or a function call. (If the result 4610 * comes back in a register other than a0, you can override "result".) 4611 * 4612 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4613 * vCC (a1). Useful for integer division and modulus. Note that we 4614 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4615 * correctly. 4616 * 4617 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4618 * xor-long, shl-long, shr-long, ushr-long 4619 */ 4620 /* binop vAA, vBB, vCC */ 4621 srl a4, rINST, 8 # a4 <- AA 4622 lbu a2, 2(rPC) # a2 <- BB 4623 lbu a3, 3(rPC) # a3 <- CC 4624 GET_VREG_WIDE a0, a2 # a0 <- vBB 4625 GET_VREG_WIDE a1, a3 # a1 <- vCC 4626 .if 0 4627 beqz a1, common_errDivideByZero # is second operand zero? 4628 .endif 4629 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4630 # optional op 4631 or a0, a0, a1 # a0 <- op, a0-a3 changed 4632 GET_INST_OPCODE v0 # extract opcode from rINST 4633 SET_VREG_WIDE a0, a4 # vAA <- a0 4634 GOTO_OPCODE v0 # jump to next instruction 4635 4636 4637/* ------------------------------ */ 4638 .balign 128 4639.L_op_xor_long: /* 0xa2 */ 4640/* File: mips64/op_xor_long.S */ 4641/* File: mips64/binopWide.S */ 4642 /* 4643 * Generic 64-bit binary operation. Provide an "instr" line that 4644 * specifies an instruction that performs "result = a0 op a1". 4645 * This could be a MIPS instruction or a function call. (If the result 4646 * comes back in a register other than a0, you can override "result".) 4647 * 4648 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4649 * vCC (a1). Useful for integer division and modulus. Note that we 4650 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4651 * correctly. 4652 * 4653 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4654 * xor-long, shl-long, shr-long, ushr-long 4655 */ 4656 /* binop vAA, vBB, vCC */ 4657 srl a4, rINST, 8 # a4 <- AA 4658 lbu a2, 2(rPC) # a2 <- BB 4659 lbu a3, 3(rPC) # a3 <- CC 4660 GET_VREG_WIDE a0, a2 # a0 <- vBB 4661 GET_VREG_WIDE a1, a3 # a1 <- vCC 4662 .if 0 4663 beqz a1, common_errDivideByZero # is second operand zero? 4664 .endif 4665 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4666 # optional op 4667 xor a0, a0, a1 # a0 <- op, a0-a3 changed 4668 GET_INST_OPCODE v0 # extract opcode from rINST 4669 SET_VREG_WIDE a0, a4 # vAA <- a0 4670 GOTO_OPCODE v0 # jump to next instruction 4671 4672 4673/* ------------------------------ */ 4674 .balign 128 4675.L_op_shl_long: /* 0xa3 */ 4676/* File: mips64/op_shl_long.S */ 4677/* File: mips64/binopWide.S */ 4678 /* 4679 * Generic 64-bit binary operation. Provide an "instr" line that 4680 * specifies an instruction that performs "result = a0 op a1". 4681 * This could be a MIPS instruction or a function call. (If the result 4682 * comes back in a register other than a0, you can override "result".) 4683 * 4684 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4685 * vCC (a1). Useful for integer division and modulus. Note that we 4686 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4687 * correctly. 4688 * 4689 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4690 * xor-long, shl-long, shr-long, ushr-long 4691 */ 4692 /* binop vAA, vBB, vCC */ 4693 srl a4, rINST, 8 # a4 <- AA 4694 lbu a2, 2(rPC) # a2 <- BB 4695 lbu a3, 3(rPC) # a3 <- CC 4696 GET_VREG_WIDE a0, a2 # a0 <- vBB 4697 GET_VREG_WIDE a1, a3 # a1 <- vCC 4698 .if 0 4699 beqz a1, common_errDivideByZero # is second operand zero? 4700 .endif 4701 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4702 # optional op 4703 dsll a0, a0, a1 # a0 <- op, a0-a3 changed 4704 GET_INST_OPCODE v0 # extract opcode from rINST 4705 SET_VREG_WIDE a0, a4 # vAA <- a0 4706 GOTO_OPCODE v0 # jump to next instruction 4707 4708 4709/* ------------------------------ */ 4710 .balign 128 4711.L_op_shr_long: /* 0xa4 */ 4712/* File: mips64/op_shr_long.S */ 4713/* File: mips64/binopWide.S */ 4714 /* 4715 * Generic 64-bit binary operation. Provide an "instr" line that 4716 * specifies an instruction that performs "result = a0 op a1". 4717 * This could be a MIPS instruction or a function call. (If the result 4718 * comes back in a register other than a0, you can override "result".) 4719 * 4720 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4721 * vCC (a1). Useful for integer division and modulus. Note that we 4722 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4723 * correctly. 4724 * 4725 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4726 * xor-long, shl-long, shr-long, ushr-long 4727 */ 4728 /* binop vAA, vBB, vCC */ 4729 srl a4, rINST, 8 # a4 <- AA 4730 lbu a2, 2(rPC) # a2 <- BB 4731 lbu a3, 3(rPC) # a3 <- CC 4732 GET_VREG_WIDE a0, a2 # a0 <- vBB 4733 GET_VREG_WIDE a1, a3 # a1 <- vCC 4734 .if 0 4735 beqz a1, common_errDivideByZero # is second operand zero? 4736 .endif 4737 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4738 # optional op 4739 dsra a0, a0, a1 # a0 <- op, a0-a3 changed 4740 GET_INST_OPCODE v0 # extract opcode from rINST 4741 SET_VREG_WIDE a0, a4 # vAA <- a0 4742 GOTO_OPCODE v0 # jump to next instruction 4743 4744 4745/* ------------------------------ */ 4746 .balign 128 4747.L_op_ushr_long: /* 0xa5 */ 4748/* File: mips64/op_ushr_long.S */ 4749/* File: mips64/binopWide.S */ 4750 /* 4751 * Generic 64-bit binary operation. Provide an "instr" line that 4752 * specifies an instruction that performs "result = a0 op a1". 4753 * This could be a MIPS instruction or a function call. (If the result 4754 * comes back in a register other than a0, you can override "result".) 4755 * 4756 * If "chkzero" is set to 1, we perform a divide-by-zero check on 4757 * vCC (a1). Useful for integer division and modulus. Note that we 4758 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 4759 * correctly. 4760 * 4761 * For: add-long, sub-long, mul-long, div-long, rem-long, and-long, or-long, 4762 * xor-long, shl-long, shr-long, ushr-long 4763 */ 4764 /* binop vAA, vBB, vCC */ 4765 srl a4, rINST, 8 # a4 <- AA 4766 lbu a2, 2(rPC) # a2 <- BB 4767 lbu a3, 3(rPC) # a3 <- CC 4768 GET_VREG_WIDE a0, a2 # a0 <- vBB 4769 GET_VREG_WIDE a1, a3 # a1 <- vCC 4770 .if 0 4771 beqz a1, common_errDivideByZero # is second operand zero? 4772 .endif 4773 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4774 # optional op 4775 dsrl a0, a0, a1 # a0 <- op, a0-a3 changed 4776 GET_INST_OPCODE v0 # extract opcode from rINST 4777 SET_VREG_WIDE a0, a4 # vAA <- a0 4778 GOTO_OPCODE v0 # jump to next instruction 4779 4780 4781/* ------------------------------ */ 4782 .balign 128 4783.L_op_add_float: /* 0xa6 */ 4784/* File: mips64/op_add_float.S */ 4785/* File: mips64/fbinop.S */ 4786 /*: 4787 * Generic 32-bit floating-point operation. 4788 * 4789 * For: add-float, sub-float, mul-float, div-float. 4790 * form: <op> f0, f0, f1 4791 */ 4792 /* binop vAA, vBB, vCC */ 4793 srl a4, rINST, 8 # a4 <- AA 4794 lbu a2, 2(rPC) # a2 <- BB 4795 lbu a3, 3(rPC) # a3 <- CC 4796 GET_VREG_FLOAT f0, a2 # f0 <- vBB 4797 GET_VREG_FLOAT f1, a3 # f1 <- vCC 4798 add.s f0, f0, f1 # f0 <- f0 op f1 4799 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4800 GET_INST_OPCODE v0 # extract opcode from rINST 4801 SET_VREG_FLOAT f0, a4 # vAA <- f0 4802 GOTO_OPCODE v0 # jump to next instruction 4803 4804 4805/* ------------------------------ */ 4806 .balign 128 4807.L_op_sub_float: /* 0xa7 */ 4808/* File: mips64/op_sub_float.S */ 4809/* File: mips64/fbinop.S */ 4810 /*: 4811 * Generic 32-bit floating-point operation. 4812 * 4813 * For: add-float, sub-float, mul-float, div-float. 4814 * form: <op> f0, f0, f1 4815 */ 4816 /* binop vAA, vBB, vCC */ 4817 srl a4, rINST, 8 # a4 <- AA 4818 lbu a2, 2(rPC) # a2 <- BB 4819 lbu a3, 3(rPC) # a3 <- CC 4820 GET_VREG_FLOAT f0, a2 # f0 <- vBB 4821 GET_VREG_FLOAT f1, a3 # f1 <- vCC 4822 sub.s f0, f0, f1 # f0 <- f0 op f1 4823 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4824 GET_INST_OPCODE v0 # extract opcode from rINST 4825 SET_VREG_FLOAT f0, a4 # vAA <- f0 4826 GOTO_OPCODE v0 # jump to next instruction 4827 4828 4829/* ------------------------------ */ 4830 .balign 128 4831.L_op_mul_float: /* 0xa8 */ 4832/* File: mips64/op_mul_float.S */ 4833/* File: mips64/fbinop.S */ 4834 /*: 4835 * Generic 32-bit floating-point operation. 4836 * 4837 * For: add-float, sub-float, mul-float, div-float. 4838 * form: <op> f0, f0, f1 4839 */ 4840 /* binop vAA, vBB, vCC */ 4841 srl a4, rINST, 8 # a4 <- AA 4842 lbu a2, 2(rPC) # a2 <- BB 4843 lbu a3, 3(rPC) # a3 <- CC 4844 GET_VREG_FLOAT f0, a2 # f0 <- vBB 4845 GET_VREG_FLOAT f1, a3 # f1 <- vCC 4846 mul.s f0, f0, f1 # f0 <- f0 op f1 4847 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4848 GET_INST_OPCODE v0 # extract opcode from rINST 4849 SET_VREG_FLOAT f0, a4 # vAA <- f0 4850 GOTO_OPCODE v0 # jump to next instruction 4851 4852 4853/* ------------------------------ */ 4854 .balign 128 4855.L_op_div_float: /* 0xa9 */ 4856/* File: mips64/op_div_float.S */ 4857/* File: mips64/fbinop.S */ 4858 /*: 4859 * Generic 32-bit floating-point operation. 4860 * 4861 * For: add-float, sub-float, mul-float, div-float. 4862 * form: <op> f0, f0, f1 4863 */ 4864 /* binop vAA, vBB, vCC */ 4865 srl a4, rINST, 8 # a4 <- AA 4866 lbu a2, 2(rPC) # a2 <- BB 4867 lbu a3, 3(rPC) # a3 <- CC 4868 GET_VREG_FLOAT f0, a2 # f0 <- vBB 4869 GET_VREG_FLOAT f1, a3 # f1 <- vCC 4870 div.s f0, f0, f1 # f0 <- f0 op f1 4871 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4872 GET_INST_OPCODE v0 # extract opcode from rINST 4873 SET_VREG_FLOAT f0, a4 # vAA <- f0 4874 GOTO_OPCODE v0 # jump to next instruction 4875 4876 4877/* ------------------------------ */ 4878 .balign 128 4879.L_op_rem_float: /* 0xaa */ 4880/* File: mips64/op_rem_float.S */ 4881 /* rem-float vAA, vBB, vCC */ 4882 .extern fmodf 4883 lbu a2, 2(rPC) # a2 <- BB 4884 lbu a3, 3(rPC) # a3 <- CC 4885 GET_VREG_FLOAT f12, a2 # f12 <- vBB 4886 GET_VREG_FLOAT f13, a3 # f13 <- vCC 4887 jal fmodf # f0 <- f12 op f13 4888 srl a4, rINST, 8 # a4 <- AA 4889 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4890 GET_INST_OPCODE v0 # extract opcode from rINST 4891 SET_VREG_FLOAT f0, a4 # vAA <- f0 4892 GOTO_OPCODE v0 # jump to next instruction 4893 4894/* ------------------------------ */ 4895 .balign 128 4896.L_op_add_double: /* 0xab */ 4897/* File: mips64/op_add_double.S */ 4898/* File: mips64/fbinopWide.S */ 4899 /*: 4900 * Generic 64-bit floating-point operation. 4901 * 4902 * For: add-double, sub-double, mul-double, div-double. 4903 * form: <op> f0, f0, f1 4904 */ 4905 /* binop vAA, vBB, vCC */ 4906 srl a4, rINST, 8 # a4 <- AA 4907 lbu a2, 2(rPC) # a2 <- BB 4908 lbu a3, 3(rPC) # a3 <- CC 4909 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 4910 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 4911 add.d f0, f0, f1 # f0 <- f0 op f1 4912 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4913 GET_INST_OPCODE v0 # extract opcode from rINST 4914 SET_VREG_DOUBLE f0, a4 # vAA <- f0 4915 GOTO_OPCODE v0 # jump to next instruction 4916 4917 4918/* ------------------------------ */ 4919 .balign 128 4920.L_op_sub_double: /* 0xac */ 4921/* File: mips64/op_sub_double.S */ 4922/* File: mips64/fbinopWide.S */ 4923 /*: 4924 * Generic 64-bit floating-point operation. 4925 * 4926 * For: add-double, sub-double, mul-double, div-double. 4927 * form: <op> f0, f0, f1 4928 */ 4929 /* binop vAA, vBB, vCC */ 4930 srl a4, rINST, 8 # a4 <- AA 4931 lbu a2, 2(rPC) # a2 <- BB 4932 lbu a3, 3(rPC) # a3 <- CC 4933 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 4934 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 4935 sub.d f0, f0, f1 # f0 <- f0 op f1 4936 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4937 GET_INST_OPCODE v0 # extract opcode from rINST 4938 SET_VREG_DOUBLE f0, a4 # vAA <- f0 4939 GOTO_OPCODE v0 # jump to next instruction 4940 4941 4942/* ------------------------------ */ 4943 .balign 128 4944.L_op_mul_double: /* 0xad */ 4945/* File: mips64/op_mul_double.S */ 4946/* File: mips64/fbinopWide.S */ 4947 /*: 4948 * Generic 64-bit floating-point operation. 4949 * 4950 * For: add-double, sub-double, mul-double, div-double. 4951 * form: <op> f0, f0, f1 4952 */ 4953 /* binop vAA, vBB, vCC */ 4954 srl a4, rINST, 8 # a4 <- AA 4955 lbu a2, 2(rPC) # a2 <- BB 4956 lbu a3, 3(rPC) # a3 <- CC 4957 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 4958 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 4959 mul.d f0, f0, f1 # f0 <- f0 op f1 4960 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4961 GET_INST_OPCODE v0 # extract opcode from rINST 4962 SET_VREG_DOUBLE f0, a4 # vAA <- f0 4963 GOTO_OPCODE v0 # jump to next instruction 4964 4965 4966/* ------------------------------ */ 4967 .balign 128 4968.L_op_div_double: /* 0xae */ 4969/* File: mips64/op_div_double.S */ 4970/* File: mips64/fbinopWide.S */ 4971 /*: 4972 * Generic 64-bit floating-point operation. 4973 * 4974 * For: add-double, sub-double, mul-double, div-double. 4975 * form: <op> f0, f0, f1 4976 */ 4977 /* binop vAA, vBB, vCC */ 4978 srl a4, rINST, 8 # a4 <- AA 4979 lbu a2, 2(rPC) # a2 <- BB 4980 lbu a3, 3(rPC) # a3 <- CC 4981 GET_VREG_DOUBLE f0, a2 # f0 <- vBB 4982 GET_VREG_DOUBLE f1, a3 # f1 <- vCC 4983 div.d f0, f0, f1 # f0 <- f0 op f1 4984 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 4985 GET_INST_OPCODE v0 # extract opcode from rINST 4986 SET_VREG_DOUBLE f0, a4 # vAA <- f0 4987 GOTO_OPCODE v0 # jump to next instruction 4988 4989 4990/* ------------------------------ */ 4991 .balign 128 4992.L_op_rem_double: /* 0xaf */ 4993/* File: mips64/op_rem_double.S */ 4994 /* rem-double vAA, vBB, vCC */ 4995 .extern fmod 4996 lbu a2, 2(rPC) # a2 <- BB 4997 lbu a3, 3(rPC) # a3 <- CC 4998 GET_VREG_DOUBLE f12, a2 # f12 <- vBB 4999 GET_VREG_DOUBLE f13, a3 # f13 <- vCC 5000 jal fmod # f0 <- f12 op f13 5001 srl a4, rINST, 8 # a4 <- AA 5002 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 5003 GET_INST_OPCODE v0 # extract opcode from rINST 5004 SET_VREG_DOUBLE f0, a4 # vAA <- f0 5005 GOTO_OPCODE v0 # jump to next instruction 5006 5007/* ------------------------------ */ 5008 .balign 128 5009.L_op_add_int_2addr: /* 0xb0 */ 5010/* File: mips64/op_add_int_2addr.S */ 5011/* File: mips64/binop2addr.S */ 5012 /* 5013 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5014 * that specifies an instruction that performs "result = a0 op a1". 5015 * This could be a MIPS instruction or a function call. (If the result 5016 * comes back in a register other than a0, you can override "result".) 5017 * 5018 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5019 * vB (a1). Useful for integer division and modulus. Note that we 5020 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5021 * correctly. 5022 * 5023 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5024 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5025 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5026 */ 5027 /* binop/2addr vA, vB */ 5028 ext a2, rINST, 8, 4 # a2 <- A 5029 ext a3, rINST, 12, 4 # a3 <- B 5030 GET_VREG a0, a2 # a0 <- vA 5031 GET_VREG a1, a3 # a1 <- vB 5032 .if 0 5033 beqz a1, common_errDivideByZero # is second operand zero? 5034 .endif 5035 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5036 # optional op 5037 addu a0, a0, a1 # a0 <- op, a0-a3 changed 5038 GET_INST_OPCODE v0 # extract opcode from rINST 5039 SET_VREG a0, a2 # vA <- a0 5040 GOTO_OPCODE v0 # jump to next instruction 5041 5042 5043/* ------------------------------ */ 5044 .balign 128 5045.L_op_sub_int_2addr: /* 0xb1 */ 5046/* File: mips64/op_sub_int_2addr.S */ 5047/* File: mips64/binop2addr.S */ 5048 /* 5049 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5050 * that specifies an instruction that performs "result = a0 op a1". 5051 * This could be a MIPS instruction or a function call. (If the result 5052 * comes back in a register other than a0, you can override "result".) 5053 * 5054 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5055 * vB (a1). Useful for integer division and modulus. Note that we 5056 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5057 * correctly. 5058 * 5059 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5060 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5061 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5062 */ 5063 /* binop/2addr vA, vB */ 5064 ext a2, rINST, 8, 4 # a2 <- A 5065 ext a3, rINST, 12, 4 # a3 <- B 5066 GET_VREG a0, a2 # a0 <- vA 5067 GET_VREG a1, a3 # a1 <- vB 5068 .if 0 5069 beqz a1, common_errDivideByZero # is second operand zero? 5070 .endif 5071 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5072 # optional op 5073 subu a0, a0, a1 # a0 <- op, a0-a3 changed 5074 GET_INST_OPCODE v0 # extract opcode from rINST 5075 SET_VREG a0, a2 # vA <- a0 5076 GOTO_OPCODE v0 # jump to next instruction 5077 5078 5079/* ------------------------------ */ 5080 .balign 128 5081.L_op_mul_int_2addr: /* 0xb2 */ 5082/* File: mips64/op_mul_int_2addr.S */ 5083/* File: mips64/binop2addr.S */ 5084 /* 5085 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5086 * that specifies an instruction that performs "result = a0 op a1". 5087 * This could be a MIPS instruction or a function call. (If the result 5088 * comes back in a register other than a0, you can override "result".) 5089 * 5090 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5091 * vB (a1). Useful for integer division and modulus. Note that we 5092 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5093 * correctly. 5094 * 5095 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5096 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5097 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5098 */ 5099 /* binop/2addr vA, vB */ 5100 ext a2, rINST, 8, 4 # a2 <- A 5101 ext a3, rINST, 12, 4 # a3 <- B 5102 GET_VREG a0, a2 # a0 <- vA 5103 GET_VREG a1, a3 # a1 <- vB 5104 .if 0 5105 beqz a1, common_errDivideByZero # is second operand zero? 5106 .endif 5107 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5108 # optional op 5109 mul a0, a0, a1 # a0 <- op, a0-a3 changed 5110 GET_INST_OPCODE v0 # extract opcode from rINST 5111 SET_VREG a0, a2 # vA <- a0 5112 GOTO_OPCODE v0 # jump to next instruction 5113 5114 5115/* ------------------------------ */ 5116 .balign 128 5117.L_op_div_int_2addr: /* 0xb3 */ 5118/* File: mips64/op_div_int_2addr.S */ 5119/* File: mips64/binop2addr.S */ 5120 /* 5121 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5122 * that specifies an instruction that performs "result = a0 op a1". 5123 * This could be a MIPS instruction or a function call. (If the result 5124 * comes back in a register other than a0, you can override "result".) 5125 * 5126 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5127 * vB (a1). Useful for integer division and modulus. Note that we 5128 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5129 * correctly. 5130 * 5131 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5132 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5133 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5134 */ 5135 /* binop/2addr vA, vB */ 5136 ext a2, rINST, 8, 4 # a2 <- A 5137 ext a3, rINST, 12, 4 # a3 <- B 5138 GET_VREG a0, a2 # a0 <- vA 5139 GET_VREG a1, a3 # a1 <- vB 5140 .if 1 5141 beqz a1, common_errDivideByZero # is second operand zero? 5142 .endif 5143 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5144 # optional op 5145 div a0, a0, a1 # a0 <- op, a0-a3 changed 5146 GET_INST_OPCODE v0 # extract opcode from rINST 5147 SET_VREG a0, a2 # vA <- a0 5148 GOTO_OPCODE v0 # jump to next instruction 5149 5150 5151/* ------------------------------ */ 5152 .balign 128 5153.L_op_rem_int_2addr: /* 0xb4 */ 5154/* File: mips64/op_rem_int_2addr.S */ 5155/* File: mips64/binop2addr.S */ 5156 /* 5157 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5158 * that specifies an instruction that performs "result = a0 op a1". 5159 * This could be a MIPS instruction or a function call. (If the result 5160 * comes back in a register other than a0, you can override "result".) 5161 * 5162 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5163 * vB (a1). Useful for integer division and modulus. Note that we 5164 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5165 * correctly. 5166 * 5167 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5168 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5169 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5170 */ 5171 /* binop/2addr vA, vB */ 5172 ext a2, rINST, 8, 4 # a2 <- A 5173 ext a3, rINST, 12, 4 # a3 <- B 5174 GET_VREG a0, a2 # a0 <- vA 5175 GET_VREG a1, a3 # a1 <- vB 5176 .if 1 5177 beqz a1, common_errDivideByZero # is second operand zero? 5178 .endif 5179 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5180 # optional op 5181 mod a0, a0, a1 # a0 <- op, a0-a3 changed 5182 GET_INST_OPCODE v0 # extract opcode from rINST 5183 SET_VREG a0, a2 # vA <- a0 5184 GOTO_OPCODE v0 # jump to next instruction 5185 5186 5187/* ------------------------------ */ 5188 .balign 128 5189.L_op_and_int_2addr: /* 0xb5 */ 5190/* File: mips64/op_and_int_2addr.S */ 5191/* File: mips64/binop2addr.S */ 5192 /* 5193 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5194 * that specifies an instruction that performs "result = a0 op a1". 5195 * This could be a MIPS instruction or a function call. (If the result 5196 * comes back in a register other than a0, you can override "result".) 5197 * 5198 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5199 * vB (a1). Useful for integer division and modulus. Note that we 5200 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5201 * correctly. 5202 * 5203 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5204 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5205 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5206 */ 5207 /* binop/2addr vA, vB */ 5208 ext a2, rINST, 8, 4 # a2 <- A 5209 ext a3, rINST, 12, 4 # a3 <- B 5210 GET_VREG a0, a2 # a0 <- vA 5211 GET_VREG a1, a3 # a1 <- vB 5212 .if 0 5213 beqz a1, common_errDivideByZero # is second operand zero? 5214 .endif 5215 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5216 # optional op 5217 and a0, a0, a1 # a0 <- op, a0-a3 changed 5218 GET_INST_OPCODE v0 # extract opcode from rINST 5219 SET_VREG a0, a2 # vA <- a0 5220 GOTO_OPCODE v0 # jump to next instruction 5221 5222 5223/* ------------------------------ */ 5224 .balign 128 5225.L_op_or_int_2addr: /* 0xb6 */ 5226/* File: mips64/op_or_int_2addr.S */ 5227/* File: mips64/binop2addr.S */ 5228 /* 5229 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5230 * that specifies an instruction that performs "result = a0 op a1". 5231 * This could be a MIPS instruction or a function call. (If the result 5232 * comes back in a register other than a0, you can override "result".) 5233 * 5234 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5235 * vB (a1). Useful for integer division and modulus. Note that we 5236 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5237 * correctly. 5238 * 5239 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5240 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5241 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5242 */ 5243 /* binop/2addr vA, vB */ 5244 ext a2, rINST, 8, 4 # a2 <- A 5245 ext a3, rINST, 12, 4 # a3 <- B 5246 GET_VREG a0, a2 # a0 <- vA 5247 GET_VREG a1, a3 # a1 <- vB 5248 .if 0 5249 beqz a1, common_errDivideByZero # is second operand zero? 5250 .endif 5251 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5252 # optional op 5253 or a0, a0, a1 # a0 <- op, a0-a3 changed 5254 GET_INST_OPCODE v0 # extract opcode from rINST 5255 SET_VREG a0, a2 # vA <- a0 5256 GOTO_OPCODE v0 # jump to next instruction 5257 5258 5259/* ------------------------------ */ 5260 .balign 128 5261.L_op_xor_int_2addr: /* 0xb7 */ 5262/* File: mips64/op_xor_int_2addr.S */ 5263/* File: mips64/binop2addr.S */ 5264 /* 5265 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5266 * that specifies an instruction that performs "result = a0 op a1". 5267 * This could be a MIPS instruction or a function call. (If the result 5268 * comes back in a register other than a0, you can override "result".) 5269 * 5270 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5271 * vB (a1). Useful for integer division and modulus. Note that we 5272 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5273 * correctly. 5274 * 5275 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5276 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5277 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5278 */ 5279 /* binop/2addr vA, vB */ 5280 ext a2, rINST, 8, 4 # a2 <- A 5281 ext a3, rINST, 12, 4 # a3 <- B 5282 GET_VREG a0, a2 # a0 <- vA 5283 GET_VREG a1, a3 # a1 <- vB 5284 .if 0 5285 beqz a1, common_errDivideByZero # is second operand zero? 5286 .endif 5287 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5288 # optional op 5289 xor a0, a0, a1 # a0 <- op, a0-a3 changed 5290 GET_INST_OPCODE v0 # extract opcode from rINST 5291 SET_VREG a0, a2 # vA <- a0 5292 GOTO_OPCODE v0 # jump to next instruction 5293 5294 5295/* ------------------------------ */ 5296 .balign 128 5297.L_op_shl_int_2addr: /* 0xb8 */ 5298/* File: mips64/op_shl_int_2addr.S */ 5299/* File: mips64/binop2addr.S */ 5300 /* 5301 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5302 * that specifies an instruction that performs "result = a0 op a1". 5303 * This could be a MIPS instruction or a function call. (If the result 5304 * comes back in a register other than a0, you can override "result".) 5305 * 5306 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5307 * vB (a1). Useful for integer division and modulus. Note that we 5308 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5309 * correctly. 5310 * 5311 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5312 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5313 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5314 */ 5315 /* binop/2addr vA, vB */ 5316 ext a2, rINST, 8, 4 # a2 <- A 5317 ext a3, rINST, 12, 4 # a3 <- B 5318 GET_VREG a0, a2 # a0 <- vA 5319 GET_VREG a1, a3 # a1 <- vB 5320 .if 0 5321 beqz a1, common_errDivideByZero # is second operand zero? 5322 .endif 5323 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5324 # optional op 5325 sll a0, a0, a1 # a0 <- op, a0-a3 changed 5326 GET_INST_OPCODE v0 # extract opcode from rINST 5327 SET_VREG a0, a2 # vA <- a0 5328 GOTO_OPCODE v0 # jump to next instruction 5329 5330 5331/* ------------------------------ */ 5332 .balign 128 5333.L_op_shr_int_2addr: /* 0xb9 */ 5334/* File: mips64/op_shr_int_2addr.S */ 5335/* File: mips64/binop2addr.S */ 5336 /* 5337 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5338 * that specifies an instruction that performs "result = a0 op a1". 5339 * This could be a MIPS instruction or a function call. (If the result 5340 * comes back in a register other than a0, you can override "result".) 5341 * 5342 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5343 * vB (a1). Useful for integer division and modulus. Note that we 5344 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5345 * correctly. 5346 * 5347 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5348 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5349 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5350 */ 5351 /* binop/2addr vA, vB */ 5352 ext a2, rINST, 8, 4 # a2 <- A 5353 ext a3, rINST, 12, 4 # a3 <- B 5354 GET_VREG a0, a2 # a0 <- vA 5355 GET_VREG a1, a3 # a1 <- vB 5356 .if 0 5357 beqz a1, common_errDivideByZero # is second operand zero? 5358 .endif 5359 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5360 # optional op 5361 sra a0, a0, a1 # a0 <- op, a0-a3 changed 5362 GET_INST_OPCODE v0 # extract opcode from rINST 5363 SET_VREG a0, a2 # vA <- a0 5364 GOTO_OPCODE v0 # jump to next instruction 5365 5366 5367/* ------------------------------ */ 5368 .balign 128 5369.L_op_ushr_int_2addr: /* 0xba */ 5370/* File: mips64/op_ushr_int_2addr.S */ 5371/* File: mips64/binop2addr.S */ 5372 /* 5373 * Generic 32-bit "/2addr" binary operation. Provide an "instr" line 5374 * that specifies an instruction that performs "result = a0 op a1". 5375 * This could be a MIPS instruction or a function call. (If the result 5376 * comes back in a register other than a0, you can override "result".) 5377 * 5378 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5379 * vB (a1). Useful for integer division and modulus. Note that we 5380 * *don't* check for (INT_MIN / -1) here, because the CPU handles it 5381 * correctly. 5382 * 5383 * For: add-int/2addr, sub-int/2addr, mul-int/2addr, div-int/2addr, 5384 * rem-int/2addr, and-int/2addr, or-int/2addr, xor-int/2addr, 5385 * shl-int/2addr, shr-int/2addr, ushr-int/2addr 5386 */ 5387 /* binop/2addr vA, vB */ 5388 ext a2, rINST, 8, 4 # a2 <- A 5389 ext a3, rINST, 12, 4 # a3 <- B 5390 GET_VREG a0, a2 # a0 <- vA 5391 GET_VREG a1, a3 # a1 <- vB 5392 .if 0 5393 beqz a1, common_errDivideByZero # is second operand zero? 5394 .endif 5395 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5396 # optional op 5397 srl a0, a0, a1 # a0 <- op, a0-a3 changed 5398 GET_INST_OPCODE v0 # extract opcode from rINST 5399 SET_VREG a0, a2 # vA <- a0 5400 GOTO_OPCODE v0 # jump to next instruction 5401 5402 5403/* ------------------------------ */ 5404 .balign 128 5405.L_op_add_long_2addr: /* 0xbb */ 5406/* File: mips64/op_add_long_2addr.S */ 5407/* File: mips64/binopWide2addr.S */ 5408 /* 5409 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5410 * that specifies an instruction that performs "result = a0 op a1". 5411 * This could be a MIPS instruction or a function call. (If the result 5412 * comes back in a register other than a0, you can override "result".) 5413 * 5414 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5415 * vB (a1). Useful for integer division and modulus. Note that we 5416 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5417 * correctly. 5418 * 5419 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5420 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5421 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5422 */ 5423 /* binop/2addr vA, vB */ 5424 ext a2, rINST, 8, 4 # a2 <- A 5425 ext a3, rINST, 12, 4 # a3 <- B 5426 GET_VREG_WIDE a0, a2 # a0 <- vA 5427 GET_VREG_WIDE a1, a3 # a1 <- vB 5428 .if 0 5429 beqz a1, common_errDivideByZero # is second operand zero? 5430 .endif 5431 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5432 # optional op 5433 daddu a0, a0, a1 # a0 <- op, a0-a3 changed 5434 GET_INST_OPCODE v0 # extract opcode from rINST 5435 SET_VREG_WIDE a0, a2 # vA <- a0 5436 GOTO_OPCODE v0 # jump to next instruction 5437 5438 5439/* ------------------------------ */ 5440 .balign 128 5441.L_op_sub_long_2addr: /* 0xbc */ 5442/* File: mips64/op_sub_long_2addr.S */ 5443/* File: mips64/binopWide2addr.S */ 5444 /* 5445 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5446 * that specifies an instruction that performs "result = a0 op a1". 5447 * This could be a MIPS instruction or a function call. (If the result 5448 * comes back in a register other than a0, you can override "result".) 5449 * 5450 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5451 * vB (a1). Useful for integer division and modulus. Note that we 5452 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5453 * correctly. 5454 * 5455 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5456 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5457 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5458 */ 5459 /* binop/2addr vA, vB */ 5460 ext a2, rINST, 8, 4 # a2 <- A 5461 ext a3, rINST, 12, 4 # a3 <- B 5462 GET_VREG_WIDE a0, a2 # a0 <- vA 5463 GET_VREG_WIDE a1, a3 # a1 <- vB 5464 .if 0 5465 beqz a1, common_errDivideByZero # is second operand zero? 5466 .endif 5467 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5468 # optional op 5469 dsubu a0, a0, a1 # a0 <- op, a0-a3 changed 5470 GET_INST_OPCODE v0 # extract opcode from rINST 5471 SET_VREG_WIDE a0, a2 # vA <- a0 5472 GOTO_OPCODE v0 # jump to next instruction 5473 5474 5475/* ------------------------------ */ 5476 .balign 128 5477.L_op_mul_long_2addr: /* 0xbd */ 5478/* File: mips64/op_mul_long_2addr.S */ 5479/* File: mips64/binopWide2addr.S */ 5480 /* 5481 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5482 * that specifies an instruction that performs "result = a0 op a1". 5483 * This could be a MIPS instruction or a function call. (If the result 5484 * comes back in a register other than a0, you can override "result".) 5485 * 5486 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5487 * vB (a1). Useful for integer division and modulus. Note that we 5488 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5489 * correctly. 5490 * 5491 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5492 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5493 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5494 */ 5495 /* binop/2addr vA, vB */ 5496 ext a2, rINST, 8, 4 # a2 <- A 5497 ext a3, rINST, 12, 4 # a3 <- B 5498 GET_VREG_WIDE a0, a2 # a0 <- vA 5499 GET_VREG_WIDE a1, a3 # a1 <- vB 5500 .if 0 5501 beqz a1, common_errDivideByZero # is second operand zero? 5502 .endif 5503 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5504 # optional op 5505 dmul a0, a0, a1 # a0 <- op, a0-a3 changed 5506 GET_INST_OPCODE v0 # extract opcode from rINST 5507 SET_VREG_WIDE a0, a2 # vA <- a0 5508 GOTO_OPCODE v0 # jump to next instruction 5509 5510 5511/* ------------------------------ */ 5512 .balign 128 5513.L_op_div_long_2addr: /* 0xbe */ 5514/* File: mips64/op_div_long_2addr.S */ 5515/* File: mips64/binopWide2addr.S */ 5516 /* 5517 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5518 * that specifies an instruction that performs "result = a0 op a1". 5519 * This could be a MIPS instruction or a function call. (If the result 5520 * comes back in a register other than a0, you can override "result".) 5521 * 5522 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5523 * vB (a1). Useful for integer division and modulus. Note that we 5524 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5525 * correctly. 5526 * 5527 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5528 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5529 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5530 */ 5531 /* binop/2addr vA, vB */ 5532 ext a2, rINST, 8, 4 # a2 <- A 5533 ext a3, rINST, 12, 4 # a3 <- B 5534 GET_VREG_WIDE a0, a2 # a0 <- vA 5535 GET_VREG_WIDE a1, a3 # a1 <- vB 5536 .if 1 5537 beqz a1, common_errDivideByZero # is second operand zero? 5538 .endif 5539 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5540 # optional op 5541 ddiv a0, a0, a1 # a0 <- op, a0-a3 changed 5542 GET_INST_OPCODE v0 # extract opcode from rINST 5543 SET_VREG_WIDE a0, a2 # vA <- a0 5544 GOTO_OPCODE v0 # jump to next instruction 5545 5546 5547/* ------------------------------ */ 5548 .balign 128 5549.L_op_rem_long_2addr: /* 0xbf */ 5550/* File: mips64/op_rem_long_2addr.S */ 5551/* File: mips64/binopWide2addr.S */ 5552 /* 5553 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5554 * that specifies an instruction that performs "result = a0 op a1". 5555 * This could be a MIPS instruction or a function call. (If the result 5556 * comes back in a register other than a0, you can override "result".) 5557 * 5558 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5559 * vB (a1). Useful for integer division and modulus. Note that we 5560 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5561 * correctly. 5562 * 5563 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5564 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5565 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5566 */ 5567 /* binop/2addr vA, vB */ 5568 ext a2, rINST, 8, 4 # a2 <- A 5569 ext a3, rINST, 12, 4 # a3 <- B 5570 GET_VREG_WIDE a0, a2 # a0 <- vA 5571 GET_VREG_WIDE a1, a3 # a1 <- vB 5572 .if 1 5573 beqz a1, common_errDivideByZero # is second operand zero? 5574 .endif 5575 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5576 # optional op 5577 dmod a0, a0, a1 # a0 <- op, a0-a3 changed 5578 GET_INST_OPCODE v0 # extract opcode from rINST 5579 SET_VREG_WIDE a0, a2 # vA <- a0 5580 GOTO_OPCODE v0 # jump to next instruction 5581 5582 5583/* ------------------------------ */ 5584 .balign 128 5585.L_op_and_long_2addr: /* 0xc0 */ 5586/* File: mips64/op_and_long_2addr.S */ 5587/* File: mips64/binopWide2addr.S */ 5588 /* 5589 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5590 * that specifies an instruction that performs "result = a0 op a1". 5591 * This could be a MIPS instruction or a function call. (If the result 5592 * comes back in a register other than a0, you can override "result".) 5593 * 5594 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5595 * vB (a1). Useful for integer division and modulus. Note that we 5596 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5597 * correctly. 5598 * 5599 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5600 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5601 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5602 */ 5603 /* binop/2addr vA, vB */ 5604 ext a2, rINST, 8, 4 # a2 <- A 5605 ext a3, rINST, 12, 4 # a3 <- B 5606 GET_VREG_WIDE a0, a2 # a0 <- vA 5607 GET_VREG_WIDE a1, a3 # a1 <- vB 5608 .if 0 5609 beqz a1, common_errDivideByZero # is second operand zero? 5610 .endif 5611 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5612 # optional op 5613 and a0, a0, a1 # a0 <- op, a0-a3 changed 5614 GET_INST_OPCODE v0 # extract opcode from rINST 5615 SET_VREG_WIDE a0, a2 # vA <- a0 5616 GOTO_OPCODE v0 # jump to next instruction 5617 5618 5619/* ------------------------------ */ 5620 .balign 128 5621.L_op_or_long_2addr: /* 0xc1 */ 5622/* File: mips64/op_or_long_2addr.S */ 5623/* File: mips64/binopWide2addr.S */ 5624 /* 5625 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5626 * that specifies an instruction that performs "result = a0 op a1". 5627 * This could be a MIPS instruction or a function call. (If the result 5628 * comes back in a register other than a0, you can override "result".) 5629 * 5630 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5631 * vB (a1). Useful for integer division and modulus. Note that we 5632 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5633 * correctly. 5634 * 5635 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5636 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5637 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5638 */ 5639 /* binop/2addr vA, vB */ 5640 ext a2, rINST, 8, 4 # a2 <- A 5641 ext a3, rINST, 12, 4 # a3 <- B 5642 GET_VREG_WIDE a0, a2 # a0 <- vA 5643 GET_VREG_WIDE a1, a3 # a1 <- vB 5644 .if 0 5645 beqz a1, common_errDivideByZero # is second operand zero? 5646 .endif 5647 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5648 # optional op 5649 or a0, a0, a1 # a0 <- op, a0-a3 changed 5650 GET_INST_OPCODE v0 # extract opcode from rINST 5651 SET_VREG_WIDE a0, a2 # vA <- a0 5652 GOTO_OPCODE v0 # jump to next instruction 5653 5654 5655/* ------------------------------ */ 5656 .balign 128 5657.L_op_xor_long_2addr: /* 0xc2 */ 5658/* File: mips64/op_xor_long_2addr.S */ 5659/* File: mips64/binopWide2addr.S */ 5660 /* 5661 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5662 * that specifies an instruction that performs "result = a0 op a1". 5663 * This could be a MIPS instruction or a function call. (If the result 5664 * comes back in a register other than a0, you can override "result".) 5665 * 5666 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5667 * vB (a1). Useful for integer division and modulus. Note that we 5668 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5669 * correctly. 5670 * 5671 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5672 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5673 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5674 */ 5675 /* binop/2addr vA, vB */ 5676 ext a2, rINST, 8, 4 # a2 <- A 5677 ext a3, rINST, 12, 4 # a3 <- B 5678 GET_VREG_WIDE a0, a2 # a0 <- vA 5679 GET_VREG_WIDE a1, a3 # a1 <- vB 5680 .if 0 5681 beqz a1, common_errDivideByZero # is second operand zero? 5682 .endif 5683 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5684 # optional op 5685 xor a0, a0, a1 # a0 <- op, a0-a3 changed 5686 GET_INST_OPCODE v0 # extract opcode from rINST 5687 SET_VREG_WIDE a0, a2 # vA <- a0 5688 GOTO_OPCODE v0 # jump to next instruction 5689 5690 5691/* ------------------------------ */ 5692 .balign 128 5693.L_op_shl_long_2addr: /* 0xc3 */ 5694/* File: mips64/op_shl_long_2addr.S */ 5695/* File: mips64/binopWide2addr.S */ 5696 /* 5697 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5698 * that specifies an instruction that performs "result = a0 op a1". 5699 * This could be a MIPS instruction or a function call. (If the result 5700 * comes back in a register other than a0, you can override "result".) 5701 * 5702 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5703 * vB (a1). Useful for integer division and modulus. Note that we 5704 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5705 * correctly. 5706 * 5707 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5708 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5709 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5710 */ 5711 /* binop/2addr vA, vB */ 5712 ext a2, rINST, 8, 4 # a2 <- A 5713 ext a3, rINST, 12, 4 # a3 <- B 5714 GET_VREG_WIDE a0, a2 # a0 <- vA 5715 GET_VREG_WIDE a1, a3 # a1 <- vB 5716 .if 0 5717 beqz a1, common_errDivideByZero # is second operand zero? 5718 .endif 5719 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5720 # optional op 5721 dsll a0, a0, a1 # a0 <- op, a0-a3 changed 5722 GET_INST_OPCODE v0 # extract opcode from rINST 5723 SET_VREG_WIDE a0, a2 # vA <- a0 5724 GOTO_OPCODE v0 # jump to next instruction 5725 5726 5727/* ------------------------------ */ 5728 .balign 128 5729.L_op_shr_long_2addr: /* 0xc4 */ 5730/* File: mips64/op_shr_long_2addr.S */ 5731/* File: mips64/binopWide2addr.S */ 5732 /* 5733 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5734 * that specifies an instruction that performs "result = a0 op a1". 5735 * This could be a MIPS instruction or a function call. (If the result 5736 * comes back in a register other than a0, you can override "result".) 5737 * 5738 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5739 * vB (a1). Useful for integer division and modulus. Note that we 5740 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5741 * correctly. 5742 * 5743 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5744 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5745 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5746 */ 5747 /* binop/2addr vA, vB */ 5748 ext a2, rINST, 8, 4 # a2 <- A 5749 ext a3, rINST, 12, 4 # a3 <- B 5750 GET_VREG_WIDE a0, a2 # a0 <- vA 5751 GET_VREG_WIDE a1, a3 # a1 <- vB 5752 .if 0 5753 beqz a1, common_errDivideByZero # is second operand zero? 5754 .endif 5755 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5756 # optional op 5757 dsra a0, a0, a1 # a0 <- op, a0-a3 changed 5758 GET_INST_OPCODE v0 # extract opcode from rINST 5759 SET_VREG_WIDE a0, a2 # vA <- a0 5760 GOTO_OPCODE v0 # jump to next instruction 5761 5762 5763/* ------------------------------ */ 5764 .balign 128 5765.L_op_ushr_long_2addr: /* 0xc5 */ 5766/* File: mips64/op_ushr_long_2addr.S */ 5767/* File: mips64/binopWide2addr.S */ 5768 /* 5769 * Generic 64-bit "/2addr" binary operation. Provide an "instr" line 5770 * that specifies an instruction that performs "result = a0 op a1". 5771 * This could be a MIPS instruction or a function call. (If the result 5772 * comes back in a register other than a0, you can override "result".) 5773 * 5774 * If "chkzero" is set to 1, we perform a divide-by-zero check on 5775 * vB (a1). Useful for integer division and modulus. Note that we 5776 * *don't* check for (LONG_MIN / -1) here, because the CPU handles it 5777 * correctly. 5778 * 5779 * For: add-long/2addr, sub-long/2addr, mul-long/2addr, div-long/2addr, 5780 * rem-long/2addr, and-long/2addr, or-long/2addr, xor-long/2addr, 5781 * shl-long/2addr, shr-long/2addr, ushr-long/2addr 5782 */ 5783 /* binop/2addr vA, vB */ 5784 ext a2, rINST, 8, 4 # a2 <- A 5785 ext a3, rINST, 12, 4 # a3 <- B 5786 GET_VREG_WIDE a0, a2 # a0 <- vA 5787 GET_VREG_WIDE a1, a3 # a1 <- vB 5788 .if 0 5789 beqz a1, common_errDivideByZero # is second operand zero? 5790 .endif 5791 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5792 # optional op 5793 dsrl a0, a0, a1 # a0 <- op, a0-a3 changed 5794 GET_INST_OPCODE v0 # extract opcode from rINST 5795 SET_VREG_WIDE a0, a2 # vA <- a0 5796 GOTO_OPCODE v0 # jump to next instruction 5797 5798 5799/* ------------------------------ */ 5800 .balign 128 5801.L_op_add_float_2addr: /* 0xc6 */ 5802/* File: mips64/op_add_float_2addr.S */ 5803/* File: mips64/fbinop2addr.S */ 5804 /*: 5805 * Generic 32-bit "/2addr" floating-point operation. 5806 * 5807 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 5808 * form: <op> f0, f0, f1 5809 */ 5810 /* binop/2addr vA, vB */ 5811 ext a2, rINST, 8, 4 # a2 <- A 5812 ext a3, rINST, 12, 4 # a3 <- B 5813 GET_VREG_FLOAT f0, a2 # f0 <- vA 5814 GET_VREG_FLOAT f1, a3 # f1 <- vB 5815 add.s f0, f0, f1 # f0 <- f0 op f1 5816 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5817 GET_INST_OPCODE v0 # extract opcode from rINST 5818 SET_VREG_FLOAT f0, a2 # vA <- f0 5819 GOTO_OPCODE v0 # jump to next instruction 5820 5821 5822/* ------------------------------ */ 5823 .balign 128 5824.L_op_sub_float_2addr: /* 0xc7 */ 5825/* File: mips64/op_sub_float_2addr.S */ 5826/* File: mips64/fbinop2addr.S */ 5827 /*: 5828 * Generic 32-bit "/2addr" floating-point operation. 5829 * 5830 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 5831 * form: <op> f0, f0, f1 5832 */ 5833 /* binop/2addr vA, vB */ 5834 ext a2, rINST, 8, 4 # a2 <- A 5835 ext a3, rINST, 12, 4 # a3 <- B 5836 GET_VREG_FLOAT f0, a2 # f0 <- vA 5837 GET_VREG_FLOAT f1, a3 # f1 <- vB 5838 sub.s f0, f0, f1 # f0 <- f0 op f1 5839 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5840 GET_INST_OPCODE v0 # extract opcode from rINST 5841 SET_VREG_FLOAT f0, a2 # vA <- f0 5842 GOTO_OPCODE v0 # jump to next instruction 5843 5844 5845/* ------------------------------ */ 5846 .balign 128 5847.L_op_mul_float_2addr: /* 0xc8 */ 5848/* File: mips64/op_mul_float_2addr.S */ 5849/* File: mips64/fbinop2addr.S */ 5850 /*: 5851 * Generic 32-bit "/2addr" floating-point operation. 5852 * 5853 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 5854 * form: <op> f0, f0, f1 5855 */ 5856 /* binop/2addr vA, vB */ 5857 ext a2, rINST, 8, 4 # a2 <- A 5858 ext a3, rINST, 12, 4 # a3 <- B 5859 GET_VREG_FLOAT f0, a2 # f0 <- vA 5860 GET_VREG_FLOAT f1, a3 # f1 <- vB 5861 mul.s f0, f0, f1 # f0 <- f0 op f1 5862 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5863 GET_INST_OPCODE v0 # extract opcode from rINST 5864 SET_VREG_FLOAT f0, a2 # vA <- f0 5865 GOTO_OPCODE v0 # jump to next instruction 5866 5867 5868/* ------------------------------ */ 5869 .balign 128 5870.L_op_div_float_2addr: /* 0xc9 */ 5871/* File: mips64/op_div_float_2addr.S */ 5872/* File: mips64/fbinop2addr.S */ 5873 /*: 5874 * Generic 32-bit "/2addr" floating-point operation. 5875 * 5876 * For: add-float/2addr, sub-float/2addr, mul-float/2addr, div-float/2addr. 5877 * form: <op> f0, f0, f1 5878 */ 5879 /* binop/2addr vA, vB */ 5880 ext a2, rINST, 8, 4 # a2 <- A 5881 ext a3, rINST, 12, 4 # a3 <- B 5882 GET_VREG_FLOAT f0, a2 # f0 <- vA 5883 GET_VREG_FLOAT f1, a3 # f1 <- vB 5884 div.s f0, f0, f1 # f0 <- f0 op f1 5885 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5886 GET_INST_OPCODE v0 # extract opcode from rINST 5887 SET_VREG_FLOAT f0, a2 # vA <- f0 5888 GOTO_OPCODE v0 # jump to next instruction 5889 5890 5891/* ------------------------------ */ 5892 .balign 128 5893.L_op_rem_float_2addr: /* 0xca */ 5894/* File: mips64/op_rem_float_2addr.S */ 5895 /* rem-float/2addr vA, vB */ 5896 .extern fmodf 5897 ext a2, rINST, 8, 4 # a2 <- A 5898 ext a3, rINST, 12, 4 # a3 <- B 5899 GET_VREG_FLOAT f12, a2 # f12 <- vA 5900 GET_VREG_FLOAT f13, a3 # f13 <- vB 5901 jal fmodf # f0 <- f12 op f13 5902 ext a2, rINST, 8, 4 # a2 <- A 5903 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5904 GET_INST_OPCODE v0 # extract opcode from rINST 5905 SET_VREG_FLOAT f0, a2 # vA <- f0 5906 GOTO_OPCODE v0 # jump to next instruction 5907 5908/* ------------------------------ */ 5909 .balign 128 5910.L_op_add_double_2addr: /* 0xcb */ 5911/* File: mips64/op_add_double_2addr.S */ 5912/* File: mips64/fbinopWide2addr.S */ 5913 /*: 5914 * Generic 64-bit "/2addr" floating-point operation. 5915 * 5916 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 5917 * form: <op> f0, f0, f1 5918 */ 5919 /* binop/2addr vA, vB */ 5920 ext a2, rINST, 8, 4 # a2 <- A 5921 ext a3, rINST, 12, 4 # a3 <- B 5922 GET_VREG_DOUBLE f0, a2 # f0 <- vA 5923 GET_VREG_DOUBLE f1, a3 # f1 <- vB 5924 add.d f0, f0, f1 # f0 <- f0 op f1 5925 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5926 GET_INST_OPCODE v0 # extract opcode from rINST 5927 SET_VREG_DOUBLE f0, a2 # vA <- f0 5928 GOTO_OPCODE v0 # jump to next instruction 5929 5930 5931/* ------------------------------ */ 5932 .balign 128 5933.L_op_sub_double_2addr: /* 0xcc */ 5934/* File: mips64/op_sub_double_2addr.S */ 5935/* File: mips64/fbinopWide2addr.S */ 5936 /*: 5937 * Generic 64-bit "/2addr" floating-point operation. 5938 * 5939 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 5940 * form: <op> f0, f0, f1 5941 */ 5942 /* binop/2addr vA, vB */ 5943 ext a2, rINST, 8, 4 # a2 <- A 5944 ext a3, rINST, 12, 4 # a3 <- B 5945 GET_VREG_DOUBLE f0, a2 # f0 <- vA 5946 GET_VREG_DOUBLE f1, a3 # f1 <- vB 5947 sub.d f0, f0, f1 # f0 <- f0 op f1 5948 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5949 GET_INST_OPCODE v0 # extract opcode from rINST 5950 SET_VREG_DOUBLE f0, a2 # vA <- f0 5951 GOTO_OPCODE v0 # jump to next instruction 5952 5953 5954/* ------------------------------ */ 5955 .balign 128 5956.L_op_mul_double_2addr: /* 0xcd */ 5957/* File: mips64/op_mul_double_2addr.S */ 5958/* File: mips64/fbinopWide2addr.S */ 5959 /*: 5960 * Generic 64-bit "/2addr" floating-point operation. 5961 * 5962 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 5963 * form: <op> f0, f0, f1 5964 */ 5965 /* binop/2addr vA, vB */ 5966 ext a2, rINST, 8, 4 # a2 <- A 5967 ext a3, rINST, 12, 4 # a3 <- B 5968 GET_VREG_DOUBLE f0, a2 # f0 <- vA 5969 GET_VREG_DOUBLE f1, a3 # f1 <- vB 5970 mul.d f0, f0, f1 # f0 <- f0 op f1 5971 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5972 GET_INST_OPCODE v0 # extract opcode from rINST 5973 SET_VREG_DOUBLE f0, a2 # vA <- f0 5974 GOTO_OPCODE v0 # jump to next instruction 5975 5976 5977/* ------------------------------ */ 5978 .balign 128 5979.L_op_div_double_2addr: /* 0xce */ 5980/* File: mips64/op_div_double_2addr.S */ 5981/* File: mips64/fbinopWide2addr.S */ 5982 /*: 5983 * Generic 64-bit "/2addr" floating-point operation. 5984 * 5985 * For: add-double/2addr, sub-double/2addr, mul-double/2addr, div-double/2addr. 5986 * form: <op> f0, f0, f1 5987 */ 5988 /* binop/2addr vA, vB */ 5989 ext a2, rINST, 8, 4 # a2 <- A 5990 ext a3, rINST, 12, 4 # a3 <- B 5991 GET_VREG_DOUBLE f0, a2 # f0 <- vA 5992 GET_VREG_DOUBLE f1, a3 # f1 <- vB 5993 div.d f0, f0, f1 # f0 <- f0 op f1 5994 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 5995 GET_INST_OPCODE v0 # extract opcode from rINST 5996 SET_VREG_DOUBLE f0, a2 # vA <- f0 5997 GOTO_OPCODE v0 # jump to next instruction 5998 5999 6000/* ------------------------------ */ 6001 .balign 128 6002.L_op_rem_double_2addr: /* 0xcf */ 6003/* File: mips64/op_rem_double_2addr.S */ 6004 /* rem-double/2addr vA, vB */ 6005 .extern fmod 6006 ext a2, rINST, 8, 4 # a2 <- A 6007 ext a3, rINST, 12, 4 # a3 <- B 6008 GET_VREG_DOUBLE f12, a2 # f12 <- vA 6009 GET_VREG_DOUBLE f13, a3 # f13 <- vB 6010 jal fmod # f0 <- f12 op f13 6011 ext a2, rINST, 8, 4 # a2 <- A 6012 FETCH_ADVANCE_INST 1 # advance rPC, load rINST 6013 GET_INST_OPCODE v0 # extract opcode from rINST 6014 SET_VREG_DOUBLE f0, a2 # vA <- f0 6015 GOTO_OPCODE v0 # jump to next instruction 6016 6017/* ------------------------------ */ 6018 .balign 128 6019.L_op_add_int_lit16: /* 0xd0 */ 6020/* File: mips64/op_add_int_lit16.S */ 6021/* File: mips64/binopLit16.S */ 6022 /* 6023 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6024 * that specifies an instruction that performs "result = a0 op a1". 6025 * This could be an MIPS instruction or a function call. (If the result 6026 * comes back in a register other than a0, you can override "result".) 6027 * 6028 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6029 * CCCC (a1). Useful for integer division and modulus. 6030 * 6031 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6032 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6033 */ 6034 /* binop/lit16 vA, vB, #+CCCC */ 6035 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6036 ext a2, rINST, 8, 4 # a2 <- A 6037 ext a3, rINST, 12, 4 # a3 <- B 6038 GET_VREG a0, a3 # a0 <- vB 6039 .if 0 6040 beqz a1, common_errDivideByZero # is second operand zero? 6041 .endif 6042 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6043 # optional op 6044 addu a0, a0, a1 # a0 <- op, a0-a3 changed 6045 GET_INST_OPCODE v0 # extract opcode from rINST 6046 SET_VREG a0, a2 # vA <- a0 6047 GOTO_OPCODE v0 # jump to next instruction 6048 6049 6050 6051/* ------------------------------ */ 6052 .balign 128 6053.L_op_rsub_int: /* 0xd1 */ 6054/* File: mips64/op_rsub_int.S */ 6055/* File: mips64/binopLit16.S */ 6056 /* 6057 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6058 * that specifies an instruction that performs "result = a0 op a1". 6059 * This could be an MIPS instruction or a function call. (If the result 6060 * comes back in a register other than a0, you can override "result".) 6061 * 6062 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6063 * CCCC (a1). Useful for integer division and modulus. 6064 * 6065 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6066 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6067 */ 6068 /* binop/lit16 vA, vB, #+CCCC */ 6069 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6070 ext a2, rINST, 8, 4 # a2 <- A 6071 ext a3, rINST, 12, 4 # a3 <- B 6072 GET_VREG a0, a3 # a0 <- vB 6073 .if 0 6074 beqz a1, common_errDivideByZero # is second operand zero? 6075 .endif 6076 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6077 # optional op 6078 subu a0, a1, a0 # a0 <- op, a0-a3 changed 6079 GET_INST_OPCODE v0 # extract opcode from rINST 6080 SET_VREG a0, a2 # vA <- a0 6081 GOTO_OPCODE v0 # jump to next instruction 6082 6083 6084 6085/* ------------------------------ */ 6086 .balign 128 6087.L_op_mul_int_lit16: /* 0xd2 */ 6088/* File: mips64/op_mul_int_lit16.S */ 6089/* File: mips64/binopLit16.S */ 6090 /* 6091 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6092 * that specifies an instruction that performs "result = a0 op a1". 6093 * This could be an MIPS instruction or a function call. (If the result 6094 * comes back in a register other than a0, you can override "result".) 6095 * 6096 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6097 * CCCC (a1). Useful for integer division and modulus. 6098 * 6099 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6100 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6101 */ 6102 /* binop/lit16 vA, vB, #+CCCC */ 6103 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6104 ext a2, rINST, 8, 4 # a2 <- A 6105 ext a3, rINST, 12, 4 # a3 <- B 6106 GET_VREG a0, a3 # a0 <- vB 6107 .if 0 6108 beqz a1, common_errDivideByZero # is second operand zero? 6109 .endif 6110 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6111 # optional op 6112 mul a0, a0, a1 # a0 <- op, a0-a3 changed 6113 GET_INST_OPCODE v0 # extract opcode from rINST 6114 SET_VREG a0, a2 # vA <- a0 6115 GOTO_OPCODE v0 # jump to next instruction 6116 6117 6118 6119/* ------------------------------ */ 6120 .balign 128 6121.L_op_div_int_lit16: /* 0xd3 */ 6122/* File: mips64/op_div_int_lit16.S */ 6123/* File: mips64/binopLit16.S */ 6124 /* 6125 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6126 * that specifies an instruction that performs "result = a0 op a1". 6127 * This could be an MIPS instruction or a function call. (If the result 6128 * comes back in a register other than a0, you can override "result".) 6129 * 6130 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6131 * CCCC (a1). Useful for integer division and modulus. 6132 * 6133 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6134 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6135 */ 6136 /* binop/lit16 vA, vB, #+CCCC */ 6137 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6138 ext a2, rINST, 8, 4 # a2 <- A 6139 ext a3, rINST, 12, 4 # a3 <- B 6140 GET_VREG a0, a3 # a0 <- vB 6141 .if 1 6142 beqz a1, common_errDivideByZero # is second operand zero? 6143 .endif 6144 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6145 # optional op 6146 div a0, a0, a1 # a0 <- op, a0-a3 changed 6147 GET_INST_OPCODE v0 # extract opcode from rINST 6148 SET_VREG a0, a2 # vA <- a0 6149 GOTO_OPCODE v0 # jump to next instruction 6150 6151 6152 6153/* ------------------------------ */ 6154 .balign 128 6155.L_op_rem_int_lit16: /* 0xd4 */ 6156/* File: mips64/op_rem_int_lit16.S */ 6157/* File: mips64/binopLit16.S */ 6158 /* 6159 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6160 * that specifies an instruction that performs "result = a0 op a1". 6161 * This could be an MIPS instruction or a function call. (If the result 6162 * comes back in a register other than a0, you can override "result".) 6163 * 6164 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6165 * CCCC (a1). Useful for integer division and modulus. 6166 * 6167 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6168 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6169 */ 6170 /* binop/lit16 vA, vB, #+CCCC */ 6171 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6172 ext a2, rINST, 8, 4 # a2 <- A 6173 ext a3, rINST, 12, 4 # a3 <- B 6174 GET_VREG a0, a3 # a0 <- vB 6175 .if 1 6176 beqz a1, common_errDivideByZero # is second operand zero? 6177 .endif 6178 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6179 # optional op 6180 mod a0, a0, a1 # a0 <- op, a0-a3 changed 6181 GET_INST_OPCODE v0 # extract opcode from rINST 6182 SET_VREG a0, a2 # vA <- a0 6183 GOTO_OPCODE v0 # jump to next instruction 6184 6185 6186 6187/* ------------------------------ */ 6188 .balign 128 6189.L_op_and_int_lit16: /* 0xd5 */ 6190/* File: mips64/op_and_int_lit16.S */ 6191/* File: mips64/binopLit16.S */ 6192 /* 6193 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6194 * that specifies an instruction that performs "result = a0 op a1". 6195 * This could be an MIPS instruction or a function call. (If the result 6196 * comes back in a register other than a0, you can override "result".) 6197 * 6198 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6199 * CCCC (a1). Useful for integer division and modulus. 6200 * 6201 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6202 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6203 */ 6204 /* binop/lit16 vA, vB, #+CCCC */ 6205 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6206 ext a2, rINST, 8, 4 # a2 <- A 6207 ext a3, rINST, 12, 4 # a3 <- B 6208 GET_VREG a0, a3 # a0 <- vB 6209 .if 0 6210 beqz a1, common_errDivideByZero # is second operand zero? 6211 .endif 6212 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6213 # optional op 6214 and a0, a0, a1 # a0 <- op, a0-a3 changed 6215 GET_INST_OPCODE v0 # extract opcode from rINST 6216 SET_VREG a0, a2 # vA <- a0 6217 GOTO_OPCODE v0 # jump to next instruction 6218 6219 6220 6221/* ------------------------------ */ 6222 .balign 128 6223.L_op_or_int_lit16: /* 0xd6 */ 6224/* File: mips64/op_or_int_lit16.S */ 6225/* File: mips64/binopLit16.S */ 6226 /* 6227 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6228 * that specifies an instruction that performs "result = a0 op a1". 6229 * This could be an MIPS instruction or a function call. (If the result 6230 * comes back in a register other than a0, you can override "result".) 6231 * 6232 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6233 * CCCC (a1). Useful for integer division and modulus. 6234 * 6235 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6236 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6237 */ 6238 /* binop/lit16 vA, vB, #+CCCC */ 6239 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6240 ext a2, rINST, 8, 4 # a2 <- A 6241 ext a3, rINST, 12, 4 # a3 <- B 6242 GET_VREG a0, a3 # a0 <- vB 6243 .if 0 6244 beqz a1, common_errDivideByZero # is second operand zero? 6245 .endif 6246 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6247 # optional op 6248 or a0, a0, a1 # a0 <- op, a0-a3 changed 6249 GET_INST_OPCODE v0 # extract opcode from rINST 6250 SET_VREG a0, a2 # vA <- a0 6251 GOTO_OPCODE v0 # jump to next instruction 6252 6253 6254 6255/* ------------------------------ */ 6256 .balign 128 6257.L_op_xor_int_lit16: /* 0xd7 */ 6258/* File: mips64/op_xor_int_lit16.S */ 6259/* File: mips64/binopLit16.S */ 6260 /* 6261 * Generic 32-bit "lit16" binary operation. Provide an "instr" line 6262 * that specifies an instruction that performs "result = a0 op a1". 6263 * This could be an MIPS instruction or a function call. (If the result 6264 * comes back in a register other than a0, you can override "result".) 6265 * 6266 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6267 * CCCC (a1). Useful for integer division and modulus. 6268 * 6269 * For: add-int/lit16, rsub-int, mul-int/lit16, div-int/lit16, 6270 * rem-int/lit16, and-int/lit16, or-int/lit16, xor-int/lit16 6271 */ 6272 /* binop/lit16 vA, vB, #+CCCC */ 6273 lh a1, 2(rPC) # a1 <- sign-extended CCCC 6274 ext a2, rINST, 8, 4 # a2 <- A 6275 ext a3, rINST, 12, 4 # a3 <- B 6276 GET_VREG a0, a3 # a0 <- vB 6277 .if 0 6278 beqz a1, common_errDivideByZero # is second operand zero? 6279 .endif 6280 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6281 # optional op 6282 xor a0, a0, a1 # a0 <- op, a0-a3 changed 6283 GET_INST_OPCODE v0 # extract opcode from rINST 6284 SET_VREG a0, a2 # vA <- a0 6285 GOTO_OPCODE v0 # jump to next instruction 6286 6287 6288 6289/* ------------------------------ */ 6290 .balign 128 6291.L_op_add_int_lit8: /* 0xd8 */ 6292/* File: mips64/op_add_int_lit8.S */ 6293/* File: mips64/binopLit8.S */ 6294 /* 6295 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6296 * that specifies an instruction that performs "result = a0 op a1". 6297 * This could be an MIPS instruction or a function call. (If the result 6298 * comes back in a register other than a0, you can override "result".) 6299 * 6300 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6301 * CC (a1). Useful for integer division and modulus. 6302 * 6303 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6304 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6305 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6306 */ 6307 /* binop/lit8 vAA, vBB, #+CC */ 6308 lbu a3, 2(rPC) # a3 <- BB 6309 lb a1, 3(rPC) # a1 <- sign-extended CC 6310 srl a2, rINST, 8 # a2 <- AA 6311 GET_VREG a0, a3 # a0 <- vBB 6312 .if 0 6313 beqz a1, common_errDivideByZero # is second operand zero? 6314 .endif 6315 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6316 # optional op 6317 addu a0, a0, a1 # a0 <- op, a0-a3 changed 6318 GET_INST_OPCODE v0 # extract opcode from rINST 6319 SET_VREG a0, a2 # vAA <- a0 6320 GOTO_OPCODE v0 # jump to next instruction 6321 6322 6323 6324/* ------------------------------ */ 6325 .balign 128 6326.L_op_rsub_int_lit8: /* 0xd9 */ 6327/* File: mips64/op_rsub_int_lit8.S */ 6328/* File: mips64/binopLit8.S */ 6329 /* 6330 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6331 * that specifies an instruction that performs "result = a0 op a1". 6332 * This could be an MIPS instruction or a function call. (If the result 6333 * comes back in a register other than a0, you can override "result".) 6334 * 6335 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6336 * CC (a1). Useful for integer division and modulus. 6337 * 6338 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6339 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6340 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6341 */ 6342 /* binop/lit8 vAA, vBB, #+CC */ 6343 lbu a3, 2(rPC) # a3 <- BB 6344 lb a1, 3(rPC) # a1 <- sign-extended CC 6345 srl a2, rINST, 8 # a2 <- AA 6346 GET_VREG a0, a3 # a0 <- vBB 6347 .if 0 6348 beqz a1, common_errDivideByZero # is second operand zero? 6349 .endif 6350 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6351 # optional op 6352 subu a0, a1, a0 # a0 <- op, a0-a3 changed 6353 GET_INST_OPCODE v0 # extract opcode from rINST 6354 SET_VREG a0, a2 # vAA <- a0 6355 GOTO_OPCODE v0 # jump to next instruction 6356 6357 6358 6359/* ------------------------------ */ 6360 .balign 128 6361.L_op_mul_int_lit8: /* 0xda */ 6362/* File: mips64/op_mul_int_lit8.S */ 6363/* File: mips64/binopLit8.S */ 6364 /* 6365 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6366 * that specifies an instruction that performs "result = a0 op a1". 6367 * This could be an MIPS instruction or a function call. (If the result 6368 * comes back in a register other than a0, you can override "result".) 6369 * 6370 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6371 * CC (a1). Useful for integer division and modulus. 6372 * 6373 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6374 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6375 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6376 */ 6377 /* binop/lit8 vAA, vBB, #+CC */ 6378 lbu a3, 2(rPC) # a3 <- BB 6379 lb a1, 3(rPC) # a1 <- sign-extended CC 6380 srl a2, rINST, 8 # a2 <- AA 6381 GET_VREG a0, a3 # a0 <- vBB 6382 .if 0 6383 beqz a1, common_errDivideByZero # is second operand zero? 6384 .endif 6385 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6386 # optional op 6387 mul a0, a0, a1 # a0 <- op, a0-a3 changed 6388 GET_INST_OPCODE v0 # extract opcode from rINST 6389 SET_VREG a0, a2 # vAA <- a0 6390 GOTO_OPCODE v0 # jump to next instruction 6391 6392 6393 6394/* ------------------------------ */ 6395 .balign 128 6396.L_op_div_int_lit8: /* 0xdb */ 6397/* File: mips64/op_div_int_lit8.S */ 6398/* File: mips64/binopLit8.S */ 6399 /* 6400 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6401 * that specifies an instruction that performs "result = a0 op a1". 6402 * This could be an MIPS instruction or a function call. (If the result 6403 * comes back in a register other than a0, you can override "result".) 6404 * 6405 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6406 * CC (a1). Useful for integer division and modulus. 6407 * 6408 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6409 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6410 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6411 */ 6412 /* binop/lit8 vAA, vBB, #+CC */ 6413 lbu a3, 2(rPC) # a3 <- BB 6414 lb a1, 3(rPC) # a1 <- sign-extended CC 6415 srl a2, rINST, 8 # a2 <- AA 6416 GET_VREG a0, a3 # a0 <- vBB 6417 .if 1 6418 beqz a1, common_errDivideByZero # is second operand zero? 6419 .endif 6420 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6421 # optional op 6422 div a0, a0, a1 # a0 <- op, a0-a3 changed 6423 GET_INST_OPCODE v0 # extract opcode from rINST 6424 SET_VREG a0, a2 # vAA <- a0 6425 GOTO_OPCODE v0 # jump to next instruction 6426 6427 6428 6429/* ------------------------------ */ 6430 .balign 128 6431.L_op_rem_int_lit8: /* 0xdc */ 6432/* File: mips64/op_rem_int_lit8.S */ 6433/* File: mips64/binopLit8.S */ 6434 /* 6435 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6436 * that specifies an instruction that performs "result = a0 op a1". 6437 * This could be an MIPS instruction or a function call. (If the result 6438 * comes back in a register other than a0, you can override "result".) 6439 * 6440 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6441 * CC (a1). Useful for integer division and modulus. 6442 * 6443 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6444 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6445 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6446 */ 6447 /* binop/lit8 vAA, vBB, #+CC */ 6448 lbu a3, 2(rPC) # a3 <- BB 6449 lb a1, 3(rPC) # a1 <- sign-extended CC 6450 srl a2, rINST, 8 # a2 <- AA 6451 GET_VREG a0, a3 # a0 <- vBB 6452 .if 1 6453 beqz a1, common_errDivideByZero # is second operand zero? 6454 .endif 6455 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6456 # optional op 6457 mod a0, a0, a1 # a0 <- op, a0-a3 changed 6458 GET_INST_OPCODE v0 # extract opcode from rINST 6459 SET_VREG a0, a2 # vAA <- a0 6460 GOTO_OPCODE v0 # jump to next instruction 6461 6462 6463 6464/* ------------------------------ */ 6465 .balign 128 6466.L_op_and_int_lit8: /* 0xdd */ 6467/* File: mips64/op_and_int_lit8.S */ 6468/* File: mips64/binopLit8.S */ 6469 /* 6470 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6471 * that specifies an instruction that performs "result = a0 op a1". 6472 * This could be an MIPS instruction or a function call. (If the result 6473 * comes back in a register other than a0, you can override "result".) 6474 * 6475 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6476 * CC (a1). Useful for integer division and modulus. 6477 * 6478 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6479 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6480 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6481 */ 6482 /* binop/lit8 vAA, vBB, #+CC */ 6483 lbu a3, 2(rPC) # a3 <- BB 6484 lb a1, 3(rPC) # a1 <- sign-extended CC 6485 srl a2, rINST, 8 # a2 <- AA 6486 GET_VREG a0, a3 # a0 <- vBB 6487 .if 0 6488 beqz a1, common_errDivideByZero # is second operand zero? 6489 .endif 6490 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6491 # optional op 6492 and a0, a0, a1 # a0 <- op, a0-a3 changed 6493 GET_INST_OPCODE v0 # extract opcode from rINST 6494 SET_VREG a0, a2 # vAA <- a0 6495 GOTO_OPCODE v0 # jump to next instruction 6496 6497 6498 6499/* ------------------------------ */ 6500 .balign 128 6501.L_op_or_int_lit8: /* 0xde */ 6502/* File: mips64/op_or_int_lit8.S */ 6503/* File: mips64/binopLit8.S */ 6504 /* 6505 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6506 * that specifies an instruction that performs "result = a0 op a1". 6507 * This could be an MIPS instruction or a function call. (If the result 6508 * comes back in a register other than a0, you can override "result".) 6509 * 6510 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6511 * CC (a1). Useful for integer division and modulus. 6512 * 6513 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6514 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6515 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6516 */ 6517 /* binop/lit8 vAA, vBB, #+CC */ 6518 lbu a3, 2(rPC) # a3 <- BB 6519 lb a1, 3(rPC) # a1 <- sign-extended CC 6520 srl a2, rINST, 8 # a2 <- AA 6521 GET_VREG a0, a3 # a0 <- vBB 6522 .if 0 6523 beqz a1, common_errDivideByZero # is second operand zero? 6524 .endif 6525 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6526 # optional op 6527 or a0, a0, a1 # a0 <- op, a0-a3 changed 6528 GET_INST_OPCODE v0 # extract opcode from rINST 6529 SET_VREG a0, a2 # vAA <- a0 6530 GOTO_OPCODE v0 # jump to next instruction 6531 6532 6533 6534/* ------------------------------ */ 6535 .balign 128 6536.L_op_xor_int_lit8: /* 0xdf */ 6537/* File: mips64/op_xor_int_lit8.S */ 6538/* File: mips64/binopLit8.S */ 6539 /* 6540 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6541 * that specifies an instruction that performs "result = a0 op a1". 6542 * This could be an MIPS instruction or a function call. (If the result 6543 * comes back in a register other than a0, you can override "result".) 6544 * 6545 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6546 * CC (a1). Useful for integer division and modulus. 6547 * 6548 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6549 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6550 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6551 */ 6552 /* binop/lit8 vAA, vBB, #+CC */ 6553 lbu a3, 2(rPC) # a3 <- BB 6554 lb a1, 3(rPC) # a1 <- sign-extended CC 6555 srl a2, rINST, 8 # a2 <- AA 6556 GET_VREG a0, a3 # a0 <- vBB 6557 .if 0 6558 beqz a1, common_errDivideByZero # is second operand zero? 6559 .endif 6560 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6561 # optional op 6562 xor a0, a0, a1 # a0 <- op, a0-a3 changed 6563 GET_INST_OPCODE v0 # extract opcode from rINST 6564 SET_VREG a0, a2 # vAA <- a0 6565 GOTO_OPCODE v0 # jump to next instruction 6566 6567 6568 6569/* ------------------------------ */ 6570 .balign 128 6571.L_op_shl_int_lit8: /* 0xe0 */ 6572/* File: mips64/op_shl_int_lit8.S */ 6573/* File: mips64/binopLit8.S */ 6574 /* 6575 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6576 * that specifies an instruction that performs "result = a0 op a1". 6577 * This could be an MIPS instruction or a function call. (If the result 6578 * comes back in a register other than a0, you can override "result".) 6579 * 6580 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6581 * CC (a1). Useful for integer division and modulus. 6582 * 6583 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6584 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6585 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6586 */ 6587 /* binop/lit8 vAA, vBB, #+CC */ 6588 lbu a3, 2(rPC) # a3 <- BB 6589 lb a1, 3(rPC) # a1 <- sign-extended CC 6590 srl a2, rINST, 8 # a2 <- AA 6591 GET_VREG a0, a3 # a0 <- vBB 6592 .if 0 6593 beqz a1, common_errDivideByZero # is second operand zero? 6594 .endif 6595 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6596 # optional op 6597 sll a0, a0, a1 # a0 <- op, a0-a3 changed 6598 GET_INST_OPCODE v0 # extract opcode from rINST 6599 SET_VREG a0, a2 # vAA <- a0 6600 GOTO_OPCODE v0 # jump to next instruction 6601 6602 6603 6604/* ------------------------------ */ 6605 .balign 128 6606.L_op_shr_int_lit8: /* 0xe1 */ 6607/* File: mips64/op_shr_int_lit8.S */ 6608/* File: mips64/binopLit8.S */ 6609 /* 6610 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6611 * that specifies an instruction that performs "result = a0 op a1". 6612 * This could be an MIPS instruction or a function call. (If the result 6613 * comes back in a register other than a0, you can override "result".) 6614 * 6615 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6616 * CC (a1). Useful for integer division and modulus. 6617 * 6618 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6619 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6620 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6621 */ 6622 /* binop/lit8 vAA, vBB, #+CC */ 6623 lbu a3, 2(rPC) # a3 <- BB 6624 lb a1, 3(rPC) # a1 <- sign-extended CC 6625 srl a2, rINST, 8 # a2 <- AA 6626 GET_VREG a0, a3 # a0 <- vBB 6627 .if 0 6628 beqz a1, common_errDivideByZero # is second operand zero? 6629 .endif 6630 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6631 # optional op 6632 sra a0, a0, a1 # a0 <- op, a0-a3 changed 6633 GET_INST_OPCODE v0 # extract opcode from rINST 6634 SET_VREG a0, a2 # vAA <- a0 6635 GOTO_OPCODE v0 # jump to next instruction 6636 6637 6638 6639/* ------------------------------ */ 6640 .balign 128 6641.L_op_ushr_int_lit8: /* 0xe2 */ 6642/* File: mips64/op_ushr_int_lit8.S */ 6643/* File: mips64/binopLit8.S */ 6644 /* 6645 * Generic 32-bit "lit8" binary operation. Provide an "instr" line 6646 * that specifies an instruction that performs "result = a0 op a1". 6647 * This could be an MIPS instruction or a function call. (If the result 6648 * comes back in a register other than a0, you can override "result".) 6649 * 6650 * If "chkzero" is set to 1, we perform a divide-by-zero check on 6651 * CC (a1). Useful for integer division and modulus. 6652 * 6653 * For: add-int/lit8, rsub-int/lit8, mul-int/lit8, div-int/lit8, 6654 * rem-int/lit8, and-int/lit8, or-int/lit8, xor-int/lit8, 6655 * shl-int/lit8, shr-int/lit8, ushr-int/lit8 6656 */ 6657 /* binop/lit8 vAA, vBB, #+CC */ 6658 lbu a3, 2(rPC) # a3 <- BB 6659 lb a1, 3(rPC) # a1 <- sign-extended CC 6660 srl a2, rINST, 8 # a2 <- AA 6661 GET_VREG a0, a3 # a0 <- vBB 6662 .if 0 6663 beqz a1, common_errDivideByZero # is second operand zero? 6664 .endif 6665 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6666 # optional op 6667 srl a0, a0, a1 # a0 <- op, a0-a3 changed 6668 GET_INST_OPCODE v0 # extract opcode from rINST 6669 SET_VREG a0, a2 # vAA <- a0 6670 GOTO_OPCODE v0 # jump to next instruction 6671 6672 6673 6674/* ------------------------------ */ 6675 .balign 128 6676.L_op_iget_quick: /* 0xe3 */ 6677/* File: mips64/op_iget_quick.S */ 6678 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6679 /* op vA, vB, offset//CCCC */ 6680 srl a2, rINST, 12 # a2 <- B 6681 lhu a1, 2(rPC) # a1 <- field byte offset 6682 GET_VREG_U a3, a2 # a3 <- object we're operating on 6683 ext a4, rINST, 8, 4 # a4 <- A 6684 daddu a1, a1, a3 6685 beqz a3, common_errNullObject # object was null 6686 lw a0, 0(a1) # a0 <- obj.field 6687 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6688 SET_VREG a0, a4 # fp[A] <- a0 6689 GET_INST_OPCODE v0 # extract opcode from rINST 6690 GOTO_OPCODE v0 # jump to next instruction 6691 6692/* ------------------------------ */ 6693 .balign 128 6694.L_op_iget_wide_quick: /* 0xe4 */ 6695/* File: mips64/op_iget_wide_quick.S */ 6696 /* iget-wide-quick vA, vB, offset//CCCC */ 6697 srl a2, rINST, 12 # a2 <- B 6698 lhu a4, 2(rPC) # a4 <- field byte offset 6699 GET_VREG_U a3, a2 # a3 <- object we're operating on 6700 ext a2, rINST, 8, 4 # a2 <- A 6701 beqz a3, common_errNullObject # object was null 6702 daddu a4, a3, a4 # create direct pointer 6703 lw a0, 0(a4) 6704 lw a1, 4(a4) 6705 dinsu a0, a1, 32, 32 6706 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6707 SET_VREG_WIDE a0, a2 6708 GET_INST_OPCODE v0 # extract opcode from rINST 6709 GOTO_OPCODE v0 # jump to next instruction 6710 6711/* ------------------------------ */ 6712 .balign 128 6713.L_op_iget_object_quick: /* 0xe5 */ 6714/* File: mips64/op_iget_object_quick.S */ 6715 /* For: iget-object-quick */ 6716 /* op vA, vB, offset//CCCC */ 6717 .extern artIGetObjectFromMterp 6718 srl a2, rINST, 12 # a2 <- B 6719 lhu a1, 2(rPC) # a1 <- field byte offset 6720 EXPORT_PC 6721 GET_VREG_U a0, a2 # a0 <- object we're operating on 6722 jal artIGetObjectFromMterp # (obj, offset) 6723 ld a3, THREAD_EXCEPTION_OFFSET(rSELF) 6724 ext a2, rINST, 8, 4 # a2 <- A 6725 PREFETCH_INST 2 6726 bnez a3, MterpPossibleException # bail out 6727 SET_VREG_OBJECT v0, a2 # fp[A] <- v0 6728 ADVANCE 2 # advance rPC 6729 GET_INST_OPCODE v0 # extract opcode from rINST 6730 GOTO_OPCODE v0 # jump to next instruction 6731 6732/* ------------------------------ */ 6733 .balign 128 6734.L_op_iput_quick: /* 0xe6 */ 6735/* File: mips64/op_iput_quick.S */ 6736 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6737 /* op vA, vB, offset//CCCC */ 6738 srl a2, rINST, 12 # a2 <- B 6739 lhu a1, 2(rPC) # a1 <- field byte offset 6740 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6741 ext a2, rINST, 8, 4 # a2 <- A 6742 beqz a3, common_errNullObject # object was null 6743 GET_VREG a0, a2 # a0 <- fp[A] 6744 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6745 daddu a1, a1, a3 6746 sw a0, 0(a1) # obj.field <- a0 6747 GET_INST_OPCODE v0 # extract opcode from rINST 6748 GOTO_OPCODE v0 # jump to next instruction 6749 6750/* ------------------------------ */ 6751 .balign 128 6752.L_op_iput_wide_quick: /* 0xe7 */ 6753/* File: mips64/op_iput_wide_quick.S */ 6754 /* iput-wide-quick vA, vB, offset//CCCC */ 6755 srl a2, rINST, 12 # a2 <- B 6756 lhu a3, 2(rPC) # a3 <- field byte offset 6757 GET_VREG_U a2, a2 # a2 <- fp[B], the object pointer 6758 ext a0, rINST, 8, 4 # a0 <- A 6759 beqz a2, common_errNullObject # object was null 6760 GET_VREG_WIDE a0, a0 # a0 <- fp[A] 6761 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6762 daddu a1, a2, a3 # create a direct pointer 6763 sw a0, 0(a1) 6764 dsrl32 a0, a0, 0 6765 sw a0, 4(a1) 6766 GET_INST_OPCODE v0 # extract opcode from rINST 6767 GOTO_OPCODE v0 # jump to next instruction 6768 6769/* ------------------------------ */ 6770 .balign 128 6771.L_op_iput_object_quick: /* 0xe8 */ 6772/* File: mips64/op_iput_object_quick.S */ 6773 .extern MterpIputObjectQuick 6774 EXPORT_PC 6775 daddu a0, rFP, OFF_FP_SHADOWFRAME 6776 move a1, rPC 6777 move a2, rINST 6778 jal MterpIputObjectQuick 6779 beqzc v0, MterpException 6780 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6781 GET_INST_OPCODE v0 # extract opcode from rINST 6782 GOTO_OPCODE v0 # jump to next instruction 6783 6784/* ------------------------------ */ 6785 .balign 128 6786.L_op_invoke_virtual_quick: /* 0xe9 */ 6787/* File: mips64/op_invoke_virtual_quick.S */ 6788/* File: mips64/invoke.S */ 6789 /* 6790 * Generic invoke handler wrapper. 6791 */ 6792 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 6793 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 6794 .extern MterpInvokeVirtualQuick 6795 .extern MterpShouldSwitchInterpreters 6796 EXPORT_PC 6797 move a0, rSELF 6798 daddu a1, rFP, OFF_FP_SHADOWFRAME 6799 move a2, rPC 6800 move a3, rINST 6801 jal MterpInvokeVirtualQuick 6802 beqzc v0, MterpException 6803 FETCH_ADVANCE_INST 3 6804 jal MterpShouldSwitchInterpreters 6805 bnezc v0, MterpFallback 6806 GET_INST_OPCODE v0 6807 GOTO_OPCODE v0 6808 6809 6810/* ------------------------------ */ 6811 .balign 128 6812.L_op_invoke_virtual_range_quick: /* 0xea */ 6813/* File: mips64/op_invoke_virtual_range_quick.S */ 6814/* File: mips64/invoke.S */ 6815 /* 6816 * Generic invoke handler wrapper. 6817 */ 6818 /* op vB, {vD, vE, vF, vG, vA}, class@CCCC */ 6819 /* op {vCCCC..v(CCCC+AA-1)}, meth@BBBB */ 6820 .extern MterpInvokeVirtualQuickRange 6821 .extern MterpShouldSwitchInterpreters 6822 EXPORT_PC 6823 move a0, rSELF 6824 daddu a1, rFP, OFF_FP_SHADOWFRAME 6825 move a2, rPC 6826 move a3, rINST 6827 jal MterpInvokeVirtualQuickRange 6828 beqzc v0, MterpException 6829 FETCH_ADVANCE_INST 3 6830 jal MterpShouldSwitchInterpreters 6831 bnezc v0, MterpFallback 6832 GET_INST_OPCODE v0 6833 GOTO_OPCODE v0 6834 6835 6836/* ------------------------------ */ 6837 .balign 128 6838.L_op_iput_boolean_quick: /* 0xeb */ 6839/* File: mips64/op_iput_boolean_quick.S */ 6840/* File: mips64/op_iput_quick.S */ 6841 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6842 /* op vA, vB, offset//CCCC */ 6843 srl a2, rINST, 12 # a2 <- B 6844 lhu a1, 2(rPC) # a1 <- field byte offset 6845 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6846 ext a2, rINST, 8, 4 # a2 <- A 6847 beqz a3, common_errNullObject # object was null 6848 GET_VREG a0, a2 # a0 <- fp[A] 6849 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6850 daddu a1, a1, a3 6851 sb a0, 0(a1) # obj.field <- a0 6852 GET_INST_OPCODE v0 # extract opcode from rINST 6853 GOTO_OPCODE v0 # jump to next instruction 6854 6855 6856/* ------------------------------ */ 6857 .balign 128 6858.L_op_iput_byte_quick: /* 0xec */ 6859/* File: mips64/op_iput_byte_quick.S */ 6860/* File: mips64/op_iput_quick.S */ 6861 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6862 /* op vA, vB, offset//CCCC */ 6863 srl a2, rINST, 12 # a2 <- B 6864 lhu a1, 2(rPC) # a1 <- field byte offset 6865 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6866 ext a2, rINST, 8, 4 # a2 <- A 6867 beqz a3, common_errNullObject # object was null 6868 GET_VREG a0, a2 # a0 <- fp[A] 6869 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6870 daddu a1, a1, a3 6871 sb a0, 0(a1) # obj.field <- a0 6872 GET_INST_OPCODE v0 # extract opcode from rINST 6873 GOTO_OPCODE v0 # jump to next instruction 6874 6875 6876/* ------------------------------ */ 6877 .balign 128 6878.L_op_iput_char_quick: /* 0xed */ 6879/* File: mips64/op_iput_char_quick.S */ 6880/* File: mips64/op_iput_quick.S */ 6881 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6882 /* op vA, vB, offset//CCCC */ 6883 srl a2, rINST, 12 # a2 <- B 6884 lhu a1, 2(rPC) # a1 <- field byte offset 6885 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6886 ext a2, rINST, 8, 4 # a2 <- A 6887 beqz a3, common_errNullObject # object was null 6888 GET_VREG a0, a2 # a0 <- fp[A] 6889 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6890 daddu a1, a1, a3 6891 sh a0, 0(a1) # obj.field <- a0 6892 GET_INST_OPCODE v0 # extract opcode from rINST 6893 GOTO_OPCODE v0 # jump to next instruction 6894 6895 6896/* ------------------------------ */ 6897 .balign 128 6898.L_op_iput_short_quick: /* 0xee */ 6899/* File: mips64/op_iput_short_quick.S */ 6900/* File: mips64/op_iput_quick.S */ 6901 /* For: iput-quick, iput-boolean-quick, iput-byte-quick, iput-char-quick, iput-short-quick */ 6902 /* op vA, vB, offset//CCCC */ 6903 srl a2, rINST, 12 # a2 <- B 6904 lhu a1, 2(rPC) # a1 <- field byte offset 6905 GET_VREG_U a3, a2 # a3 <- fp[B], the object pointer 6906 ext a2, rINST, 8, 4 # a2 <- A 6907 beqz a3, common_errNullObject # object was null 6908 GET_VREG a0, a2 # a0 <- fp[A] 6909 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6910 daddu a1, a1, a3 6911 sh a0, 0(a1) # obj.field <- a0 6912 GET_INST_OPCODE v0 # extract opcode from rINST 6913 GOTO_OPCODE v0 # jump to next instruction 6914 6915 6916/* ------------------------------ */ 6917 .balign 128 6918.L_op_iget_boolean_quick: /* 0xef */ 6919/* File: mips64/op_iget_boolean_quick.S */ 6920/* File: mips64/op_iget_quick.S */ 6921 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6922 /* op vA, vB, offset//CCCC */ 6923 srl a2, rINST, 12 # a2 <- B 6924 lhu a1, 2(rPC) # a1 <- field byte offset 6925 GET_VREG_U a3, a2 # a3 <- object we're operating on 6926 ext a4, rINST, 8, 4 # a4 <- A 6927 daddu a1, a1, a3 6928 beqz a3, common_errNullObject # object was null 6929 lbu a0, 0(a1) # a0 <- obj.field 6930 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6931 SET_VREG a0, a4 # fp[A] <- a0 6932 GET_INST_OPCODE v0 # extract opcode from rINST 6933 GOTO_OPCODE v0 # jump to next instruction 6934 6935 6936/* ------------------------------ */ 6937 .balign 128 6938.L_op_iget_byte_quick: /* 0xf0 */ 6939/* File: mips64/op_iget_byte_quick.S */ 6940/* File: mips64/op_iget_quick.S */ 6941 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6942 /* op vA, vB, offset//CCCC */ 6943 srl a2, rINST, 12 # a2 <- B 6944 lhu a1, 2(rPC) # a1 <- field byte offset 6945 GET_VREG_U a3, a2 # a3 <- object we're operating on 6946 ext a4, rINST, 8, 4 # a4 <- A 6947 daddu a1, a1, a3 6948 beqz a3, common_errNullObject # object was null 6949 lb a0, 0(a1) # a0 <- obj.field 6950 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6951 SET_VREG a0, a4 # fp[A] <- a0 6952 GET_INST_OPCODE v0 # extract opcode from rINST 6953 GOTO_OPCODE v0 # jump to next instruction 6954 6955 6956/* ------------------------------ */ 6957 .balign 128 6958.L_op_iget_char_quick: /* 0xf1 */ 6959/* File: mips64/op_iget_char_quick.S */ 6960/* File: mips64/op_iget_quick.S */ 6961 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6962 /* op vA, vB, offset//CCCC */ 6963 srl a2, rINST, 12 # a2 <- B 6964 lhu a1, 2(rPC) # a1 <- field byte offset 6965 GET_VREG_U a3, a2 # a3 <- object we're operating on 6966 ext a4, rINST, 8, 4 # a4 <- A 6967 daddu a1, a1, a3 6968 beqz a3, common_errNullObject # object was null 6969 lhu a0, 0(a1) # a0 <- obj.field 6970 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6971 SET_VREG a0, a4 # fp[A] <- a0 6972 GET_INST_OPCODE v0 # extract opcode from rINST 6973 GOTO_OPCODE v0 # jump to next instruction 6974 6975 6976/* ------------------------------ */ 6977 .balign 128 6978.L_op_iget_short_quick: /* 0xf2 */ 6979/* File: mips64/op_iget_short_quick.S */ 6980/* File: mips64/op_iget_quick.S */ 6981 /* For: iget-quick, iget-boolean-quick, iget-byte-quick, iget-char-quick, iget-short-quick */ 6982 /* op vA, vB, offset//CCCC */ 6983 srl a2, rINST, 12 # a2 <- B 6984 lhu a1, 2(rPC) # a1 <- field byte offset 6985 GET_VREG_U a3, a2 # a3 <- object we're operating on 6986 ext a4, rINST, 8, 4 # a4 <- A 6987 daddu a1, a1, a3 6988 beqz a3, common_errNullObject # object was null 6989 lh a0, 0(a1) # a0 <- obj.field 6990 FETCH_ADVANCE_INST 2 # advance rPC, load rINST 6991 SET_VREG a0, a4 # fp[A] <- a0 6992 GET_INST_OPCODE v0 # extract opcode from rINST 6993 GOTO_OPCODE v0 # jump to next instruction 6994 6995 6996/* ------------------------------ */ 6997 .balign 128 6998.L_op_unused_f3: /* 0xf3 */ 6999/* File: mips64/op_unused_f3.S */ 7000/* File: mips64/unused.S */ 7001/* 7002 * Bail to reference interpreter to throw. 7003 */ 7004 b MterpFallback 7005 7006 7007/* ------------------------------ */ 7008 .balign 128 7009.L_op_unused_f4: /* 0xf4 */ 7010/* File: mips64/op_unused_f4.S */ 7011/* File: mips64/unused.S */ 7012/* 7013 * Bail to reference interpreter to throw. 7014 */ 7015 b MterpFallback 7016 7017 7018/* ------------------------------ */ 7019 .balign 128 7020.L_op_unused_f5: /* 0xf5 */ 7021/* File: mips64/op_unused_f5.S */ 7022/* File: mips64/unused.S */ 7023/* 7024 * Bail to reference interpreter to throw. 7025 */ 7026 b MterpFallback 7027 7028 7029/* ------------------------------ */ 7030 .balign 128 7031.L_op_unused_f6: /* 0xf6 */ 7032/* File: mips64/op_unused_f6.S */ 7033/* File: mips64/unused.S */ 7034/* 7035 * Bail to reference interpreter to throw. 7036 */ 7037 b MterpFallback 7038 7039 7040/* ------------------------------ */ 7041 .balign 128 7042.L_op_unused_f7: /* 0xf7 */ 7043/* File: mips64/op_unused_f7.S */ 7044/* File: mips64/unused.S */ 7045/* 7046 * Bail to reference interpreter to throw. 7047 */ 7048 b MterpFallback 7049 7050 7051/* ------------------------------ */ 7052 .balign 128 7053.L_op_unused_f8: /* 0xf8 */ 7054/* File: mips64/op_unused_f8.S */ 7055/* File: mips64/unused.S */ 7056/* 7057 * Bail to reference interpreter to throw. 7058 */ 7059 b MterpFallback 7060 7061 7062/* ------------------------------ */ 7063 .balign 128 7064.L_op_unused_f9: /* 0xf9 */ 7065/* File: mips64/op_unused_f9.S */ 7066/* File: mips64/unused.S */ 7067/* 7068 * Bail to reference interpreter to throw. 7069 */ 7070 b MterpFallback 7071 7072 7073/* ------------------------------ */ 7074 .balign 128 7075.L_op_invoke_polymorphic: /* 0xfa */ 7076/* Transfer stub to alternate interpreter */ 7077 b MterpFallback 7078 7079/* ------------------------------ */ 7080 .balign 128 7081.L_op_invoke_polymorphic_range: /* 0xfb */ 7082/* Transfer stub to alternate interpreter */ 7083 b MterpFallback 7084 7085/* ------------------------------ */ 7086 .balign 128 7087.L_op_invoke_custom: /* 0xfc */ 7088/* Transfer stub to alternate interpreter */ 7089 b MterpFallback 7090 7091/* ------------------------------ */ 7092 .balign 128 7093.L_op_invoke_custom_range: /* 0xfd */ 7094/* Transfer stub to alternate interpreter */ 7095 b MterpFallback 7096 7097/* ------------------------------ */ 7098 .balign 128 7099.L_op_unused_fe: /* 0xfe */ 7100/* File: mips64/op_unused_fe.S */ 7101/* File: mips64/unused.S */ 7102/* 7103 * Bail to reference interpreter to throw. 7104 */ 7105 b MterpFallback 7106 7107 7108/* ------------------------------ */ 7109 .balign 128 7110.L_op_unused_ff: /* 0xff */ 7111/* File: mips64/op_unused_ff.S */ 7112/* File: mips64/unused.S */ 7113/* 7114 * Bail to reference interpreter to throw. 7115 */ 7116 b MterpFallback 7117 7118 7119 .balign 128 7120 .size artMterpAsmInstructionStart, .-artMterpAsmInstructionStart 7121 .global artMterpAsmInstructionEnd 7122artMterpAsmInstructionEnd: 7123 7124/* 7125 * =========================================================================== 7126 * Sister implementations 7127 * =========================================================================== 7128 */ 7129 .global artMterpAsmSisterStart 7130 .type artMterpAsmSisterStart, %function 7131 .text 7132 .balign 4 7133artMterpAsmSisterStart: 7134 7135/* continuation for op_float_to_int */ 7136.Lop_float_to_int_trunc: 7137 trunc.w.s f0, f0 7138 mfc1 t0, f0 7139.Lop_float_to_int_done: 7140 /* Can't include fcvtFooter.S after break */ 7141 GET_INST_OPCODE v0 # extract opcode from rINST 7142 SET_VREG t0, a1 7143 GOTO_OPCODE v0 # jump to next instruction 7144 7145/* continuation for op_float_to_long */ 7146.Lop_float_to_long_trunc: 7147 trunc.l.s f0, f0 7148 dmfc1 t0, f0 7149.Lop_float_to_long_done: 7150 /* Can't include fcvtFooter.S after break */ 7151 GET_INST_OPCODE v0 # extract opcode from rINST 7152 SET_VREG_WIDE t0, a1 7153 GOTO_OPCODE v0 # jump to next instruction 7154 7155/* continuation for op_double_to_int */ 7156.Lop_double_to_int_trunc: 7157 trunc.w.d f0, f0 7158 mfc1 t0, f0 7159.Lop_double_to_int_done: 7160 /* Can't include fcvtFooter.S after break */ 7161 GET_INST_OPCODE v0 # extract opcode from rINST 7162 SET_VREG t0, a1 7163 GOTO_OPCODE v0 # jump to next instruction 7164 7165/* continuation for op_double_to_long */ 7166.Lop_double_to_long_trunc: 7167 trunc.l.d f0, f0 7168 dmfc1 t0, f0 7169.Lop_double_to_long_done: 7170 /* Can't include fcvtFooter.S after break */ 7171 GET_INST_OPCODE v0 # extract opcode from rINST 7172 SET_VREG_WIDE t0, a1 7173 GOTO_OPCODE v0 # jump to next instruction 7174 7175 .size artMterpAsmSisterStart, .-artMterpAsmSisterStart 7176 .global artMterpAsmSisterEnd 7177artMterpAsmSisterEnd: 7178 7179 7180 .global artMterpAsmAltInstructionStart 7181 .type artMterpAsmAltInstructionStart, %function 7182 .text 7183 7184artMterpAsmAltInstructionStart = .L_ALT_op_nop 7185/* ------------------------------ */ 7186 .balign 128 7187.L_ALT_op_nop: /* 0x00 */ 7188/* File: mips64/alt_stub.S */ 7189/* 7190 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7191 * any interesting requests and then jump to the real instruction 7192 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7193 */ 7194 .extern MterpCheckBefore 7195 REFRESH_IBASE 7196 dla ra, artMterpAsmInstructionStart 7197 dla t9, MterpCheckBefore 7198 move a0, rSELF 7199 daddu a1, rFP, OFF_FP_SHADOWFRAME 7200 move a2, rPC 7201 daddu ra, ra, (0 * 128) # Addr of primary handler. 7202 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7203 7204/* ------------------------------ */ 7205 .balign 128 7206.L_ALT_op_move: /* 0x01 */ 7207/* File: mips64/alt_stub.S */ 7208/* 7209 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7210 * any interesting requests and then jump to the real instruction 7211 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7212 */ 7213 .extern MterpCheckBefore 7214 REFRESH_IBASE 7215 dla ra, artMterpAsmInstructionStart 7216 dla t9, MterpCheckBefore 7217 move a0, rSELF 7218 daddu a1, rFP, OFF_FP_SHADOWFRAME 7219 move a2, rPC 7220 daddu ra, ra, (1 * 128) # Addr of primary handler. 7221 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7222 7223/* ------------------------------ */ 7224 .balign 128 7225.L_ALT_op_move_from16: /* 0x02 */ 7226/* File: mips64/alt_stub.S */ 7227/* 7228 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7229 * any interesting requests and then jump to the real instruction 7230 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7231 */ 7232 .extern MterpCheckBefore 7233 REFRESH_IBASE 7234 dla ra, artMterpAsmInstructionStart 7235 dla t9, MterpCheckBefore 7236 move a0, rSELF 7237 daddu a1, rFP, OFF_FP_SHADOWFRAME 7238 move a2, rPC 7239 daddu ra, ra, (2 * 128) # Addr of primary handler. 7240 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7241 7242/* ------------------------------ */ 7243 .balign 128 7244.L_ALT_op_move_16: /* 0x03 */ 7245/* File: mips64/alt_stub.S */ 7246/* 7247 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7248 * any interesting requests and then jump to the real instruction 7249 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7250 */ 7251 .extern MterpCheckBefore 7252 REFRESH_IBASE 7253 dla ra, artMterpAsmInstructionStart 7254 dla t9, MterpCheckBefore 7255 move a0, rSELF 7256 daddu a1, rFP, OFF_FP_SHADOWFRAME 7257 move a2, rPC 7258 daddu ra, ra, (3 * 128) # Addr of primary handler. 7259 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7260 7261/* ------------------------------ */ 7262 .balign 128 7263.L_ALT_op_move_wide: /* 0x04 */ 7264/* File: mips64/alt_stub.S */ 7265/* 7266 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7267 * any interesting requests and then jump to the real instruction 7268 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7269 */ 7270 .extern MterpCheckBefore 7271 REFRESH_IBASE 7272 dla ra, artMterpAsmInstructionStart 7273 dla t9, MterpCheckBefore 7274 move a0, rSELF 7275 daddu a1, rFP, OFF_FP_SHADOWFRAME 7276 move a2, rPC 7277 daddu ra, ra, (4 * 128) # Addr of primary handler. 7278 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7279 7280/* ------------------------------ */ 7281 .balign 128 7282.L_ALT_op_move_wide_from16: /* 0x05 */ 7283/* File: mips64/alt_stub.S */ 7284/* 7285 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7286 * any interesting requests and then jump to the real instruction 7287 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7288 */ 7289 .extern MterpCheckBefore 7290 REFRESH_IBASE 7291 dla ra, artMterpAsmInstructionStart 7292 dla t9, MterpCheckBefore 7293 move a0, rSELF 7294 daddu a1, rFP, OFF_FP_SHADOWFRAME 7295 move a2, rPC 7296 daddu ra, ra, (5 * 128) # Addr of primary handler. 7297 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7298 7299/* ------------------------------ */ 7300 .balign 128 7301.L_ALT_op_move_wide_16: /* 0x06 */ 7302/* File: mips64/alt_stub.S */ 7303/* 7304 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7305 * any interesting requests and then jump to the real instruction 7306 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7307 */ 7308 .extern MterpCheckBefore 7309 REFRESH_IBASE 7310 dla ra, artMterpAsmInstructionStart 7311 dla t9, MterpCheckBefore 7312 move a0, rSELF 7313 daddu a1, rFP, OFF_FP_SHADOWFRAME 7314 move a2, rPC 7315 daddu ra, ra, (6 * 128) # Addr of primary handler. 7316 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7317 7318/* ------------------------------ */ 7319 .balign 128 7320.L_ALT_op_move_object: /* 0x07 */ 7321/* File: mips64/alt_stub.S */ 7322/* 7323 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7324 * any interesting requests and then jump to the real instruction 7325 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7326 */ 7327 .extern MterpCheckBefore 7328 REFRESH_IBASE 7329 dla ra, artMterpAsmInstructionStart 7330 dla t9, MterpCheckBefore 7331 move a0, rSELF 7332 daddu a1, rFP, OFF_FP_SHADOWFRAME 7333 move a2, rPC 7334 daddu ra, ra, (7 * 128) # Addr of primary handler. 7335 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7336 7337/* ------------------------------ */ 7338 .balign 128 7339.L_ALT_op_move_object_from16: /* 0x08 */ 7340/* File: mips64/alt_stub.S */ 7341/* 7342 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7343 * any interesting requests and then jump to the real instruction 7344 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7345 */ 7346 .extern MterpCheckBefore 7347 REFRESH_IBASE 7348 dla ra, artMterpAsmInstructionStart 7349 dla t9, MterpCheckBefore 7350 move a0, rSELF 7351 daddu a1, rFP, OFF_FP_SHADOWFRAME 7352 move a2, rPC 7353 daddu ra, ra, (8 * 128) # Addr of primary handler. 7354 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7355 7356/* ------------------------------ */ 7357 .balign 128 7358.L_ALT_op_move_object_16: /* 0x09 */ 7359/* File: mips64/alt_stub.S */ 7360/* 7361 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7362 * any interesting requests and then jump to the real instruction 7363 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7364 */ 7365 .extern MterpCheckBefore 7366 REFRESH_IBASE 7367 dla ra, artMterpAsmInstructionStart 7368 dla t9, MterpCheckBefore 7369 move a0, rSELF 7370 daddu a1, rFP, OFF_FP_SHADOWFRAME 7371 move a2, rPC 7372 daddu ra, ra, (9 * 128) # Addr of primary handler. 7373 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7374 7375/* ------------------------------ */ 7376 .balign 128 7377.L_ALT_op_move_result: /* 0x0a */ 7378/* File: mips64/alt_stub.S */ 7379/* 7380 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7381 * any interesting requests and then jump to the real instruction 7382 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7383 */ 7384 .extern MterpCheckBefore 7385 REFRESH_IBASE 7386 dla ra, artMterpAsmInstructionStart 7387 dla t9, MterpCheckBefore 7388 move a0, rSELF 7389 daddu a1, rFP, OFF_FP_SHADOWFRAME 7390 move a2, rPC 7391 daddu ra, ra, (10 * 128) # Addr of primary handler. 7392 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7393 7394/* ------------------------------ */ 7395 .balign 128 7396.L_ALT_op_move_result_wide: /* 0x0b */ 7397/* File: mips64/alt_stub.S */ 7398/* 7399 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7400 * any interesting requests and then jump to the real instruction 7401 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7402 */ 7403 .extern MterpCheckBefore 7404 REFRESH_IBASE 7405 dla ra, artMterpAsmInstructionStart 7406 dla t9, MterpCheckBefore 7407 move a0, rSELF 7408 daddu a1, rFP, OFF_FP_SHADOWFRAME 7409 move a2, rPC 7410 daddu ra, ra, (11 * 128) # Addr of primary handler. 7411 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7412 7413/* ------------------------------ */ 7414 .balign 128 7415.L_ALT_op_move_result_object: /* 0x0c */ 7416/* File: mips64/alt_stub.S */ 7417/* 7418 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7419 * any interesting requests and then jump to the real instruction 7420 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7421 */ 7422 .extern MterpCheckBefore 7423 REFRESH_IBASE 7424 dla ra, artMterpAsmInstructionStart 7425 dla t9, MterpCheckBefore 7426 move a0, rSELF 7427 daddu a1, rFP, OFF_FP_SHADOWFRAME 7428 move a2, rPC 7429 daddu ra, ra, (12 * 128) # Addr of primary handler. 7430 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7431 7432/* ------------------------------ */ 7433 .balign 128 7434.L_ALT_op_move_exception: /* 0x0d */ 7435/* File: mips64/alt_stub.S */ 7436/* 7437 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7438 * any interesting requests and then jump to the real instruction 7439 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7440 */ 7441 .extern MterpCheckBefore 7442 REFRESH_IBASE 7443 dla ra, artMterpAsmInstructionStart 7444 dla t9, MterpCheckBefore 7445 move a0, rSELF 7446 daddu a1, rFP, OFF_FP_SHADOWFRAME 7447 move a2, rPC 7448 daddu ra, ra, (13 * 128) # Addr of primary handler. 7449 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7450 7451/* ------------------------------ */ 7452 .balign 128 7453.L_ALT_op_return_void: /* 0x0e */ 7454/* File: mips64/alt_stub.S */ 7455/* 7456 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7457 * any interesting requests and then jump to the real instruction 7458 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7459 */ 7460 .extern MterpCheckBefore 7461 REFRESH_IBASE 7462 dla ra, artMterpAsmInstructionStart 7463 dla t9, MterpCheckBefore 7464 move a0, rSELF 7465 daddu a1, rFP, OFF_FP_SHADOWFRAME 7466 move a2, rPC 7467 daddu ra, ra, (14 * 128) # Addr of primary handler. 7468 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7469 7470/* ------------------------------ */ 7471 .balign 128 7472.L_ALT_op_return: /* 0x0f */ 7473/* File: mips64/alt_stub.S */ 7474/* 7475 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7476 * any interesting requests and then jump to the real instruction 7477 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7478 */ 7479 .extern MterpCheckBefore 7480 REFRESH_IBASE 7481 dla ra, artMterpAsmInstructionStart 7482 dla t9, MterpCheckBefore 7483 move a0, rSELF 7484 daddu a1, rFP, OFF_FP_SHADOWFRAME 7485 move a2, rPC 7486 daddu ra, ra, (15 * 128) # Addr of primary handler. 7487 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7488 7489/* ------------------------------ */ 7490 .balign 128 7491.L_ALT_op_return_wide: /* 0x10 */ 7492/* File: mips64/alt_stub.S */ 7493/* 7494 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7495 * any interesting requests and then jump to the real instruction 7496 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7497 */ 7498 .extern MterpCheckBefore 7499 REFRESH_IBASE 7500 dla ra, artMterpAsmInstructionStart 7501 dla t9, MterpCheckBefore 7502 move a0, rSELF 7503 daddu a1, rFP, OFF_FP_SHADOWFRAME 7504 move a2, rPC 7505 daddu ra, ra, (16 * 128) # Addr of primary handler. 7506 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7507 7508/* ------------------------------ */ 7509 .balign 128 7510.L_ALT_op_return_object: /* 0x11 */ 7511/* File: mips64/alt_stub.S */ 7512/* 7513 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7514 * any interesting requests and then jump to the real instruction 7515 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7516 */ 7517 .extern MterpCheckBefore 7518 REFRESH_IBASE 7519 dla ra, artMterpAsmInstructionStart 7520 dla t9, MterpCheckBefore 7521 move a0, rSELF 7522 daddu a1, rFP, OFF_FP_SHADOWFRAME 7523 move a2, rPC 7524 daddu ra, ra, (17 * 128) # Addr of primary handler. 7525 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7526 7527/* ------------------------------ */ 7528 .balign 128 7529.L_ALT_op_const_4: /* 0x12 */ 7530/* File: mips64/alt_stub.S */ 7531/* 7532 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7533 * any interesting requests and then jump to the real instruction 7534 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7535 */ 7536 .extern MterpCheckBefore 7537 REFRESH_IBASE 7538 dla ra, artMterpAsmInstructionStart 7539 dla t9, MterpCheckBefore 7540 move a0, rSELF 7541 daddu a1, rFP, OFF_FP_SHADOWFRAME 7542 move a2, rPC 7543 daddu ra, ra, (18 * 128) # Addr of primary handler. 7544 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7545 7546/* ------------------------------ */ 7547 .balign 128 7548.L_ALT_op_const_16: /* 0x13 */ 7549/* File: mips64/alt_stub.S */ 7550/* 7551 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7552 * any interesting requests and then jump to the real instruction 7553 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7554 */ 7555 .extern MterpCheckBefore 7556 REFRESH_IBASE 7557 dla ra, artMterpAsmInstructionStart 7558 dla t9, MterpCheckBefore 7559 move a0, rSELF 7560 daddu a1, rFP, OFF_FP_SHADOWFRAME 7561 move a2, rPC 7562 daddu ra, ra, (19 * 128) # Addr of primary handler. 7563 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7564 7565/* ------------------------------ */ 7566 .balign 128 7567.L_ALT_op_const: /* 0x14 */ 7568/* File: mips64/alt_stub.S */ 7569/* 7570 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7571 * any interesting requests and then jump to the real instruction 7572 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7573 */ 7574 .extern MterpCheckBefore 7575 REFRESH_IBASE 7576 dla ra, artMterpAsmInstructionStart 7577 dla t9, MterpCheckBefore 7578 move a0, rSELF 7579 daddu a1, rFP, OFF_FP_SHADOWFRAME 7580 move a2, rPC 7581 daddu ra, ra, (20 * 128) # Addr of primary handler. 7582 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7583 7584/* ------------------------------ */ 7585 .balign 128 7586.L_ALT_op_const_high16: /* 0x15 */ 7587/* File: mips64/alt_stub.S */ 7588/* 7589 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7590 * any interesting requests and then jump to the real instruction 7591 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7592 */ 7593 .extern MterpCheckBefore 7594 REFRESH_IBASE 7595 dla ra, artMterpAsmInstructionStart 7596 dla t9, MterpCheckBefore 7597 move a0, rSELF 7598 daddu a1, rFP, OFF_FP_SHADOWFRAME 7599 move a2, rPC 7600 daddu ra, ra, (21 * 128) # Addr of primary handler. 7601 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7602 7603/* ------------------------------ */ 7604 .balign 128 7605.L_ALT_op_const_wide_16: /* 0x16 */ 7606/* File: mips64/alt_stub.S */ 7607/* 7608 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7609 * any interesting requests and then jump to the real instruction 7610 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7611 */ 7612 .extern MterpCheckBefore 7613 REFRESH_IBASE 7614 dla ra, artMterpAsmInstructionStart 7615 dla t9, MterpCheckBefore 7616 move a0, rSELF 7617 daddu a1, rFP, OFF_FP_SHADOWFRAME 7618 move a2, rPC 7619 daddu ra, ra, (22 * 128) # Addr of primary handler. 7620 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7621 7622/* ------------------------------ */ 7623 .balign 128 7624.L_ALT_op_const_wide_32: /* 0x17 */ 7625/* File: mips64/alt_stub.S */ 7626/* 7627 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7628 * any interesting requests and then jump to the real instruction 7629 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7630 */ 7631 .extern MterpCheckBefore 7632 REFRESH_IBASE 7633 dla ra, artMterpAsmInstructionStart 7634 dla t9, MterpCheckBefore 7635 move a0, rSELF 7636 daddu a1, rFP, OFF_FP_SHADOWFRAME 7637 move a2, rPC 7638 daddu ra, ra, (23 * 128) # Addr of primary handler. 7639 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7640 7641/* ------------------------------ */ 7642 .balign 128 7643.L_ALT_op_const_wide: /* 0x18 */ 7644/* File: mips64/alt_stub.S */ 7645/* 7646 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7647 * any interesting requests and then jump to the real instruction 7648 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7649 */ 7650 .extern MterpCheckBefore 7651 REFRESH_IBASE 7652 dla ra, artMterpAsmInstructionStart 7653 dla t9, MterpCheckBefore 7654 move a0, rSELF 7655 daddu a1, rFP, OFF_FP_SHADOWFRAME 7656 move a2, rPC 7657 daddu ra, ra, (24 * 128) # Addr of primary handler. 7658 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7659 7660/* ------------------------------ */ 7661 .balign 128 7662.L_ALT_op_const_wide_high16: /* 0x19 */ 7663/* File: mips64/alt_stub.S */ 7664/* 7665 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7666 * any interesting requests and then jump to the real instruction 7667 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7668 */ 7669 .extern MterpCheckBefore 7670 REFRESH_IBASE 7671 dla ra, artMterpAsmInstructionStart 7672 dla t9, MterpCheckBefore 7673 move a0, rSELF 7674 daddu a1, rFP, OFF_FP_SHADOWFRAME 7675 move a2, rPC 7676 daddu ra, ra, (25 * 128) # Addr of primary handler. 7677 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7678 7679/* ------------------------------ */ 7680 .balign 128 7681.L_ALT_op_const_string: /* 0x1a */ 7682/* File: mips64/alt_stub.S */ 7683/* 7684 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7685 * any interesting requests and then jump to the real instruction 7686 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7687 */ 7688 .extern MterpCheckBefore 7689 REFRESH_IBASE 7690 dla ra, artMterpAsmInstructionStart 7691 dla t9, MterpCheckBefore 7692 move a0, rSELF 7693 daddu a1, rFP, OFF_FP_SHADOWFRAME 7694 move a2, rPC 7695 daddu ra, ra, (26 * 128) # Addr of primary handler. 7696 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7697 7698/* ------------------------------ */ 7699 .balign 128 7700.L_ALT_op_const_string_jumbo: /* 0x1b */ 7701/* File: mips64/alt_stub.S */ 7702/* 7703 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7704 * any interesting requests and then jump to the real instruction 7705 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7706 */ 7707 .extern MterpCheckBefore 7708 REFRESH_IBASE 7709 dla ra, artMterpAsmInstructionStart 7710 dla t9, MterpCheckBefore 7711 move a0, rSELF 7712 daddu a1, rFP, OFF_FP_SHADOWFRAME 7713 move a2, rPC 7714 daddu ra, ra, (27 * 128) # Addr of primary handler. 7715 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7716 7717/* ------------------------------ */ 7718 .balign 128 7719.L_ALT_op_const_class: /* 0x1c */ 7720/* File: mips64/alt_stub.S */ 7721/* 7722 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7723 * any interesting requests and then jump to the real instruction 7724 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7725 */ 7726 .extern MterpCheckBefore 7727 REFRESH_IBASE 7728 dla ra, artMterpAsmInstructionStart 7729 dla t9, MterpCheckBefore 7730 move a0, rSELF 7731 daddu a1, rFP, OFF_FP_SHADOWFRAME 7732 move a2, rPC 7733 daddu ra, ra, (28 * 128) # Addr of primary handler. 7734 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7735 7736/* ------------------------------ */ 7737 .balign 128 7738.L_ALT_op_monitor_enter: /* 0x1d */ 7739/* File: mips64/alt_stub.S */ 7740/* 7741 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7742 * any interesting requests and then jump to the real instruction 7743 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7744 */ 7745 .extern MterpCheckBefore 7746 REFRESH_IBASE 7747 dla ra, artMterpAsmInstructionStart 7748 dla t9, MterpCheckBefore 7749 move a0, rSELF 7750 daddu a1, rFP, OFF_FP_SHADOWFRAME 7751 move a2, rPC 7752 daddu ra, ra, (29 * 128) # Addr of primary handler. 7753 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7754 7755/* ------------------------------ */ 7756 .balign 128 7757.L_ALT_op_monitor_exit: /* 0x1e */ 7758/* File: mips64/alt_stub.S */ 7759/* 7760 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7761 * any interesting requests and then jump to the real instruction 7762 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7763 */ 7764 .extern MterpCheckBefore 7765 REFRESH_IBASE 7766 dla ra, artMterpAsmInstructionStart 7767 dla t9, MterpCheckBefore 7768 move a0, rSELF 7769 daddu a1, rFP, OFF_FP_SHADOWFRAME 7770 move a2, rPC 7771 daddu ra, ra, (30 * 128) # Addr of primary handler. 7772 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7773 7774/* ------------------------------ */ 7775 .balign 128 7776.L_ALT_op_check_cast: /* 0x1f */ 7777/* File: mips64/alt_stub.S */ 7778/* 7779 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7780 * any interesting requests and then jump to the real instruction 7781 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7782 */ 7783 .extern MterpCheckBefore 7784 REFRESH_IBASE 7785 dla ra, artMterpAsmInstructionStart 7786 dla t9, MterpCheckBefore 7787 move a0, rSELF 7788 daddu a1, rFP, OFF_FP_SHADOWFRAME 7789 move a2, rPC 7790 daddu ra, ra, (31 * 128) # Addr of primary handler. 7791 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7792 7793/* ------------------------------ */ 7794 .balign 128 7795.L_ALT_op_instance_of: /* 0x20 */ 7796/* File: mips64/alt_stub.S */ 7797/* 7798 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7799 * any interesting requests and then jump to the real instruction 7800 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7801 */ 7802 .extern MterpCheckBefore 7803 REFRESH_IBASE 7804 dla ra, artMterpAsmInstructionStart 7805 dla t9, MterpCheckBefore 7806 move a0, rSELF 7807 daddu a1, rFP, OFF_FP_SHADOWFRAME 7808 move a2, rPC 7809 daddu ra, ra, (32 * 128) # Addr of primary handler. 7810 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7811 7812/* ------------------------------ */ 7813 .balign 128 7814.L_ALT_op_array_length: /* 0x21 */ 7815/* File: mips64/alt_stub.S */ 7816/* 7817 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7818 * any interesting requests and then jump to the real instruction 7819 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7820 */ 7821 .extern MterpCheckBefore 7822 REFRESH_IBASE 7823 dla ra, artMterpAsmInstructionStart 7824 dla t9, MterpCheckBefore 7825 move a0, rSELF 7826 daddu a1, rFP, OFF_FP_SHADOWFRAME 7827 move a2, rPC 7828 daddu ra, ra, (33 * 128) # Addr of primary handler. 7829 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7830 7831/* ------------------------------ */ 7832 .balign 128 7833.L_ALT_op_new_instance: /* 0x22 */ 7834/* File: mips64/alt_stub.S */ 7835/* 7836 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7837 * any interesting requests and then jump to the real instruction 7838 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7839 */ 7840 .extern MterpCheckBefore 7841 REFRESH_IBASE 7842 dla ra, artMterpAsmInstructionStart 7843 dla t9, MterpCheckBefore 7844 move a0, rSELF 7845 daddu a1, rFP, OFF_FP_SHADOWFRAME 7846 move a2, rPC 7847 daddu ra, ra, (34 * 128) # Addr of primary handler. 7848 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7849 7850/* ------------------------------ */ 7851 .balign 128 7852.L_ALT_op_new_array: /* 0x23 */ 7853/* File: mips64/alt_stub.S */ 7854/* 7855 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7856 * any interesting requests and then jump to the real instruction 7857 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7858 */ 7859 .extern MterpCheckBefore 7860 REFRESH_IBASE 7861 dla ra, artMterpAsmInstructionStart 7862 dla t9, MterpCheckBefore 7863 move a0, rSELF 7864 daddu a1, rFP, OFF_FP_SHADOWFRAME 7865 move a2, rPC 7866 daddu ra, ra, (35 * 128) # Addr of primary handler. 7867 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7868 7869/* ------------------------------ */ 7870 .balign 128 7871.L_ALT_op_filled_new_array: /* 0x24 */ 7872/* File: mips64/alt_stub.S */ 7873/* 7874 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7875 * any interesting requests and then jump to the real instruction 7876 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7877 */ 7878 .extern MterpCheckBefore 7879 REFRESH_IBASE 7880 dla ra, artMterpAsmInstructionStart 7881 dla t9, MterpCheckBefore 7882 move a0, rSELF 7883 daddu a1, rFP, OFF_FP_SHADOWFRAME 7884 move a2, rPC 7885 daddu ra, ra, (36 * 128) # Addr of primary handler. 7886 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7887 7888/* ------------------------------ */ 7889 .balign 128 7890.L_ALT_op_filled_new_array_range: /* 0x25 */ 7891/* File: mips64/alt_stub.S */ 7892/* 7893 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7894 * any interesting requests and then jump to the real instruction 7895 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7896 */ 7897 .extern MterpCheckBefore 7898 REFRESH_IBASE 7899 dla ra, artMterpAsmInstructionStart 7900 dla t9, MterpCheckBefore 7901 move a0, rSELF 7902 daddu a1, rFP, OFF_FP_SHADOWFRAME 7903 move a2, rPC 7904 daddu ra, ra, (37 * 128) # Addr of primary handler. 7905 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7906 7907/* ------------------------------ */ 7908 .balign 128 7909.L_ALT_op_fill_array_data: /* 0x26 */ 7910/* File: mips64/alt_stub.S */ 7911/* 7912 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7913 * any interesting requests and then jump to the real instruction 7914 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7915 */ 7916 .extern MterpCheckBefore 7917 REFRESH_IBASE 7918 dla ra, artMterpAsmInstructionStart 7919 dla t9, MterpCheckBefore 7920 move a0, rSELF 7921 daddu a1, rFP, OFF_FP_SHADOWFRAME 7922 move a2, rPC 7923 daddu ra, ra, (38 * 128) # Addr of primary handler. 7924 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7925 7926/* ------------------------------ */ 7927 .balign 128 7928.L_ALT_op_throw: /* 0x27 */ 7929/* File: mips64/alt_stub.S */ 7930/* 7931 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7932 * any interesting requests and then jump to the real instruction 7933 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7934 */ 7935 .extern MterpCheckBefore 7936 REFRESH_IBASE 7937 dla ra, artMterpAsmInstructionStart 7938 dla t9, MterpCheckBefore 7939 move a0, rSELF 7940 daddu a1, rFP, OFF_FP_SHADOWFRAME 7941 move a2, rPC 7942 daddu ra, ra, (39 * 128) # Addr of primary handler. 7943 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7944 7945/* ------------------------------ */ 7946 .balign 128 7947.L_ALT_op_goto: /* 0x28 */ 7948/* File: mips64/alt_stub.S */ 7949/* 7950 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7951 * any interesting requests and then jump to the real instruction 7952 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7953 */ 7954 .extern MterpCheckBefore 7955 REFRESH_IBASE 7956 dla ra, artMterpAsmInstructionStart 7957 dla t9, MterpCheckBefore 7958 move a0, rSELF 7959 daddu a1, rFP, OFF_FP_SHADOWFRAME 7960 move a2, rPC 7961 daddu ra, ra, (40 * 128) # Addr of primary handler. 7962 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7963 7964/* ------------------------------ */ 7965 .balign 128 7966.L_ALT_op_goto_16: /* 0x29 */ 7967/* File: mips64/alt_stub.S */ 7968/* 7969 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7970 * any interesting requests and then jump to the real instruction 7971 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7972 */ 7973 .extern MterpCheckBefore 7974 REFRESH_IBASE 7975 dla ra, artMterpAsmInstructionStart 7976 dla t9, MterpCheckBefore 7977 move a0, rSELF 7978 daddu a1, rFP, OFF_FP_SHADOWFRAME 7979 move a2, rPC 7980 daddu ra, ra, (41 * 128) # Addr of primary handler. 7981 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 7982 7983/* ------------------------------ */ 7984 .balign 128 7985.L_ALT_op_goto_32: /* 0x2a */ 7986/* File: mips64/alt_stub.S */ 7987/* 7988 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 7989 * any interesting requests and then jump to the real instruction 7990 * handler. Note that the call to MterpCheckBefore is done as a tail call. 7991 */ 7992 .extern MterpCheckBefore 7993 REFRESH_IBASE 7994 dla ra, artMterpAsmInstructionStart 7995 dla t9, MterpCheckBefore 7996 move a0, rSELF 7997 daddu a1, rFP, OFF_FP_SHADOWFRAME 7998 move a2, rPC 7999 daddu ra, ra, (42 * 128) # Addr of primary handler. 8000 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8001 8002/* ------------------------------ */ 8003 .balign 128 8004.L_ALT_op_packed_switch: /* 0x2b */ 8005/* File: mips64/alt_stub.S */ 8006/* 8007 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8008 * any interesting requests and then jump to the real instruction 8009 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8010 */ 8011 .extern MterpCheckBefore 8012 REFRESH_IBASE 8013 dla ra, artMterpAsmInstructionStart 8014 dla t9, MterpCheckBefore 8015 move a0, rSELF 8016 daddu a1, rFP, OFF_FP_SHADOWFRAME 8017 move a2, rPC 8018 daddu ra, ra, (43 * 128) # Addr of primary handler. 8019 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8020 8021/* ------------------------------ */ 8022 .balign 128 8023.L_ALT_op_sparse_switch: /* 0x2c */ 8024/* File: mips64/alt_stub.S */ 8025/* 8026 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8027 * any interesting requests and then jump to the real instruction 8028 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8029 */ 8030 .extern MterpCheckBefore 8031 REFRESH_IBASE 8032 dla ra, artMterpAsmInstructionStart 8033 dla t9, MterpCheckBefore 8034 move a0, rSELF 8035 daddu a1, rFP, OFF_FP_SHADOWFRAME 8036 move a2, rPC 8037 daddu ra, ra, (44 * 128) # Addr of primary handler. 8038 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8039 8040/* ------------------------------ */ 8041 .balign 128 8042.L_ALT_op_cmpl_float: /* 0x2d */ 8043/* File: mips64/alt_stub.S */ 8044/* 8045 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8046 * any interesting requests and then jump to the real instruction 8047 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8048 */ 8049 .extern MterpCheckBefore 8050 REFRESH_IBASE 8051 dla ra, artMterpAsmInstructionStart 8052 dla t9, MterpCheckBefore 8053 move a0, rSELF 8054 daddu a1, rFP, OFF_FP_SHADOWFRAME 8055 move a2, rPC 8056 daddu ra, ra, (45 * 128) # Addr of primary handler. 8057 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8058 8059/* ------------------------------ */ 8060 .balign 128 8061.L_ALT_op_cmpg_float: /* 0x2e */ 8062/* File: mips64/alt_stub.S */ 8063/* 8064 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8065 * any interesting requests and then jump to the real instruction 8066 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8067 */ 8068 .extern MterpCheckBefore 8069 REFRESH_IBASE 8070 dla ra, artMterpAsmInstructionStart 8071 dla t9, MterpCheckBefore 8072 move a0, rSELF 8073 daddu a1, rFP, OFF_FP_SHADOWFRAME 8074 move a2, rPC 8075 daddu ra, ra, (46 * 128) # Addr of primary handler. 8076 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8077 8078/* ------------------------------ */ 8079 .balign 128 8080.L_ALT_op_cmpl_double: /* 0x2f */ 8081/* File: mips64/alt_stub.S */ 8082/* 8083 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8084 * any interesting requests and then jump to the real instruction 8085 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8086 */ 8087 .extern MterpCheckBefore 8088 REFRESH_IBASE 8089 dla ra, artMterpAsmInstructionStart 8090 dla t9, MterpCheckBefore 8091 move a0, rSELF 8092 daddu a1, rFP, OFF_FP_SHADOWFRAME 8093 move a2, rPC 8094 daddu ra, ra, (47 * 128) # Addr of primary handler. 8095 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8096 8097/* ------------------------------ */ 8098 .balign 128 8099.L_ALT_op_cmpg_double: /* 0x30 */ 8100/* File: mips64/alt_stub.S */ 8101/* 8102 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8103 * any interesting requests and then jump to the real instruction 8104 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8105 */ 8106 .extern MterpCheckBefore 8107 REFRESH_IBASE 8108 dla ra, artMterpAsmInstructionStart 8109 dla t9, MterpCheckBefore 8110 move a0, rSELF 8111 daddu a1, rFP, OFF_FP_SHADOWFRAME 8112 move a2, rPC 8113 daddu ra, ra, (48 * 128) # Addr of primary handler. 8114 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8115 8116/* ------------------------------ */ 8117 .balign 128 8118.L_ALT_op_cmp_long: /* 0x31 */ 8119/* File: mips64/alt_stub.S */ 8120/* 8121 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8122 * any interesting requests and then jump to the real instruction 8123 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8124 */ 8125 .extern MterpCheckBefore 8126 REFRESH_IBASE 8127 dla ra, artMterpAsmInstructionStart 8128 dla t9, MterpCheckBefore 8129 move a0, rSELF 8130 daddu a1, rFP, OFF_FP_SHADOWFRAME 8131 move a2, rPC 8132 daddu ra, ra, (49 * 128) # Addr of primary handler. 8133 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8134 8135/* ------------------------------ */ 8136 .balign 128 8137.L_ALT_op_if_eq: /* 0x32 */ 8138/* File: mips64/alt_stub.S */ 8139/* 8140 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8141 * any interesting requests and then jump to the real instruction 8142 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8143 */ 8144 .extern MterpCheckBefore 8145 REFRESH_IBASE 8146 dla ra, artMterpAsmInstructionStart 8147 dla t9, MterpCheckBefore 8148 move a0, rSELF 8149 daddu a1, rFP, OFF_FP_SHADOWFRAME 8150 move a2, rPC 8151 daddu ra, ra, (50 * 128) # Addr of primary handler. 8152 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8153 8154/* ------------------------------ */ 8155 .balign 128 8156.L_ALT_op_if_ne: /* 0x33 */ 8157/* File: mips64/alt_stub.S */ 8158/* 8159 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8160 * any interesting requests and then jump to the real instruction 8161 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8162 */ 8163 .extern MterpCheckBefore 8164 REFRESH_IBASE 8165 dla ra, artMterpAsmInstructionStart 8166 dla t9, MterpCheckBefore 8167 move a0, rSELF 8168 daddu a1, rFP, OFF_FP_SHADOWFRAME 8169 move a2, rPC 8170 daddu ra, ra, (51 * 128) # Addr of primary handler. 8171 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8172 8173/* ------------------------------ */ 8174 .balign 128 8175.L_ALT_op_if_lt: /* 0x34 */ 8176/* File: mips64/alt_stub.S */ 8177/* 8178 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8179 * any interesting requests and then jump to the real instruction 8180 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8181 */ 8182 .extern MterpCheckBefore 8183 REFRESH_IBASE 8184 dla ra, artMterpAsmInstructionStart 8185 dla t9, MterpCheckBefore 8186 move a0, rSELF 8187 daddu a1, rFP, OFF_FP_SHADOWFRAME 8188 move a2, rPC 8189 daddu ra, ra, (52 * 128) # Addr of primary handler. 8190 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8191 8192/* ------------------------------ */ 8193 .balign 128 8194.L_ALT_op_if_ge: /* 0x35 */ 8195/* File: mips64/alt_stub.S */ 8196/* 8197 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8198 * any interesting requests and then jump to the real instruction 8199 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8200 */ 8201 .extern MterpCheckBefore 8202 REFRESH_IBASE 8203 dla ra, artMterpAsmInstructionStart 8204 dla t9, MterpCheckBefore 8205 move a0, rSELF 8206 daddu a1, rFP, OFF_FP_SHADOWFRAME 8207 move a2, rPC 8208 daddu ra, ra, (53 * 128) # Addr of primary handler. 8209 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8210 8211/* ------------------------------ */ 8212 .balign 128 8213.L_ALT_op_if_gt: /* 0x36 */ 8214/* File: mips64/alt_stub.S */ 8215/* 8216 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8217 * any interesting requests and then jump to the real instruction 8218 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8219 */ 8220 .extern MterpCheckBefore 8221 REFRESH_IBASE 8222 dla ra, artMterpAsmInstructionStart 8223 dla t9, MterpCheckBefore 8224 move a0, rSELF 8225 daddu a1, rFP, OFF_FP_SHADOWFRAME 8226 move a2, rPC 8227 daddu ra, ra, (54 * 128) # Addr of primary handler. 8228 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8229 8230/* ------------------------------ */ 8231 .balign 128 8232.L_ALT_op_if_le: /* 0x37 */ 8233/* File: mips64/alt_stub.S */ 8234/* 8235 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8236 * any interesting requests and then jump to the real instruction 8237 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8238 */ 8239 .extern MterpCheckBefore 8240 REFRESH_IBASE 8241 dla ra, artMterpAsmInstructionStart 8242 dla t9, MterpCheckBefore 8243 move a0, rSELF 8244 daddu a1, rFP, OFF_FP_SHADOWFRAME 8245 move a2, rPC 8246 daddu ra, ra, (55 * 128) # Addr of primary handler. 8247 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8248 8249/* ------------------------------ */ 8250 .balign 128 8251.L_ALT_op_if_eqz: /* 0x38 */ 8252/* File: mips64/alt_stub.S */ 8253/* 8254 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8255 * any interesting requests and then jump to the real instruction 8256 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8257 */ 8258 .extern MterpCheckBefore 8259 REFRESH_IBASE 8260 dla ra, artMterpAsmInstructionStart 8261 dla t9, MterpCheckBefore 8262 move a0, rSELF 8263 daddu a1, rFP, OFF_FP_SHADOWFRAME 8264 move a2, rPC 8265 daddu ra, ra, (56 * 128) # Addr of primary handler. 8266 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8267 8268/* ------------------------------ */ 8269 .balign 128 8270.L_ALT_op_if_nez: /* 0x39 */ 8271/* File: mips64/alt_stub.S */ 8272/* 8273 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8274 * any interesting requests and then jump to the real instruction 8275 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8276 */ 8277 .extern MterpCheckBefore 8278 REFRESH_IBASE 8279 dla ra, artMterpAsmInstructionStart 8280 dla t9, MterpCheckBefore 8281 move a0, rSELF 8282 daddu a1, rFP, OFF_FP_SHADOWFRAME 8283 move a2, rPC 8284 daddu ra, ra, (57 * 128) # Addr of primary handler. 8285 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8286 8287/* ------------------------------ */ 8288 .balign 128 8289.L_ALT_op_if_ltz: /* 0x3a */ 8290/* File: mips64/alt_stub.S */ 8291/* 8292 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8293 * any interesting requests and then jump to the real instruction 8294 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8295 */ 8296 .extern MterpCheckBefore 8297 REFRESH_IBASE 8298 dla ra, artMterpAsmInstructionStart 8299 dla t9, MterpCheckBefore 8300 move a0, rSELF 8301 daddu a1, rFP, OFF_FP_SHADOWFRAME 8302 move a2, rPC 8303 daddu ra, ra, (58 * 128) # Addr of primary handler. 8304 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8305 8306/* ------------------------------ */ 8307 .balign 128 8308.L_ALT_op_if_gez: /* 0x3b */ 8309/* File: mips64/alt_stub.S */ 8310/* 8311 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8312 * any interesting requests and then jump to the real instruction 8313 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8314 */ 8315 .extern MterpCheckBefore 8316 REFRESH_IBASE 8317 dla ra, artMterpAsmInstructionStart 8318 dla t9, MterpCheckBefore 8319 move a0, rSELF 8320 daddu a1, rFP, OFF_FP_SHADOWFRAME 8321 move a2, rPC 8322 daddu ra, ra, (59 * 128) # Addr of primary handler. 8323 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8324 8325/* ------------------------------ */ 8326 .balign 128 8327.L_ALT_op_if_gtz: /* 0x3c */ 8328/* File: mips64/alt_stub.S */ 8329/* 8330 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8331 * any interesting requests and then jump to the real instruction 8332 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8333 */ 8334 .extern MterpCheckBefore 8335 REFRESH_IBASE 8336 dla ra, artMterpAsmInstructionStart 8337 dla t9, MterpCheckBefore 8338 move a0, rSELF 8339 daddu a1, rFP, OFF_FP_SHADOWFRAME 8340 move a2, rPC 8341 daddu ra, ra, (60 * 128) # Addr of primary handler. 8342 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8343 8344/* ------------------------------ */ 8345 .balign 128 8346.L_ALT_op_if_lez: /* 0x3d */ 8347/* File: mips64/alt_stub.S */ 8348/* 8349 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8350 * any interesting requests and then jump to the real instruction 8351 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8352 */ 8353 .extern MterpCheckBefore 8354 REFRESH_IBASE 8355 dla ra, artMterpAsmInstructionStart 8356 dla t9, MterpCheckBefore 8357 move a0, rSELF 8358 daddu a1, rFP, OFF_FP_SHADOWFRAME 8359 move a2, rPC 8360 daddu ra, ra, (61 * 128) # Addr of primary handler. 8361 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8362 8363/* ------------------------------ */ 8364 .balign 128 8365.L_ALT_op_unused_3e: /* 0x3e */ 8366/* File: mips64/alt_stub.S */ 8367/* 8368 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8369 * any interesting requests and then jump to the real instruction 8370 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8371 */ 8372 .extern MterpCheckBefore 8373 REFRESH_IBASE 8374 dla ra, artMterpAsmInstructionStart 8375 dla t9, MterpCheckBefore 8376 move a0, rSELF 8377 daddu a1, rFP, OFF_FP_SHADOWFRAME 8378 move a2, rPC 8379 daddu ra, ra, (62 * 128) # Addr of primary handler. 8380 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8381 8382/* ------------------------------ */ 8383 .balign 128 8384.L_ALT_op_unused_3f: /* 0x3f */ 8385/* File: mips64/alt_stub.S */ 8386/* 8387 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8388 * any interesting requests and then jump to the real instruction 8389 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8390 */ 8391 .extern MterpCheckBefore 8392 REFRESH_IBASE 8393 dla ra, artMterpAsmInstructionStart 8394 dla t9, MterpCheckBefore 8395 move a0, rSELF 8396 daddu a1, rFP, OFF_FP_SHADOWFRAME 8397 move a2, rPC 8398 daddu ra, ra, (63 * 128) # Addr of primary handler. 8399 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8400 8401/* ------------------------------ */ 8402 .balign 128 8403.L_ALT_op_unused_40: /* 0x40 */ 8404/* File: mips64/alt_stub.S */ 8405/* 8406 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8407 * any interesting requests and then jump to the real instruction 8408 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8409 */ 8410 .extern MterpCheckBefore 8411 REFRESH_IBASE 8412 dla ra, artMterpAsmInstructionStart 8413 dla t9, MterpCheckBefore 8414 move a0, rSELF 8415 daddu a1, rFP, OFF_FP_SHADOWFRAME 8416 move a2, rPC 8417 daddu ra, ra, (64 * 128) # Addr of primary handler. 8418 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8419 8420/* ------------------------------ */ 8421 .balign 128 8422.L_ALT_op_unused_41: /* 0x41 */ 8423/* File: mips64/alt_stub.S */ 8424/* 8425 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8426 * any interesting requests and then jump to the real instruction 8427 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8428 */ 8429 .extern MterpCheckBefore 8430 REFRESH_IBASE 8431 dla ra, artMterpAsmInstructionStart 8432 dla t9, MterpCheckBefore 8433 move a0, rSELF 8434 daddu a1, rFP, OFF_FP_SHADOWFRAME 8435 move a2, rPC 8436 daddu ra, ra, (65 * 128) # Addr of primary handler. 8437 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8438 8439/* ------------------------------ */ 8440 .balign 128 8441.L_ALT_op_unused_42: /* 0x42 */ 8442/* File: mips64/alt_stub.S */ 8443/* 8444 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8445 * any interesting requests and then jump to the real instruction 8446 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8447 */ 8448 .extern MterpCheckBefore 8449 REFRESH_IBASE 8450 dla ra, artMterpAsmInstructionStart 8451 dla t9, MterpCheckBefore 8452 move a0, rSELF 8453 daddu a1, rFP, OFF_FP_SHADOWFRAME 8454 move a2, rPC 8455 daddu ra, ra, (66 * 128) # Addr of primary handler. 8456 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8457 8458/* ------------------------------ */ 8459 .balign 128 8460.L_ALT_op_unused_43: /* 0x43 */ 8461/* File: mips64/alt_stub.S */ 8462/* 8463 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8464 * any interesting requests and then jump to the real instruction 8465 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8466 */ 8467 .extern MterpCheckBefore 8468 REFRESH_IBASE 8469 dla ra, artMterpAsmInstructionStart 8470 dla t9, MterpCheckBefore 8471 move a0, rSELF 8472 daddu a1, rFP, OFF_FP_SHADOWFRAME 8473 move a2, rPC 8474 daddu ra, ra, (67 * 128) # Addr of primary handler. 8475 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8476 8477/* ------------------------------ */ 8478 .balign 128 8479.L_ALT_op_aget: /* 0x44 */ 8480/* File: mips64/alt_stub.S */ 8481/* 8482 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8483 * any interesting requests and then jump to the real instruction 8484 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8485 */ 8486 .extern MterpCheckBefore 8487 REFRESH_IBASE 8488 dla ra, artMterpAsmInstructionStart 8489 dla t9, MterpCheckBefore 8490 move a0, rSELF 8491 daddu a1, rFP, OFF_FP_SHADOWFRAME 8492 move a2, rPC 8493 daddu ra, ra, (68 * 128) # Addr of primary handler. 8494 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8495 8496/* ------------------------------ */ 8497 .balign 128 8498.L_ALT_op_aget_wide: /* 0x45 */ 8499/* File: mips64/alt_stub.S */ 8500/* 8501 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8502 * any interesting requests and then jump to the real instruction 8503 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8504 */ 8505 .extern MterpCheckBefore 8506 REFRESH_IBASE 8507 dla ra, artMterpAsmInstructionStart 8508 dla t9, MterpCheckBefore 8509 move a0, rSELF 8510 daddu a1, rFP, OFF_FP_SHADOWFRAME 8511 move a2, rPC 8512 daddu ra, ra, (69 * 128) # Addr of primary handler. 8513 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8514 8515/* ------------------------------ */ 8516 .balign 128 8517.L_ALT_op_aget_object: /* 0x46 */ 8518/* File: mips64/alt_stub.S */ 8519/* 8520 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8521 * any interesting requests and then jump to the real instruction 8522 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8523 */ 8524 .extern MterpCheckBefore 8525 REFRESH_IBASE 8526 dla ra, artMterpAsmInstructionStart 8527 dla t9, MterpCheckBefore 8528 move a0, rSELF 8529 daddu a1, rFP, OFF_FP_SHADOWFRAME 8530 move a2, rPC 8531 daddu ra, ra, (70 * 128) # Addr of primary handler. 8532 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8533 8534/* ------------------------------ */ 8535 .balign 128 8536.L_ALT_op_aget_boolean: /* 0x47 */ 8537/* File: mips64/alt_stub.S */ 8538/* 8539 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8540 * any interesting requests and then jump to the real instruction 8541 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8542 */ 8543 .extern MterpCheckBefore 8544 REFRESH_IBASE 8545 dla ra, artMterpAsmInstructionStart 8546 dla t9, MterpCheckBefore 8547 move a0, rSELF 8548 daddu a1, rFP, OFF_FP_SHADOWFRAME 8549 move a2, rPC 8550 daddu ra, ra, (71 * 128) # Addr of primary handler. 8551 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8552 8553/* ------------------------------ */ 8554 .balign 128 8555.L_ALT_op_aget_byte: /* 0x48 */ 8556/* File: mips64/alt_stub.S */ 8557/* 8558 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8559 * any interesting requests and then jump to the real instruction 8560 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8561 */ 8562 .extern MterpCheckBefore 8563 REFRESH_IBASE 8564 dla ra, artMterpAsmInstructionStart 8565 dla t9, MterpCheckBefore 8566 move a0, rSELF 8567 daddu a1, rFP, OFF_FP_SHADOWFRAME 8568 move a2, rPC 8569 daddu ra, ra, (72 * 128) # Addr of primary handler. 8570 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8571 8572/* ------------------------------ */ 8573 .balign 128 8574.L_ALT_op_aget_char: /* 0x49 */ 8575/* File: mips64/alt_stub.S */ 8576/* 8577 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8578 * any interesting requests and then jump to the real instruction 8579 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8580 */ 8581 .extern MterpCheckBefore 8582 REFRESH_IBASE 8583 dla ra, artMterpAsmInstructionStart 8584 dla t9, MterpCheckBefore 8585 move a0, rSELF 8586 daddu a1, rFP, OFF_FP_SHADOWFRAME 8587 move a2, rPC 8588 daddu ra, ra, (73 * 128) # Addr of primary handler. 8589 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8590 8591/* ------------------------------ */ 8592 .balign 128 8593.L_ALT_op_aget_short: /* 0x4a */ 8594/* File: mips64/alt_stub.S */ 8595/* 8596 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8597 * any interesting requests and then jump to the real instruction 8598 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8599 */ 8600 .extern MterpCheckBefore 8601 REFRESH_IBASE 8602 dla ra, artMterpAsmInstructionStart 8603 dla t9, MterpCheckBefore 8604 move a0, rSELF 8605 daddu a1, rFP, OFF_FP_SHADOWFRAME 8606 move a2, rPC 8607 daddu ra, ra, (74 * 128) # Addr of primary handler. 8608 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8609 8610/* ------------------------------ */ 8611 .balign 128 8612.L_ALT_op_aput: /* 0x4b */ 8613/* File: mips64/alt_stub.S */ 8614/* 8615 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8616 * any interesting requests and then jump to the real instruction 8617 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8618 */ 8619 .extern MterpCheckBefore 8620 REFRESH_IBASE 8621 dla ra, artMterpAsmInstructionStart 8622 dla t9, MterpCheckBefore 8623 move a0, rSELF 8624 daddu a1, rFP, OFF_FP_SHADOWFRAME 8625 move a2, rPC 8626 daddu ra, ra, (75 * 128) # Addr of primary handler. 8627 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8628 8629/* ------------------------------ */ 8630 .balign 128 8631.L_ALT_op_aput_wide: /* 0x4c */ 8632/* File: mips64/alt_stub.S */ 8633/* 8634 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8635 * any interesting requests and then jump to the real instruction 8636 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8637 */ 8638 .extern MterpCheckBefore 8639 REFRESH_IBASE 8640 dla ra, artMterpAsmInstructionStart 8641 dla t9, MterpCheckBefore 8642 move a0, rSELF 8643 daddu a1, rFP, OFF_FP_SHADOWFRAME 8644 move a2, rPC 8645 daddu ra, ra, (76 * 128) # Addr of primary handler. 8646 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8647 8648/* ------------------------------ */ 8649 .balign 128 8650.L_ALT_op_aput_object: /* 0x4d */ 8651/* File: mips64/alt_stub.S */ 8652/* 8653 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8654 * any interesting requests and then jump to the real instruction 8655 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8656 */ 8657 .extern MterpCheckBefore 8658 REFRESH_IBASE 8659 dla ra, artMterpAsmInstructionStart 8660 dla t9, MterpCheckBefore 8661 move a0, rSELF 8662 daddu a1, rFP, OFF_FP_SHADOWFRAME 8663 move a2, rPC 8664 daddu ra, ra, (77 * 128) # Addr of primary handler. 8665 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8666 8667/* ------------------------------ */ 8668 .balign 128 8669.L_ALT_op_aput_boolean: /* 0x4e */ 8670/* File: mips64/alt_stub.S */ 8671/* 8672 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8673 * any interesting requests and then jump to the real instruction 8674 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8675 */ 8676 .extern MterpCheckBefore 8677 REFRESH_IBASE 8678 dla ra, artMterpAsmInstructionStart 8679 dla t9, MterpCheckBefore 8680 move a0, rSELF 8681 daddu a1, rFP, OFF_FP_SHADOWFRAME 8682 move a2, rPC 8683 daddu ra, ra, (78 * 128) # Addr of primary handler. 8684 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8685 8686/* ------------------------------ */ 8687 .balign 128 8688.L_ALT_op_aput_byte: /* 0x4f */ 8689/* File: mips64/alt_stub.S */ 8690/* 8691 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8692 * any interesting requests and then jump to the real instruction 8693 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8694 */ 8695 .extern MterpCheckBefore 8696 REFRESH_IBASE 8697 dla ra, artMterpAsmInstructionStart 8698 dla t9, MterpCheckBefore 8699 move a0, rSELF 8700 daddu a1, rFP, OFF_FP_SHADOWFRAME 8701 move a2, rPC 8702 daddu ra, ra, (79 * 128) # Addr of primary handler. 8703 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8704 8705/* ------------------------------ */ 8706 .balign 128 8707.L_ALT_op_aput_char: /* 0x50 */ 8708/* File: mips64/alt_stub.S */ 8709/* 8710 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8711 * any interesting requests and then jump to the real instruction 8712 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8713 */ 8714 .extern MterpCheckBefore 8715 REFRESH_IBASE 8716 dla ra, artMterpAsmInstructionStart 8717 dla t9, MterpCheckBefore 8718 move a0, rSELF 8719 daddu a1, rFP, OFF_FP_SHADOWFRAME 8720 move a2, rPC 8721 daddu ra, ra, (80 * 128) # Addr of primary handler. 8722 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8723 8724/* ------------------------------ */ 8725 .balign 128 8726.L_ALT_op_aput_short: /* 0x51 */ 8727/* File: mips64/alt_stub.S */ 8728/* 8729 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8730 * any interesting requests and then jump to the real instruction 8731 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8732 */ 8733 .extern MterpCheckBefore 8734 REFRESH_IBASE 8735 dla ra, artMterpAsmInstructionStart 8736 dla t9, MterpCheckBefore 8737 move a0, rSELF 8738 daddu a1, rFP, OFF_FP_SHADOWFRAME 8739 move a2, rPC 8740 daddu ra, ra, (81 * 128) # Addr of primary handler. 8741 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8742 8743/* ------------------------------ */ 8744 .balign 128 8745.L_ALT_op_iget: /* 0x52 */ 8746/* File: mips64/alt_stub.S */ 8747/* 8748 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8749 * any interesting requests and then jump to the real instruction 8750 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8751 */ 8752 .extern MterpCheckBefore 8753 REFRESH_IBASE 8754 dla ra, artMterpAsmInstructionStart 8755 dla t9, MterpCheckBefore 8756 move a0, rSELF 8757 daddu a1, rFP, OFF_FP_SHADOWFRAME 8758 move a2, rPC 8759 daddu ra, ra, (82 * 128) # Addr of primary handler. 8760 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8761 8762/* ------------------------------ */ 8763 .balign 128 8764.L_ALT_op_iget_wide: /* 0x53 */ 8765/* File: mips64/alt_stub.S */ 8766/* 8767 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8768 * any interesting requests and then jump to the real instruction 8769 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8770 */ 8771 .extern MterpCheckBefore 8772 REFRESH_IBASE 8773 dla ra, artMterpAsmInstructionStart 8774 dla t9, MterpCheckBefore 8775 move a0, rSELF 8776 daddu a1, rFP, OFF_FP_SHADOWFRAME 8777 move a2, rPC 8778 daddu ra, ra, (83 * 128) # Addr of primary handler. 8779 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8780 8781/* ------------------------------ */ 8782 .balign 128 8783.L_ALT_op_iget_object: /* 0x54 */ 8784/* File: mips64/alt_stub.S */ 8785/* 8786 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8787 * any interesting requests and then jump to the real instruction 8788 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8789 */ 8790 .extern MterpCheckBefore 8791 REFRESH_IBASE 8792 dla ra, artMterpAsmInstructionStart 8793 dla t9, MterpCheckBefore 8794 move a0, rSELF 8795 daddu a1, rFP, OFF_FP_SHADOWFRAME 8796 move a2, rPC 8797 daddu ra, ra, (84 * 128) # Addr of primary handler. 8798 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8799 8800/* ------------------------------ */ 8801 .balign 128 8802.L_ALT_op_iget_boolean: /* 0x55 */ 8803/* File: mips64/alt_stub.S */ 8804/* 8805 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8806 * any interesting requests and then jump to the real instruction 8807 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8808 */ 8809 .extern MterpCheckBefore 8810 REFRESH_IBASE 8811 dla ra, artMterpAsmInstructionStart 8812 dla t9, MterpCheckBefore 8813 move a0, rSELF 8814 daddu a1, rFP, OFF_FP_SHADOWFRAME 8815 move a2, rPC 8816 daddu ra, ra, (85 * 128) # Addr of primary handler. 8817 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8818 8819/* ------------------------------ */ 8820 .balign 128 8821.L_ALT_op_iget_byte: /* 0x56 */ 8822/* File: mips64/alt_stub.S */ 8823/* 8824 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8825 * any interesting requests and then jump to the real instruction 8826 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8827 */ 8828 .extern MterpCheckBefore 8829 REFRESH_IBASE 8830 dla ra, artMterpAsmInstructionStart 8831 dla t9, MterpCheckBefore 8832 move a0, rSELF 8833 daddu a1, rFP, OFF_FP_SHADOWFRAME 8834 move a2, rPC 8835 daddu ra, ra, (86 * 128) # Addr of primary handler. 8836 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8837 8838/* ------------------------------ */ 8839 .balign 128 8840.L_ALT_op_iget_char: /* 0x57 */ 8841/* File: mips64/alt_stub.S */ 8842/* 8843 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8844 * any interesting requests and then jump to the real instruction 8845 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8846 */ 8847 .extern MterpCheckBefore 8848 REFRESH_IBASE 8849 dla ra, artMterpAsmInstructionStart 8850 dla t9, MterpCheckBefore 8851 move a0, rSELF 8852 daddu a1, rFP, OFF_FP_SHADOWFRAME 8853 move a2, rPC 8854 daddu ra, ra, (87 * 128) # Addr of primary handler. 8855 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8856 8857/* ------------------------------ */ 8858 .balign 128 8859.L_ALT_op_iget_short: /* 0x58 */ 8860/* File: mips64/alt_stub.S */ 8861/* 8862 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8863 * any interesting requests and then jump to the real instruction 8864 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8865 */ 8866 .extern MterpCheckBefore 8867 REFRESH_IBASE 8868 dla ra, artMterpAsmInstructionStart 8869 dla t9, MterpCheckBefore 8870 move a0, rSELF 8871 daddu a1, rFP, OFF_FP_SHADOWFRAME 8872 move a2, rPC 8873 daddu ra, ra, (88 * 128) # Addr of primary handler. 8874 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8875 8876/* ------------------------------ */ 8877 .balign 128 8878.L_ALT_op_iput: /* 0x59 */ 8879/* File: mips64/alt_stub.S */ 8880/* 8881 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8882 * any interesting requests and then jump to the real instruction 8883 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8884 */ 8885 .extern MterpCheckBefore 8886 REFRESH_IBASE 8887 dla ra, artMterpAsmInstructionStart 8888 dla t9, MterpCheckBefore 8889 move a0, rSELF 8890 daddu a1, rFP, OFF_FP_SHADOWFRAME 8891 move a2, rPC 8892 daddu ra, ra, (89 * 128) # Addr of primary handler. 8893 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8894 8895/* ------------------------------ */ 8896 .balign 128 8897.L_ALT_op_iput_wide: /* 0x5a */ 8898/* File: mips64/alt_stub.S */ 8899/* 8900 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8901 * any interesting requests and then jump to the real instruction 8902 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8903 */ 8904 .extern MterpCheckBefore 8905 REFRESH_IBASE 8906 dla ra, artMterpAsmInstructionStart 8907 dla t9, MterpCheckBefore 8908 move a0, rSELF 8909 daddu a1, rFP, OFF_FP_SHADOWFRAME 8910 move a2, rPC 8911 daddu ra, ra, (90 * 128) # Addr of primary handler. 8912 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8913 8914/* ------------------------------ */ 8915 .balign 128 8916.L_ALT_op_iput_object: /* 0x5b */ 8917/* File: mips64/alt_stub.S */ 8918/* 8919 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8920 * any interesting requests and then jump to the real instruction 8921 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8922 */ 8923 .extern MterpCheckBefore 8924 REFRESH_IBASE 8925 dla ra, artMterpAsmInstructionStart 8926 dla t9, MterpCheckBefore 8927 move a0, rSELF 8928 daddu a1, rFP, OFF_FP_SHADOWFRAME 8929 move a2, rPC 8930 daddu ra, ra, (91 * 128) # Addr of primary handler. 8931 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8932 8933/* ------------------------------ */ 8934 .balign 128 8935.L_ALT_op_iput_boolean: /* 0x5c */ 8936/* File: mips64/alt_stub.S */ 8937/* 8938 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8939 * any interesting requests and then jump to the real instruction 8940 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8941 */ 8942 .extern MterpCheckBefore 8943 REFRESH_IBASE 8944 dla ra, artMterpAsmInstructionStart 8945 dla t9, MterpCheckBefore 8946 move a0, rSELF 8947 daddu a1, rFP, OFF_FP_SHADOWFRAME 8948 move a2, rPC 8949 daddu ra, ra, (92 * 128) # Addr of primary handler. 8950 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8951 8952/* ------------------------------ */ 8953 .balign 128 8954.L_ALT_op_iput_byte: /* 0x5d */ 8955/* File: mips64/alt_stub.S */ 8956/* 8957 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8958 * any interesting requests and then jump to the real instruction 8959 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8960 */ 8961 .extern MterpCheckBefore 8962 REFRESH_IBASE 8963 dla ra, artMterpAsmInstructionStart 8964 dla t9, MterpCheckBefore 8965 move a0, rSELF 8966 daddu a1, rFP, OFF_FP_SHADOWFRAME 8967 move a2, rPC 8968 daddu ra, ra, (93 * 128) # Addr of primary handler. 8969 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8970 8971/* ------------------------------ */ 8972 .balign 128 8973.L_ALT_op_iput_char: /* 0x5e */ 8974/* File: mips64/alt_stub.S */ 8975/* 8976 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8977 * any interesting requests and then jump to the real instruction 8978 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8979 */ 8980 .extern MterpCheckBefore 8981 REFRESH_IBASE 8982 dla ra, artMterpAsmInstructionStart 8983 dla t9, MterpCheckBefore 8984 move a0, rSELF 8985 daddu a1, rFP, OFF_FP_SHADOWFRAME 8986 move a2, rPC 8987 daddu ra, ra, (94 * 128) # Addr of primary handler. 8988 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 8989 8990/* ------------------------------ */ 8991 .balign 128 8992.L_ALT_op_iput_short: /* 0x5f */ 8993/* File: mips64/alt_stub.S */ 8994/* 8995 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 8996 * any interesting requests and then jump to the real instruction 8997 * handler. Note that the call to MterpCheckBefore is done as a tail call. 8998 */ 8999 .extern MterpCheckBefore 9000 REFRESH_IBASE 9001 dla ra, artMterpAsmInstructionStart 9002 dla t9, MterpCheckBefore 9003 move a0, rSELF 9004 daddu a1, rFP, OFF_FP_SHADOWFRAME 9005 move a2, rPC 9006 daddu ra, ra, (95 * 128) # Addr of primary handler. 9007 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9008 9009/* ------------------------------ */ 9010 .balign 128 9011.L_ALT_op_sget: /* 0x60 */ 9012/* File: mips64/alt_stub.S */ 9013/* 9014 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9015 * any interesting requests and then jump to the real instruction 9016 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9017 */ 9018 .extern MterpCheckBefore 9019 REFRESH_IBASE 9020 dla ra, artMterpAsmInstructionStart 9021 dla t9, MterpCheckBefore 9022 move a0, rSELF 9023 daddu a1, rFP, OFF_FP_SHADOWFRAME 9024 move a2, rPC 9025 daddu ra, ra, (96 * 128) # Addr of primary handler. 9026 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9027 9028/* ------------------------------ */ 9029 .balign 128 9030.L_ALT_op_sget_wide: /* 0x61 */ 9031/* File: mips64/alt_stub.S */ 9032/* 9033 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9034 * any interesting requests and then jump to the real instruction 9035 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9036 */ 9037 .extern MterpCheckBefore 9038 REFRESH_IBASE 9039 dla ra, artMterpAsmInstructionStart 9040 dla t9, MterpCheckBefore 9041 move a0, rSELF 9042 daddu a1, rFP, OFF_FP_SHADOWFRAME 9043 move a2, rPC 9044 daddu ra, ra, (97 * 128) # Addr of primary handler. 9045 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9046 9047/* ------------------------------ */ 9048 .balign 128 9049.L_ALT_op_sget_object: /* 0x62 */ 9050/* File: mips64/alt_stub.S */ 9051/* 9052 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9053 * any interesting requests and then jump to the real instruction 9054 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9055 */ 9056 .extern MterpCheckBefore 9057 REFRESH_IBASE 9058 dla ra, artMterpAsmInstructionStart 9059 dla t9, MterpCheckBefore 9060 move a0, rSELF 9061 daddu a1, rFP, OFF_FP_SHADOWFRAME 9062 move a2, rPC 9063 daddu ra, ra, (98 * 128) # Addr of primary handler. 9064 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9065 9066/* ------------------------------ */ 9067 .balign 128 9068.L_ALT_op_sget_boolean: /* 0x63 */ 9069/* File: mips64/alt_stub.S */ 9070/* 9071 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9072 * any interesting requests and then jump to the real instruction 9073 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9074 */ 9075 .extern MterpCheckBefore 9076 REFRESH_IBASE 9077 dla ra, artMterpAsmInstructionStart 9078 dla t9, MterpCheckBefore 9079 move a0, rSELF 9080 daddu a1, rFP, OFF_FP_SHADOWFRAME 9081 move a2, rPC 9082 daddu ra, ra, (99 * 128) # Addr of primary handler. 9083 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9084 9085/* ------------------------------ */ 9086 .balign 128 9087.L_ALT_op_sget_byte: /* 0x64 */ 9088/* File: mips64/alt_stub.S */ 9089/* 9090 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9091 * any interesting requests and then jump to the real instruction 9092 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9093 */ 9094 .extern MterpCheckBefore 9095 REFRESH_IBASE 9096 dla ra, artMterpAsmInstructionStart 9097 dla t9, MterpCheckBefore 9098 move a0, rSELF 9099 daddu a1, rFP, OFF_FP_SHADOWFRAME 9100 move a2, rPC 9101 daddu ra, ra, (100 * 128) # Addr of primary handler. 9102 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9103 9104/* ------------------------------ */ 9105 .balign 128 9106.L_ALT_op_sget_char: /* 0x65 */ 9107/* File: mips64/alt_stub.S */ 9108/* 9109 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9110 * any interesting requests and then jump to the real instruction 9111 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9112 */ 9113 .extern MterpCheckBefore 9114 REFRESH_IBASE 9115 dla ra, artMterpAsmInstructionStart 9116 dla t9, MterpCheckBefore 9117 move a0, rSELF 9118 daddu a1, rFP, OFF_FP_SHADOWFRAME 9119 move a2, rPC 9120 daddu ra, ra, (101 * 128) # Addr of primary handler. 9121 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9122 9123/* ------------------------------ */ 9124 .balign 128 9125.L_ALT_op_sget_short: /* 0x66 */ 9126/* File: mips64/alt_stub.S */ 9127/* 9128 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9129 * any interesting requests and then jump to the real instruction 9130 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9131 */ 9132 .extern MterpCheckBefore 9133 REFRESH_IBASE 9134 dla ra, artMterpAsmInstructionStart 9135 dla t9, MterpCheckBefore 9136 move a0, rSELF 9137 daddu a1, rFP, OFF_FP_SHADOWFRAME 9138 move a2, rPC 9139 daddu ra, ra, (102 * 128) # Addr of primary handler. 9140 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9141 9142/* ------------------------------ */ 9143 .balign 128 9144.L_ALT_op_sput: /* 0x67 */ 9145/* File: mips64/alt_stub.S */ 9146/* 9147 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9148 * any interesting requests and then jump to the real instruction 9149 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9150 */ 9151 .extern MterpCheckBefore 9152 REFRESH_IBASE 9153 dla ra, artMterpAsmInstructionStart 9154 dla t9, MterpCheckBefore 9155 move a0, rSELF 9156 daddu a1, rFP, OFF_FP_SHADOWFRAME 9157 move a2, rPC 9158 daddu ra, ra, (103 * 128) # Addr of primary handler. 9159 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9160 9161/* ------------------------------ */ 9162 .balign 128 9163.L_ALT_op_sput_wide: /* 0x68 */ 9164/* File: mips64/alt_stub.S */ 9165/* 9166 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9167 * any interesting requests and then jump to the real instruction 9168 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9169 */ 9170 .extern MterpCheckBefore 9171 REFRESH_IBASE 9172 dla ra, artMterpAsmInstructionStart 9173 dla t9, MterpCheckBefore 9174 move a0, rSELF 9175 daddu a1, rFP, OFF_FP_SHADOWFRAME 9176 move a2, rPC 9177 daddu ra, ra, (104 * 128) # Addr of primary handler. 9178 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9179 9180/* ------------------------------ */ 9181 .balign 128 9182.L_ALT_op_sput_object: /* 0x69 */ 9183/* File: mips64/alt_stub.S */ 9184/* 9185 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9186 * any interesting requests and then jump to the real instruction 9187 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9188 */ 9189 .extern MterpCheckBefore 9190 REFRESH_IBASE 9191 dla ra, artMterpAsmInstructionStart 9192 dla t9, MterpCheckBefore 9193 move a0, rSELF 9194 daddu a1, rFP, OFF_FP_SHADOWFRAME 9195 move a2, rPC 9196 daddu ra, ra, (105 * 128) # Addr of primary handler. 9197 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9198 9199/* ------------------------------ */ 9200 .balign 128 9201.L_ALT_op_sput_boolean: /* 0x6a */ 9202/* File: mips64/alt_stub.S */ 9203/* 9204 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9205 * any interesting requests and then jump to the real instruction 9206 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9207 */ 9208 .extern MterpCheckBefore 9209 REFRESH_IBASE 9210 dla ra, artMterpAsmInstructionStart 9211 dla t9, MterpCheckBefore 9212 move a0, rSELF 9213 daddu a1, rFP, OFF_FP_SHADOWFRAME 9214 move a2, rPC 9215 daddu ra, ra, (106 * 128) # Addr of primary handler. 9216 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9217 9218/* ------------------------------ */ 9219 .balign 128 9220.L_ALT_op_sput_byte: /* 0x6b */ 9221/* File: mips64/alt_stub.S */ 9222/* 9223 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9224 * any interesting requests and then jump to the real instruction 9225 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9226 */ 9227 .extern MterpCheckBefore 9228 REFRESH_IBASE 9229 dla ra, artMterpAsmInstructionStart 9230 dla t9, MterpCheckBefore 9231 move a0, rSELF 9232 daddu a1, rFP, OFF_FP_SHADOWFRAME 9233 move a2, rPC 9234 daddu ra, ra, (107 * 128) # Addr of primary handler. 9235 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9236 9237/* ------------------------------ */ 9238 .balign 128 9239.L_ALT_op_sput_char: /* 0x6c */ 9240/* File: mips64/alt_stub.S */ 9241/* 9242 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9243 * any interesting requests and then jump to the real instruction 9244 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9245 */ 9246 .extern MterpCheckBefore 9247 REFRESH_IBASE 9248 dla ra, artMterpAsmInstructionStart 9249 dla t9, MterpCheckBefore 9250 move a0, rSELF 9251 daddu a1, rFP, OFF_FP_SHADOWFRAME 9252 move a2, rPC 9253 daddu ra, ra, (108 * 128) # Addr of primary handler. 9254 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9255 9256/* ------------------------------ */ 9257 .balign 128 9258.L_ALT_op_sput_short: /* 0x6d */ 9259/* File: mips64/alt_stub.S */ 9260/* 9261 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9262 * any interesting requests and then jump to the real instruction 9263 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9264 */ 9265 .extern MterpCheckBefore 9266 REFRESH_IBASE 9267 dla ra, artMterpAsmInstructionStart 9268 dla t9, MterpCheckBefore 9269 move a0, rSELF 9270 daddu a1, rFP, OFF_FP_SHADOWFRAME 9271 move a2, rPC 9272 daddu ra, ra, (109 * 128) # Addr of primary handler. 9273 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9274 9275/* ------------------------------ */ 9276 .balign 128 9277.L_ALT_op_invoke_virtual: /* 0x6e */ 9278/* File: mips64/alt_stub.S */ 9279/* 9280 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9281 * any interesting requests and then jump to the real instruction 9282 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9283 */ 9284 .extern MterpCheckBefore 9285 REFRESH_IBASE 9286 dla ra, artMterpAsmInstructionStart 9287 dla t9, MterpCheckBefore 9288 move a0, rSELF 9289 daddu a1, rFP, OFF_FP_SHADOWFRAME 9290 move a2, rPC 9291 daddu ra, ra, (110 * 128) # Addr of primary handler. 9292 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9293 9294/* ------------------------------ */ 9295 .balign 128 9296.L_ALT_op_invoke_super: /* 0x6f */ 9297/* File: mips64/alt_stub.S */ 9298/* 9299 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9300 * any interesting requests and then jump to the real instruction 9301 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9302 */ 9303 .extern MterpCheckBefore 9304 REFRESH_IBASE 9305 dla ra, artMterpAsmInstructionStart 9306 dla t9, MterpCheckBefore 9307 move a0, rSELF 9308 daddu a1, rFP, OFF_FP_SHADOWFRAME 9309 move a2, rPC 9310 daddu ra, ra, (111 * 128) # Addr of primary handler. 9311 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9312 9313/* ------------------------------ */ 9314 .balign 128 9315.L_ALT_op_invoke_direct: /* 0x70 */ 9316/* File: mips64/alt_stub.S */ 9317/* 9318 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9319 * any interesting requests and then jump to the real instruction 9320 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9321 */ 9322 .extern MterpCheckBefore 9323 REFRESH_IBASE 9324 dla ra, artMterpAsmInstructionStart 9325 dla t9, MterpCheckBefore 9326 move a0, rSELF 9327 daddu a1, rFP, OFF_FP_SHADOWFRAME 9328 move a2, rPC 9329 daddu ra, ra, (112 * 128) # Addr of primary handler. 9330 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9331 9332/* ------------------------------ */ 9333 .balign 128 9334.L_ALT_op_invoke_static: /* 0x71 */ 9335/* File: mips64/alt_stub.S */ 9336/* 9337 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9338 * any interesting requests and then jump to the real instruction 9339 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9340 */ 9341 .extern MterpCheckBefore 9342 REFRESH_IBASE 9343 dla ra, artMterpAsmInstructionStart 9344 dla t9, MterpCheckBefore 9345 move a0, rSELF 9346 daddu a1, rFP, OFF_FP_SHADOWFRAME 9347 move a2, rPC 9348 daddu ra, ra, (113 * 128) # Addr of primary handler. 9349 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9350 9351/* ------------------------------ */ 9352 .balign 128 9353.L_ALT_op_invoke_interface: /* 0x72 */ 9354/* File: mips64/alt_stub.S */ 9355/* 9356 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9357 * any interesting requests and then jump to the real instruction 9358 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9359 */ 9360 .extern MterpCheckBefore 9361 REFRESH_IBASE 9362 dla ra, artMterpAsmInstructionStart 9363 dla t9, MterpCheckBefore 9364 move a0, rSELF 9365 daddu a1, rFP, OFF_FP_SHADOWFRAME 9366 move a2, rPC 9367 daddu ra, ra, (114 * 128) # Addr of primary handler. 9368 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9369 9370/* ------------------------------ */ 9371 .balign 128 9372.L_ALT_op_return_void_no_barrier: /* 0x73 */ 9373/* File: mips64/alt_stub.S */ 9374/* 9375 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9376 * any interesting requests and then jump to the real instruction 9377 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9378 */ 9379 .extern MterpCheckBefore 9380 REFRESH_IBASE 9381 dla ra, artMterpAsmInstructionStart 9382 dla t9, MterpCheckBefore 9383 move a0, rSELF 9384 daddu a1, rFP, OFF_FP_SHADOWFRAME 9385 move a2, rPC 9386 daddu ra, ra, (115 * 128) # Addr of primary handler. 9387 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9388 9389/* ------------------------------ */ 9390 .balign 128 9391.L_ALT_op_invoke_virtual_range: /* 0x74 */ 9392/* File: mips64/alt_stub.S */ 9393/* 9394 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9395 * any interesting requests and then jump to the real instruction 9396 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9397 */ 9398 .extern MterpCheckBefore 9399 REFRESH_IBASE 9400 dla ra, artMterpAsmInstructionStart 9401 dla t9, MterpCheckBefore 9402 move a0, rSELF 9403 daddu a1, rFP, OFF_FP_SHADOWFRAME 9404 move a2, rPC 9405 daddu ra, ra, (116 * 128) # Addr of primary handler. 9406 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9407 9408/* ------------------------------ */ 9409 .balign 128 9410.L_ALT_op_invoke_super_range: /* 0x75 */ 9411/* File: mips64/alt_stub.S */ 9412/* 9413 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9414 * any interesting requests and then jump to the real instruction 9415 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9416 */ 9417 .extern MterpCheckBefore 9418 REFRESH_IBASE 9419 dla ra, artMterpAsmInstructionStart 9420 dla t9, MterpCheckBefore 9421 move a0, rSELF 9422 daddu a1, rFP, OFF_FP_SHADOWFRAME 9423 move a2, rPC 9424 daddu ra, ra, (117 * 128) # Addr of primary handler. 9425 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9426 9427/* ------------------------------ */ 9428 .balign 128 9429.L_ALT_op_invoke_direct_range: /* 0x76 */ 9430/* File: mips64/alt_stub.S */ 9431/* 9432 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9433 * any interesting requests and then jump to the real instruction 9434 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9435 */ 9436 .extern MterpCheckBefore 9437 REFRESH_IBASE 9438 dla ra, artMterpAsmInstructionStart 9439 dla t9, MterpCheckBefore 9440 move a0, rSELF 9441 daddu a1, rFP, OFF_FP_SHADOWFRAME 9442 move a2, rPC 9443 daddu ra, ra, (118 * 128) # Addr of primary handler. 9444 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9445 9446/* ------------------------------ */ 9447 .balign 128 9448.L_ALT_op_invoke_static_range: /* 0x77 */ 9449/* File: mips64/alt_stub.S */ 9450/* 9451 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9452 * any interesting requests and then jump to the real instruction 9453 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9454 */ 9455 .extern MterpCheckBefore 9456 REFRESH_IBASE 9457 dla ra, artMterpAsmInstructionStart 9458 dla t9, MterpCheckBefore 9459 move a0, rSELF 9460 daddu a1, rFP, OFF_FP_SHADOWFRAME 9461 move a2, rPC 9462 daddu ra, ra, (119 * 128) # Addr of primary handler. 9463 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9464 9465/* ------------------------------ */ 9466 .balign 128 9467.L_ALT_op_invoke_interface_range: /* 0x78 */ 9468/* File: mips64/alt_stub.S */ 9469/* 9470 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9471 * any interesting requests and then jump to the real instruction 9472 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9473 */ 9474 .extern MterpCheckBefore 9475 REFRESH_IBASE 9476 dla ra, artMterpAsmInstructionStart 9477 dla t9, MterpCheckBefore 9478 move a0, rSELF 9479 daddu a1, rFP, OFF_FP_SHADOWFRAME 9480 move a2, rPC 9481 daddu ra, ra, (120 * 128) # Addr of primary handler. 9482 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9483 9484/* ------------------------------ */ 9485 .balign 128 9486.L_ALT_op_unused_79: /* 0x79 */ 9487/* File: mips64/alt_stub.S */ 9488/* 9489 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9490 * any interesting requests and then jump to the real instruction 9491 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9492 */ 9493 .extern MterpCheckBefore 9494 REFRESH_IBASE 9495 dla ra, artMterpAsmInstructionStart 9496 dla t9, MterpCheckBefore 9497 move a0, rSELF 9498 daddu a1, rFP, OFF_FP_SHADOWFRAME 9499 move a2, rPC 9500 daddu ra, ra, (121 * 128) # Addr of primary handler. 9501 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9502 9503/* ------------------------------ */ 9504 .balign 128 9505.L_ALT_op_unused_7a: /* 0x7a */ 9506/* File: mips64/alt_stub.S */ 9507/* 9508 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9509 * any interesting requests and then jump to the real instruction 9510 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9511 */ 9512 .extern MterpCheckBefore 9513 REFRESH_IBASE 9514 dla ra, artMterpAsmInstructionStart 9515 dla t9, MterpCheckBefore 9516 move a0, rSELF 9517 daddu a1, rFP, OFF_FP_SHADOWFRAME 9518 move a2, rPC 9519 daddu ra, ra, (122 * 128) # Addr of primary handler. 9520 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9521 9522/* ------------------------------ */ 9523 .balign 128 9524.L_ALT_op_neg_int: /* 0x7b */ 9525/* File: mips64/alt_stub.S */ 9526/* 9527 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9528 * any interesting requests and then jump to the real instruction 9529 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9530 */ 9531 .extern MterpCheckBefore 9532 REFRESH_IBASE 9533 dla ra, artMterpAsmInstructionStart 9534 dla t9, MterpCheckBefore 9535 move a0, rSELF 9536 daddu a1, rFP, OFF_FP_SHADOWFRAME 9537 move a2, rPC 9538 daddu ra, ra, (123 * 128) # Addr of primary handler. 9539 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9540 9541/* ------------------------------ */ 9542 .balign 128 9543.L_ALT_op_not_int: /* 0x7c */ 9544/* File: mips64/alt_stub.S */ 9545/* 9546 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9547 * any interesting requests and then jump to the real instruction 9548 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9549 */ 9550 .extern MterpCheckBefore 9551 REFRESH_IBASE 9552 dla ra, artMterpAsmInstructionStart 9553 dla t9, MterpCheckBefore 9554 move a0, rSELF 9555 daddu a1, rFP, OFF_FP_SHADOWFRAME 9556 move a2, rPC 9557 daddu ra, ra, (124 * 128) # Addr of primary handler. 9558 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9559 9560/* ------------------------------ */ 9561 .balign 128 9562.L_ALT_op_neg_long: /* 0x7d */ 9563/* File: mips64/alt_stub.S */ 9564/* 9565 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9566 * any interesting requests and then jump to the real instruction 9567 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9568 */ 9569 .extern MterpCheckBefore 9570 REFRESH_IBASE 9571 dla ra, artMterpAsmInstructionStart 9572 dla t9, MterpCheckBefore 9573 move a0, rSELF 9574 daddu a1, rFP, OFF_FP_SHADOWFRAME 9575 move a2, rPC 9576 daddu ra, ra, (125 * 128) # Addr of primary handler. 9577 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9578 9579/* ------------------------------ */ 9580 .balign 128 9581.L_ALT_op_not_long: /* 0x7e */ 9582/* File: mips64/alt_stub.S */ 9583/* 9584 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9585 * any interesting requests and then jump to the real instruction 9586 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9587 */ 9588 .extern MterpCheckBefore 9589 REFRESH_IBASE 9590 dla ra, artMterpAsmInstructionStart 9591 dla t9, MterpCheckBefore 9592 move a0, rSELF 9593 daddu a1, rFP, OFF_FP_SHADOWFRAME 9594 move a2, rPC 9595 daddu ra, ra, (126 * 128) # Addr of primary handler. 9596 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9597 9598/* ------------------------------ */ 9599 .balign 128 9600.L_ALT_op_neg_float: /* 0x7f */ 9601/* File: mips64/alt_stub.S */ 9602/* 9603 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9604 * any interesting requests and then jump to the real instruction 9605 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9606 */ 9607 .extern MterpCheckBefore 9608 REFRESH_IBASE 9609 dla ra, artMterpAsmInstructionStart 9610 dla t9, MterpCheckBefore 9611 move a0, rSELF 9612 daddu a1, rFP, OFF_FP_SHADOWFRAME 9613 move a2, rPC 9614 daddu ra, ra, (127 * 128) # Addr of primary handler. 9615 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9616 9617/* ------------------------------ */ 9618 .balign 128 9619.L_ALT_op_neg_double: /* 0x80 */ 9620/* File: mips64/alt_stub.S */ 9621/* 9622 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9623 * any interesting requests and then jump to the real instruction 9624 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9625 */ 9626 .extern MterpCheckBefore 9627 REFRESH_IBASE 9628 dla ra, artMterpAsmInstructionStart 9629 dla t9, MterpCheckBefore 9630 move a0, rSELF 9631 daddu a1, rFP, OFF_FP_SHADOWFRAME 9632 move a2, rPC 9633 daddu ra, ra, (128 * 128) # Addr of primary handler. 9634 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9635 9636/* ------------------------------ */ 9637 .balign 128 9638.L_ALT_op_int_to_long: /* 0x81 */ 9639/* File: mips64/alt_stub.S */ 9640/* 9641 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9642 * any interesting requests and then jump to the real instruction 9643 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9644 */ 9645 .extern MterpCheckBefore 9646 REFRESH_IBASE 9647 dla ra, artMterpAsmInstructionStart 9648 dla t9, MterpCheckBefore 9649 move a0, rSELF 9650 daddu a1, rFP, OFF_FP_SHADOWFRAME 9651 move a2, rPC 9652 daddu ra, ra, (129 * 128) # Addr of primary handler. 9653 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9654 9655/* ------------------------------ */ 9656 .balign 128 9657.L_ALT_op_int_to_float: /* 0x82 */ 9658/* File: mips64/alt_stub.S */ 9659/* 9660 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9661 * any interesting requests and then jump to the real instruction 9662 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9663 */ 9664 .extern MterpCheckBefore 9665 REFRESH_IBASE 9666 dla ra, artMterpAsmInstructionStart 9667 dla t9, MterpCheckBefore 9668 move a0, rSELF 9669 daddu a1, rFP, OFF_FP_SHADOWFRAME 9670 move a2, rPC 9671 daddu ra, ra, (130 * 128) # Addr of primary handler. 9672 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9673 9674/* ------------------------------ */ 9675 .balign 128 9676.L_ALT_op_int_to_double: /* 0x83 */ 9677/* File: mips64/alt_stub.S */ 9678/* 9679 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9680 * any interesting requests and then jump to the real instruction 9681 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9682 */ 9683 .extern MterpCheckBefore 9684 REFRESH_IBASE 9685 dla ra, artMterpAsmInstructionStart 9686 dla t9, MterpCheckBefore 9687 move a0, rSELF 9688 daddu a1, rFP, OFF_FP_SHADOWFRAME 9689 move a2, rPC 9690 daddu ra, ra, (131 * 128) # Addr of primary handler. 9691 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9692 9693/* ------------------------------ */ 9694 .balign 128 9695.L_ALT_op_long_to_int: /* 0x84 */ 9696/* File: mips64/alt_stub.S */ 9697/* 9698 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9699 * any interesting requests and then jump to the real instruction 9700 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9701 */ 9702 .extern MterpCheckBefore 9703 REFRESH_IBASE 9704 dla ra, artMterpAsmInstructionStart 9705 dla t9, MterpCheckBefore 9706 move a0, rSELF 9707 daddu a1, rFP, OFF_FP_SHADOWFRAME 9708 move a2, rPC 9709 daddu ra, ra, (132 * 128) # Addr of primary handler. 9710 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9711 9712/* ------------------------------ */ 9713 .balign 128 9714.L_ALT_op_long_to_float: /* 0x85 */ 9715/* File: mips64/alt_stub.S */ 9716/* 9717 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9718 * any interesting requests and then jump to the real instruction 9719 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9720 */ 9721 .extern MterpCheckBefore 9722 REFRESH_IBASE 9723 dla ra, artMterpAsmInstructionStart 9724 dla t9, MterpCheckBefore 9725 move a0, rSELF 9726 daddu a1, rFP, OFF_FP_SHADOWFRAME 9727 move a2, rPC 9728 daddu ra, ra, (133 * 128) # Addr of primary handler. 9729 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9730 9731/* ------------------------------ */ 9732 .balign 128 9733.L_ALT_op_long_to_double: /* 0x86 */ 9734/* File: mips64/alt_stub.S */ 9735/* 9736 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9737 * any interesting requests and then jump to the real instruction 9738 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9739 */ 9740 .extern MterpCheckBefore 9741 REFRESH_IBASE 9742 dla ra, artMterpAsmInstructionStart 9743 dla t9, MterpCheckBefore 9744 move a0, rSELF 9745 daddu a1, rFP, OFF_FP_SHADOWFRAME 9746 move a2, rPC 9747 daddu ra, ra, (134 * 128) # Addr of primary handler. 9748 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9749 9750/* ------------------------------ */ 9751 .balign 128 9752.L_ALT_op_float_to_int: /* 0x87 */ 9753/* File: mips64/alt_stub.S */ 9754/* 9755 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9756 * any interesting requests and then jump to the real instruction 9757 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9758 */ 9759 .extern MterpCheckBefore 9760 REFRESH_IBASE 9761 dla ra, artMterpAsmInstructionStart 9762 dla t9, MterpCheckBefore 9763 move a0, rSELF 9764 daddu a1, rFP, OFF_FP_SHADOWFRAME 9765 move a2, rPC 9766 daddu ra, ra, (135 * 128) # Addr of primary handler. 9767 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9768 9769/* ------------------------------ */ 9770 .balign 128 9771.L_ALT_op_float_to_long: /* 0x88 */ 9772/* File: mips64/alt_stub.S */ 9773/* 9774 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9775 * any interesting requests and then jump to the real instruction 9776 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9777 */ 9778 .extern MterpCheckBefore 9779 REFRESH_IBASE 9780 dla ra, artMterpAsmInstructionStart 9781 dla t9, MterpCheckBefore 9782 move a0, rSELF 9783 daddu a1, rFP, OFF_FP_SHADOWFRAME 9784 move a2, rPC 9785 daddu ra, ra, (136 * 128) # Addr of primary handler. 9786 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9787 9788/* ------------------------------ */ 9789 .balign 128 9790.L_ALT_op_float_to_double: /* 0x89 */ 9791/* File: mips64/alt_stub.S */ 9792/* 9793 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9794 * any interesting requests and then jump to the real instruction 9795 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9796 */ 9797 .extern MterpCheckBefore 9798 REFRESH_IBASE 9799 dla ra, artMterpAsmInstructionStart 9800 dla t9, MterpCheckBefore 9801 move a0, rSELF 9802 daddu a1, rFP, OFF_FP_SHADOWFRAME 9803 move a2, rPC 9804 daddu ra, ra, (137 * 128) # Addr of primary handler. 9805 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9806 9807/* ------------------------------ */ 9808 .balign 128 9809.L_ALT_op_double_to_int: /* 0x8a */ 9810/* File: mips64/alt_stub.S */ 9811/* 9812 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9813 * any interesting requests and then jump to the real instruction 9814 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9815 */ 9816 .extern MterpCheckBefore 9817 REFRESH_IBASE 9818 dla ra, artMterpAsmInstructionStart 9819 dla t9, MterpCheckBefore 9820 move a0, rSELF 9821 daddu a1, rFP, OFF_FP_SHADOWFRAME 9822 move a2, rPC 9823 daddu ra, ra, (138 * 128) # Addr of primary handler. 9824 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9825 9826/* ------------------------------ */ 9827 .balign 128 9828.L_ALT_op_double_to_long: /* 0x8b */ 9829/* File: mips64/alt_stub.S */ 9830/* 9831 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9832 * any interesting requests and then jump to the real instruction 9833 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9834 */ 9835 .extern MterpCheckBefore 9836 REFRESH_IBASE 9837 dla ra, artMterpAsmInstructionStart 9838 dla t9, MterpCheckBefore 9839 move a0, rSELF 9840 daddu a1, rFP, OFF_FP_SHADOWFRAME 9841 move a2, rPC 9842 daddu ra, ra, (139 * 128) # Addr of primary handler. 9843 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9844 9845/* ------------------------------ */ 9846 .balign 128 9847.L_ALT_op_double_to_float: /* 0x8c */ 9848/* File: mips64/alt_stub.S */ 9849/* 9850 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9851 * any interesting requests and then jump to the real instruction 9852 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9853 */ 9854 .extern MterpCheckBefore 9855 REFRESH_IBASE 9856 dla ra, artMterpAsmInstructionStart 9857 dla t9, MterpCheckBefore 9858 move a0, rSELF 9859 daddu a1, rFP, OFF_FP_SHADOWFRAME 9860 move a2, rPC 9861 daddu ra, ra, (140 * 128) # Addr of primary handler. 9862 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9863 9864/* ------------------------------ */ 9865 .balign 128 9866.L_ALT_op_int_to_byte: /* 0x8d */ 9867/* File: mips64/alt_stub.S */ 9868/* 9869 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9870 * any interesting requests and then jump to the real instruction 9871 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9872 */ 9873 .extern MterpCheckBefore 9874 REFRESH_IBASE 9875 dla ra, artMterpAsmInstructionStart 9876 dla t9, MterpCheckBefore 9877 move a0, rSELF 9878 daddu a1, rFP, OFF_FP_SHADOWFRAME 9879 move a2, rPC 9880 daddu ra, ra, (141 * 128) # Addr of primary handler. 9881 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9882 9883/* ------------------------------ */ 9884 .balign 128 9885.L_ALT_op_int_to_char: /* 0x8e */ 9886/* File: mips64/alt_stub.S */ 9887/* 9888 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9889 * any interesting requests and then jump to the real instruction 9890 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9891 */ 9892 .extern MterpCheckBefore 9893 REFRESH_IBASE 9894 dla ra, artMterpAsmInstructionStart 9895 dla t9, MterpCheckBefore 9896 move a0, rSELF 9897 daddu a1, rFP, OFF_FP_SHADOWFRAME 9898 move a2, rPC 9899 daddu ra, ra, (142 * 128) # Addr of primary handler. 9900 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9901 9902/* ------------------------------ */ 9903 .balign 128 9904.L_ALT_op_int_to_short: /* 0x8f */ 9905/* File: mips64/alt_stub.S */ 9906/* 9907 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9908 * any interesting requests and then jump to the real instruction 9909 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9910 */ 9911 .extern MterpCheckBefore 9912 REFRESH_IBASE 9913 dla ra, artMterpAsmInstructionStart 9914 dla t9, MterpCheckBefore 9915 move a0, rSELF 9916 daddu a1, rFP, OFF_FP_SHADOWFRAME 9917 move a2, rPC 9918 daddu ra, ra, (143 * 128) # Addr of primary handler. 9919 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9920 9921/* ------------------------------ */ 9922 .balign 128 9923.L_ALT_op_add_int: /* 0x90 */ 9924/* File: mips64/alt_stub.S */ 9925/* 9926 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9927 * any interesting requests and then jump to the real instruction 9928 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9929 */ 9930 .extern MterpCheckBefore 9931 REFRESH_IBASE 9932 dla ra, artMterpAsmInstructionStart 9933 dla t9, MterpCheckBefore 9934 move a0, rSELF 9935 daddu a1, rFP, OFF_FP_SHADOWFRAME 9936 move a2, rPC 9937 daddu ra, ra, (144 * 128) # Addr of primary handler. 9938 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9939 9940/* ------------------------------ */ 9941 .balign 128 9942.L_ALT_op_sub_int: /* 0x91 */ 9943/* File: mips64/alt_stub.S */ 9944/* 9945 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9946 * any interesting requests and then jump to the real instruction 9947 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9948 */ 9949 .extern MterpCheckBefore 9950 REFRESH_IBASE 9951 dla ra, artMterpAsmInstructionStart 9952 dla t9, MterpCheckBefore 9953 move a0, rSELF 9954 daddu a1, rFP, OFF_FP_SHADOWFRAME 9955 move a2, rPC 9956 daddu ra, ra, (145 * 128) # Addr of primary handler. 9957 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9958 9959/* ------------------------------ */ 9960 .balign 128 9961.L_ALT_op_mul_int: /* 0x92 */ 9962/* File: mips64/alt_stub.S */ 9963/* 9964 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9965 * any interesting requests and then jump to the real instruction 9966 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9967 */ 9968 .extern MterpCheckBefore 9969 REFRESH_IBASE 9970 dla ra, artMterpAsmInstructionStart 9971 dla t9, MterpCheckBefore 9972 move a0, rSELF 9973 daddu a1, rFP, OFF_FP_SHADOWFRAME 9974 move a2, rPC 9975 daddu ra, ra, (146 * 128) # Addr of primary handler. 9976 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9977 9978/* ------------------------------ */ 9979 .balign 128 9980.L_ALT_op_div_int: /* 0x93 */ 9981/* File: mips64/alt_stub.S */ 9982/* 9983 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 9984 * any interesting requests and then jump to the real instruction 9985 * handler. Note that the call to MterpCheckBefore is done as a tail call. 9986 */ 9987 .extern MterpCheckBefore 9988 REFRESH_IBASE 9989 dla ra, artMterpAsmInstructionStart 9990 dla t9, MterpCheckBefore 9991 move a0, rSELF 9992 daddu a1, rFP, OFF_FP_SHADOWFRAME 9993 move a2, rPC 9994 daddu ra, ra, (147 * 128) # Addr of primary handler. 9995 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 9996 9997/* ------------------------------ */ 9998 .balign 128 9999.L_ALT_op_rem_int: /* 0x94 */ 10000/* File: mips64/alt_stub.S */ 10001/* 10002 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10003 * any interesting requests and then jump to the real instruction 10004 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10005 */ 10006 .extern MterpCheckBefore 10007 REFRESH_IBASE 10008 dla ra, artMterpAsmInstructionStart 10009 dla t9, MterpCheckBefore 10010 move a0, rSELF 10011 daddu a1, rFP, OFF_FP_SHADOWFRAME 10012 move a2, rPC 10013 daddu ra, ra, (148 * 128) # Addr of primary handler. 10014 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10015 10016/* ------------------------------ */ 10017 .balign 128 10018.L_ALT_op_and_int: /* 0x95 */ 10019/* File: mips64/alt_stub.S */ 10020/* 10021 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10022 * any interesting requests and then jump to the real instruction 10023 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10024 */ 10025 .extern MterpCheckBefore 10026 REFRESH_IBASE 10027 dla ra, artMterpAsmInstructionStart 10028 dla t9, MterpCheckBefore 10029 move a0, rSELF 10030 daddu a1, rFP, OFF_FP_SHADOWFRAME 10031 move a2, rPC 10032 daddu ra, ra, (149 * 128) # Addr of primary handler. 10033 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10034 10035/* ------------------------------ */ 10036 .balign 128 10037.L_ALT_op_or_int: /* 0x96 */ 10038/* File: mips64/alt_stub.S */ 10039/* 10040 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10041 * any interesting requests and then jump to the real instruction 10042 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10043 */ 10044 .extern MterpCheckBefore 10045 REFRESH_IBASE 10046 dla ra, artMterpAsmInstructionStart 10047 dla t9, MterpCheckBefore 10048 move a0, rSELF 10049 daddu a1, rFP, OFF_FP_SHADOWFRAME 10050 move a2, rPC 10051 daddu ra, ra, (150 * 128) # Addr of primary handler. 10052 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10053 10054/* ------------------------------ */ 10055 .balign 128 10056.L_ALT_op_xor_int: /* 0x97 */ 10057/* File: mips64/alt_stub.S */ 10058/* 10059 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10060 * any interesting requests and then jump to the real instruction 10061 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10062 */ 10063 .extern MterpCheckBefore 10064 REFRESH_IBASE 10065 dla ra, artMterpAsmInstructionStart 10066 dla t9, MterpCheckBefore 10067 move a0, rSELF 10068 daddu a1, rFP, OFF_FP_SHADOWFRAME 10069 move a2, rPC 10070 daddu ra, ra, (151 * 128) # Addr of primary handler. 10071 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10072 10073/* ------------------------------ */ 10074 .balign 128 10075.L_ALT_op_shl_int: /* 0x98 */ 10076/* File: mips64/alt_stub.S */ 10077/* 10078 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10079 * any interesting requests and then jump to the real instruction 10080 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10081 */ 10082 .extern MterpCheckBefore 10083 REFRESH_IBASE 10084 dla ra, artMterpAsmInstructionStart 10085 dla t9, MterpCheckBefore 10086 move a0, rSELF 10087 daddu a1, rFP, OFF_FP_SHADOWFRAME 10088 move a2, rPC 10089 daddu ra, ra, (152 * 128) # Addr of primary handler. 10090 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10091 10092/* ------------------------------ */ 10093 .balign 128 10094.L_ALT_op_shr_int: /* 0x99 */ 10095/* File: mips64/alt_stub.S */ 10096/* 10097 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10098 * any interesting requests and then jump to the real instruction 10099 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10100 */ 10101 .extern MterpCheckBefore 10102 REFRESH_IBASE 10103 dla ra, artMterpAsmInstructionStart 10104 dla t9, MterpCheckBefore 10105 move a0, rSELF 10106 daddu a1, rFP, OFF_FP_SHADOWFRAME 10107 move a2, rPC 10108 daddu ra, ra, (153 * 128) # Addr of primary handler. 10109 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10110 10111/* ------------------------------ */ 10112 .balign 128 10113.L_ALT_op_ushr_int: /* 0x9a */ 10114/* File: mips64/alt_stub.S */ 10115/* 10116 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10117 * any interesting requests and then jump to the real instruction 10118 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10119 */ 10120 .extern MterpCheckBefore 10121 REFRESH_IBASE 10122 dla ra, artMterpAsmInstructionStart 10123 dla t9, MterpCheckBefore 10124 move a0, rSELF 10125 daddu a1, rFP, OFF_FP_SHADOWFRAME 10126 move a2, rPC 10127 daddu ra, ra, (154 * 128) # Addr of primary handler. 10128 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10129 10130/* ------------------------------ */ 10131 .balign 128 10132.L_ALT_op_add_long: /* 0x9b */ 10133/* File: mips64/alt_stub.S */ 10134/* 10135 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10136 * any interesting requests and then jump to the real instruction 10137 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10138 */ 10139 .extern MterpCheckBefore 10140 REFRESH_IBASE 10141 dla ra, artMterpAsmInstructionStart 10142 dla t9, MterpCheckBefore 10143 move a0, rSELF 10144 daddu a1, rFP, OFF_FP_SHADOWFRAME 10145 move a2, rPC 10146 daddu ra, ra, (155 * 128) # Addr of primary handler. 10147 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10148 10149/* ------------------------------ */ 10150 .balign 128 10151.L_ALT_op_sub_long: /* 0x9c */ 10152/* File: mips64/alt_stub.S */ 10153/* 10154 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10155 * any interesting requests and then jump to the real instruction 10156 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10157 */ 10158 .extern MterpCheckBefore 10159 REFRESH_IBASE 10160 dla ra, artMterpAsmInstructionStart 10161 dla t9, MterpCheckBefore 10162 move a0, rSELF 10163 daddu a1, rFP, OFF_FP_SHADOWFRAME 10164 move a2, rPC 10165 daddu ra, ra, (156 * 128) # Addr of primary handler. 10166 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10167 10168/* ------------------------------ */ 10169 .balign 128 10170.L_ALT_op_mul_long: /* 0x9d */ 10171/* File: mips64/alt_stub.S */ 10172/* 10173 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10174 * any interesting requests and then jump to the real instruction 10175 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10176 */ 10177 .extern MterpCheckBefore 10178 REFRESH_IBASE 10179 dla ra, artMterpAsmInstructionStart 10180 dla t9, MterpCheckBefore 10181 move a0, rSELF 10182 daddu a1, rFP, OFF_FP_SHADOWFRAME 10183 move a2, rPC 10184 daddu ra, ra, (157 * 128) # Addr of primary handler. 10185 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10186 10187/* ------------------------------ */ 10188 .balign 128 10189.L_ALT_op_div_long: /* 0x9e */ 10190/* File: mips64/alt_stub.S */ 10191/* 10192 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10193 * any interesting requests and then jump to the real instruction 10194 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10195 */ 10196 .extern MterpCheckBefore 10197 REFRESH_IBASE 10198 dla ra, artMterpAsmInstructionStart 10199 dla t9, MterpCheckBefore 10200 move a0, rSELF 10201 daddu a1, rFP, OFF_FP_SHADOWFRAME 10202 move a2, rPC 10203 daddu ra, ra, (158 * 128) # Addr of primary handler. 10204 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10205 10206/* ------------------------------ */ 10207 .balign 128 10208.L_ALT_op_rem_long: /* 0x9f */ 10209/* File: mips64/alt_stub.S */ 10210/* 10211 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10212 * any interesting requests and then jump to the real instruction 10213 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10214 */ 10215 .extern MterpCheckBefore 10216 REFRESH_IBASE 10217 dla ra, artMterpAsmInstructionStart 10218 dla t9, MterpCheckBefore 10219 move a0, rSELF 10220 daddu a1, rFP, OFF_FP_SHADOWFRAME 10221 move a2, rPC 10222 daddu ra, ra, (159 * 128) # Addr of primary handler. 10223 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10224 10225/* ------------------------------ */ 10226 .balign 128 10227.L_ALT_op_and_long: /* 0xa0 */ 10228/* File: mips64/alt_stub.S */ 10229/* 10230 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10231 * any interesting requests and then jump to the real instruction 10232 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10233 */ 10234 .extern MterpCheckBefore 10235 REFRESH_IBASE 10236 dla ra, artMterpAsmInstructionStart 10237 dla t9, MterpCheckBefore 10238 move a0, rSELF 10239 daddu a1, rFP, OFF_FP_SHADOWFRAME 10240 move a2, rPC 10241 daddu ra, ra, (160 * 128) # Addr of primary handler. 10242 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10243 10244/* ------------------------------ */ 10245 .balign 128 10246.L_ALT_op_or_long: /* 0xa1 */ 10247/* File: mips64/alt_stub.S */ 10248/* 10249 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10250 * any interesting requests and then jump to the real instruction 10251 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10252 */ 10253 .extern MterpCheckBefore 10254 REFRESH_IBASE 10255 dla ra, artMterpAsmInstructionStart 10256 dla t9, MterpCheckBefore 10257 move a0, rSELF 10258 daddu a1, rFP, OFF_FP_SHADOWFRAME 10259 move a2, rPC 10260 daddu ra, ra, (161 * 128) # Addr of primary handler. 10261 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10262 10263/* ------------------------------ */ 10264 .balign 128 10265.L_ALT_op_xor_long: /* 0xa2 */ 10266/* File: mips64/alt_stub.S */ 10267/* 10268 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10269 * any interesting requests and then jump to the real instruction 10270 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10271 */ 10272 .extern MterpCheckBefore 10273 REFRESH_IBASE 10274 dla ra, artMterpAsmInstructionStart 10275 dla t9, MterpCheckBefore 10276 move a0, rSELF 10277 daddu a1, rFP, OFF_FP_SHADOWFRAME 10278 move a2, rPC 10279 daddu ra, ra, (162 * 128) # Addr of primary handler. 10280 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10281 10282/* ------------------------------ */ 10283 .balign 128 10284.L_ALT_op_shl_long: /* 0xa3 */ 10285/* File: mips64/alt_stub.S */ 10286/* 10287 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10288 * any interesting requests and then jump to the real instruction 10289 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10290 */ 10291 .extern MterpCheckBefore 10292 REFRESH_IBASE 10293 dla ra, artMterpAsmInstructionStart 10294 dla t9, MterpCheckBefore 10295 move a0, rSELF 10296 daddu a1, rFP, OFF_FP_SHADOWFRAME 10297 move a2, rPC 10298 daddu ra, ra, (163 * 128) # Addr of primary handler. 10299 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10300 10301/* ------------------------------ */ 10302 .balign 128 10303.L_ALT_op_shr_long: /* 0xa4 */ 10304/* File: mips64/alt_stub.S */ 10305/* 10306 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10307 * any interesting requests and then jump to the real instruction 10308 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10309 */ 10310 .extern MterpCheckBefore 10311 REFRESH_IBASE 10312 dla ra, artMterpAsmInstructionStart 10313 dla t9, MterpCheckBefore 10314 move a0, rSELF 10315 daddu a1, rFP, OFF_FP_SHADOWFRAME 10316 move a2, rPC 10317 daddu ra, ra, (164 * 128) # Addr of primary handler. 10318 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10319 10320/* ------------------------------ */ 10321 .balign 128 10322.L_ALT_op_ushr_long: /* 0xa5 */ 10323/* File: mips64/alt_stub.S */ 10324/* 10325 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10326 * any interesting requests and then jump to the real instruction 10327 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10328 */ 10329 .extern MterpCheckBefore 10330 REFRESH_IBASE 10331 dla ra, artMterpAsmInstructionStart 10332 dla t9, MterpCheckBefore 10333 move a0, rSELF 10334 daddu a1, rFP, OFF_FP_SHADOWFRAME 10335 move a2, rPC 10336 daddu ra, ra, (165 * 128) # Addr of primary handler. 10337 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10338 10339/* ------------------------------ */ 10340 .balign 128 10341.L_ALT_op_add_float: /* 0xa6 */ 10342/* File: mips64/alt_stub.S */ 10343/* 10344 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10345 * any interesting requests and then jump to the real instruction 10346 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10347 */ 10348 .extern MterpCheckBefore 10349 REFRESH_IBASE 10350 dla ra, artMterpAsmInstructionStart 10351 dla t9, MterpCheckBefore 10352 move a0, rSELF 10353 daddu a1, rFP, OFF_FP_SHADOWFRAME 10354 move a2, rPC 10355 daddu ra, ra, (166 * 128) # Addr of primary handler. 10356 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10357 10358/* ------------------------------ */ 10359 .balign 128 10360.L_ALT_op_sub_float: /* 0xa7 */ 10361/* File: mips64/alt_stub.S */ 10362/* 10363 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10364 * any interesting requests and then jump to the real instruction 10365 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10366 */ 10367 .extern MterpCheckBefore 10368 REFRESH_IBASE 10369 dla ra, artMterpAsmInstructionStart 10370 dla t9, MterpCheckBefore 10371 move a0, rSELF 10372 daddu a1, rFP, OFF_FP_SHADOWFRAME 10373 move a2, rPC 10374 daddu ra, ra, (167 * 128) # Addr of primary handler. 10375 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10376 10377/* ------------------------------ */ 10378 .balign 128 10379.L_ALT_op_mul_float: /* 0xa8 */ 10380/* File: mips64/alt_stub.S */ 10381/* 10382 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10383 * any interesting requests and then jump to the real instruction 10384 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10385 */ 10386 .extern MterpCheckBefore 10387 REFRESH_IBASE 10388 dla ra, artMterpAsmInstructionStart 10389 dla t9, MterpCheckBefore 10390 move a0, rSELF 10391 daddu a1, rFP, OFF_FP_SHADOWFRAME 10392 move a2, rPC 10393 daddu ra, ra, (168 * 128) # Addr of primary handler. 10394 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10395 10396/* ------------------------------ */ 10397 .balign 128 10398.L_ALT_op_div_float: /* 0xa9 */ 10399/* File: mips64/alt_stub.S */ 10400/* 10401 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10402 * any interesting requests and then jump to the real instruction 10403 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10404 */ 10405 .extern MterpCheckBefore 10406 REFRESH_IBASE 10407 dla ra, artMterpAsmInstructionStart 10408 dla t9, MterpCheckBefore 10409 move a0, rSELF 10410 daddu a1, rFP, OFF_FP_SHADOWFRAME 10411 move a2, rPC 10412 daddu ra, ra, (169 * 128) # Addr of primary handler. 10413 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10414 10415/* ------------------------------ */ 10416 .balign 128 10417.L_ALT_op_rem_float: /* 0xaa */ 10418/* File: mips64/alt_stub.S */ 10419/* 10420 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10421 * any interesting requests and then jump to the real instruction 10422 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10423 */ 10424 .extern MterpCheckBefore 10425 REFRESH_IBASE 10426 dla ra, artMterpAsmInstructionStart 10427 dla t9, MterpCheckBefore 10428 move a0, rSELF 10429 daddu a1, rFP, OFF_FP_SHADOWFRAME 10430 move a2, rPC 10431 daddu ra, ra, (170 * 128) # Addr of primary handler. 10432 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10433 10434/* ------------------------------ */ 10435 .balign 128 10436.L_ALT_op_add_double: /* 0xab */ 10437/* File: mips64/alt_stub.S */ 10438/* 10439 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10440 * any interesting requests and then jump to the real instruction 10441 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10442 */ 10443 .extern MterpCheckBefore 10444 REFRESH_IBASE 10445 dla ra, artMterpAsmInstructionStart 10446 dla t9, MterpCheckBefore 10447 move a0, rSELF 10448 daddu a1, rFP, OFF_FP_SHADOWFRAME 10449 move a2, rPC 10450 daddu ra, ra, (171 * 128) # Addr of primary handler. 10451 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10452 10453/* ------------------------------ */ 10454 .balign 128 10455.L_ALT_op_sub_double: /* 0xac */ 10456/* File: mips64/alt_stub.S */ 10457/* 10458 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10459 * any interesting requests and then jump to the real instruction 10460 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10461 */ 10462 .extern MterpCheckBefore 10463 REFRESH_IBASE 10464 dla ra, artMterpAsmInstructionStart 10465 dla t9, MterpCheckBefore 10466 move a0, rSELF 10467 daddu a1, rFP, OFF_FP_SHADOWFRAME 10468 move a2, rPC 10469 daddu ra, ra, (172 * 128) # Addr of primary handler. 10470 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10471 10472/* ------------------------------ */ 10473 .balign 128 10474.L_ALT_op_mul_double: /* 0xad */ 10475/* File: mips64/alt_stub.S */ 10476/* 10477 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10478 * any interesting requests and then jump to the real instruction 10479 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10480 */ 10481 .extern MterpCheckBefore 10482 REFRESH_IBASE 10483 dla ra, artMterpAsmInstructionStart 10484 dla t9, MterpCheckBefore 10485 move a0, rSELF 10486 daddu a1, rFP, OFF_FP_SHADOWFRAME 10487 move a2, rPC 10488 daddu ra, ra, (173 * 128) # Addr of primary handler. 10489 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10490 10491/* ------------------------------ */ 10492 .balign 128 10493.L_ALT_op_div_double: /* 0xae */ 10494/* File: mips64/alt_stub.S */ 10495/* 10496 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10497 * any interesting requests and then jump to the real instruction 10498 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10499 */ 10500 .extern MterpCheckBefore 10501 REFRESH_IBASE 10502 dla ra, artMterpAsmInstructionStart 10503 dla t9, MterpCheckBefore 10504 move a0, rSELF 10505 daddu a1, rFP, OFF_FP_SHADOWFRAME 10506 move a2, rPC 10507 daddu ra, ra, (174 * 128) # Addr of primary handler. 10508 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10509 10510/* ------------------------------ */ 10511 .balign 128 10512.L_ALT_op_rem_double: /* 0xaf */ 10513/* File: mips64/alt_stub.S */ 10514/* 10515 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10516 * any interesting requests and then jump to the real instruction 10517 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10518 */ 10519 .extern MterpCheckBefore 10520 REFRESH_IBASE 10521 dla ra, artMterpAsmInstructionStart 10522 dla t9, MterpCheckBefore 10523 move a0, rSELF 10524 daddu a1, rFP, OFF_FP_SHADOWFRAME 10525 move a2, rPC 10526 daddu ra, ra, (175 * 128) # Addr of primary handler. 10527 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10528 10529/* ------------------------------ */ 10530 .balign 128 10531.L_ALT_op_add_int_2addr: /* 0xb0 */ 10532/* File: mips64/alt_stub.S */ 10533/* 10534 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10535 * any interesting requests and then jump to the real instruction 10536 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10537 */ 10538 .extern MterpCheckBefore 10539 REFRESH_IBASE 10540 dla ra, artMterpAsmInstructionStart 10541 dla t9, MterpCheckBefore 10542 move a0, rSELF 10543 daddu a1, rFP, OFF_FP_SHADOWFRAME 10544 move a2, rPC 10545 daddu ra, ra, (176 * 128) # Addr of primary handler. 10546 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10547 10548/* ------------------------------ */ 10549 .balign 128 10550.L_ALT_op_sub_int_2addr: /* 0xb1 */ 10551/* File: mips64/alt_stub.S */ 10552/* 10553 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10554 * any interesting requests and then jump to the real instruction 10555 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10556 */ 10557 .extern MterpCheckBefore 10558 REFRESH_IBASE 10559 dla ra, artMterpAsmInstructionStart 10560 dla t9, MterpCheckBefore 10561 move a0, rSELF 10562 daddu a1, rFP, OFF_FP_SHADOWFRAME 10563 move a2, rPC 10564 daddu ra, ra, (177 * 128) # Addr of primary handler. 10565 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10566 10567/* ------------------------------ */ 10568 .balign 128 10569.L_ALT_op_mul_int_2addr: /* 0xb2 */ 10570/* File: mips64/alt_stub.S */ 10571/* 10572 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10573 * any interesting requests and then jump to the real instruction 10574 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10575 */ 10576 .extern MterpCheckBefore 10577 REFRESH_IBASE 10578 dla ra, artMterpAsmInstructionStart 10579 dla t9, MterpCheckBefore 10580 move a0, rSELF 10581 daddu a1, rFP, OFF_FP_SHADOWFRAME 10582 move a2, rPC 10583 daddu ra, ra, (178 * 128) # Addr of primary handler. 10584 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10585 10586/* ------------------------------ */ 10587 .balign 128 10588.L_ALT_op_div_int_2addr: /* 0xb3 */ 10589/* File: mips64/alt_stub.S */ 10590/* 10591 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10592 * any interesting requests and then jump to the real instruction 10593 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10594 */ 10595 .extern MterpCheckBefore 10596 REFRESH_IBASE 10597 dla ra, artMterpAsmInstructionStart 10598 dla t9, MterpCheckBefore 10599 move a0, rSELF 10600 daddu a1, rFP, OFF_FP_SHADOWFRAME 10601 move a2, rPC 10602 daddu ra, ra, (179 * 128) # Addr of primary handler. 10603 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10604 10605/* ------------------------------ */ 10606 .balign 128 10607.L_ALT_op_rem_int_2addr: /* 0xb4 */ 10608/* File: mips64/alt_stub.S */ 10609/* 10610 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10611 * any interesting requests and then jump to the real instruction 10612 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10613 */ 10614 .extern MterpCheckBefore 10615 REFRESH_IBASE 10616 dla ra, artMterpAsmInstructionStart 10617 dla t9, MterpCheckBefore 10618 move a0, rSELF 10619 daddu a1, rFP, OFF_FP_SHADOWFRAME 10620 move a2, rPC 10621 daddu ra, ra, (180 * 128) # Addr of primary handler. 10622 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10623 10624/* ------------------------------ */ 10625 .balign 128 10626.L_ALT_op_and_int_2addr: /* 0xb5 */ 10627/* File: mips64/alt_stub.S */ 10628/* 10629 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10630 * any interesting requests and then jump to the real instruction 10631 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10632 */ 10633 .extern MterpCheckBefore 10634 REFRESH_IBASE 10635 dla ra, artMterpAsmInstructionStart 10636 dla t9, MterpCheckBefore 10637 move a0, rSELF 10638 daddu a1, rFP, OFF_FP_SHADOWFRAME 10639 move a2, rPC 10640 daddu ra, ra, (181 * 128) # Addr of primary handler. 10641 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10642 10643/* ------------------------------ */ 10644 .balign 128 10645.L_ALT_op_or_int_2addr: /* 0xb6 */ 10646/* File: mips64/alt_stub.S */ 10647/* 10648 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10649 * any interesting requests and then jump to the real instruction 10650 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10651 */ 10652 .extern MterpCheckBefore 10653 REFRESH_IBASE 10654 dla ra, artMterpAsmInstructionStart 10655 dla t9, MterpCheckBefore 10656 move a0, rSELF 10657 daddu a1, rFP, OFF_FP_SHADOWFRAME 10658 move a2, rPC 10659 daddu ra, ra, (182 * 128) # Addr of primary handler. 10660 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10661 10662/* ------------------------------ */ 10663 .balign 128 10664.L_ALT_op_xor_int_2addr: /* 0xb7 */ 10665/* File: mips64/alt_stub.S */ 10666/* 10667 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10668 * any interesting requests and then jump to the real instruction 10669 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10670 */ 10671 .extern MterpCheckBefore 10672 REFRESH_IBASE 10673 dla ra, artMterpAsmInstructionStart 10674 dla t9, MterpCheckBefore 10675 move a0, rSELF 10676 daddu a1, rFP, OFF_FP_SHADOWFRAME 10677 move a2, rPC 10678 daddu ra, ra, (183 * 128) # Addr of primary handler. 10679 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10680 10681/* ------------------------------ */ 10682 .balign 128 10683.L_ALT_op_shl_int_2addr: /* 0xb8 */ 10684/* File: mips64/alt_stub.S */ 10685/* 10686 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10687 * any interesting requests and then jump to the real instruction 10688 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10689 */ 10690 .extern MterpCheckBefore 10691 REFRESH_IBASE 10692 dla ra, artMterpAsmInstructionStart 10693 dla t9, MterpCheckBefore 10694 move a0, rSELF 10695 daddu a1, rFP, OFF_FP_SHADOWFRAME 10696 move a2, rPC 10697 daddu ra, ra, (184 * 128) # Addr of primary handler. 10698 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10699 10700/* ------------------------------ */ 10701 .balign 128 10702.L_ALT_op_shr_int_2addr: /* 0xb9 */ 10703/* File: mips64/alt_stub.S */ 10704/* 10705 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10706 * any interesting requests and then jump to the real instruction 10707 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10708 */ 10709 .extern MterpCheckBefore 10710 REFRESH_IBASE 10711 dla ra, artMterpAsmInstructionStart 10712 dla t9, MterpCheckBefore 10713 move a0, rSELF 10714 daddu a1, rFP, OFF_FP_SHADOWFRAME 10715 move a2, rPC 10716 daddu ra, ra, (185 * 128) # Addr of primary handler. 10717 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10718 10719/* ------------------------------ */ 10720 .balign 128 10721.L_ALT_op_ushr_int_2addr: /* 0xba */ 10722/* File: mips64/alt_stub.S */ 10723/* 10724 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10725 * any interesting requests and then jump to the real instruction 10726 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10727 */ 10728 .extern MterpCheckBefore 10729 REFRESH_IBASE 10730 dla ra, artMterpAsmInstructionStart 10731 dla t9, MterpCheckBefore 10732 move a0, rSELF 10733 daddu a1, rFP, OFF_FP_SHADOWFRAME 10734 move a2, rPC 10735 daddu ra, ra, (186 * 128) # Addr of primary handler. 10736 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10737 10738/* ------------------------------ */ 10739 .balign 128 10740.L_ALT_op_add_long_2addr: /* 0xbb */ 10741/* File: mips64/alt_stub.S */ 10742/* 10743 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10744 * any interesting requests and then jump to the real instruction 10745 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10746 */ 10747 .extern MterpCheckBefore 10748 REFRESH_IBASE 10749 dla ra, artMterpAsmInstructionStart 10750 dla t9, MterpCheckBefore 10751 move a0, rSELF 10752 daddu a1, rFP, OFF_FP_SHADOWFRAME 10753 move a2, rPC 10754 daddu ra, ra, (187 * 128) # Addr of primary handler. 10755 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10756 10757/* ------------------------------ */ 10758 .balign 128 10759.L_ALT_op_sub_long_2addr: /* 0xbc */ 10760/* File: mips64/alt_stub.S */ 10761/* 10762 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10763 * any interesting requests and then jump to the real instruction 10764 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10765 */ 10766 .extern MterpCheckBefore 10767 REFRESH_IBASE 10768 dla ra, artMterpAsmInstructionStart 10769 dla t9, MterpCheckBefore 10770 move a0, rSELF 10771 daddu a1, rFP, OFF_FP_SHADOWFRAME 10772 move a2, rPC 10773 daddu ra, ra, (188 * 128) # Addr of primary handler. 10774 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10775 10776/* ------------------------------ */ 10777 .balign 128 10778.L_ALT_op_mul_long_2addr: /* 0xbd */ 10779/* File: mips64/alt_stub.S */ 10780/* 10781 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10782 * any interesting requests and then jump to the real instruction 10783 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10784 */ 10785 .extern MterpCheckBefore 10786 REFRESH_IBASE 10787 dla ra, artMterpAsmInstructionStart 10788 dla t9, MterpCheckBefore 10789 move a0, rSELF 10790 daddu a1, rFP, OFF_FP_SHADOWFRAME 10791 move a2, rPC 10792 daddu ra, ra, (189 * 128) # Addr of primary handler. 10793 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10794 10795/* ------------------------------ */ 10796 .balign 128 10797.L_ALT_op_div_long_2addr: /* 0xbe */ 10798/* File: mips64/alt_stub.S */ 10799/* 10800 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10801 * any interesting requests and then jump to the real instruction 10802 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10803 */ 10804 .extern MterpCheckBefore 10805 REFRESH_IBASE 10806 dla ra, artMterpAsmInstructionStart 10807 dla t9, MterpCheckBefore 10808 move a0, rSELF 10809 daddu a1, rFP, OFF_FP_SHADOWFRAME 10810 move a2, rPC 10811 daddu ra, ra, (190 * 128) # Addr of primary handler. 10812 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10813 10814/* ------------------------------ */ 10815 .balign 128 10816.L_ALT_op_rem_long_2addr: /* 0xbf */ 10817/* File: mips64/alt_stub.S */ 10818/* 10819 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10820 * any interesting requests and then jump to the real instruction 10821 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10822 */ 10823 .extern MterpCheckBefore 10824 REFRESH_IBASE 10825 dla ra, artMterpAsmInstructionStart 10826 dla t9, MterpCheckBefore 10827 move a0, rSELF 10828 daddu a1, rFP, OFF_FP_SHADOWFRAME 10829 move a2, rPC 10830 daddu ra, ra, (191 * 128) # Addr of primary handler. 10831 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10832 10833/* ------------------------------ */ 10834 .balign 128 10835.L_ALT_op_and_long_2addr: /* 0xc0 */ 10836/* File: mips64/alt_stub.S */ 10837/* 10838 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10839 * any interesting requests and then jump to the real instruction 10840 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10841 */ 10842 .extern MterpCheckBefore 10843 REFRESH_IBASE 10844 dla ra, artMterpAsmInstructionStart 10845 dla t9, MterpCheckBefore 10846 move a0, rSELF 10847 daddu a1, rFP, OFF_FP_SHADOWFRAME 10848 move a2, rPC 10849 daddu ra, ra, (192 * 128) # Addr of primary handler. 10850 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10851 10852/* ------------------------------ */ 10853 .balign 128 10854.L_ALT_op_or_long_2addr: /* 0xc1 */ 10855/* File: mips64/alt_stub.S */ 10856/* 10857 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10858 * any interesting requests and then jump to the real instruction 10859 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10860 */ 10861 .extern MterpCheckBefore 10862 REFRESH_IBASE 10863 dla ra, artMterpAsmInstructionStart 10864 dla t9, MterpCheckBefore 10865 move a0, rSELF 10866 daddu a1, rFP, OFF_FP_SHADOWFRAME 10867 move a2, rPC 10868 daddu ra, ra, (193 * 128) # Addr of primary handler. 10869 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10870 10871/* ------------------------------ */ 10872 .balign 128 10873.L_ALT_op_xor_long_2addr: /* 0xc2 */ 10874/* File: mips64/alt_stub.S */ 10875/* 10876 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10877 * any interesting requests and then jump to the real instruction 10878 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10879 */ 10880 .extern MterpCheckBefore 10881 REFRESH_IBASE 10882 dla ra, artMterpAsmInstructionStart 10883 dla t9, MterpCheckBefore 10884 move a0, rSELF 10885 daddu a1, rFP, OFF_FP_SHADOWFRAME 10886 move a2, rPC 10887 daddu ra, ra, (194 * 128) # Addr of primary handler. 10888 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10889 10890/* ------------------------------ */ 10891 .balign 128 10892.L_ALT_op_shl_long_2addr: /* 0xc3 */ 10893/* File: mips64/alt_stub.S */ 10894/* 10895 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10896 * any interesting requests and then jump to the real instruction 10897 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10898 */ 10899 .extern MterpCheckBefore 10900 REFRESH_IBASE 10901 dla ra, artMterpAsmInstructionStart 10902 dla t9, MterpCheckBefore 10903 move a0, rSELF 10904 daddu a1, rFP, OFF_FP_SHADOWFRAME 10905 move a2, rPC 10906 daddu ra, ra, (195 * 128) # Addr of primary handler. 10907 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10908 10909/* ------------------------------ */ 10910 .balign 128 10911.L_ALT_op_shr_long_2addr: /* 0xc4 */ 10912/* File: mips64/alt_stub.S */ 10913/* 10914 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10915 * any interesting requests and then jump to the real instruction 10916 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10917 */ 10918 .extern MterpCheckBefore 10919 REFRESH_IBASE 10920 dla ra, artMterpAsmInstructionStart 10921 dla t9, MterpCheckBefore 10922 move a0, rSELF 10923 daddu a1, rFP, OFF_FP_SHADOWFRAME 10924 move a2, rPC 10925 daddu ra, ra, (196 * 128) # Addr of primary handler. 10926 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10927 10928/* ------------------------------ */ 10929 .balign 128 10930.L_ALT_op_ushr_long_2addr: /* 0xc5 */ 10931/* File: mips64/alt_stub.S */ 10932/* 10933 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10934 * any interesting requests and then jump to the real instruction 10935 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10936 */ 10937 .extern MterpCheckBefore 10938 REFRESH_IBASE 10939 dla ra, artMterpAsmInstructionStart 10940 dla t9, MterpCheckBefore 10941 move a0, rSELF 10942 daddu a1, rFP, OFF_FP_SHADOWFRAME 10943 move a2, rPC 10944 daddu ra, ra, (197 * 128) # Addr of primary handler. 10945 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10946 10947/* ------------------------------ */ 10948 .balign 128 10949.L_ALT_op_add_float_2addr: /* 0xc6 */ 10950/* File: mips64/alt_stub.S */ 10951/* 10952 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10953 * any interesting requests and then jump to the real instruction 10954 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10955 */ 10956 .extern MterpCheckBefore 10957 REFRESH_IBASE 10958 dla ra, artMterpAsmInstructionStart 10959 dla t9, MterpCheckBefore 10960 move a0, rSELF 10961 daddu a1, rFP, OFF_FP_SHADOWFRAME 10962 move a2, rPC 10963 daddu ra, ra, (198 * 128) # Addr of primary handler. 10964 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10965 10966/* ------------------------------ */ 10967 .balign 128 10968.L_ALT_op_sub_float_2addr: /* 0xc7 */ 10969/* File: mips64/alt_stub.S */ 10970/* 10971 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10972 * any interesting requests and then jump to the real instruction 10973 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10974 */ 10975 .extern MterpCheckBefore 10976 REFRESH_IBASE 10977 dla ra, artMterpAsmInstructionStart 10978 dla t9, MterpCheckBefore 10979 move a0, rSELF 10980 daddu a1, rFP, OFF_FP_SHADOWFRAME 10981 move a2, rPC 10982 daddu ra, ra, (199 * 128) # Addr of primary handler. 10983 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 10984 10985/* ------------------------------ */ 10986 .balign 128 10987.L_ALT_op_mul_float_2addr: /* 0xc8 */ 10988/* File: mips64/alt_stub.S */ 10989/* 10990 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 10991 * any interesting requests and then jump to the real instruction 10992 * handler. Note that the call to MterpCheckBefore is done as a tail call. 10993 */ 10994 .extern MterpCheckBefore 10995 REFRESH_IBASE 10996 dla ra, artMterpAsmInstructionStart 10997 dla t9, MterpCheckBefore 10998 move a0, rSELF 10999 daddu a1, rFP, OFF_FP_SHADOWFRAME 11000 move a2, rPC 11001 daddu ra, ra, (200 * 128) # Addr of primary handler. 11002 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11003 11004/* ------------------------------ */ 11005 .balign 128 11006.L_ALT_op_div_float_2addr: /* 0xc9 */ 11007/* File: mips64/alt_stub.S */ 11008/* 11009 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11010 * any interesting requests and then jump to the real instruction 11011 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11012 */ 11013 .extern MterpCheckBefore 11014 REFRESH_IBASE 11015 dla ra, artMterpAsmInstructionStart 11016 dla t9, MterpCheckBefore 11017 move a0, rSELF 11018 daddu a1, rFP, OFF_FP_SHADOWFRAME 11019 move a2, rPC 11020 daddu ra, ra, (201 * 128) # Addr of primary handler. 11021 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11022 11023/* ------------------------------ */ 11024 .balign 128 11025.L_ALT_op_rem_float_2addr: /* 0xca */ 11026/* File: mips64/alt_stub.S */ 11027/* 11028 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11029 * any interesting requests and then jump to the real instruction 11030 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11031 */ 11032 .extern MterpCheckBefore 11033 REFRESH_IBASE 11034 dla ra, artMterpAsmInstructionStart 11035 dla t9, MterpCheckBefore 11036 move a0, rSELF 11037 daddu a1, rFP, OFF_FP_SHADOWFRAME 11038 move a2, rPC 11039 daddu ra, ra, (202 * 128) # Addr of primary handler. 11040 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11041 11042/* ------------------------------ */ 11043 .balign 128 11044.L_ALT_op_add_double_2addr: /* 0xcb */ 11045/* File: mips64/alt_stub.S */ 11046/* 11047 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11048 * any interesting requests and then jump to the real instruction 11049 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11050 */ 11051 .extern MterpCheckBefore 11052 REFRESH_IBASE 11053 dla ra, artMterpAsmInstructionStart 11054 dla t9, MterpCheckBefore 11055 move a0, rSELF 11056 daddu a1, rFP, OFF_FP_SHADOWFRAME 11057 move a2, rPC 11058 daddu ra, ra, (203 * 128) # Addr of primary handler. 11059 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11060 11061/* ------------------------------ */ 11062 .balign 128 11063.L_ALT_op_sub_double_2addr: /* 0xcc */ 11064/* File: mips64/alt_stub.S */ 11065/* 11066 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11067 * any interesting requests and then jump to the real instruction 11068 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11069 */ 11070 .extern MterpCheckBefore 11071 REFRESH_IBASE 11072 dla ra, artMterpAsmInstructionStart 11073 dla t9, MterpCheckBefore 11074 move a0, rSELF 11075 daddu a1, rFP, OFF_FP_SHADOWFRAME 11076 move a2, rPC 11077 daddu ra, ra, (204 * 128) # Addr of primary handler. 11078 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11079 11080/* ------------------------------ */ 11081 .balign 128 11082.L_ALT_op_mul_double_2addr: /* 0xcd */ 11083/* File: mips64/alt_stub.S */ 11084/* 11085 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11086 * any interesting requests and then jump to the real instruction 11087 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11088 */ 11089 .extern MterpCheckBefore 11090 REFRESH_IBASE 11091 dla ra, artMterpAsmInstructionStart 11092 dla t9, MterpCheckBefore 11093 move a0, rSELF 11094 daddu a1, rFP, OFF_FP_SHADOWFRAME 11095 move a2, rPC 11096 daddu ra, ra, (205 * 128) # Addr of primary handler. 11097 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11098 11099/* ------------------------------ */ 11100 .balign 128 11101.L_ALT_op_div_double_2addr: /* 0xce */ 11102/* File: mips64/alt_stub.S */ 11103/* 11104 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11105 * any interesting requests and then jump to the real instruction 11106 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11107 */ 11108 .extern MterpCheckBefore 11109 REFRESH_IBASE 11110 dla ra, artMterpAsmInstructionStart 11111 dla t9, MterpCheckBefore 11112 move a0, rSELF 11113 daddu a1, rFP, OFF_FP_SHADOWFRAME 11114 move a2, rPC 11115 daddu ra, ra, (206 * 128) # Addr of primary handler. 11116 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11117 11118/* ------------------------------ */ 11119 .balign 128 11120.L_ALT_op_rem_double_2addr: /* 0xcf */ 11121/* File: mips64/alt_stub.S */ 11122/* 11123 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11124 * any interesting requests and then jump to the real instruction 11125 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11126 */ 11127 .extern MterpCheckBefore 11128 REFRESH_IBASE 11129 dla ra, artMterpAsmInstructionStart 11130 dla t9, MterpCheckBefore 11131 move a0, rSELF 11132 daddu a1, rFP, OFF_FP_SHADOWFRAME 11133 move a2, rPC 11134 daddu ra, ra, (207 * 128) # Addr of primary handler. 11135 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11136 11137/* ------------------------------ */ 11138 .balign 128 11139.L_ALT_op_add_int_lit16: /* 0xd0 */ 11140/* File: mips64/alt_stub.S */ 11141/* 11142 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11143 * any interesting requests and then jump to the real instruction 11144 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11145 */ 11146 .extern MterpCheckBefore 11147 REFRESH_IBASE 11148 dla ra, artMterpAsmInstructionStart 11149 dla t9, MterpCheckBefore 11150 move a0, rSELF 11151 daddu a1, rFP, OFF_FP_SHADOWFRAME 11152 move a2, rPC 11153 daddu ra, ra, (208 * 128) # Addr of primary handler. 11154 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11155 11156/* ------------------------------ */ 11157 .balign 128 11158.L_ALT_op_rsub_int: /* 0xd1 */ 11159/* File: mips64/alt_stub.S */ 11160/* 11161 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11162 * any interesting requests and then jump to the real instruction 11163 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11164 */ 11165 .extern MterpCheckBefore 11166 REFRESH_IBASE 11167 dla ra, artMterpAsmInstructionStart 11168 dla t9, MterpCheckBefore 11169 move a0, rSELF 11170 daddu a1, rFP, OFF_FP_SHADOWFRAME 11171 move a2, rPC 11172 daddu ra, ra, (209 * 128) # Addr of primary handler. 11173 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11174 11175/* ------------------------------ */ 11176 .balign 128 11177.L_ALT_op_mul_int_lit16: /* 0xd2 */ 11178/* File: mips64/alt_stub.S */ 11179/* 11180 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11181 * any interesting requests and then jump to the real instruction 11182 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11183 */ 11184 .extern MterpCheckBefore 11185 REFRESH_IBASE 11186 dla ra, artMterpAsmInstructionStart 11187 dla t9, MterpCheckBefore 11188 move a0, rSELF 11189 daddu a1, rFP, OFF_FP_SHADOWFRAME 11190 move a2, rPC 11191 daddu ra, ra, (210 * 128) # Addr of primary handler. 11192 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11193 11194/* ------------------------------ */ 11195 .balign 128 11196.L_ALT_op_div_int_lit16: /* 0xd3 */ 11197/* File: mips64/alt_stub.S */ 11198/* 11199 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11200 * any interesting requests and then jump to the real instruction 11201 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11202 */ 11203 .extern MterpCheckBefore 11204 REFRESH_IBASE 11205 dla ra, artMterpAsmInstructionStart 11206 dla t9, MterpCheckBefore 11207 move a0, rSELF 11208 daddu a1, rFP, OFF_FP_SHADOWFRAME 11209 move a2, rPC 11210 daddu ra, ra, (211 * 128) # Addr of primary handler. 11211 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11212 11213/* ------------------------------ */ 11214 .balign 128 11215.L_ALT_op_rem_int_lit16: /* 0xd4 */ 11216/* File: mips64/alt_stub.S */ 11217/* 11218 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11219 * any interesting requests and then jump to the real instruction 11220 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11221 */ 11222 .extern MterpCheckBefore 11223 REFRESH_IBASE 11224 dla ra, artMterpAsmInstructionStart 11225 dla t9, MterpCheckBefore 11226 move a0, rSELF 11227 daddu a1, rFP, OFF_FP_SHADOWFRAME 11228 move a2, rPC 11229 daddu ra, ra, (212 * 128) # Addr of primary handler. 11230 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11231 11232/* ------------------------------ */ 11233 .balign 128 11234.L_ALT_op_and_int_lit16: /* 0xd5 */ 11235/* File: mips64/alt_stub.S */ 11236/* 11237 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11238 * any interesting requests and then jump to the real instruction 11239 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11240 */ 11241 .extern MterpCheckBefore 11242 REFRESH_IBASE 11243 dla ra, artMterpAsmInstructionStart 11244 dla t9, MterpCheckBefore 11245 move a0, rSELF 11246 daddu a1, rFP, OFF_FP_SHADOWFRAME 11247 move a2, rPC 11248 daddu ra, ra, (213 * 128) # Addr of primary handler. 11249 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11250 11251/* ------------------------------ */ 11252 .balign 128 11253.L_ALT_op_or_int_lit16: /* 0xd6 */ 11254/* File: mips64/alt_stub.S */ 11255/* 11256 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11257 * any interesting requests and then jump to the real instruction 11258 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11259 */ 11260 .extern MterpCheckBefore 11261 REFRESH_IBASE 11262 dla ra, artMterpAsmInstructionStart 11263 dla t9, MterpCheckBefore 11264 move a0, rSELF 11265 daddu a1, rFP, OFF_FP_SHADOWFRAME 11266 move a2, rPC 11267 daddu ra, ra, (214 * 128) # Addr of primary handler. 11268 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11269 11270/* ------------------------------ */ 11271 .balign 128 11272.L_ALT_op_xor_int_lit16: /* 0xd7 */ 11273/* File: mips64/alt_stub.S */ 11274/* 11275 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11276 * any interesting requests and then jump to the real instruction 11277 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11278 */ 11279 .extern MterpCheckBefore 11280 REFRESH_IBASE 11281 dla ra, artMterpAsmInstructionStart 11282 dla t9, MterpCheckBefore 11283 move a0, rSELF 11284 daddu a1, rFP, OFF_FP_SHADOWFRAME 11285 move a2, rPC 11286 daddu ra, ra, (215 * 128) # Addr of primary handler. 11287 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11288 11289/* ------------------------------ */ 11290 .balign 128 11291.L_ALT_op_add_int_lit8: /* 0xd8 */ 11292/* File: mips64/alt_stub.S */ 11293/* 11294 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11295 * any interesting requests and then jump to the real instruction 11296 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11297 */ 11298 .extern MterpCheckBefore 11299 REFRESH_IBASE 11300 dla ra, artMterpAsmInstructionStart 11301 dla t9, MterpCheckBefore 11302 move a0, rSELF 11303 daddu a1, rFP, OFF_FP_SHADOWFRAME 11304 move a2, rPC 11305 daddu ra, ra, (216 * 128) # Addr of primary handler. 11306 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11307 11308/* ------------------------------ */ 11309 .balign 128 11310.L_ALT_op_rsub_int_lit8: /* 0xd9 */ 11311/* File: mips64/alt_stub.S */ 11312/* 11313 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11314 * any interesting requests and then jump to the real instruction 11315 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11316 */ 11317 .extern MterpCheckBefore 11318 REFRESH_IBASE 11319 dla ra, artMterpAsmInstructionStart 11320 dla t9, MterpCheckBefore 11321 move a0, rSELF 11322 daddu a1, rFP, OFF_FP_SHADOWFRAME 11323 move a2, rPC 11324 daddu ra, ra, (217 * 128) # Addr of primary handler. 11325 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11326 11327/* ------------------------------ */ 11328 .balign 128 11329.L_ALT_op_mul_int_lit8: /* 0xda */ 11330/* File: mips64/alt_stub.S */ 11331/* 11332 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11333 * any interesting requests and then jump to the real instruction 11334 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11335 */ 11336 .extern MterpCheckBefore 11337 REFRESH_IBASE 11338 dla ra, artMterpAsmInstructionStart 11339 dla t9, MterpCheckBefore 11340 move a0, rSELF 11341 daddu a1, rFP, OFF_FP_SHADOWFRAME 11342 move a2, rPC 11343 daddu ra, ra, (218 * 128) # Addr of primary handler. 11344 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11345 11346/* ------------------------------ */ 11347 .balign 128 11348.L_ALT_op_div_int_lit8: /* 0xdb */ 11349/* File: mips64/alt_stub.S */ 11350/* 11351 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11352 * any interesting requests and then jump to the real instruction 11353 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11354 */ 11355 .extern MterpCheckBefore 11356 REFRESH_IBASE 11357 dla ra, artMterpAsmInstructionStart 11358 dla t9, MterpCheckBefore 11359 move a0, rSELF 11360 daddu a1, rFP, OFF_FP_SHADOWFRAME 11361 move a2, rPC 11362 daddu ra, ra, (219 * 128) # Addr of primary handler. 11363 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11364 11365/* ------------------------------ */ 11366 .balign 128 11367.L_ALT_op_rem_int_lit8: /* 0xdc */ 11368/* File: mips64/alt_stub.S */ 11369/* 11370 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11371 * any interesting requests and then jump to the real instruction 11372 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11373 */ 11374 .extern MterpCheckBefore 11375 REFRESH_IBASE 11376 dla ra, artMterpAsmInstructionStart 11377 dla t9, MterpCheckBefore 11378 move a0, rSELF 11379 daddu a1, rFP, OFF_FP_SHADOWFRAME 11380 move a2, rPC 11381 daddu ra, ra, (220 * 128) # Addr of primary handler. 11382 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11383 11384/* ------------------------------ */ 11385 .balign 128 11386.L_ALT_op_and_int_lit8: /* 0xdd */ 11387/* File: mips64/alt_stub.S */ 11388/* 11389 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11390 * any interesting requests and then jump to the real instruction 11391 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11392 */ 11393 .extern MterpCheckBefore 11394 REFRESH_IBASE 11395 dla ra, artMterpAsmInstructionStart 11396 dla t9, MterpCheckBefore 11397 move a0, rSELF 11398 daddu a1, rFP, OFF_FP_SHADOWFRAME 11399 move a2, rPC 11400 daddu ra, ra, (221 * 128) # Addr of primary handler. 11401 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11402 11403/* ------------------------------ */ 11404 .balign 128 11405.L_ALT_op_or_int_lit8: /* 0xde */ 11406/* File: mips64/alt_stub.S */ 11407/* 11408 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11409 * any interesting requests and then jump to the real instruction 11410 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11411 */ 11412 .extern MterpCheckBefore 11413 REFRESH_IBASE 11414 dla ra, artMterpAsmInstructionStart 11415 dla t9, MterpCheckBefore 11416 move a0, rSELF 11417 daddu a1, rFP, OFF_FP_SHADOWFRAME 11418 move a2, rPC 11419 daddu ra, ra, (222 * 128) # Addr of primary handler. 11420 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11421 11422/* ------------------------------ */ 11423 .balign 128 11424.L_ALT_op_xor_int_lit8: /* 0xdf */ 11425/* File: mips64/alt_stub.S */ 11426/* 11427 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11428 * any interesting requests and then jump to the real instruction 11429 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11430 */ 11431 .extern MterpCheckBefore 11432 REFRESH_IBASE 11433 dla ra, artMterpAsmInstructionStart 11434 dla t9, MterpCheckBefore 11435 move a0, rSELF 11436 daddu a1, rFP, OFF_FP_SHADOWFRAME 11437 move a2, rPC 11438 daddu ra, ra, (223 * 128) # Addr of primary handler. 11439 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11440 11441/* ------------------------------ */ 11442 .balign 128 11443.L_ALT_op_shl_int_lit8: /* 0xe0 */ 11444/* File: mips64/alt_stub.S */ 11445/* 11446 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11447 * any interesting requests and then jump to the real instruction 11448 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11449 */ 11450 .extern MterpCheckBefore 11451 REFRESH_IBASE 11452 dla ra, artMterpAsmInstructionStart 11453 dla t9, MterpCheckBefore 11454 move a0, rSELF 11455 daddu a1, rFP, OFF_FP_SHADOWFRAME 11456 move a2, rPC 11457 daddu ra, ra, (224 * 128) # Addr of primary handler. 11458 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11459 11460/* ------------------------------ */ 11461 .balign 128 11462.L_ALT_op_shr_int_lit8: /* 0xe1 */ 11463/* File: mips64/alt_stub.S */ 11464/* 11465 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11466 * any interesting requests and then jump to the real instruction 11467 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11468 */ 11469 .extern MterpCheckBefore 11470 REFRESH_IBASE 11471 dla ra, artMterpAsmInstructionStart 11472 dla t9, MterpCheckBefore 11473 move a0, rSELF 11474 daddu a1, rFP, OFF_FP_SHADOWFRAME 11475 move a2, rPC 11476 daddu ra, ra, (225 * 128) # Addr of primary handler. 11477 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11478 11479/* ------------------------------ */ 11480 .balign 128 11481.L_ALT_op_ushr_int_lit8: /* 0xe2 */ 11482/* File: mips64/alt_stub.S */ 11483/* 11484 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11485 * any interesting requests and then jump to the real instruction 11486 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11487 */ 11488 .extern MterpCheckBefore 11489 REFRESH_IBASE 11490 dla ra, artMterpAsmInstructionStart 11491 dla t9, MterpCheckBefore 11492 move a0, rSELF 11493 daddu a1, rFP, OFF_FP_SHADOWFRAME 11494 move a2, rPC 11495 daddu ra, ra, (226 * 128) # Addr of primary handler. 11496 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11497 11498/* ------------------------------ */ 11499 .balign 128 11500.L_ALT_op_iget_quick: /* 0xe3 */ 11501/* File: mips64/alt_stub.S */ 11502/* 11503 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11504 * any interesting requests and then jump to the real instruction 11505 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11506 */ 11507 .extern MterpCheckBefore 11508 REFRESH_IBASE 11509 dla ra, artMterpAsmInstructionStart 11510 dla t9, MterpCheckBefore 11511 move a0, rSELF 11512 daddu a1, rFP, OFF_FP_SHADOWFRAME 11513 move a2, rPC 11514 daddu ra, ra, (227 * 128) # Addr of primary handler. 11515 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11516 11517/* ------------------------------ */ 11518 .balign 128 11519.L_ALT_op_iget_wide_quick: /* 0xe4 */ 11520/* File: mips64/alt_stub.S */ 11521/* 11522 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11523 * any interesting requests and then jump to the real instruction 11524 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11525 */ 11526 .extern MterpCheckBefore 11527 REFRESH_IBASE 11528 dla ra, artMterpAsmInstructionStart 11529 dla t9, MterpCheckBefore 11530 move a0, rSELF 11531 daddu a1, rFP, OFF_FP_SHADOWFRAME 11532 move a2, rPC 11533 daddu ra, ra, (228 * 128) # Addr of primary handler. 11534 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11535 11536/* ------------------------------ */ 11537 .balign 128 11538.L_ALT_op_iget_object_quick: /* 0xe5 */ 11539/* File: mips64/alt_stub.S */ 11540/* 11541 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11542 * any interesting requests and then jump to the real instruction 11543 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11544 */ 11545 .extern MterpCheckBefore 11546 REFRESH_IBASE 11547 dla ra, artMterpAsmInstructionStart 11548 dla t9, MterpCheckBefore 11549 move a0, rSELF 11550 daddu a1, rFP, OFF_FP_SHADOWFRAME 11551 move a2, rPC 11552 daddu ra, ra, (229 * 128) # Addr of primary handler. 11553 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11554 11555/* ------------------------------ */ 11556 .balign 128 11557.L_ALT_op_iput_quick: /* 0xe6 */ 11558/* File: mips64/alt_stub.S */ 11559/* 11560 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11561 * any interesting requests and then jump to the real instruction 11562 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11563 */ 11564 .extern MterpCheckBefore 11565 REFRESH_IBASE 11566 dla ra, artMterpAsmInstructionStart 11567 dla t9, MterpCheckBefore 11568 move a0, rSELF 11569 daddu a1, rFP, OFF_FP_SHADOWFRAME 11570 move a2, rPC 11571 daddu ra, ra, (230 * 128) # Addr of primary handler. 11572 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11573 11574/* ------------------------------ */ 11575 .balign 128 11576.L_ALT_op_iput_wide_quick: /* 0xe7 */ 11577/* File: mips64/alt_stub.S */ 11578/* 11579 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11580 * any interesting requests and then jump to the real instruction 11581 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11582 */ 11583 .extern MterpCheckBefore 11584 REFRESH_IBASE 11585 dla ra, artMterpAsmInstructionStart 11586 dla t9, MterpCheckBefore 11587 move a0, rSELF 11588 daddu a1, rFP, OFF_FP_SHADOWFRAME 11589 move a2, rPC 11590 daddu ra, ra, (231 * 128) # Addr of primary handler. 11591 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11592 11593/* ------------------------------ */ 11594 .balign 128 11595.L_ALT_op_iput_object_quick: /* 0xe8 */ 11596/* File: mips64/alt_stub.S */ 11597/* 11598 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11599 * any interesting requests and then jump to the real instruction 11600 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11601 */ 11602 .extern MterpCheckBefore 11603 REFRESH_IBASE 11604 dla ra, artMterpAsmInstructionStart 11605 dla t9, MterpCheckBefore 11606 move a0, rSELF 11607 daddu a1, rFP, OFF_FP_SHADOWFRAME 11608 move a2, rPC 11609 daddu ra, ra, (232 * 128) # Addr of primary handler. 11610 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11611 11612/* ------------------------------ */ 11613 .balign 128 11614.L_ALT_op_invoke_virtual_quick: /* 0xe9 */ 11615/* File: mips64/alt_stub.S */ 11616/* 11617 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11618 * any interesting requests and then jump to the real instruction 11619 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11620 */ 11621 .extern MterpCheckBefore 11622 REFRESH_IBASE 11623 dla ra, artMterpAsmInstructionStart 11624 dla t9, MterpCheckBefore 11625 move a0, rSELF 11626 daddu a1, rFP, OFF_FP_SHADOWFRAME 11627 move a2, rPC 11628 daddu ra, ra, (233 * 128) # Addr of primary handler. 11629 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11630 11631/* ------------------------------ */ 11632 .balign 128 11633.L_ALT_op_invoke_virtual_range_quick: /* 0xea */ 11634/* File: mips64/alt_stub.S */ 11635/* 11636 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11637 * any interesting requests and then jump to the real instruction 11638 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11639 */ 11640 .extern MterpCheckBefore 11641 REFRESH_IBASE 11642 dla ra, artMterpAsmInstructionStart 11643 dla t9, MterpCheckBefore 11644 move a0, rSELF 11645 daddu a1, rFP, OFF_FP_SHADOWFRAME 11646 move a2, rPC 11647 daddu ra, ra, (234 * 128) # Addr of primary handler. 11648 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11649 11650/* ------------------------------ */ 11651 .balign 128 11652.L_ALT_op_iput_boolean_quick: /* 0xeb */ 11653/* File: mips64/alt_stub.S */ 11654/* 11655 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11656 * any interesting requests and then jump to the real instruction 11657 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11658 */ 11659 .extern MterpCheckBefore 11660 REFRESH_IBASE 11661 dla ra, artMterpAsmInstructionStart 11662 dla t9, MterpCheckBefore 11663 move a0, rSELF 11664 daddu a1, rFP, OFF_FP_SHADOWFRAME 11665 move a2, rPC 11666 daddu ra, ra, (235 * 128) # Addr of primary handler. 11667 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11668 11669/* ------------------------------ */ 11670 .balign 128 11671.L_ALT_op_iput_byte_quick: /* 0xec */ 11672/* File: mips64/alt_stub.S */ 11673/* 11674 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11675 * any interesting requests and then jump to the real instruction 11676 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11677 */ 11678 .extern MterpCheckBefore 11679 REFRESH_IBASE 11680 dla ra, artMterpAsmInstructionStart 11681 dla t9, MterpCheckBefore 11682 move a0, rSELF 11683 daddu a1, rFP, OFF_FP_SHADOWFRAME 11684 move a2, rPC 11685 daddu ra, ra, (236 * 128) # Addr of primary handler. 11686 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11687 11688/* ------------------------------ */ 11689 .balign 128 11690.L_ALT_op_iput_char_quick: /* 0xed */ 11691/* File: mips64/alt_stub.S */ 11692/* 11693 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11694 * any interesting requests and then jump to the real instruction 11695 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11696 */ 11697 .extern MterpCheckBefore 11698 REFRESH_IBASE 11699 dla ra, artMterpAsmInstructionStart 11700 dla t9, MterpCheckBefore 11701 move a0, rSELF 11702 daddu a1, rFP, OFF_FP_SHADOWFRAME 11703 move a2, rPC 11704 daddu ra, ra, (237 * 128) # Addr of primary handler. 11705 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11706 11707/* ------------------------------ */ 11708 .balign 128 11709.L_ALT_op_iput_short_quick: /* 0xee */ 11710/* File: mips64/alt_stub.S */ 11711/* 11712 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11713 * any interesting requests and then jump to the real instruction 11714 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11715 */ 11716 .extern MterpCheckBefore 11717 REFRESH_IBASE 11718 dla ra, artMterpAsmInstructionStart 11719 dla t9, MterpCheckBefore 11720 move a0, rSELF 11721 daddu a1, rFP, OFF_FP_SHADOWFRAME 11722 move a2, rPC 11723 daddu ra, ra, (238 * 128) # Addr of primary handler. 11724 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11725 11726/* ------------------------------ */ 11727 .balign 128 11728.L_ALT_op_iget_boolean_quick: /* 0xef */ 11729/* File: mips64/alt_stub.S */ 11730/* 11731 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11732 * any interesting requests and then jump to the real instruction 11733 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11734 */ 11735 .extern MterpCheckBefore 11736 REFRESH_IBASE 11737 dla ra, artMterpAsmInstructionStart 11738 dla t9, MterpCheckBefore 11739 move a0, rSELF 11740 daddu a1, rFP, OFF_FP_SHADOWFRAME 11741 move a2, rPC 11742 daddu ra, ra, (239 * 128) # Addr of primary handler. 11743 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11744 11745/* ------------------------------ */ 11746 .balign 128 11747.L_ALT_op_iget_byte_quick: /* 0xf0 */ 11748/* File: mips64/alt_stub.S */ 11749/* 11750 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11751 * any interesting requests and then jump to the real instruction 11752 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11753 */ 11754 .extern MterpCheckBefore 11755 REFRESH_IBASE 11756 dla ra, artMterpAsmInstructionStart 11757 dla t9, MterpCheckBefore 11758 move a0, rSELF 11759 daddu a1, rFP, OFF_FP_SHADOWFRAME 11760 move a2, rPC 11761 daddu ra, ra, (240 * 128) # Addr of primary handler. 11762 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11763 11764/* ------------------------------ */ 11765 .balign 128 11766.L_ALT_op_iget_char_quick: /* 0xf1 */ 11767/* File: mips64/alt_stub.S */ 11768/* 11769 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11770 * any interesting requests and then jump to the real instruction 11771 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11772 */ 11773 .extern MterpCheckBefore 11774 REFRESH_IBASE 11775 dla ra, artMterpAsmInstructionStart 11776 dla t9, MterpCheckBefore 11777 move a0, rSELF 11778 daddu a1, rFP, OFF_FP_SHADOWFRAME 11779 move a2, rPC 11780 daddu ra, ra, (241 * 128) # Addr of primary handler. 11781 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11782 11783/* ------------------------------ */ 11784 .balign 128 11785.L_ALT_op_iget_short_quick: /* 0xf2 */ 11786/* File: mips64/alt_stub.S */ 11787/* 11788 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11789 * any interesting requests and then jump to the real instruction 11790 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11791 */ 11792 .extern MterpCheckBefore 11793 REFRESH_IBASE 11794 dla ra, artMterpAsmInstructionStart 11795 dla t9, MterpCheckBefore 11796 move a0, rSELF 11797 daddu a1, rFP, OFF_FP_SHADOWFRAME 11798 move a2, rPC 11799 daddu ra, ra, (242 * 128) # Addr of primary handler. 11800 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11801 11802/* ------------------------------ */ 11803 .balign 128 11804.L_ALT_op_unused_f3: /* 0xf3 */ 11805/* File: mips64/alt_stub.S */ 11806/* 11807 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11808 * any interesting requests and then jump to the real instruction 11809 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11810 */ 11811 .extern MterpCheckBefore 11812 REFRESH_IBASE 11813 dla ra, artMterpAsmInstructionStart 11814 dla t9, MterpCheckBefore 11815 move a0, rSELF 11816 daddu a1, rFP, OFF_FP_SHADOWFRAME 11817 move a2, rPC 11818 daddu ra, ra, (243 * 128) # Addr of primary handler. 11819 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11820 11821/* ------------------------------ */ 11822 .balign 128 11823.L_ALT_op_unused_f4: /* 0xf4 */ 11824/* File: mips64/alt_stub.S */ 11825/* 11826 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11827 * any interesting requests and then jump to the real instruction 11828 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11829 */ 11830 .extern MterpCheckBefore 11831 REFRESH_IBASE 11832 dla ra, artMterpAsmInstructionStart 11833 dla t9, MterpCheckBefore 11834 move a0, rSELF 11835 daddu a1, rFP, OFF_FP_SHADOWFRAME 11836 move a2, rPC 11837 daddu ra, ra, (244 * 128) # Addr of primary handler. 11838 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11839 11840/* ------------------------------ */ 11841 .balign 128 11842.L_ALT_op_unused_f5: /* 0xf5 */ 11843/* File: mips64/alt_stub.S */ 11844/* 11845 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11846 * any interesting requests and then jump to the real instruction 11847 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11848 */ 11849 .extern MterpCheckBefore 11850 REFRESH_IBASE 11851 dla ra, artMterpAsmInstructionStart 11852 dla t9, MterpCheckBefore 11853 move a0, rSELF 11854 daddu a1, rFP, OFF_FP_SHADOWFRAME 11855 move a2, rPC 11856 daddu ra, ra, (245 * 128) # Addr of primary handler. 11857 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11858 11859/* ------------------------------ */ 11860 .balign 128 11861.L_ALT_op_unused_f6: /* 0xf6 */ 11862/* File: mips64/alt_stub.S */ 11863/* 11864 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11865 * any interesting requests and then jump to the real instruction 11866 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11867 */ 11868 .extern MterpCheckBefore 11869 REFRESH_IBASE 11870 dla ra, artMterpAsmInstructionStart 11871 dla t9, MterpCheckBefore 11872 move a0, rSELF 11873 daddu a1, rFP, OFF_FP_SHADOWFRAME 11874 move a2, rPC 11875 daddu ra, ra, (246 * 128) # Addr of primary handler. 11876 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11877 11878/* ------------------------------ */ 11879 .balign 128 11880.L_ALT_op_unused_f7: /* 0xf7 */ 11881/* File: mips64/alt_stub.S */ 11882/* 11883 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11884 * any interesting requests and then jump to the real instruction 11885 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11886 */ 11887 .extern MterpCheckBefore 11888 REFRESH_IBASE 11889 dla ra, artMterpAsmInstructionStart 11890 dla t9, MterpCheckBefore 11891 move a0, rSELF 11892 daddu a1, rFP, OFF_FP_SHADOWFRAME 11893 move a2, rPC 11894 daddu ra, ra, (247 * 128) # Addr of primary handler. 11895 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11896 11897/* ------------------------------ */ 11898 .balign 128 11899.L_ALT_op_unused_f8: /* 0xf8 */ 11900/* File: mips64/alt_stub.S */ 11901/* 11902 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11903 * any interesting requests and then jump to the real instruction 11904 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11905 */ 11906 .extern MterpCheckBefore 11907 REFRESH_IBASE 11908 dla ra, artMterpAsmInstructionStart 11909 dla t9, MterpCheckBefore 11910 move a0, rSELF 11911 daddu a1, rFP, OFF_FP_SHADOWFRAME 11912 move a2, rPC 11913 daddu ra, ra, (248 * 128) # Addr of primary handler. 11914 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11915 11916/* ------------------------------ */ 11917 .balign 128 11918.L_ALT_op_unused_f9: /* 0xf9 */ 11919/* File: mips64/alt_stub.S */ 11920/* 11921 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11922 * any interesting requests and then jump to the real instruction 11923 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11924 */ 11925 .extern MterpCheckBefore 11926 REFRESH_IBASE 11927 dla ra, artMterpAsmInstructionStart 11928 dla t9, MterpCheckBefore 11929 move a0, rSELF 11930 daddu a1, rFP, OFF_FP_SHADOWFRAME 11931 move a2, rPC 11932 daddu ra, ra, (249 * 128) # Addr of primary handler. 11933 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11934 11935/* ------------------------------ */ 11936 .balign 128 11937.L_ALT_op_invoke_polymorphic: /* 0xfa */ 11938/* File: mips64/alt_stub.S */ 11939/* 11940 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11941 * any interesting requests and then jump to the real instruction 11942 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11943 */ 11944 .extern MterpCheckBefore 11945 REFRESH_IBASE 11946 dla ra, artMterpAsmInstructionStart 11947 dla t9, MterpCheckBefore 11948 move a0, rSELF 11949 daddu a1, rFP, OFF_FP_SHADOWFRAME 11950 move a2, rPC 11951 daddu ra, ra, (250 * 128) # Addr of primary handler. 11952 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11953 11954/* ------------------------------ */ 11955 .balign 128 11956.L_ALT_op_invoke_polymorphic_range: /* 0xfb */ 11957/* File: mips64/alt_stub.S */ 11958/* 11959 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11960 * any interesting requests and then jump to the real instruction 11961 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11962 */ 11963 .extern MterpCheckBefore 11964 REFRESH_IBASE 11965 dla ra, artMterpAsmInstructionStart 11966 dla t9, MterpCheckBefore 11967 move a0, rSELF 11968 daddu a1, rFP, OFF_FP_SHADOWFRAME 11969 move a2, rPC 11970 daddu ra, ra, (251 * 128) # Addr of primary handler. 11971 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11972 11973/* ------------------------------ */ 11974 .balign 128 11975.L_ALT_op_invoke_custom: /* 0xfc */ 11976/* File: mips64/alt_stub.S */ 11977/* 11978 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11979 * any interesting requests and then jump to the real instruction 11980 * handler. Note that the call to MterpCheckBefore is done as a tail call. 11981 */ 11982 .extern MterpCheckBefore 11983 REFRESH_IBASE 11984 dla ra, artMterpAsmInstructionStart 11985 dla t9, MterpCheckBefore 11986 move a0, rSELF 11987 daddu a1, rFP, OFF_FP_SHADOWFRAME 11988 move a2, rPC 11989 daddu ra, ra, (252 * 128) # Addr of primary handler. 11990 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 11991 11992/* ------------------------------ */ 11993 .balign 128 11994.L_ALT_op_invoke_custom_range: /* 0xfd */ 11995/* File: mips64/alt_stub.S */ 11996/* 11997 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 11998 * any interesting requests and then jump to the real instruction 11999 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12000 */ 12001 .extern MterpCheckBefore 12002 REFRESH_IBASE 12003 dla ra, artMterpAsmInstructionStart 12004 dla t9, MterpCheckBefore 12005 move a0, rSELF 12006 daddu a1, rFP, OFF_FP_SHADOWFRAME 12007 move a2, rPC 12008 daddu ra, ra, (253 * 128) # Addr of primary handler. 12009 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 12010 12011/* ------------------------------ */ 12012 .balign 128 12013.L_ALT_op_unused_fe: /* 0xfe */ 12014/* File: mips64/alt_stub.S */ 12015/* 12016 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12017 * any interesting requests and then jump to the real instruction 12018 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12019 */ 12020 .extern MterpCheckBefore 12021 REFRESH_IBASE 12022 dla ra, artMterpAsmInstructionStart 12023 dla t9, MterpCheckBefore 12024 move a0, rSELF 12025 daddu a1, rFP, OFF_FP_SHADOWFRAME 12026 move a2, rPC 12027 daddu ra, ra, (254 * 128) # Addr of primary handler. 12028 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 12029 12030/* ------------------------------ */ 12031 .balign 128 12032.L_ALT_op_unused_ff: /* 0xff */ 12033/* File: mips64/alt_stub.S */ 12034/* 12035 * Inter-instruction transfer stub. Call out to MterpCheckBefore to handle 12036 * any interesting requests and then jump to the real instruction 12037 * handler. Note that the call to MterpCheckBefore is done as a tail call. 12038 */ 12039 .extern MterpCheckBefore 12040 REFRESH_IBASE 12041 dla ra, artMterpAsmInstructionStart 12042 dla t9, MterpCheckBefore 12043 move a0, rSELF 12044 daddu a1, rFP, OFF_FP_SHADOWFRAME 12045 move a2, rPC 12046 daddu ra, ra, (255 * 128) # Addr of primary handler. 12047 jalr zero, t9 # (self, shadow_frame, dex_pc_ptr) Note: tail call. 12048 12049 .balign 128 12050 .size artMterpAsmAltInstructionStart, .-artMterpAsmAltInstructionStart 12051 .global artMterpAsmAltInstructionEnd 12052artMterpAsmAltInstructionEnd: 12053/* File: mips64/footer.S */ 12054/* 12055 * We've detected a condition that will result in an exception, but the exception 12056 * has not yet been thrown. Just bail out to the reference interpreter to deal with it. 12057 * TUNING: for consistency, we may want to just go ahead and handle these here. 12058 */ 12059 12060 .extern MterpLogDivideByZeroException 12061common_errDivideByZero: 12062 EXPORT_PC 12063#if MTERP_LOGGING 12064 move a0, rSELF 12065 daddu a1, rFP, OFF_FP_SHADOWFRAME 12066 jal MterpLogDivideByZeroException 12067#endif 12068 b MterpCommonFallback 12069 12070 .extern MterpLogArrayIndexException 12071common_errArrayIndex: 12072 EXPORT_PC 12073#if MTERP_LOGGING 12074 move a0, rSELF 12075 daddu a1, rFP, OFF_FP_SHADOWFRAME 12076 jal MterpLogArrayIndexException 12077#endif 12078 b MterpCommonFallback 12079 12080 .extern MterpLogNullObjectException 12081common_errNullObject: 12082 EXPORT_PC 12083#if MTERP_LOGGING 12084 move a0, rSELF 12085 daddu a1, rFP, OFF_FP_SHADOWFRAME 12086 jal MterpLogNullObjectException 12087#endif 12088 b MterpCommonFallback 12089 12090/* 12091 * If we're here, something is out of the ordinary. If there is a pending 12092 * exception, handle it. Otherwise, roll back and retry with the reference 12093 * interpreter. 12094 */ 12095MterpPossibleException: 12096 ld a0, THREAD_EXCEPTION_OFFSET(rSELF) 12097 beqzc a0, MterpFallback # If not, fall back to reference interpreter. 12098 /* intentional fallthrough - handle pending exception. */ 12099/* 12100 * On return from a runtime helper routine, we've found a pending exception. 12101 * Can we handle it here - or need to bail out to caller? 12102 * 12103 */ 12104 .extern MterpHandleException 12105 .extern MterpShouldSwitchInterpreters 12106MterpException: 12107 move a0, rSELF 12108 daddu a1, rFP, OFF_FP_SHADOWFRAME 12109 jal MterpHandleException # (self, shadow_frame) 12110 beqzc v0, MterpExceptionReturn # no local catch, back to caller. 12111 ld a0, OFF_FP_CODE_ITEM(rFP) 12112 lwu a1, OFF_FP_DEX_PC(rFP) 12113 REFRESH_IBASE 12114 daddu rPC, a0, CODEITEM_INSNS_OFFSET 12115 dlsa rPC, a1, rPC, 1 # generate new dex_pc_ptr 12116 /* Do we need to switch interpreters? */ 12117 jal MterpShouldSwitchInterpreters 12118 bnezc v0, MterpFallback 12119 /* resume execution at catch block */ 12120 EXPORT_PC 12121 FETCH_INST 12122 GET_INST_OPCODE v0 12123 GOTO_OPCODE v0 12124 /* NOTE: no fallthrough */ 12125 12126/* 12127 * Common handling for branches with support for Jit profiling. 12128 * On entry: 12129 * rINST <= signed offset 12130 * rPROFILE <= signed hotness countdown (expanded to 64 bits) 12131 * 12132 * We have quite a few different cases for branch profiling, OSR detection and 12133 * suspend check support here. 12134 * 12135 * Taken backward branches: 12136 * If profiling active, do hotness countdown and report if we hit zero. 12137 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 12138 * Is there a pending suspend request? If so, suspend. 12139 * 12140 * Taken forward branches and not-taken backward branches: 12141 * If in osr check mode, see if our target is a compiled loop header entry and do OSR if so. 12142 * 12143 * Our most common case is expected to be a taken backward branch with active jit profiling, 12144 * but no full OSR check and no pending suspend request. 12145 * Next most common case is not-taken branch with no full OSR check. 12146 * 12147 */ 12148MterpCommonTakenBranchNoFlags: 12149 bgtzc rINST, .L_forward_branch # don't add forward branches to hotness 12150/* 12151 * We need to subtract 1 from positive values and we should not see 0 here, 12152 * so we may use the result of the comparison with -1. 12153 */ 12154 li v0, JIT_CHECK_OSR 12155 beqc rPROFILE, v0, .L_osr_check 12156 bltc rPROFILE, v0, .L_resume_backward_branch 12157 dsubu rPROFILE, 1 12158 beqzc rPROFILE, .L_add_batch # counted down to zero - report 12159.L_resume_backward_branch: 12160 lw ra, THREAD_FLAGS_OFFSET(rSELF) 12161 REFRESH_IBASE 12162 daddu a2, rINST, rINST # a2<- byte offset 12163 FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST 12164 and ra, THREAD_SUSPEND_OR_CHECKPOINT_REQUEST 12165 bnezc ra, .L_suspend_request_pending 12166 GET_INST_OPCODE v0 # extract opcode from rINST 12167 GOTO_OPCODE v0 # jump to next instruction 12168 12169.L_suspend_request_pending: 12170 EXPORT_PC 12171 move a0, rSELF 12172 jal MterpSuspendCheck # (self) 12173 bnezc v0, MterpFallback 12174 REFRESH_IBASE # might have changed during suspend 12175 GET_INST_OPCODE v0 # extract opcode from rINST 12176 GOTO_OPCODE v0 # jump to next instruction 12177 12178.L_no_count_backwards: 12179 li v0, JIT_CHECK_OSR # check for possible OSR re-entry 12180 bnec rPROFILE, v0, .L_resume_backward_branch 12181.L_osr_check: 12182 move a0, rSELF 12183 daddu a1, rFP, OFF_FP_SHADOWFRAME 12184 move a2, rINST 12185 EXPORT_PC 12186 jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) 12187 bnezc v0, MterpOnStackReplacement 12188 b .L_resume_backward_branch 12189 12190.L_forward_branch: 12191 li v0, JIT_CHECK_OSR # check for possible OSR re-entry 12192 beqc rPROFILE, v0, .L_check_osr_forward 12193.L_resume_forward_branch: 12194 daddu a2, rINST, rINST # a2<- byte offset 12195 FETCH_ADVANCE_INST_RB a2 # update rPC, load rINST 12196 GET_INST_OPCODE v0 # extract opcode from rINST 12197 GOTO_OPCODE v0 # jump to next instruction 12198 12199.L_check_osr_forward: 12200 move a0, rSELF 12201 daddu a1, rFP, OFF_FP_SHADOWFRAME 12202 move a2, rINST 12203 EXPORT_PC 12204 jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) 12205 bnezc v0, MterpOnStackReplacement 12206 b .L_resume_forward_branch 12207 12208.L_add_batch: 12209 daddu a1, rFP, OFF_FP_SHADOWFRAME 12210 sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) 12211 ld a0, OFF_FP_METHOD(rFP) 12212 move a2, rSELF 12213 jal MterpAddHotnessBatch # (method, shadow_frame, self) 12214 move rPROFILE, v0 # restore new hotness countdown to rPROFILE 12215 b .L_no_count_backwards 12216 12217/* 12218 * Entered from the conditional branch handlers when OSR check request active on 12219 * not-taken path. All Dalvik not-taken conditional branch offsets are 2. 12220 */ 12221.L_check_not_taken_osr: 12222 move a0, rSELF 12223 daddu a1, rFP, OFF_FP_SHADOWFRAME 12224 li a2, 2 12225 EXPORT_PC 12226 jal MterpMaybeDoOnStackReplacement # (self, shadow_frame, offset) 12227 bnezc v0, MterpOnStackReplacement 12228 FETCH_ADVANCE_INST 2 12229 GET_INST_OPCODE v0 # extract opcode from rINST 12230 GOTO_OPCODE v0 # jump to next instruction 12231 12232/* 12233 * On-stack replacement has happened, and now we've returned from the compiled method. 12234 */ 12235MterpOnStackReplacement: 12236#if MTERP_LOGGING 12237 move a0, rSELF 12238 daddu a1, rFP, OFF_FP_SHADOWFRAME 12239 move a2, rINST # rINST contains offset 12240 jal MterpLogOSR 12241#endif 12242 li v0, 1 # Signal normal return 12243 b MterpDone 12244 12245/* 12246 * Bail out to reference interpreter. 12247 */ 12248 .extern MterpLogFallback 12249MterpFallback: 12250 EXPORT_PC 12251#if MTERP_LOGGING 12252 move a0, rSELF 12253 daddu a1, rFP, OFF_FP_SHADOWFRAME 12254 jal MterpLogFallback 12255#endif 12256MterpCommonFallback: 12257 li v0, 0 # signal retry with reference interpreter. 12258 b MterpDone 12259 12260/* 12261 * We pushed some registers on the stack in ExecuteMterpImpl, then saved 12262 * SP and RA. Here we restore SP, restore the registers, and then restore 12263 * RA to PC. 12264 * 12265 * On entry: 12266 * uint32_t* rFP (should still be live, pointer to base of vregs) 12267 */ 12268MterpExceptionReturn: 12269 li v0, 1 # signal return to caller. 12270 b MterpDone 12271/* 12272 * Returned value is expected in a0 and if it's not 64-bit, the 32 most 12273 * significant bits of a0 must be zero-extended or sign-extended 12274 * depending on the return type. 12275 */ 12276MterpReturn: 12277 ld a2, OFF_FP_RESULT_REGISTER(rFP) 12278 sd a0, 0(a2) 12279 li v0, 1 # signal return to caller. 12280MterpDone: 12281/* 12282 * At this point, we expect rPROFILE to be non-zero. If negative, hotness is disabled or we're 12283 * checking for OSR. If greater than zero, we might have unreported hotness to register 12284 * (the difference between the ending rPROFILE and the cached hotness counter). rPROFILE 12285 * should only reach zero immediately after a hotness decrement, and is then reset to either 12286 * a negative special state or the new non-zero countdown value. 12287 */ 12288 blez rPROFILE, .L_pop_and_return # if > 0, we may have some counts to report. 12289 12290MterpProfileActive: 12291 move rINST, v0 # stash return value 12292 /* Report cached hotness counts */ 12293 ld a0, OFF_FP_METHOD(rFP) 12294 daddu a1, rFP, OFF_FP_SHADOWFRAME 12295 move a2, rSELF 12296 sh rPROFILE, SHADOWFRAME_HOTNESS_COUNTDOWN_OFFSET(a1) 12297 jal MterpAddHotnessBatch # (method, shadow_frame, self) 12298 move v0, rINST # restore return value 12299 12300.L_pop_and_return: 12301 ld s6, STACK_OFFSET_S6(sp) 12302 .cfi_restore 22 12303 ld s5, STACK_OFFSET_S5(sp) 12304 .cfi_restore 21 12305 ld s4, STACK_OFFSET_S4(sp) 12306 .cfi_restore 20 12307 ld s3, STACK_OFFSET_S3(sp) 12308 .cfi_restore 19 12309 ld s2, STACK_OFFSET_S2(sp) 12310 .cfi_restore 18 12311 ld s1, STACK_OFFSET_S1(sp) 12312 .cfi_restore 17 12313 ld s0, STACK_OFFSET_S0(sp) 12314 .cfi_restore 16 12315 12316 ld ra, STACK_OFFSET_RA(sp) 12317 .cfi_restore 31 12318 12319 ld t8, STACK_OFFSET_GP(sp) 12320 .cpreturn 12321 .cfi_restore 28 12322 12323 .set noreorder 12324 jr ra 12325 daddu sp, sp, STACK_SIZE 12326 .cfi_adjust_cfa_offset -STACK_SIZE 12327 12328 .cfi_endproc 12329 .set reorder 12330 .size ExecuteMterpImpl, .-ExecuteMterpImpl 12331 12332