1 /*
2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <arch.h>
32 #include <debug.h>
33 #include <gic_v3.h>
34
gicv3_get_rdist(uintptr_t gicr_base,uint64_t mpidr)35 uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr)
36 {
37 uint32_t cpu_aff, gicr_aff;
38 uint64_t gicr_typer;
39 uintptr_t addr;
40
41 /* Construct the affinity as used by GICv3. MPIDR and GIC affinity level
42 * mask is the same.
43 */
44 cpu_aff = ((mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK) <<
45 GICV3_AFF0_SHIFT;
46 cpu_aff |= ((mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK) <<
47 GICV3_AFF1_SHIFT;
48 cpu_aff |= ((mpidr >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK) <<
49 GICV3_AFF2_SHIFT;
50 cpu_aff |= ((mpidr >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK) <<
51 GICV3_AFF3_SHIFT;
52
53 addr = gicr_base;
54 do {
55 gicr_typer = gicr_read_typer(addr);
56
57 gicr_aff = (gicr_typer >> GICR_TYPER_AFF_SHIFT) &
58 GICR_TYPER_AFF_MASK;
59 if (cpu_aff == gicr_aff) {
60 /* Disable this print for now as it appears every time
61 * when using PSCI CPU_SUSPEND.
62 * TODO: Print this only the first time for each CPU.
63 * INFO("GICv3 - Found RDIST for MPIDR(0x%lx) at 0x%lx\n",
64 * mpidr, addr);
65 */
66 return addr;
67 }
68
69 /* TODO:
70 * For GICv4 we need to adjust the Base address based on
71 * GICR_TYPER.VLPIS
72 */
73 addr += (1 << GICR_PCPUBASE_SHIFT);
74
75 } while (!(gicr_typer & GICR_TYPER_LAST));
76
77 /* If we get here we did not find a match. */
78 ERROR("GICv3 - Did not find RDIST for CPU with MPIDR 0x%lx\n", mpidr);
79 return (uintptr_t)NULL;
80 }
81