1 /*
2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include <arch_helpers.h>
32 #include <assert.h>
33 #include <bl_common.h>
34 #include <debug.h>
35 #include <console.h>
36 #include <mmio.h>
37 #include <platform.h>
38 #include <platform_def.h>
39 #include "../../bl1/bl1_private.h"
40 #include "fvp_def.h"
41 #include "fvp_private.h"
42
43 #if USE_COHERENT_MEM
44 /*******************************************************************************
45 * Declarations of linker defined symbols which will help us find the layout
46 * of trusted SRAM
47 ******************************************************************************/
48 extern unsigned long __COHERENT_RAM_START__;
49 extern unsigned long __COHERENT_RAM_END__;
50
51 /*
52 * The next 2 constants identify the extents of the coherent memory region.
53 * These addresses are used by the MMU setup code and therefore they must be
54 * page-aligned. It is the responsibility of the linker script to ensure that
55 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
56 * page-aligned addresses.
57 */
58 #define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
59 #define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
60 #endif
61
62 /* Data structure which holds the extents of the trusted SRAM for BL1*/
63 static meminfo_t bl1_tzram_layout;
64
bl1_plat_sec_mem_layout(void)65 meminfo_t *bl1_plat_sec_mem_layout(void)
66 {
67 return &bl1_tzram_layout;
68 }
69
70 /*******************************************************************************
71 * Perform any BL1 specific platform actions.
72 ******************************************************************************/
bl1_early_platform_setup(void)73 void bl1_early_platform_setup(void)
74 {
75 const size_t bl1_size = BL1_RAM_LIMIT - BL1_RAM_BASE;
76
77 /* Initialize the console to provide early debug support */
78 console_init(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ, PL011_BAUDRATE);
79
80 /* Allow BL1 to see the whole Trusted RAM */
81 bl1_tzram_layout.total_base = FVP_TRUSTED_SRAM_BASE;
82 bl1_tzram_layout.total_size = FVP_TRUSTED_SRAM_SIZE;
83
84 /* Calculate how much RAM BL1 is using and how much remains free */
85 bl1_tzram_layout.free_base = FVP_TRUSTED_SRAM_BASE;
86 bl1_tzram_layout.free_size = FVP_TRUSTED_SRAM_SIZE;
87 reserve_mem(&bl1_tzram_layout.free_base,
88 &bl1_tzram_layout.free_size,
89 BL1_RAM_BASE,
90 bl1_size);
91
92 /* Initialize the platform config for future decision making */
93 fvp_config_setup();
94 }
95
96 /*******************************************************************************
97 * Function which will evaluate how much of the trusted ram has been gobbled
98 * up by BL1 and return the base and size of whats available for loading BL2.
99 * Its called after coherency and the MMU have been turned on.
100 ******************************************************************************/
bl1_platform_setup(void)101 void bl1_platform_setup(void)
102 {
103 /* Initialise the IO layer and register platform IO devices */
104 fvp_io_setup();
105 }
106
107
108 /*******************************************************************************
109 * Perform the very early platform specific architecture setup here. At the
110 * moment this only does basic initialization. Later architectural setup
111 * (bl1_arch_setup()) does not do anything platform specific.
112 ******************************************************************************/
bl1_plat_arch_setup(void)113 void bl1_plat_arch_setup(void)
114 {
115 fvp_cci_init();
116 fvp_cci_enable();
117
118 fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
119 bl1_tzram_layout.total_size,
120 BL1_RO_BASE,
121 BL1_RO_LIMIT
122 #if USE_COHERENT_MEM
123 , BL1_COHERENT_RAM_BASE,
124 BL1_COHERENT_RAM_LIMIT
125 #endif
126 );
127 }
128
129
130 /*******************************************************************************
131 * Before calling this function BL2 is loaded in memory and its entrypoint
132 * is set by load_image. This is a placeholder for the platform to change
133 * the entrypoint of BL2 and set SPSR and security state.
134 * On FVP we are only setting the security state, entrypoint
135 ******************************************************************************/
bl1_plat_set_bl2_ep_info(image_info_t * bl2_image,entry_point_info_t * bl2_ep)136 void bl1_plat_set_bl2_ep_info(image_info_t *bl2_image,
137 entry_point_info_t *bl2_ep)
138 {
139 SET_SECURITY_STATE(bl2_ep->h.attr, SECURE);
140 bl2_ep->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
141 }
142