1 /*
2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved.
3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * Neither the name of ARM nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific
17 * prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <arch_helpers.h>
33 #include <assert.h>
34 #include <bl_common.h>
35 #include <console.h>
36 #include <debug.h>
37 #include <partitions.h>
38 #include <platform.h>
39 #include <platform_def.h>
40 #include <string.h>
41 #include <mmio.h>
42 #include <hi6220.h>
43 #include "hikey_def.h"
44 #include "hikey_private.h"
45
46 /*******************************************************************************
47 * Declarations of linker defined symbols which will help us find the layout
48 * of trusted RAM
49 ******************************************************************************/
50 extern unsigned long __RO_START__;
51 extern unsigned long __RO_END__;
52
53 extern unsigned long __COHERENT_RAM_START__;
54 extern unsigned long __COHERENT_RAM_END__;
55
56 /*
57 * The next 2 constants identify the extents of the code & RO data region.
58 * These addresses are used by the MMU setup code and therefore they must be
59 * page-aligned. It is the responsibility of the linker script to ensure that
60 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
61 */
62 #define BL2_RO_BASE (unsigned long)(&__RO_START__)
63 #define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
64
65 /*
66 * The next 2 constants identify the extents of the coherent memory region.
67 * These addresses are used by the MMU setup code and therefore they must be
68 * page-aligned. It is the responsibility of the linker script to ensure that
69 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
70 * page-aligned addresses.
71 */
72 #define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
73 #define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
74
75 /* Data structure which holds the extents of the trusted RAM for BL2 */
76 static meminfo_t bl2_tzram_layout
77 __attribute__ ((aligned(PLATFORM_CACHE_LINE_SIZE),
78 section("tzfw_coherent_mem")));
79
80 /*******************************************************************************
81 * Structure which holds the arguments which need to be passed to BL3-1
82 ******************************************************************************/
83 static bl2_to_bl31_params_mem_t bl31_params_mem;
84
bl2_plat_sec_mem_layout(void)85 meminfo_t *bl2_plat_sec_mem_layout(void)
86 {
87 return &bl2_tzram_layout;
88 }
89
90 /*******************************************************************************
91 * This function assigns a pointer to the memory that the platform has kept
92 * aside to pass platform specific and trusted firmware related information
93 * to BL31. This memory is allocated by allocating memory to
94 * bl2_to_bl31_params_mem_t structure which is a superset of all the
95 * structure whose information is passed to BL31
96 * NOTE: This function should be called only once and should be done
97 * before generating params to BL31
98 ******************************************************************************/
bl2_plat_get_bl31_params(void)99 bl31_params_t *bl2_plat_get_bl31_params(void)
100 {
101 bl31_params_t *bl2_to_bl31_params;
102
103 /*
104 * Initialise the memory for all the arguments that needs to
105 * be passed to BL3-1
106 */
107 memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t));
108
109 /* Assign memory for TF related information */
110 bl2_to_bl31_params = &bl31_params_mem.bl31_params;
111 SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
112
113 /* Fill BL3-1 related information */
114 bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
115 SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
116 VERSION_1, 0);
117
118 /* Fill BL3-2 related information if it exists */
119 #if BL32_BASE
120 bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
121 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
122 VERSION_1, 0);
123 bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
124 SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
125 VERSION_1, 0);
126 #endif
127
128 /* Fill BL3-3 related information */
129 bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
130 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
131 PARAM_EP, VERSION_1, 0);
132
133 /* BL3-3 expects to receive the primary CPU MPID (through x0) */
134 bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
135
136 bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
137 SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
138 VERSION_1, 0);
139
140 return bl2_to_bl31_params;
141 }
142
143 /*******************************************************************************
144 * This function returns a pointer to the shared memory that the platform
145 * has kept to point to entry point information of BL31 to BL2
146 ******************************************************************************/
bl2_plat_get_bl31_ep_info(void)147 struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
148 {
149 return &bl31_params_mem.bl31_ep_info;
150 }
151
init_boardid(void)152 void init_boardid(void)
153 {
154 unsigned int reg;
155
156 /* Set chip id to sram */
157 reg = read_midr_el1();
158 mmio_write_32(MEMORY_AXI_CHIP_ADDR, reg);
159 INFO("[BDID] [%x] midr: 0x%x\n", MEMORY_AXI_CHIP_ADDR, reg);
160
161 /* Set board type to sram */
162 mmio_write_32(MEMORY_AXI_BOARD_TYPE_ADDR, 0x0);
163 INFO("[BDID] [%x] board type: 0\n", MEMORY_AXI_BOARD_TYPE_ADDR);
164
165 /* Set board id to sram */
166 mmio_write_32(MEMORY_AXI_BOARD_ID_ADDR, 0x2b);
167 INFO("[BDID] [%x] board id: 0x2b\n", MEMORY_AXI_BOARD_ID_ADDR);
168
169 mmio_write_32(ACPU_ARM64_FLAGA, 0x1234);
170 mmio_write_32(ACPU_ARM64_FLAGB, 0x5678);
171 return;
172 }
173
174 /*******************************************************************************
175 * BL1 has passed the extents of the trusted RAM that should be visible to BL2
176 * in x0. This memory layout is sitting at the base of the free trusted RAM.
177 * Copy it to a safe loaction before its reclaimed by later BL2 functionality.
178 ******************************************************************************/
bl2_early_platform_setup(meminfo_t * mem_layout)179 void bl2_early_platform_setup(meminfo_t *mem_layout)
180 {
181 /* Initialize the console to provide early debug support */
182 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
183
184 /* Setup the BL2 memory layout */
185 bl2_tzram_layout = *mem_layout;
186
187 init_boardid();
188 init_acpu_dvfs();
189
190 io_setup();
191 get_partition();
192 }
193
194 /*******************************************************************************
195 * Perform platform specific setup, i.e. initialize the IO layer, load BL3-0
196 * image and initialise the memory location to use for passing arguments to
197 * BL3-1.
198 ******************************************************************************/
bl2_platform_setup(void)199 void bl2_platform_setup(void)
200 {
201 plat_security_setup();
202 }
203
204 /* Flush the TF params and the TF plat params */
bl2_plat_flush_bl31_params(void)205 void bl2_plat_flush_bl31_params(void)
206 {
207 flush_dcache_range((unsigned long)&bl31_params_mem,
208 sizeof(bl2_to_bl31_params_mem_t));
209 }
210
211 /*******************************************************************************
212 * Perform the very early platform specific architectural setup here. At the
213 * moment this is only intializes the mmu in a quick and dirty way.
214 ******************************************************************************/
bl2_plat_arch_setup(void)215 void bl2_plat_arch_setup(void)
216 {
217 configure_mmu_el1(bl2_tzram_layout.total_base,
218 bl2_tzram_layout.total_size,
219 BL2_RO_BASE,
220 BL2_RO_LIMIT,
221 BL2_COHERENT_RAM_BASE,
222 BL2_COHERENT_RAM_LIMIT);
223 }
224
225 /*******************************************************************************
226 * Populate the extents of memory available for loading BL3-0, i.e. anywhere
227 * in trusted RAM as long as it doesn't overwrite BL2.
228 ******************************************************************************/
bl2_plat_get_bl30_meminfo(meminfo_t * bl30_meminfo)229 void bl2_plat_get_bl30_meminfo(meminfo_t *bl30_meminfo)
230 {
231 bl30_meminfo->total_base = BL30_BASE;
232 bl30_meminfo->total_size = BL30_SIZE;
233 bl30_meminfo->free_base = BL30_BASE;
234 bl30_meminfo->free_size = BL30_SIZE;
235 }
236
237 /*******************************************************************************
238 * Transfer BL3-0 from Trusted RAM using the SCP Download protocol.
239 * Return 0 on success, -1 otherwise.
240 ******************************************************************************/
bl2_plat_handle_bl30(image_info_t * bl30_image_info)241 int bl2_plat_handle_bl30(image_info_t *bl30_image_info)
242 {
243 int *buf = (int *)bl30_image_info->image_base;
244
245 INFO("%s: [%x] %x %x %x %x\n",
246 __func__, buf, buf[0], buf[1], buf[2], buf[3]);
247
248 buf += 50;
249 INFO("%s: [%x] %x %x %x %x\n",
250 __func__, buf, buf[0], buf[1], buf[2], buf[3]);
251
252 buf += 50;
253 INFO("%s: [%x] %x %x %x %x\n",
254 __func__, buf, buf[0], buf[1], buf[2], buf[3]);
255
256 buf = (int *)(bl30_image_info->image_base +
257 bl30_image_info->image_size);
258 buf -= 4;
259 INFO("%s: [%x] %x %x %x %x\n",
260 __func__, buf, buf[0], buf[1], buf[2], buf[3]);
261
262 /* enable mcu sram */
263 hisi_mcu_enable_sram();
264
265 /* load mcu binary to sram */
266 hisi_mcu_load_image(bl30_image_info->image_base,
267 bl30_image_info->image_size);
268
269 /* let mcu to run */
270 hisi_mcu_start_run();
271
272 INFO("%s: mcu pc is %x\n",
273 __func__, mmio_read_32(AO_SC_MCU_SUBSYS_STAT2));
274
275 INFO("%s: AO_SC_PERIPH_CLKSTAT4 is %x\n",
276 __func__, mmio_read_32(AO_SC_PERIPH_CLKSTAT4));
277 return 0;
278 }
279
280 /*******************************************************************************
281 * Before calling this function BL31 is loaded in memory and its entrypoint
282 * is set by load_image. This is a placeholder for the platform to change
283 * the entrypoint of BL31 and set SPSR and security state.
284 * On Juno we are only setting the security state, entrypoint
285 ******************************************************************************/
bl2_plat_set_bl31_ep_info(image_info_t * bl31_image_info,entry_point_info_t * bl31_ep_info)286 void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
287 entry_point_info_t *bl31_ep_info)
288 {
289 SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
290 bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
291 DISABLE_ALL_EXCEPTIONS);
292 }
293
294 /*******************************************************************************
295 * Before calling this function BL32 is loaded in memory and its entrypoint
296 * is set by load_image. This is a placeholder for the platform to change
297 * the entrypoint of BL32 and set SPSR and security state.
298 * On Juno we are only setting the security state, entrypoint
299 ******************************************************************************/
bl2_plat_set_bl32_ep_info(image_info_t * bl32_image_info,entry_point_info_t * bl32_ep_info)300 void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
301 entry_point_info_t *bl32_ep_info)
302 {
303 SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
304 /*
305 * The Secure Payload Dispatcher service is responsible for
306 * setting the SPSR prior to entry into the BL32 image.
307 */
308 bl32_ep_info->spsr = 0;
309 }
310
311 /*******************************************************************************
312 * Before calling this function BL33 is loaded in memory and its entrypoint
313 * is set by load_image. This is a placeholder for the platform to change
314 * the entrypoint of BL33 and set SPSR and security state.
315 * On Juno we are only setting the security state, entrypoint
316 ******************************************************************************/
bl2_plat_set_bl33_ep_info(image_info_t * image,entry_point_info_t * bl33_ep_info)317 void bl2_plat_set_bl33_ep_info(image_info_t *image,
318 entry_point_info_t *bl33_ep_info)
319 {
320 unsigned long el_status;
321 unsigned int mode;
322
323 /* Figure out what mode we enter the non-secure world in */
324 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
325 el_status &= ID_AA64PFR0_ELX_MASK;
326
327 if (el_status)
328 mode = MODE_EL2;
329 else
330 mode = MODE_EL1;
331
332 /*
333 * TODO: Consider the possibility of specifying the SPSR in
334 * the FIP ToC and allowing the platform to have a say as
335 * well.
336 */
337 bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX,
338 DISABLE_ALL_EXCEPTIONS);
339 SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
340 }
341
342 /*******************************************************************************
343 * Populate the extents of memory available for loading BL3-2
344 ******************************************************************************/
bl2_plat_get_bl32_meminfo(meminfo_t * bl32_meminfo)345 void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
346 {
347 /*
348 * Populate the extents of memory available for loading BL3-2.
349 */
350 bl32_meminfo->total_base = BL32_BASE;
351 bl32_meminfo->free_base = BL32_BASE;
352 bl32_meminfo->total_size =
353 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
354 bl32_meminfo->free_size =
355 (TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
356 }
357
358 /*******************************************************************************
359 * Populate the extents of memory available for loading BL3-3
360 ******************************************************************************/
bl2_plat_get_bl33_meminfo(meminfo_t * bl33_meminfo)361 void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
362 {
363 bl33_meminfo->total_base = DRAM_NS_BASE;
364 bl33_meminfo->total_size = DRAM_NS_SIZE;
365 bl33_meminfo->free_base = DRAM_NS_BASE;
366 bl33_meminfo->free_size = DRAM_NS_SIZE;
367 }
368