1 /*
2 * Copyright (c) 2014-2015, Linaro Ltd and Contributors. All rights reserved.
3 * Copyright (c) 2014-2015, Hisilicon Ltd and Contributors. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * Redistributions of source code must retain the above copyright notice, this
9 * list of conditions and the following disclaimer.
10 *
11 * Redistributions in binary form must reproduce the above copyright notice,
12 * this list of conditions and the following disclaimer in the documentation
13 * and/or other materials provided with the distribution.
14 *
15 * Neither the name of ARM nor the names of its contributors may be used
16 * to endorse or promote products derived from this software without specific
17 * prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <arch.h>
33 #include <arm_gic.h>
34 #include <assert.h>
35 #include <bl31.h>
36 #include <bl_common.h>
37 #include <cci400.h>
38 #include <console.h>
39 #include <debug.h>
40 #include <hisi_ipc.h>
41 #include <hisi_pwrc.h>
42 #include <mmio.h>
43 #include <platform.h>
44 #include <stddef.h>
45 #include <hi6220_regs_ao.h>
46 #include <hi6220.h>
47
48 #include "hikey_def.h"
49 #include "hikey_private.h"
50
51 /*******************************************************************************
52 * Declarations of linker defined symbols which will help us find the layout
53 * of trusted RAM
54 ******************************************************************************/
55 extern unsigned long __RO_START__;
56 extern unsigned long __RO_END__;
57
58 extern unsigned long __COHERENT_RAM_START__;
59 extern unsigned long __COHERENT_RAM_END__;
60
61 /*
62 * The next 2 constants identify the extents of the code & RO data region.
63 * These addresses are used by the MMU setup code and therefore they must be
64 * page-aligned. It is the responsibility of the linker script to ensure that
65 * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
66 */
67 #define BL31_RO_BASE (unsigned long)(&__RO_START__)
68 #define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
69
70 /*
71 * The next 2 constants identify the extents of the coherent memory region.
72 * These addresses are used by the MMU setup code and therefore they must be
73 * page-aligned. It is the responsibility of the linker script to ensure that
74 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
75 * refer to page-aligned addresses.
76 */
77 #define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
78 #define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
79
80 /******************************************************************************
81 * Placeholder variables for copying the arguments that have been passed to
82 * BL3-1 from BL2.
83 ******************************************************************************/
84 static entry_point_info_t bl32_ep_info;
85 static entry_point_info_t bl33_ep_info;
86
87 /*******************************************************************************
88 * Return a pointer to the 'entry_point_info' structure of the next image for
89 * the security state specified. BL3-3 corresponds to the non-secure image type
90 * while BL3-2 corresponds to the secure image type. A NULL pointer is returned
91 * if the image does not exist.
92 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)93 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
94 {
95 entry_point_info_t *next_image_info;
96
97 next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
98
99 /* None of the images on this platform can have 0x0 as the entrypoint */
100 if (next_image_info->pc)
101 return next_image_info;
102 else
103 return NULL;
104 }
105
106 /*******************************************************************************
107 * Perform any BL3-1 specific platform actions. Here is an opportunity to copy
108 * parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
109 * are lost (potentially). This needs to be done before the MMU is initialized
110 * so that the memory layout can be used while creating page tables. Also, BL2
111 * has flushed this information to memory, so we are guaranteed to pick up good
112 * data
113 ******************************************************************************/
bl31_early_platform_setup(bl31_params_t * from_bl2,void * plat_params_from_bl2)114 void bl31_early_platform_setup(bl31_params_t *from_bl2,
115 void *plat_params_from_bl2)
116 {
117 /* Initialize the console to provide early debug support */
118 console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
119
120 /*
121 * Initialise the CCI-400 driver for BL31 so that it is accessible after
122 * a warm boot. BL1 should have already enabled CCI coherency for this
123 * cluster during cold boot.
124 */
125 cci_init(CCI400_BASE,
126 CCI400_SL_IFACE3_CLUSTER_IX,
127 CCI400_SL_IFACE4_CLUSTER_IX);
128
129 /*
130 * Copy BL3-2 and BL3-3 entry point information.
131 * They are stored in Secure RAM, in BL2's address space.
132 */
133 bl32_ep_info = *from_bl2->bl32_ep_info;
134 bl33_ep_info = *from_bl2->bl33_ep_info;
135 }
136
init_rtc(void)137 static void init_rtc(void)
138 {
139 uint32_t data;
140
141 data = mmio_read_32(AO_SC_PERIPH_CLKEN4);
142 data |= AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N;
143 mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
144 }
145
init_edma(void)146 static void init_edma(void)
147 {
148 int i;
149
150 mmio_write_32(EDMAC_SEC_CTRL, 0x3);
151
152 for (i = 0; i <= 15; i++) {
153 VERBOSE("EDMAC_AXI_CONF(%d): data:0x%x\n", i, mmio_read_32(EDMAC_AXI_CONF(i)));
154 mmio_write_32(EDMAC_AXI_CONF(i), (1 << 6) | (1 << 18));
155 VERBOSE("EDMAC_AXI_CONF(%d): data:0x%x\n", i, mmio_read_32(EDMAC_AXI_CONF(i)));
156 }
157 }
158
159 /*******************************************************************************
160 * Initialize the GIC.
161 ******************************************************************************/
bl31_platform_setup(void)162 void bl31_platform_setup(void)
163 {
164 /* Initialize the gic cpu and distributor interfaces */
165 plat_gic_init();
166 arm_gic_setup();
167
168 init_rtc();
169 init_edma();
170 hisi_ipc_init();
171 hisi_pwrc_setup();
172 }
173
174 /*******************************************************************************
175 * Perform the very early platform specific architectural setup here. At the
176 * moment this is only intializes the mmu in a quick and dirty way.
177 ******************************************************************************/
bl31_plat_arch_setup()178 void bl31_plat_arch_setup()
179 {
180 configure_mmu_el3(BL31_RO_BASE,
181 BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE,
182 BL31_RO_BASE,
183 BL31_RO_LIMIT,
184 BL31_COHERENT_RAM_BASE,
185 BL31_COHERENT_RAM_LIMIT);
186 }
187