1/* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31#include <arch.h> 32#include <asm_macros.S> 33#include "../juno_def.h" 34 35 .globl platform_is_primary_cpu 36 .globl platform_get_entrypoint 37 .globl platform_cold_boot_init 38 .globl plat_secondary_cold_boot_setup 39 40 /* ----------------------------------------------------- 41 * unsigned int platform_is_primary_cpu (unsigned int mpid); 42 * 43 * Given the mpidr say whether this cpu is the primary 44 * cpu (applicable ony after a cold boot) 45 * ----------------------------------------------------- 46 */ 47func platform_is_primary_cpu 48 mov x9, x30 49 bl platform_get_core_pos 50 ldr x1, =SCP_BOOT_CFG_ADDR 51 ldr x1, [x1] 52 ubfx x1, x1, #PRIMARY_CPU_SHIFT, #PRIMARY_CPU_MASK 53 cmp x0, x1 54 cset x0, eq 55 ret x9 56 57 /* ----------------------------------------------------- 58 * void plat_secondary_cold_boot_setup (void); 59 * 60 * This function performs any platform specific actions 61 * needed for a secondary cpu after a cold reset e.g 62 * mark the cpu's presence, mechanism to place it in a 63 * holding pen etc. 64 * ----------------------------------------------------- 65 */ 66func plat_secondary_cold_boot_setup 67 /* Juno todo: Implement secondary CPU cold boot setup on Juno */ 68cb_panic: 69 b cb_panic 70 71 72 /* ----------------------------------------------------- 73 * void platform_get_entrypoint (unsigned int mpid); 74 * 75 * Main job of this routine is to distinguish between 76 * a cold and warm boot. 77 * On a cold boot the secondaries first wait for the 78 * platform to be initialized after which they are 79 * hotplugged in. The primary proceeds to perform the 80 * platform initialization. 81 * On a warm boot, each cpu jumps to the address in its 82 * mailbox. 83 * 84 * TODO: Not a good idea to save lr in a temp reg 85 * ----------------------------------------------------- 86 */ 87func platform_get_entrypoint 88 mov x9, x30 // lr 89 bl platform_get_core_pos 90 ldr x1, =TRUSTED_MAILBOXES_BASE 91 lsl x0, x0, #TRUSTED_MAILBOX_SHIFT 92 ldr x0, [x1, x0] 93 ret x9 94 95 96 /* ----------------------------------------------------- 97 * void platform_cold_boot_init (bl1_main function); 98 * 99 * Routine called only by the primary cpu after a cold 100 * boot to perform early platform initialization 101 * ----------------------------------------------------- 102 */ 103func platform_cold_boot_init 104 mov x20, x0 105 106 /* --------------------------------------------- 107 * Give ourselves a small coherent stack to 108 * ease the pain of initializing the MMU and 109 * CCI in assembler 110 * --------------------------------------------- 111 */ 112 mrs x0, mpidr_el1 113 bl platform_set_coherent_stack 114 115 /* --------------------------------------------- 116 * Architectural init. can be generic e.g. 117 * enabling stack alignment and platform spec- 118 * ific e.g. MMU & page table setup as per the 119 * platform memory map. Perform the latter here 120 * and the former in bl1_main. 121 * --------------------------------------------- 122 */ 123 bl bl1_early_platform_setup 124 bl bl1_plat_arch_setup 125 126 /* --------------------------------------------- 127 * Give ourselves a stack allocated in Normal 128 * -IS-WBWA memory 129 * --------------------------------------------- 130 */ 131 mrs x0, mpidr_el1 132 bl platform_set_stack 133 134 /* --------------------------------------------- 135 * Jump to the main function. Returning from it 136 * is a terminal error. 137 * --------------------------------------------- 138 */ 139 blr x20 140 141cb_init_panic: 142 b cb_init_panic 143