1 /* 2 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __PLATFORM_DEF_H__ 32 #define __PLATFORM_DEF_H__ 33 34 #include <arch.h> 35 #include "../juno_def.h" 36 37 /******************************************************************************* 38 * Platform binary types for linking 39 ******************************************************************************/ 40 #define PLATFORM_LINKER_FORMAT "elf64-littleaarch64" 41 #define PLATFORM_LINKER_ARCH aarch64 42 43 /******************************************************************************* 44 * Generic platform constants 45 ******************************************************************************/ 46 47 /* Size of cacheable stacks */ 48 #if TRUSTED_BOARD_BOOT && (IMAGE_BL1 || IMAGE_BL2) 49 #define PLATFORM_STACK_SIZE 0x1000 50 #else 51 #define PLATFORM_STACK_SIZE 0x800 52 #endif 53 54 #define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n" 55 56 /* Trusted Boot Firmware BL2 */ 57 #define BL2_IMAGE_NAME "bl2.bin" 58 59 /* EL3 Runtime Firmware BL3-1 */ 60 #define BL31_IMAGE_NAME "bl31.bin" 61 62 /* SCP Firmware BL3-0 */ 63 #define BL30_IMAGE_NAME "bl30.bin" 64 65 /* Secure Payload BL3-2 (Trusted OS) */ 66 #define BL32_IMAGE_NAME "bl32.bin" 67 68 /* Non-Trusted Firmware BL3-3 */ 69 #define BL33_IMAGE_NAME "bl33.bin" /* e.g. UEFI */ 70 71 /* Firmware Image Package */ 72 #define FIP_IMAGE_NAME "fip.bin" 73 74 #if TRUSTED_BOARD_BOOT 75 /* Certificates */ 76 # define BL2_CERT_NAME "bl2.crt" 77 # define TRUSTED_KEY_CERT_NAME "trusted_key.crt" 78 79 # define BL30_KEY_CERT_NAME "bl30_key.crt" 80 # define BL31_KEY_CERT_NAME "bl31_key.crt" 81 # define BL32_KEY_CERT_NAME "bl32_key.crt" 82 # define BL33_KEY_CERT_NAME "bl33_key.crt" 83 84 # define BL30_CERT_NAME "bl30.crt" 85 # define BL31_CERT_NAME "bl31.crt" 86 # define BL32_CERT_NAME "bl32.crt" 87 # define BL33_CERT_NAME "bl33.crt" 88 #endif /* TRUSTED_BOARD_BOOT */ 89 90 #define PLATFORM_CACHE_LINE_SIZE 64 91 #define PLATFORM_CLUSTER_COUNT 2 92 #define PLATFORM_CORE_COUNT 6 93 #define PLATFORM_NUM_AFFS (PLATFORM_CLUSTER_COUNT + \ 94 PLATFORM_CORE_COUNT) 95 #define MAX_IO_DEVICES 3 96 #define MAX_IO_HANDLES 4 97 98 /******************************************************************************* 99 * BL1 specific defines. 100 * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base 101 * addresses. 102 ******************************************************************************/ 103 #define BL1_RO_BASE TZROM_BASE 104 #define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE) 105 106 /* 107 * Put BL1 RW at the top of the Trusted SRAM. BL1_RW_BASE is calculated using 108 * the current BL1 RW debug size plus a little space for growth. 109 */ 110 #if TRUSTED_BOARD_BOOT 111 #define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x8000) 112 #else 113 #define BL1_RW_BASE (TZRAM_BASE + TZRAM_SIZE - 0x6000) 114 #endif 115 #define BL1_RW_LIMIT (TZRAM_BASE + TZRAM_SIZE) 116 117 /******************************************************************************* 118 * BL2 specific defines. 119 ******************************************************************************/ 120 /* 121 * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug 122 * size plus a little space for growth. 123 */ 124 #if TRUSTED_BOARD_BOOT 125 #define BL2_BASE (BL31_BASE - 0x1D000) 126 #else 127 #define BL2_BASE (BL31_BASE - 0xC000) 128 #endif 129 #define BL2_LIMIT BL31_BASE 130 131 /******************************************************************************* 132 * Load address of BL3-0 in the Juno port 133 * BL3-0 is loaded to the same place as BL3-1. Once BL3-0 is transferred to the 134 * SCP, it is discarded and BL3-1 is loaded over the top. 135 ******************************************************************************/ 136 #define BL30_BASE BL31_BASE 137 138 /******************************************************************************* 139 * BL3-1 specific defines. 140 ******************************************************************************/ 141 /* 142 * Put BL3-1 at the top of the Trusted SRAM. BL31_BASE is calculated using the 143 * current BL3-1 debug size plus a little space for growth. 144 */ 145 #define BL31_BASE (TZRAM_BASE + TZRAM_SIZE - 0x1D000) 146 #define BL31_PROGBITS_LIMIT BL1_RW_BASE 147 #define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE) 148 149 /******************************************************************************* 150 * BL3-2 specific defines. 151 ******************************************************************************/ 152 153 /* 154 * The TSP can execute either from Trusted SRAM or Trusted DRAM. 155 */ 156 #define BL32_SRAM_BASE TZRAM_BASE 157 #define BL32_SRAM_LIMIT BL31_BASE 158 #define BL32_DRAM_BASE DRAM_SEC_BASE 159 #define BL32_DRAM_LIMIT (DRAM_SEC_BASE + DRAM_SEC_SIZE) 160 161 #if (PLAT_TSP_LOCATION_ID == PLAT_TRUSTED_SRAM_ID) 162 # define TSP_SEC_MEM_BASE TZRAM_BASE 163 # define TSP_SEC_MEM_SIZE TZRAM_SIZE 164 # define BL32_BASE BL32_SRAM_BASE 165 # define BL32_LIMIT BL32_SRAM_LIMIT 166 //# define BL32_PROGBITS_LIMIT BL2_BASE 167 #elif (PLAT_TSP_LOCATION_ID == PLAT_DRAM_ID) 168 # define TSP_SEC_MEM_BASE DRAM_SEC_BASE 169 # define TSP_SEC_MEM_SIZE DRAM_SEC_SIZE 170 # define BL32_BASE BL32_DRAM_BASE 171 # define BL32_LIMIT BL32_DRAM_LIMIT 172 #else 173 # error "Unsupported PLAT_TSP_LOCATION_ID value" 174 #endif 175 176 /******************************************************************************* 177 * Load address of BL3-3 in the Juno port 178 ******************************************************************************/ 179 #define NS_IMAGE_OFFSET 0xE0000000 180 181 /******************************************************************************* 182 * Platform specific page table and MMU setup constants 183 ******************************************************************************/ 184 #define ADDR_SPACE_SIZE (1ull << 32) 185 186 #if IMAGE_BL1 || IMAGE_BL31 187 # define MAX_XLAT_TABLES 3 188 #endif 189 190 #if IMAGE_BL2 || IMAGE_BL32 191 # define MAX_XLAT_TABLES 3 192 #endif 193 194 #define MAX_MMAP_REGIONS 16 195 196 /******************************************************************************* 197 * ID of the secure physical generic timer interrupt used by the TSP 198 ******************************************************************************/ 199 #define TSP_IRQ_SEC_PHY_TIMER IRQ_SEC_PHY_TIMER 200 201 /******************************************************************************* 202 * Declarations and constants to access the mailboxes safely. Each mailbox is 203 * aligned on the biggest cache line size in the platform. This is known only 204 * to the platform as it might have a combination of integrated and external 205 * caches. Such alignment ensures that two maiboxes do not sit on the same cache 206 * line at any cache level. They could belong to different cpus/clusters & 207 * get written while being protected by different locks causing corruption of 208 * a valid mailbox address. 209 ******************************************************************************/ 210 #define CACHE_WRITEBACK_SHIFT 6 211 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) 212 213 #if !USE_COHERENT_MEM 214 /******************************************************************************* 215 * Size of the per-cpu data in bytes that should be reserved in the generic 216 * per-cpu data structure for the Juno port. 217 ******************************************************************************/ 218 #define PLAT_PCPU_DATA_SIZE 2 219 #endif 220 221 #endif /* __PLATFORM_DEF_H__ */ 222