1#/** @file 2# ARM processor package. 3# 4# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR> 5# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved. 6# 7# This program and the accompanying materials 8# are licensed and made available under the terms and conditions of the BSD License 9# which accompanies this distribution. The full text of the license may be found at 10# http://opensource.org/licenses/bsd-license.php 11# 12# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 13# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 14# 15#**/ 16 17[Defines] 18 DEC_SPECIFICATION = 0x00010005 19 PACKAGE_NAME = ArmPkg 20 PACKAGE_GUID = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F 21 PACKAGE_VERSION = 0.1 22 23################################################################################ 24# 25# Include Section - list of Include Paths that are provided by this package. 26# Comments are used for Keywords and Module Types. 27# 28# Supported Module Types: 29# BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION 30# 31################################################################################ 32[Includes.common] 33 Include # Root include for the package 34 35[LibraryClasses.common] 36 ArmLib|Include/Library/ArmLib.h 37 SemihostLib|Include/Library/Semihosting.h 38 UncachedMemoryAllocationLib|Include/Library/UncachedMemoryAllocationLib.h 39 DefaultExceptionHandlerLib|Include/Library/DefaultExceptionHandlerLib.h 40 ArmDisassemblerLib|Include/Library/ArmDisassemblerLib.h 41 ArmGicArchLib|Include/Library/ArmGicArchLib.h 42 43[Guids.common] 44 gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } } 45 46 ## ARM MPCore table 47 # Include/Guid/ArmMpCoreInfo.h 48 gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} } 49 50[Ppis] 51 ## Include/Ppi/ArmMpCoreInfo.h 52 gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} } 53 54[Protocols.common] 55 gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } } 56 57[PcdsFeatureFlag.common] 58 gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001 59 60 # On ARM Architecture with the Security Extension, the address for the 61 # Vector Table can be mapped anywhere in the memory map. It means we can 62 # point the Exception Vector Table to its location in CpuDxe. 63 # By default we copy the Vector Table at PcdGet32(PcdCpuVectorBaseAddress) 64 gArmTokenSpaceGuid.PcdRelocateVectorTable|TRUE|BOOLEAN|0x00000022 65 # Set this PCD to TRUE if the Exception Vector is changed to add debugger support before 66 # it has been configured by the CPU DXE 67 gArmTokenSpaceGuid.PcdDebuggerExceptionSupport|FALSE|BOOLEAN|0x00000032 68 69 # Define if the spin-table mechanism is used by the secondary cores when booting 70 # Linux (instead of PSCI) 71 gArmTokenSpaceGuid.PcdArmLinuxSpinTable|FALSE|BOOLEAN|0x00000033 72 73 # Define if the GICv3 controller should use the GICv2 legacy 74 gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042 75 76[PcdsFeatureFlag.ARM] 77 # Whether to map normal memory as non-shareable. FALSE is the safe choice, but 78 # TRUE may be appropriate to fix performance problems if you don't care about 79 # hardware coherency (i.e., no virtualization or cache coherent DMA) 80 gArmTokenSpaceGuid.PcdNormalMemoryNonshareableOverride|FALSE|BOOLEAN|0x00000043 81 82[PcdsFixedAtBuild.common] 83 gArmTokenSpaceGuid.PcdTrustzoneSupport|FALSE|BOOLEAN|0x00000006 84 85 # This PCD should be a FeaturePcd. But we used this PCD as an '#if' in an ASM file. 86 # Using a FeaturePcd make a '(BOOLEAN) casting for its value which is not understood by the preprocessor. 87 gArmTokenSpaceGuid.PcdVFPEnabled|0|UINT32|0x00000024 88 89 gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002 90 # This PCD will free the unallocated buffers if their size reach this threshold. 91 # We set the default value to 512MB. 92 gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003 93 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004 94 gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005 95 96 # 97 # ARM Secure Firmware PCDs 98 # 99 gArmTokenSpaceGuid.PcdSecureFdBaseAddress|0|UINT64|0x00000015 100 gArmTokenSpaceGuid.PcdSecureFdSize|0|UINT32|0x00000016 101 gArmTokenSpaceGuid.PcdSecureFvBaseAddress|0x0|UINT64|0x0000002F 102 gArmTokenSpaceGuid.PcdSecureFvSize|0x0|UINT32|0x00000030 103 104 # 105 # ARM Hypervisor Firmware PCDs 106 # 107 gArmTokenSpaceGuid.PcdHypFdBaseAddress|0|UINT32|0x0000003A 108 gArmTokenSpaceGuid.PcdHypFdSize|0|UINT32|0x0000003B 109 gArmTokenSpaceGuid.PcdHypFvBaseAddress|0|UINT32|0x0000003C 110 gArmTokenSpaceGuid.PcdHypFvSize|0|UINT32|0x0000003D 111 112 # Use ClusterId + CoreId to identify the PrimaryCore 113 gArmTokenSpaceGuid.PcdArmPrimaryCoreMask|0xF03|UINT32|0x00000031 114 # The Primary Core is ClusterId[0] & CoreId[0] 115 gArmTokenSpaceGuid.PcdArmPrimaryCore|0|UINT32|0x00000037 116 117 # 118 # ARM L2x0 PCDs 119 # 120 gArmTokenSpaceGuid.PcdL2x0ControllerBase|0|UINT32|0x0000001B 121 122 # 123 # BdsLib 124 # 125 # The compressed Linux kernel is expected to be under 128MB from the beginning of the System Memory 126 gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x08000000|UINT32|0x0000001F 127 # Maximum file size for TFTP servers that do not support 'tsize' extension 128 gArmTokenSpaceGuid.PcdMaxTftpFileSize|0x01000000|UINT32|0x00000000 129 130 # 131 # ARM Normal (or Non Secure) Firmware PCDs 132 # 133 gArmTokenSpaceGuid.PcdFdSize|0|UINT32|0x0000002C 134 gArmTokenSpaceGuid.PcdFvSize|0|UINT32|0x0000002E 135 136[PcdsFixedAtBuild.common, PcdsPatchableInModule.common] 137 gArmTokenSpaceGuid.PcdFdBaseAddress|0|UINT64|0x0000002B 138 gArmTokenSpaceGuid.PcdFvBaseAddress|0|UINT64|0x0000002D 139 140[PcdsFixedAtBuild.ARM] 141 # 142 # ARM Security Extension 143 # 144 145 # Secure Configuration Register 146 # - BIT0 : NS - Non Secure bit 147 # - BIT1 : IRQ Handler 148 # - BIT2 : FIQ Handler 149 # - BIT3 : EA - External Abort 150 # - BIT4 : FW - F bit writable 151 # - BIT5 : AW - A bit writable 152 # - BIT6 : nET - Not Early Termination 153 # - BIT7 : SCD - Secure Monitor Call Disable 154 # - BIT8 : HCE - Hyp Call enable 155 # - BIT9 : SIF - Secure Instruction Fetch 156 # 0x31 = NS | EA | FW 157 gArmTokenSpaceGuid.PcdArmScr|0x31|UINT32|0x00000038 158 159 # By default we do not do a transition to non-secure mode 160 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x0|UINT32|0x0000003E 161 162 # The Linux ATAGs are expected to be under 0x4000 (16KB) from the beginning of the System Memory 163 gArmTokenSpaceGuid.PcdArmLinuxAtagMaxOffset|0x4000|UINT32|0x00000020 164 165 # If the fixed FDT address is not available, then it should be loaded below the kernel. 166 # The recommendation from the Linux kernel is to have the FDT below 16KB. 167 # (see the kernel doc: Documentation/arm/Booting) 168 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x4000|UINT32|0x00000023 169 # The FDT blob must be loaded at a 64bit aligned address. 170 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x8|UINT32|0x00000026 171 172 # Non Secure Access Control Register 173 # - BIT15 : NSASEDIS - Disable Non-secure Advanced SIMD functionality 174 # - BIT14 : NSD32DIS - Disable Non-secure use of D16-D31 175 # - BIT11 : cp11 - Non-secure access to coprocessor 11 enable 176 # - BIT10 : cp10 - Non-secure access to coprocessor 10 enable 177 # 0xC00 = cp10 | cp11 178 gArmTokenSpaceGuid.PcdArmNsacr|0xC00|UINT32|0x00000039 179 180[PcdsFixedAtBuild.AARCH64] 181 # 182 # AArch64 Security Extension 183 # 184 185 # Secure Configuration Register 186 # - BIT0 : NS - Non Secure bit 187 # - BIT1 : IRQ Handler 188 # - BIT2 : FIQ Handler 189 # - BIT3 : EA - External Abort 190 # - BIT4 : FW - F bit writable 191 # - BIT5 : AW - A bit writable 192 # - BIT6 : nET - Not Early Termination 193 # - BIT7 : SCD - Secure Monitor Call Disable 194 # - BIT8 : HCE - Hyp Call enable 195 # - BIT9 : SIF - Secure Instruction Fetch 196 # - BIT10: RW - Register width control for lower exception levels 197 # - BIT11: SIF - Enables Secure EL1 access to EL1 Architectural Timer 198 # - BIT12: TWI - Trap WFI 199 # - BIT13: TWE - Trap WFE 200 # 0x501 = NS | HCE | RW 201 gArmTokenSpaceGuid.PcdArmScr|0x501|UINT32|0x00000038 202 203 # By default we do transition to EL2 non-secure mode with Stack for EL2. 204 # Mode Description Bits 205 # NS EL2 SP2 all interrupts disabled = 0x3c9 206 # NS EL1 SP1 all interrupts disabled = 0x3c5 207 # Other modes include using SP0 or switching to Aarch32, but these are 208 # not currently supported. 209 gArmTokenSpaceGuid.PcdArmNonSecModeTransition|0x3c9|UINT32|0x0000003E 210 # If the fixed FDT address is not available, then it should be loaded above the kernel. 211 # The recommendation from the AArch64 Linux kernel is to have the FDT below 512MB. 212 # (see the kernel doc: Documentation/arm64/booting.txt) 213 gArmTokenSpaceGuid.PcdArmLinuxFdtMaxOffset|0x20000000|UINT32|0x00000023 214 # The FDT blob must be loaded at a 2MB aligned address. 215 gArmTokenSpaceGuid.PcdArmLinuxFdtAlignment|0x00200000|UINT32|0x00000026 216 217 218# 219# These PCDs are also defined as 'PcdsDynamic' or 'PcdsPatchableInModule' to be 220# redefined when using UEFI in a context of virtual machine. 221# 222[PcdsFixedAtBuild.common, PcdsDynamic.common, PcdsPatchableInModule.common] 223 224 # System Memory (DRAM): These PCDs define the region of in-built system memory 225 # Some platforms can get DRAM extensions, these additional regions will be declared 226 # to UEFI by ArmPlatformLib 227 gArmTokenSpaceGuid.PcdSystemMemoryBase|0|UINT64|0x00000029 228 gArmTokenSpaceGuid.PcdSystemMemorySize|0|UINT64|0x0000002A 229 230[PcdsFixedAtBuild.common, PcdsDynamic.common] 231 # 232 # ARM Architectural Timer 233 # 234 gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0|UINT32|0x00000034 235 236 # ARM Architectural Timer Interrupt(GIC PPI) numbers 237 gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum|29|UINT32|0x00000035 238 gArmTokenSpaceGuid.PcdArmArchTimerIntrNum|30|UINT32|0x00000036 239 gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum|26|UINT32|0x00000040 240 gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum|27|UINT32|0x00000041 241 242 # 243 # ARM Generic Watchdog 244 # 245 246 gArmTokenSpaceGuid.PcdGenericWatchdogControlBase|0x2A440000|UINT32|0x00000007 247 gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase|0x2A450000|UINT32|0x00000008 248 gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum|93|UINT32|0x00000009 249 250 # 251 # ARM Generic Interrupt Controller 252 # 253 gArmTokenSpaceGuid.PcdGicDistributorBase|0|UINT32|0x0000000C 254 # Base address for the GIC Redistributor region that contains the boot CPU 255 gArmTokenSpaceGuid.PcdGicRedistributorsBase|0|UINT32|0x0000000E 256 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0|UINT32|0x0000000D 257 gArmTokenSpaceGuid.PcdGicSgiIntId|0|UINT32|0x00000025 258