1 /** @file 2 * 3 * Copyright (c) 2012, ARM Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #include <Library/ArmPlatformLib.h> 16 #include <Library/DebugLib.h> 17 #include <Library/HobLib.h> 18 #include <Library/IoLib.h> 19 #include <Library/MemoryAllocationLib.h> 20 #include <Library/PcdLib.h> 21 22 #include <ArmPlatform.h> 23 24 #define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 14 25 26 // DDR attributes 27 #define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK 28 #define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED 29 30 /** 31 Return the Virtual Memory Map of your platform 32 33 This Virtual Memory Map is used by MemoryInitPei Module to initialize the MMU on your platform. 34 35 @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTOR describing a Physical-to- 36 Virtual Memory mapping. This array must be ended by a zero-filled 37 entry 38 39 **/ 40 VOID ArmPlatformGetVirtualMemoryMap(IN ARM_MEMORY_REGION_DESCRIPTOR ** VirtualMemoryMap)41ArmPlatformGetVirtualMemoryMap ( 42 IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap 43 ) 44 { 45 ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; 46 UINTN Index = 0; 47 ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; 48 49 ASSERT (VirtualMemoryMap != NULL); 50 51 VirtualMemoryTable = (ARM_MEMORY_REGION_DESCRIPTOR*)AllocatePages(EFI_SIZE_TO_PAGES (sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS)); 52 if (VirtualMemoryTable == NULL) { 53 return; 54 } 55 56 if (FeaturePcdGet(PcdCacheEnable) == TRUE) { 57 CacheAttributes = DDR_ATTRIBUTES_CACHED; 58 } else { 59 CacheAttributes = DDR_ATTRIBUTES_UNCACHED; 60 } 61 62 #ifdef ARM_BIGLITTLE_TC2 63 // Secure NOR0 Flash 64 VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SEC_NOR0_BASE; 65 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_NOR0_BASE; 66 VirtualMemoryTable[Index].Length = ARM_VE_SEC_NOR0_SZ; 67 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 68 // Secure RAM 69 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SEC_RAM0_BASE; 70 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SEC_RAM0_BASE; 71 VirtualMemoryTable[Index].Length = ARM_VE_SEC_RAM0_SZ; 72 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 73 #endif 74 75 // SMB CS0 - NOR0 Flash 76 VirtualMemoryTable[Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE; 77 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE; 78 VirtualMemoryTable[Index].Length = SIZE_256KB * 255; 79 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 80 // Environment Variables region 81 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255); 82 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR0_BASE + (SIZE_256KB * 255); 83 VirtualMemoryTable[Index].Length = SIZE_64KB * 4; 84 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 85 86 // SMB CS1 or CS4 - NOR1 Flash 87 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE; 88 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE; 89 VirtualMemoryTable[Index].Length = SIZE_256KB * 255; 90 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 91 // Environment Variables region 92 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255); 93 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_NOR1_BASE + (SIZE_256KB * 255); 94 VirtualMemoryTable[Index].Length = SIZE_64KB * 4; 95 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 96 97 // SMB CS3 or CS1 - PSRAM 98 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_SRAM_BASE; 99 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_SRAM_BASE; 100 VirtualMemoryTable[Index].Length = ARM_VE_SMB_SRAM_SZ; 101 VirtualMemoryTable[Index].Attributes = CacheAttributes; 102 103 // Motherboard peripherals 104 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_SMB_PERIPH_BASE; 105 VirtualMemoryTable[Index].VirtualBase = ARM_VE_SMB_PERIPH_BASE; 106 VirtualMemoryTable[Index].Length = ARM_VE_SMB_PERIPH_SZ; 107 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 108 109 #ifdef ARM_BIGLITTLE_TC2 110 // Non-secure ROM 111 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_ROM_BASE; 112 VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_ROM_BASE; 113 VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_ROM_SZ; 114 VirtualMemoryTable[Index].Attributes = CacheAttributes; 115 #endif 116 117 // OnChip peripherals 118 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_ONCHIP_PERIPH_BASE; 119 VirtualMemoryTable[Index].VirtualBase = ARM_VE_ONCHIP_PERIPH_BASE; 120 VirtualMemoryTable[Index].Length = ARM_VE_ONCHIP_PERIPH_SZ; 121 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 122 123 // SCC Region 124 VirtualMemoryTable[++Index].PhysicalBase = ARM_CTA15A7_SCC_BASE; 125 VirtualMemoryTable[Index].VirtualBase = ARM_CTA15A7_SCC_BASE; 126 VirtualMemoryTable[Index].Length = SIZE_64KB; 127 VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE; 128 129 #ifdef ARM_BIGLITTLE_TC2 130 // TC2 OnChip non-secure SRAM 131 VirtualMemoryTable[++Index].PhysicalBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE; 132 VirtualMemoryTable[Index].VirtualBase = ARM_VE_TC2_NON_SECURE_SRAM_BASE; 133 VirtualMemoryTable[Index].Length = ARM_VE_TC2_NON_SECURE_SRAM_SZ; 134 VirtualMemoryTable[Index].Attributes = CacheAttributes; 135 #endif 136 137 #ifndef ARM_BIGLITTLE_TC2 138 // Workaround for SRAM bug in RTSM 139 if (PcdGet64 (PcdSystemMemoryBase) != 0x80000000) { 140 VirtualMemoryTable[++Index].PhysicalBase = 0x80000000; 141 VirtualMemoryTable[Index].VirtualBase = 0x80000000; 142 VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemoryBase) - 0x80000000; 143 VirtualMemoryTable[Index].Attributes = CacheAttributes; 144 } 145 #endif 146 147 // DDR 148 VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase); 149 VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase); 150 VirtualMemoryTable[Index].Length = PcdGet64 (PcdSystemMemorySize); 151 VirtualMemoryTable[Index].Attributes = CacheAttributes; 152 153 // Detect if it is a 1GB or 2GB Test Chip 154 // [16:19]: 0=1GB TC2, 1=2GB TC2 155 if (MmioRead32(ARM_VE_SYS_PROCID0_REG) & (0xF << 16)) { 156 DEBUG((EFI_D_ERROR,"Info: 2GB Test Chip 2 detected.\n")); 157 BuildResourceDescriptorHob ( 158 EFI_RESOURCE_SYSTEM_MEMORY, 159 EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | 160 EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | 161 EFI_RESOURCE_ATTRIBUTE_TESTED, 162 PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize), 163 SIZE_1GB 164 ); 165 166 // Map the additional 1GB into the MMU 167 VirtualMemoryTable[++Index].PhysicalBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize); 168 VirtualMemoryTable[Index].VirtualBase = PcdGet64 (PcdSystemMemoryBase) + PcdGet64 (PcdSystemMemorySize); 169 VirtualMemoryTable[Index].Length = SIZE_1GB; 170 VirtualMemoryTable[Index].Attributes = CacheAttributes; 171 } 172 173 // End of Table 174 VirtualMemoryTable[++Index].PhysicalBase = 0; 175 VirtualMemoryTable[Index].VirtualBase = 0; 176 VirtualMemoryTable[Index].Length = 0; 177 VirtualMemoryTable[Index].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)0; 178 179 ASSERT((Index + 1) <= MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS); 180 181 *VirtualMemoryMap = VirtualMemoryTable; 182 } 183