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1 /*++
2 
3 Copyright (c) 2007, Intel Corporation. All rights reserved.<BR>
4 This program and the accompanying materials
5 are licensed and made available under the terms and conditions of the BSD License
6 which accompanies this distribution.  The full text of the license may be found at
7 http://opensource.org/licenses/bsd-license.php
8 
9 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
10 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
11 
12 Module Name:
13 
14     Atapi.h
15 
16 Abstract:
17 
18 
19 Revision History
20 --*/
21 
22 #ifndef _ATAPI_H
23 #define _ATAPI_H
24 
25 #include "Tiano.h"
26 
27 #pragma pack(1)
28 
29 typedef struct {
30   UINT16  config;                     /* General Configuration */
31   UINT16  cylinders;                  /* Number of Cylinders */
32   UINT16  reserved_2;
33   UINT16  heads;                      /* Number of logical heads */
34   UINT16  vendor_data1;
35   UINT16  vendoe_data2;
36   UINT16  sectors_per_track;
37   UINT16  vendor_specific_7_9[3];
38   CHAR8   SerialNo[20];               /* ASCII */
39   UINT16  vendor_specific_20_21[2];
40   UINT16  ecc_bytes_available;
41   CHAR8   FirmwareVer[8];             /* ASCII */
42   CHAR8   ModelName[40];              /* ASCII */
43   UINT16  multi_sector_cmd_max_sct_cnt;
44   UINT16  reserved_48;
45   UINT16  capabilities;
46   UINT16  reserved_50;
47   UINT16  pio_cycle_timing;
48   UINT16  reserved_52;
49   UINT16  field_validity;
50   UINT16  current_cylinders;
51   UINT16  current_heads;
52   UINT16  current_sectors;
53   UINT16  CurrentCapacityLsb;
54   UINT16  CurrentCapacityMsb;
55   UINT16  reserved_59;
56   UINT16  user_addressable_sectors_lo;
57   UINT16  user_addressable_sectors_hi;
58   UINT16  reserved_62;
59   UINT16  multi_word_dma_mode;
60   UINT16  advanced_pio_modes;
61   UINT16  min_multi_word_dma_cycle_time;
62   UINT16  rec_multi_word_dma_cycle_time;
63   UINT16  min_pio_cycle_time_without_flow_control;
64   UINT16  min_pio_cycle_time_with_flow_control;
65   UINT16  reserved_69_79[11];
66   UINT16  major_version_no;
67   UINT16  minor_version_no;
68   UINT16  reserved_82_127[46];
69   UINT16  security_status;
70   UINT16  vendor_data_129_159[31];
71   UINT16  reserved_160_255[96];
72 } IDENTIFY;
73 
74 typedef struct {
75   UINT8 peripheral_type;
76   UINT8 RMB;
77   UINT8 version;
78   UINT8 response_data_format;
79   UINT8 addnl_length;
80   UINT8 reserved_5;
81   UINT8 reserved_6;
82   UINT8 reserved_7;
83   UINT8 vendor_info[8];
84   UINT8 product_id[12];
85   UINT8 eeprom_product_code[4];
86   UINT8 firmware_rev_level[4];
87   UINT8 firmware_sub_rev_level[1];
88   UINT8 reserved_37;
89   UINT8 reserved_38;
90   UINT8 reserved_39;
91   UINT8 max_capacity_hi;
92   UINT8 max_capacity_mid;
93   UINT8 max_capacity_lo;
94   UINT8 reserved_43_95[95 - 43 + 1];
95   UINT8 vendor_id[20];
96   UINT8 eeprom_drive_sno[12];
97 } INQUIRY_DATA;
98 
99 typedef struct {
100   UINT8 error_code : 7;
101   UINT8 valid : 1;
102   UINT8 reserved_1;
103   UINT8 sense_key : 4;
104   UINT8 reserved_21 : 1;
105   UINT8 ILI : 1;
106   UINT8 reserved_22 : 2;
107   UINT8 vendor_specific_3;
108   UINT8 vendor_specific_4;
109   UINT8 vendor_specific_5;
110   UINT8 vendor_specific_6;
111   UINT8 addnl_sense_length;           // n - 7
112   UINT8 vendor_specific_8;
113   UINT8 vendor_specific_9;
114   UINT8 vendor_specific_10;
115   UINT8 vendor_specific_11;
116   UINT8 addnl_sense_code;             // mandatory
117   UINT8 addnl_sense_code_qualifier;   // mandatory
118   UINT8 field_replaceable_unit_code;  // optional
119   UINT8 reserved_15;
120   UINT8 reserved_16;
121   UINT8 reserved_17;
122   //
123   // Followed by additional sense bytes     : FIXME
124   //
125 } REQUEST_SENSE_DATA;
126 
127 typedef struct {
128   UINT8 LastLba3;
129   UINT8 LastLba2;
130   UINT8 LastLba1;
131   UINT8 LastLba0;
132   UINT8 BlockSize3;
133   UINT8 BlockSize2;
134   UINT8 BlockSize1;
135   UINT8 BlockSize0;
136 } READ_CAPACITY_DATA;
137 
138 typedef struct {
139   UINT8 reserved_0;
140   UINT8 reserved_1;
141   UINT8 reserved_2;
142   UINT8 Capacity_Length;
143   UINT8 LastLba3;
144   UINT8 LastLba2;
145   UINT8 LastLba1;
146   UINT8 LastLba0;
147   UINT8 DesCode : 2;
148   UINT8 reserved_9 : 6;
149   UINT8 BlockSize2;
150   UINT8 BlockSize1;
151   UINT8 BlockSize0;
152 } READ_FORMAT_CAPACITY_DATA;
153 
154 #pragma pack()
155 //
156 // ATAPI Command
157 //
158 #define ATAPI_SOFT_RESET_CMD      0x08
159 #define PACKET_CMD                0xA0
160 #define ATAPI_IDENTIFY_DEVICE_CMD 0xA1
161 #define ATAPI_SERVICE_CMD         0xA2
162 
163 //
164 // ATAPI Packet Command
165 //
166 #pragma pack(1)
167 
168 typedef struct {
169   UINT8 opcode;
170   UINT8 reserved_1;
171   UINT8 reserved_2;
172   UINT8 reserved_3;
173   UINT8 reserved_4;
174   UINT8 reserved_5;
175   UINT8 reserved_6;
176   UINT8 reserved_7;
177   UINT8 reserved_8;
178   UINT8 reserved_9;
179   UINT8 reserved_10;
180   UINT8 reserved_11;
181 } TEST_UNIT_READY_CMD;
182 
183 typedef struct {
184   UINT8 opcode;
185   UINT8 reserved_1 : 4;
186   UINT8 lun : 4;
187   UINT8 page_code;
188   UINT8 reserved_3;
189   UINT8 allocation_length;
190   UINT8 reserved_5;
191   UINT8 reserved_6;
192   UINT8 reserved_7;
193   UINT8 reserved_8;
194   UINT8 reserved_9;
195   UINT8 reserved_10;
196   UINT8 reserved_11;
197 } INQUIRY_CMD;
198 
199 typedef struct {
200   UINT8 opcode;
201   UINT8 reserved_1 : 4;
202   UINT8 lun : 4;
203   UINT8 reserved_2;
204   UINT8 reserved_3;
205   UINT8 allocation_length;
206   UINT8 reserved_5;
207   UINT8 reserved_6;
208   UINT8 reserved_7;
209   UINT8 reserved_8;
210   UINT8 reserved_9;
211   UINT8 reserved_10;
212   UINT8 reserved_11;
213 } REQUEST_SENSE_CMD;
214 
215 typedef struct {
216   UINT8 opcode;
217   UINT8 reserved_1 : 5;
218   UINT8 lun : 3;
219   UINT8 Lba0;
220   UINT8 Lba1;
221   UINT8 Lba2;
222   UINT8 Lba3;
223   UINT8 reserved_6;
224   UINT8 TranLen0;
225   UINT8 TranLen1;
226   UINT8 reserved_9;
227   UINT8 reserved_10;
228   UINT8 reserved_11;
229 } READ10_CMD;
230 
231 typedef struct {
232   UINT8 opcode;
233   UINT8 reserved_1;
234   UINT8 reserved_2;
235   UINT8 reserved_3;
236   UINT8 reserved_4;
237   UINT8 reserved_5;
238   UINT8 reserved_6;
239   UINT8 allocation_length_hi;
240   UINT8 allocation_length_lo;
241   UINT8 reserved_9;
242   UINT8 reserved_10;
243   UINT8 reserved_11;
244 } READ_FORMAT_CAP_CMD;
245 
246 typedef struct {
247   UINT8 peripheral_type;
248   UINT8 RMB;
249   UINT8 version;
250   UINT8 response_data_format;
251   UINT8 addnl_length;
252   UINT8 reserved_5;
253   UINT8 reserved_6;
254   UINT8 reserved_7;
255   UINT8 vendor_info[8];
256   UINT8 product_id[12];
257   UINT8 eeprom_product_code[4];
258   UINT8 firmware_rev_level[4];
259 } USB_INQUIRY_DATA;
260 
261 typedef union {
262   UINT16              Data16[6];
263   TEST_UNIT_READY_CMD TestUnitReady;
264   READ10_CMD          Read10;
265   REQUEST_SENSE_CMD   RequestSence;
266   INQUIRY_CMD         Inquiry;
267   READ_FORMAT_CAP_CMD ReadFormatCapacity;
268 } ATAPI_PACKET_COMMAND;
269 
270 #pragma pack()
271 //
272 // Packet Command Code
273 //
274 #define TEST_UNIT_READY       0x00
275 #define REQUEST_SENSE         0x03
276 #define INQUIRY               0x12
277 #define READ_FORMAT_CAPACITY  0x23
278 #define READ_CAPACITY         0x25
279 #define READ_10               0x28
280 
281 #define DEFAULT_CTL           (0x0a)  // default content of device control register, disable INT
282 #define DEFAULT_CMD           (0xa0)
283 
284 #define MAX_ATAPI_BYTE_COUNT  (0xfffe)
285 
286 //
287 // Sense Key
288 //
289 #define REQUEST_SENSE_ERROR (0x70)
290 #define SK_NO_SENSE         (0x0)
291 #define SK_RECOVERY_ERROR   (0x1)
292 #define SK_NOT_READY        (0x2)
293 #define SK_MEDIUM_ERROR     (0x3)
294 #define SK_HARDWARE_ERROR   (0x4)
295 #define SK_ILLEGAL_REQUEST  (0x5)
296 #define SK_UNIT_ATTENTION   (0x6)
297 #define SK_DATA_PROTECT     (0x7)
298 #define SK_BLANK_CHECK      (0x8)
299 #define SK_VENDOR_SPECIFIC  (0x9)
300 #define SK_RESERVED_A       (0xA)
301 #define SK_ABORT            (0xB)
302 #define SK_RESERVED_C       (0xC)
303 #define SK_OVERFLOW         (0xD)
304 #define SK_MISCOMPARE       (0xE)
305 #define SK_RESERVED_F       (0xF)
306 
307 //
308 // Additional Sense Codes
309 //
310 #define ASC_NOT_READY                   (0x04)
311 #define ASC_MEDIA_ERR1                  (0x10)
312 #define ASC_MEDIA_ERR2                  (0x11)
313 #define ASC_MEDIA_ERR3                  (0x14)
314 #define ASC_MEDIA_ERR4                  (0x30)
315 #define ASC_MEDIA_UPSIDE_DOWN           (0x06)
316 #define ASC_INVALID_CMD                 (0x20)
317 #define ASC_LBA_OUT_OF_RANGE            (0x21)
318 #define ASC_INVALID_FIELD               (0x24)
319 #define ASC_WRITE_PROTECTED             (0x27)
320 #define ASC_MEDIA_CHANGE                (0x28)
321 #define ASC_RESET                       (0x29)  /* Power On Reset or Bus Reset occurred */
322 #define ASC_ILLEGAL_FIELD               (0x26)
323 #define ASC_NO_MEDIA                    (0x3A)
324 #define ASC_ILLEGAL_MODE_FOR_THIS_TRACK (0x64)
325 
326 //
327 // Additional Sense Code Qualifier
328 //
329 #define ASCQ_IN_PROGRESS  (0x01)
330 
331 #endif
332