1 /** @file
2 Provide constructor and GetTick for BaseRom instance of ACPI Timer Library
3
4 Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.
5 Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>
6
7 This program and the accompanying materials are licensed and made
8 available under the terms and conditions of the BSD License which
9 accompanies this distribution. The full text of the license may
10 be found at http://opensource.org/licenses/bsd-license.php
11
12 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
13 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
14 **/
15
16 #include <Library/DebugLib.h>
17 #include <Library/IoLib.h>
18 #include <Library/PciLib.h>
19 #include <Library/PcdLib.h>
20 #include <OvmfPlatforms.h>
21
22 /**
23 The constructor function enables ACPI IO space.
24
25 If ACPI I/O space not enabled, this function will enable it.
26 It will always return RETURN_SUCCESS.
27
28 @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.
29
30 **/
31 RETURN_STATUS
32 EFIAPI
AcpiTimerLibConstructor(VOID)33 AcpiTimerLibConstructor (
34 VOID
35 )
36 {
37 UINT16 HostBridgeDevId;
38 UINTN Pmba;
39 UINTN AcpiCtlReg;
40 UINT8 AcpiEnBit;
41
42 //
43 // Query Host Bridge DID to determine platform type
44 //
45 HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
46 switch (HostBridgeDevId) {
47 case INTEL_82441_DEVICE_ID:
48 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
49 AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);
50 AcpiEnBit = PIIX4_PMREGMISC_PMIOSE;
51 break;
52 case INTEL_Q35_MCH_DEVICE_ID:
53 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
54 AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);
55 AcpiEnBit = ICH9_ACPI_CNTL_ACPI_EN;
56 break;
57 default:
58 DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
59 __FUNCTION__, HostBridgeDevId));
60 ASSERT (FALSE);
61 return RETURN_UNSUPPORTED;
62 }
63
64 //
65 // Check to see if the Power Management Base Address is already enabled
66 //
67 if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {
68 //
69 // If the Power Management Base Address is not programmed,
70 // then program the Power Management Base Address from a PCD.
71 //
72 PciAndThenOr32 (Pmba, (UINT32) ~0xFFC0, PcdGet16 (PcdAcpiPmBaseAddress));
73
74 //
75 // Enable PMBA I/O port decodes
76 //
77 PciOr8 (AcpiCtlReg, AcpiEnBit);
78 }
79
80 return RETURN_SUCCESS;
81 }
82
83 /**
84 Internal function to read the current tick counter of ACPI.
85
86 Dynamically compute the address of the ACPI tick counter based on the
87 properties of the underlying platform, to avoid relying on global variables.
88
89 @return The tick counter read.
90
91 **/
92 UINT32
InternalAcpiGetTimerTick(VOID)93 InternalAcpiGetTimerTick (
94 VOID
95 )
96 {
97 UINT16 HostBridgeDevId;
98 UINTN Pmba;
99
100 //
101 // Query Host Bridge DID to determine platform type
102 //
103 HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);
104 switch (HostBridgeDevId) {
105 case INTEL_82441_DEVICE_ID:
106 Pmba = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);
107 break;
108 case INTEL_Q35_MCH_DEVICE_ID:
109 Pmba = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);
110 break;
111 default:
112 DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
113 __FUNCTION__, HostBridgeDevId));
114 ASSERT (FALSE);
115 return 0;
116 }
117
118 //
119 // Read PMBA to read and return the current ACPI timer value.
120 //
121 return IoRead32 ((PciRead32 (Pmba) & ~PMBA_RTE) + ACPI_TIMER_OFFSET);
122 }
123