1 // Copyright (c) 2012 The Chromium Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style license that can be
3 // found in the LICENSE file.
4
5 #include "base/cpu.h"
6
7 #include <limits.h>
8 #include <stddef.h>
9 #include <stdint.h>
10 #include <string.h>
11
12 #include <algorithm>
13
14 #include "base/macros.h"
15 #include "build/build_config.h"
16
17 #if defined(ARCH_CPU_ARM_FAMILY) && (defined(OS_ANDROID) || defined(OS_LINUX))
18 #include "base/files/file_util.h"
19 #include "base/lazy_instance.h"
20 #endif
21
22 #if defined(ARCH_CPU_X86_FAMILY)
23 #if defined(_MSC_VER)
24 #include <intrin.h>
25 #include <immintrin.h> // For _xgetbv()
26 #endif
27 #endif
28
29 namespace base {
30
CPU()31 CPU::CPU()
32 : signature_(0),
33 type_(0),
34 family_(0),
35 model_(0),
36 stepping_(0),
37 ext_model_(0),
38 ext_family_(0),
39 has_mmx_(false),
40 has_sse_(false),
41 has_sse2_(false),
42 has_sse3_(false),
43 has_ssse3_(false),
44 has_sse41_(false),
45 has_sse42_(false),
46 has_avx_(false),
47 has_avx2_(false),
48 has_aesni_(false),
49 has_non_stop_time_stamp_counter_(false),
50 cpu_vendor_("unknown") {
51 Initialize();
52 }
53
54 namespace {
55
56 #if defined(ARCH_CPU_X86_FAMILY)
57 #ifndef _MSC_VER
58
59 #if defined(__pic__) && defined(__i386__)
60
__cpuid(int cpu_info[4],int info_type)61 void __cpuid(int cpu_info[4], int info_type) {
62 __asm__ volatile (
63 "mov %%ebx, %%edi\n"
64 "cpuid\n"
65 "xchg %%edi, %%ebx\n"
66 : "=a"(cpu_info[0]), "=D"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3])
67 : "a"(info_type)
68 );
69 }
70
71 #else
72
73 void __cpuid(int cpu_info[4], int info_type) {
74 __asm__ volatile (
75 "cpuid\n"
76 : "=a"(cpu_info[0]), "=b"(cpu_info[1]), "=c"(cpu_info[2]), "=d"(cpu_info[3])
77 : "a"(info_type)
78 );
79 }
80
81 #endif
82
83 // _xgetbv returns the value of an Intel Extended Control Register (XCR).
84 // Currently only XCR0 is defined by Intel so |xcr| should always be zero.
_xgetbv(uint32_t xcr)85 uint64_t _xgetbv(uint32_t xcr) {
86 uint32_t eax, edx;
87
88 __asm__ volatile (
89 "xgetbv" : "=a"(eax), "=d"(edx) : "c"(xcr));
90 return (static_cast<uint64_t>(edx) << 32) | eax;
91 }
92
93 #endif // !_MSC_VER
94 #endif // ARCH_CPU_X86_FAMILY
95
96 #if defined(ARCH_CPU_ARM_FAMILY) && (defined(OS_ANDROID) || defined(OS_LINUX))
97 class LazyCpuInfoValue {
98 public:
LazyCpuInfoValue()99 LazyCpuInfoValue() {
100 // This function finds the value from /proc/cpuinfo under the key "model
101 // name" or "Processor". "model name" is used in Linux 3.8 and later (3.7
102 // and later for arm64) and is shown once per CPU. "Processor" is used in
103 // earler versions and is shown only once at the top of /proc/cpuinfo
104 // regardless of the number CPUs.
105 const char kModelNamePrefix[] = "model name\t: ";
106 const char kProcessorPrefix[] = "Processor\t: ";
107
108 std::string contents;
109 ReadFileToString(FilePath("/proc/cpuinfo"), &contents);
110 DCHECK(!contents.empty());
111 if (contents.empty()) {
112 return;
113 }
114
115 std::istringstream iss(contents);
116 std::string line;
117 while (std::getline(iss, line)) {
118 if (brand_.empty() &&
119 (line.compare(0, strlen(kModelNamePrefix), kModelNamePrefix) == 0 ||
120 line.compare(0, strlen(kProcessorPrefix), kProcessorPrefix) == 0)) {
121 brand_.assign(line.substr(strlen(kModelNamePrefix)));
122 }
123 }
124 }
125
brand() const126 const std::string& brand() const { return brand_; }
127
128 private:
129 std::string brand_;
130 DISALLOW_COPY_AND_ASSIGN(LazyCpuInfoValue);
131 };
132
133 base::LazyInstance<LazyCpuInfoValue>::Leaky g_lazy_cpuinfo =
134 LAZY_INSTANCE_INITIALIZER;
135
136 #endif // defined(ARCH_CPU_ARM_FAMILY) && (defined(OS_ANDROID) ||
137 // defined(OS_LINUX))
138
139 } // anonymous namespace
140
Initialize()141 void CPU::Initialize() {
142 #if defined(ARCH_CPU_X86_FAMILY)
143 int cpu_info[4] = {-1};
144 char cpu_string[48];
145
146 // __cpuid with an InfoType argument of 0 returns the number of
147 // valid Ids in CPUInfo[0] and the CPU identification string in
148 // the other three array elements. The CPU identification string is
149 // not in linear order. The code below arranges the information
150 // in a human readable form. The human readable order is CPUInfo[1] |
151 // CPUInfo[3] | CPUInfo[2]. CPUInfo[2] and CPUInfo[3] are swapped
152 // before using memcpy to copy these three array elements to cpu_string.
153 __cpuid(cpu_info, 0);
154 int num_ids = cpu_info[0];
155 std::swap(cpu_info[2], cpu_info[3]);
156 memcpy(cpu_string, &cpu_info[1], 3 * sizeof(cpu_info[1]));
157 cpu_vendor_.assign(cpu_string, 3 * sizeof(cpu_info[1]));
158
159 // Interpret CPU feature information.
160 if (num_ids > 0) {
161 int cpu_info7[4] = {0};
162 __cpuid(cpu_info, 1);
163 if (num_ids >= 7) {
164 __cpuid(cpu_info7, 7);
165 }
166 signature_ = cpu_info[0];
167 stepping_ = cpu_info[0] & 0xf;
168 model_ = ((cpu_info[0] >> 4) & 0xf) + ((cpu_info[0] >> 12) & 0xf0);
169 family_ = (cpu_info[0] >> 8) & 0xf;
170 type_ = (cpu_info[0] >> 12) & 0x3;
171 ext_model_ = (cpu_info[0] >> 16) & 0xf;
172 ext_family_ = (cpu_info[0] >> 20) & 0xff;
173 has_mmx_ = (cpu_info[3] & 0x00800000) != 0;
174 has_sse_ = (cpu_info[3] & 0x02000000) != 0;
175 has_sse2_ = (cpu_info[3] & 0x04000000) != 0;
176 has_sse3_ = (cpu_info[2] & 0x00000001) != 0;
177 has_ssse3_ = (cpu_info[2] & 0x00000200) != 0;
178 has_sse41_ = (cpu_info[2] & 0x00080000) != 0;
179 has_sse42_ = (cpu_info[2] & 0x00100000) != 0;
180 // AVX instructions will generate an illegal instruction exception unless
181 // a) they are supported by the CPU,
182 // b) XSAVE is supported by the CPU and
183 // c) XSAVE is enabled by the kernel.
184 // See http://software.intel.com/en-us/blogs/2011/04/14/is-avx-enabled
185 //
186 // In addition, we have observed some crashes with the xgetbv instruction
187 // even after following Intel's example code. (See crbug.com/375968.)
188 // Because of that, we also test the XSAVE bit because its description in
189 // the CPUID documentation suggests that it signals xgetbv support.
190 has_avx_ =
191 (cpu_info[2] & 0x10000000) != 0 &&
192 (cpu_info[2] & 0x04000000) != 0 /* XSAVE */ &&
193 (cpu_info[2] & 0x08000000) != 0 /* OSXSAVE */ &&
194 (_xgetbv(0) & 6) == 6 /* XSAVE enabled by kernel */;
195 has_aesni_ = (cpu_info[2] & 0x02000000) != 0;
196 has_avx2_ = has_avx_ && (cpu_info7[1] & 0x00000020) != 0;
197 }
198
199 // Get the brand string of the cpu.
200 __cpuid(cpu_info, 0x80000000);
201 const int parameter_end = 0x80000004;
202 int max_parameter = cpu_info[0];
203
204 if (cpu_info[0] >= parameter_end) {
205 char* cpu_string_ptr = cpu_string;
206
207 for (int parameter = 0x80000002; parameter <= parameter_end &&
208 cpu_string_ptr < &cpu_string[sizeof(cpu_string)]; parameter++) {
209 __cpuid(cpu_info, parameter);
210 memcpy(cpu_string_ptr, cpu_info, sizeof(cpu_info));
211 cpu_string_ptr += sizeof(cpu_info);
212 }
213 cpu_brand_.assign(cpu_string, cpu_string_ptr - cpu_string);
214 }
215
216 const int parameter_containing_non_stop_time_stamp_counter = 0x80000007;
217 if (max_parameter >= parameter_containing_non_stop_time_stamp_counter) {
218 __cpuid(cpu_info, parameter_containing_non_stop_time_stamp_counter);
219 has_non_stop_time_stamp_counter_ = (cpu_info[3] & (1 << 8)) != 0;
220 }
221 #elif defined(ARCH_CPU_ARM_FAMILY) && (defined(OS_ANDROID) || defined(OS_LINUX))
222 cpu_brand_.assign(g_lazy_cpuinfo.Get().brand());
223 #endif
224 }
225
GetIntelMicroArchitecture() const226 CPU::IntelMicroArchitecture CPU::GetIntelMicroArchitecture() const {
227 if (has_avx2()) return AVX2;
228 if (has_avx()) return AVX;
229 if (has_sse42()) return SSE42;
230 if (has_sse41()) return SSE41;
231 if (has_ssse3()) return SSSE3;
232 if (has_sse3()) return SSE3;
233 if (has_sse2()) return SSE2;
234 if (has_sse()) return SSE;
235 return PENTIUM;
236 }
237
238 } // namespace base
239