1 /******************************************************************************
2 *
3 * Copyright (C) 2015 The Android Open Source Project
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at:
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************
18 * Originally developed and contributed by Ittiam Systems Pvt. Ltd, Bangalore
19 */
20 /*****************************************************************************/
21 /* */
22 /* File Name : decoder_api_main.c */
23 /* */
24 /* Description : Functions which recieve the API call from user */
25 /* */
26 /* List of Functions : <List the functions defined in this file> */
27 /* */
28 /* Issues / Problems : None */
29 /* */
30 /* Revision History : */
31 /* */
32 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
33 /* 30 05 2007 Rajneesh Creation */
34 /* */
35 /*****************************************************************************/
36
37 /*****************************************************************************/
38 /* File Includes */
39 /*****************************************************************************/
40
41 /* System include files */
42 #include <stdio.h>
43 #include <stdlib.h>
44 #include <stddef.h>
45 #include <string.h>
46
47 /* User include files */
48 #include "iv_datatypedef.h"
49 #include "iv.h"
50 #include "ivd.h"
51 #include "ithread.h"
52
53 #include "impeg2_job_queue.h"
54 #include "impeg2_macros.h"
55 #include "impeg2_buf_mgr.h"
56 #include "impeg2_disp_mgr.h"
57 #include "impeg2_defs.h"
58 #include "impeg2_platform_macros.h"
59 #include "impeg2_inter_pred.h"
60 #include "impeg2_idct.h"
61 #include "impeg2_format_conv.h"
62 #include "impeg2_mem_func.h"
63
64 #include "impeg2d.h"
65 #include "impeg2d_api.h"
66 #include "impeg2d_bitstream.h"
67 #include "impeg2d_debug.h"
68 #include "impeg2d_structs.h"
69 #include "impeg2d_mc.h"
70 #include "impeg2d_pic_proc.h"
71 #include "impeg2d_deinterlace.h"
72
73 #define NUM_FRAMES_LIMIT_ENABLED 0
74
75 #ifdef LOGO_EN
76 #include "impeg2_ittiam_logo.h"
77 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht) impeg2_insert_logo(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht);
78 #else
79 #define INSERT_LOGO(buf_y, buf_u, buf_v, stride, x_pos, y_pos, yuv_fmt,disp_wd,disp_ht)
80 #endif
81
82 #if NUM_FRAMES_LIMIT_ENABLED
83 #define NUM_FRAMES_LIMIT 10000
84 #else
85 #define NUM_FRAMES_LIMIT 0x7FFFFFFF
86 #endif
87
88 #define CODEC_NAME "MPEG2VDEC"
89 #define CODEC_RELEASE_TYPE "eval"
90 #define CODEC_RELEASE_VER "01.00"
91 #define CODEC_VENDOR "ITTIAM"
92
93 #ifdef __ANDROID__
94 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
95 strcpy(version_string,"@(#)Id:"); \
96 strcat(version_string,codec_name); \
97 strcat(version_string,"_"); \
98 strcat(version_string,codec_release_type); \
99 strcat(version_string," Ver:"); \
100 strcat(version_string,codec_release_ver); \
101 strcat(version_string," Released by "); \
102 strcat(version_string,codec_vendor);
103 #else
104 #define VERSION(version_string, codec_name, codec_release_type, codec_release_ver, codec_vendor) \
105 strcpy(version_string,"@(#)Id:"); \
106 strcat(version_string,codec_name); \
107 strcat(version_string,"_"); \
108 strcat(version_string,codec_release_type); \
109 strcat(version_string," Ver:"); \
110 strcat(version_string,codec_release_ver); \
111 strcat(version_string," Released by "); \
112 strcat(version_string,codec_vendor); \
113 strcat(version_string," Build: "); \
114 strcat(version_string,__DATE__); \
115 strcat(version_string," @ "); \
116 strcat(version_string,__TIME__);
117 #endif
118
119
120 #define MIN_OUT_BUFS_420 3
121 #define MIN_OUT_BUFS_422ILE 1
122 #define MIN_OUT_BUFS_RGB565 1
123 #define MIN_OUT_BUFS_420SP 2
124
125
126 void impeg2d_init_arch(void *pv_codec);
127 void impeg2d_init_function_ptr(void *pv_codec);
128
129 /*****************************************************************************/
130 /* */
131 /* Function Name : impeg2d_api_rel_display_frame */
132 /* */
133 /* Description : Release displ buffers that will be shared between decoder */
134 /* and application */
135 /* Inputs : Error message */
136 /* Globals : None */
137 /* Processing : Just prints error message to console */
138 /* Outputs : Error mesage to the console */
139 /* Returns : None */
140 /* */
141 /* Issues : <List any issues or problems with this function> */
142 /* */
143 /* Revision History: */
144 /* */
145 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
146 /* 27 05 2006 Sankar Creation */
147 /* */
148 /*****************************************************************************/
impeg2d_api_rel_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)149 IV_API_CALL_STATUS_T impeg2d_api_rel_display_frame(iv_obj_t *ps_dechdl,
150 void *pv_api_ip,
151 void *pv_api_op)
152 {
153
154 ivd_rel_display_frame_ip_t *dec_rel_disp_ip;
155 ivd_rel_display_frame_op_t *dec_rel_disp_op;
156
157 dec_state_t *ps_dec_state;
158 dec_state_multi_core_t *ps_dec_state_multi_core;
159
160
161 dec_rel_disp_ip = (ivd_rel_display_frame_ip_t *)pv_api_ip;
162 dec_rel_disp_op = (ivd_rel_display_frame_op_t *)pv_api_op;
163
164 dec_rel_disp_op->u4_error_code = 0;
165 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
166 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
167
168
169 /* If not in shared disp buf mode, return */
170 if(0 == ps_dec_state->u4_share_disp_buf)
171 return IV_SUCCESS;
172
173 if(NULL == ps_dec_state->pv_pic_buf_mg)
174 return IV_SUCCESS;
175
176
177 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, dec_rel_disp_ip->u4_disp_buf_id, BUF_MGR_DISP);
178
179 return IV_SUCCESS;
180 }
181
182 /*****************************************************************************/
183 /* */
184 /* Function Name : impeg2d_api_set_display_frame */
185 /* */
186 /* Description : Sets display buffers that will be shared between decoder */
187 /* and application */
188 /* Inputs : Error message */
189 /* Globals : None */
190 /* Processing : Just prints error message to console */
191 /* Outputs : Error mesage to the console */
192 /* Returns : None */
193 /* */
194 /* Issues : <List any issues or problems with this function> */
195 /* */
196 /* Revision History: */
197 /* */
198 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
199 /* 27 05 2006 Sankar Creation */
200 /* */
201 /*****************************************************************************/
impeg2d_api_set_display_frame(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)202 IV_API_CALL_STATUS_T impeg2d_api_set_display_frame(iv_obj_t *ps_dechdl,
203 void *pv_api_ip,
204 void *pv_api_op)
205 {
206
207 ivd_set_display_frame_ip_t *dec_disp_ip;
208 ivd_set_display_frame_op_t *dec_disp_op;
209
210 UWORD32 i;
211 dec_state_t *ps_dec_state;
212 dec_state_multi_core_t *ps_dec_state_multi_core;
213 UWORD32 u4_num_disp_bufs;
214
215
216 dec_disp_ip = (ivd_set_display_frame_ip_t *)pv_api_ip;
217 dec_disp_op = (ivd_set_display_frame_op_t *)pv_api_op;
218 dec_disp_op->u4_error_code = 0;
219
220 u4_num_disp_bufs = dec_disp_ip->num_disp_bufs;
221 if(u4_num_disp_bufs > BUF_MGR_MAX_CNT)
222 u4_num_disp_bufs = BUF_MGR_MAX_CNT;
223
224 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
225 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
226
227 if(ps_dec_state->u4_share_disp_buf)
228 {
229 pic_buf_t *ps_pic_buf;
230 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
231 for(i = 0; i < u4_num_disp_bufs; i++)
232 {
233
234 ps_pic_buf->pu1_y = dec_disp_ip->s_disp_buffer[i].pu1_bufs[0];
235 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
236 {
237 ps_pic_buf->pu1_u = dec_disp_ip->s_disp_buffer[i].pu1_bufs[1];
238 ps_pic_buf->pu1_v = dec_disp_ip->s_disp_buffer[i].pu1_bufs[2];
239 }
240 else
241 {
242 ps_pic_buf->pu1_u = ps_dec_state->pu1_chroma_ref_buf[i];
243 ps_pic_buf->pu1_v = ps_dec_state->pu1_chroma_ref_buf[i] +
244 ((ps_dec_state->u2_create_max_width * ps_dec_state->u2_create_max_height) >> 2);
245 }
246
247 ps_pic_buf->i4_buf_id = i;
248
249 ps_pic_buf->u1_used_as_ref = 0;
250
251 ps_pic_buf->u4_ts = 0;
252
253 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
254 impeg2_buf_mgr_set_status(ps_dec_state->pv_pic_buf_mg, i, BUF_MGR_DISP);
255 ps_pic_buf++;
256
257 }
258 }
259 memcpy(&(ps_dec_state->as_disp_buffers[0]),
260 &(dec_disp_ip->s_disp_buffer),
261 u4_num_disp_bufs * sizeof(ivd_out_bufdesc_t));
262
263 return IV_SUCCESS;
264
265 }
266
impeg2d_api_set_num_cores(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)267 IV_API_CALL_STATUS_T impeg2d_api_set_num_cores(iv_obj_t *ps_dechdl,
268 void *pv_api_ip,
269 void *pv_api_op)
270 {
271 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
272 impeg2d_ctl_set_num_cores_op_t *ps_op;
273 dec_state_t *ps_dec_state;
274 dec_state_multi_core_t *ps_dec_state_multi_core;
275
276 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
277 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
278
279 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
280 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
281
282 if(ps_ip->u4_num_cores > 0)
283 {
284
285
286 WORD32 i;
287 for(i = 0; i < MAX_THREADS; i++)
288 ps_dec_state_multi_core->ps_dec_state[i]->i4_num_cores = ps_ip->u4_num_cores;
289 }
290 else
291 {
292 ps_dec_state->i4_num_cores = 1;
293 }
294 ps_op->u4_error_code = IV_SUCCESS;
295
296 return IV_SUCCESS;
297 }
298
impeg2d_api_get_seq_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)299 IV_API_CALL_STATUS_T impeg2d_api_get_seq_info(iv_obj_t *ps_dechdl,
300 void *pv_api_ip,
301 void *pv_api_op)
302 {
303 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
304 impeg2d_ctl_get_seq_info_op_t *ps_op;
305 dec_state_t *ps_codec;
306 dec_state_multi_core_t *ps_dec_state_multi_core;
307
308 ps_ip = (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
309 ps_op = (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
310
311 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
312 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
313 UNUSED(ps_ip);
314 if(ps_codec->u2_header_done == 1)
315 {
316 ps_op->u1_aspect_ratio_information = ps_codec->u2_aspect_ratio_info;
317 ps_op->u1_frame_rate_code = ps_codec->u2_frame_rate_code;
318 ps_op->u1_frame_rate_extension_n = ps_codec->u2_frame_rate_extension_n;
319 ps_op->u1_frame_rate_extension_d = ps_codec->u2_frame_rate_extension_d;
320 if(ps_codec->u1_seq_disp_extn_present == 1)
321 {
322 ps_op->u1_video_format = ps_codec->u1_video_format;
323 ps_op->u1_colour_primaries = ps_codec->u1_colour_primaries;
324 ps_op->u1_transfer_characteristics = ps_codec->u1_transfer_characteristics;
325 ps_op->u1_matrix_coefficients = ps_codec->u1_matrix_coefficients;
326 ps_op->u2_display_horizontal_size = ps_codec->u2_display_horizontal_size;
327 ps_op->u2_display_vertical_size = ps_codec->u2_display_vertical_size;
328 }
329 else
330 {
331 ps_op->u1_video_format = 5;
332 ps_op->u1_colour_primaries = 2;
333 ps_op->u1_transfer_characteristics = 2;
334 ps_op->u1_matrix_coefficients = 2;
335 ps_op->u2_display_horizontal_size = ps_codec->u2_horizontal_size;
336 ps_op->u2_display_vertical_size = ps_codec->u2_vertical_size;
337 }
338 ps_op->u4_error_code = IV_SUCCESS;
339 return IV_SUCCESS;
340 }
341 else
342 {
343 ps_op->u4_error_code = IV_FAIL;
344 return IV_FAIL;
345 }
346 }
347
348 /**
349 *******************************************************************************
350 *
351 * @brief
352 * Sets Processor type
353 *
354 * @par Description:
355 * Sets Processor type
356 *
357 * @param[in] ps_codec_obj
358 * Pointer to codec object at API level
359 *
360 * @param[in] pv_api_ip
361 * Pointer to input argument structure
362 *
363 * @param[out] pv_api_op
364 * Pointer to output argument structure
365 *
366 * @returns Status
367 *
368 * @remarks
369 *
370 *
371 *******************************************************************************
372 */
373
impeg2d_set_processor(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)374 IV_API_CALL_STATUS_T impeg2d_set_processor(iv_obj_t *ps_codec_obj,
375 void *pv_api_ip,
376 void *pv_api_op)
377 {
378 impeg2d_ctl_set_processor_ip_t *ps_ip;
379 impeg2d_ctl_set_processor_op_t *ps_op;
380 dec_state_t *ps_codec;
381 dec_state_multi_core_t *ps_dec_state_multi_core;
382
383 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
384 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
385
386 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
387 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
388
389 ps_codec->e_processor_arch = (IVD_ARCH_T)ps_ip->u4_arch;
390 ps_codec->e_processor_soc = (IVD_SOC_T)ps_ip->u4_soc;
391
392 impeg2d_init_function_ptr(ps_codec);
393
394
395 ps_op->u4_error_code = 0;
396 return IV_SUCCESS;
397 }
398 /*****************************************************************************/
399 /* */
400 /* Function Name : impeg2d_fill_mem_rec */
401 /* */
402 /* Description : */
403 /* Inputs : */
404 /* Globals : */
405 /* Processing : */
406 /* Outputs : */
407 /* Returns : */
408 /* */
409 /* Issues : */
410 /* */
411 /* Revision History: */
412 /* */
413 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
414 /* 17 09 2007 Rajendra C Y Draft */
415 /* */
416 /*****************************************************************************/
impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t * ps_ip,impeg2d_fill_mem_rec_op_t * ps_op)417 void impeg2d_fill_mem_rec(impeg2d_fill_mem_rec_ip_t *ps_ip,
418 impeg2d_fill_mem_rec_op_t *ps_op)
419 {
420 UWORD32 u4_i;
421
422 UWORD8 u1_no_rec = 0;
423 UWORD32 max_frm_width,max_frm_height,max_frm_size;
424 iv_mem_rec_t *ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
425 WORD32 i4_num_threads;
426 WORD32 i4_share_disp_buf, i4_chroma_format;
427 WORD32 i4_chroma_size;
428 UWORD32 u4_deinterlace;
429 UNUSED(u4_deinterlace);
430 max_frm_width = ALIGN16(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd);
431 /* In error clips with field prediction, the mv may incorrectly refer to
432 * the last MB row, causing an out of bounds read access. Allocating 8 extra
433 * rows to handle this. Adding another extra row to handle half_y prediction.
434 */
435 max_frm_height = ALIGN32(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht) + 9;
436
437 max_frm_size = (max_frm_width * max_frm_height * 3) >> 1;/* 420 P */
438
439 i4_chroma_size = max_frm_width * max_frm_height / 4;
440
441 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_share_disp_buf))
442 {
443 #ifndef LOGO_EN
444 i4_share_disp_buf = ps_ip->u4_share_disp_buf;
445 #else
446 i4_share_disp_buf = 0;
447 #endif
448 }
449 else
450 {
451 i4_share_disp_buf = 0;
452 }
453 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, e_output_format))
454 {
455 i4_chroma_format = ps_ip->e_output_format;
456 }
457 else
458 {
459 i4_chroma_format = -1;
460 }
461
462 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size > offsetof(impeg2d_fill_mem_rec_ip_t, u4_deinterlace))
463 {
464 u4_deinterlace = ps_ip->u4_deinterlace;
465 }
466 else
467 {
468 u4_deinterlace = 0;
469 }
470
471
472 if( (i4_chroma_format != IV_YUV_420P) &&
473 (i4_chroma_format != IV_YUV_420SP_UV) &&
474 (i4_chroma_format != IV_YUV_420SP_VU))
475 {
476 i4_share_disp_buf = 0;
477 }
478
479 /* Disable deinterlacer in shared mode */
480 if(i4_share_disp_buf)
481 {
482 u4_deinterlace = 0;
483 }
484
485 /*************************************************************************/
486 /* Fill the memory requirement XDM Handle */
487 /*************************************************************************/
488 /* ! */
489 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
490 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
491 ps_mem_rec->u4_mem_size = sizeof(iv_obj_t);
492
493 ps_mem_rec++;
494 u1_no_rec++;
495
496 {
497 /*************************************************************************/
498 /* Fill the memory requirement for threads context */
499 /*************************************************************************/
500 /* ! */
501 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
502 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
503 ps_mem_rec->u4_mem_size = sizeof(dec_state_multi_core_t);
504
505 ps_mem_rec++;
506 u1_no_rec++;
507 }
508
509 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
510 {
511 /*************************************************************************/
512 /* Fill the memory requirement for MPEG2 Decoder Context */
513 /*************************************************************************/
514 /* ! */
515 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
516 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
517 ps_mem_rec->u4_mem_size = sizeof(dec_state_t);
518
519 ps_mem_rec++;
520 u1_no_rec++;
521
522 /* To store thread handle */
523 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
524 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
525 ps_mem_rec->u4_mem_size = ithread_get_handle_size();
526
527 ps_mem_rec++;
528 u1_no_rec++;
529
530 /*************************************************************************/
531 /* Fill the memory requirement for Motion Compensation Buffers */
532 /*************************************************************************/
533 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
534 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_SCRATCH_MEM;
535
536 /* for mc_fw_buf.pu1_y */
537 ps_mem_rec->u4_mem_size = MB_LUMA_MEM_SIZE;
538
539 /* for mc_fw_buf.pu1_u */
540 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
541
542 /* for mc_fw_buf.pu1_v */
543 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
544
545 /* for mc_bk_buf.pu1_y */
546 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
547
548 /* for mc_bk_buf.pu1_u */
549 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
550
551 /* for mc_bk_buf.pu1_v */
552 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
553
554 /* for mc_buf.pu1_y */
555 ps_mem_rec->u4_mem_size += MB_LUMA_MEM_SIZE;
556
557 /* for mc_buf.pu1_u */
558 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
559
560 /* for mc_buf.pu1_v */
561 ps_mem_rec->u4_mem_size += MB_CHROMA_MEM_SIZE;
562
563 ps_mem_rec++;
564 u1_no_rec++;
565
566
567 /*************************************************************************/
568 /* Fill the memory requirement Stack Context */
569 /*************************************************************************/
570 /* ! */
571 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
572 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
573 ps_mem_rec->u4_mem_size = 392;
574
575 ps_mem_rec++;
576 u1_no_rec++;
577 }
578
579
580
581 {
582 /*************************************************************************/
583 /* Fill the memory requirement for Picture Buffer Manager */
584 /*************************************************************************/
585 /* ! */
586 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
587 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
588 ps_mem_rec->u4_mem_size = sizeof(buf_mgr_t) + sizeof(pic_buf_t) * BUF_MGR_MAX_CNT;
589
590 ps_mem_rec++;
591 u1_no_rec++;
592 }
593 /*************************************************************************/
594 /* Internal Frame Buffers */
595 /*************************************************************************/
596 /* ! */
597
598 {
599 for(u4_i = 0; u4_i < NUM_INT_FRAME_BUFFERS; u4_i++)
600 {
601 /* ! */
602 ps_mem_rec->u4_mem_alignment = 128 /* 128 byte alignment*/;
603 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
604 if(0 == i4_share_disp_buf)
605 ps_mem_rec->u4_mem_size = max_frm_size;
606 else if(IV_YUV_420P != i4_chroma_format)
607 {
608 /* If color format is not 420P and it is shared, then allocate for chroma */
609 ps_mem_rec->u4_mem_size = i4_chroma_size * 2;
610 }
611 else
612 ps_mem_rec->u4_mem_size = 64;
613 ps_mem_rec++;
614 u1_no_rec++;
615 }
616 }
617
618
619
620 {
621 WORD32 i4_job_queue_size;
622 WORD32 i4_num_jobs;
623
624 /* One job per row of MBs */
625 i4_num_jobs = max_frm_height >> 4;
626
627 /* One format convert/frame copy job per row of MBs for non-shared mode*/
628 i4_num_jobs += max_frm_height >> 4;
629
630
631 i4_job_queue_size = impeg2_jobq_ctxt_size();
632 i4_job_queue_size += i4_num_jobs * sizeof(job_t);
633 ps_mem_rec->u4_mem_size = i4_job_queue_size;
634 ps_mem_rec->u4_mem_alignment = 128;
635 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
636
637 ps_mem_rec++;
638 u1_no_rec++;
639
640 }
641
642 ps_mem_rec->u4_mem_alignment = 128;
643 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
644 ps_mem_rec->u4_mem_size = impeg2d_deint_ctxt_size();
645 ps_mem_rec++;
646 u1_no_rec++;
647
648 ps_mem_rec->u4_mem_alignment = 128;
649 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
650
651 if(IV_YUV_420P != i4_chroma_format)
652 ps_mem_rec->u4_mem_size = max_frm_size;
653 else
654 ps_mem_rec->u4_mem_size = 64;
655
656 ps_mem_rec++;
657 u1_no_rec++;
658
659 ps_mem_rec->u4_mem_alignment = 128;
660 ps_mem_rec->e_mem_type = IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM;
661 ps_mem_rec->u4_mem_size = sizeof(iv_mem_rec_t) * (NUM_MEM_RECORDS);
662 ps_mem_rec++;
663 u1_no_rec++;
664 ps_op->s_ivd_fill_mem_rec_op_t.u4_num_mem_rec_filled = u1_no_rec;
665 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
666 }
667
668
669 /*****************************************************************************/
670 /* */
671 /* Function Name : impeg2d_api_get_version */
672 /* */
673 /* Description : */
674 /* */
675 /* Inputs : */
676 /* Globals : <Does it use any global variables?> */
677 /* Outputs : */
678 /* Returns : void */
679 /* */
680 /* Issues : none */
681 /* */
682 /* Revision History: */
683 /* */
684 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
685 /* 22 10 2008 100356 Draft */
686 /* */
687 /*****************************************************************************/
impeg2d_api_get_version(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)688 IV_API_CALL_STATUS_T impeg2d_api_get_version(iv_obj_t *ps_dechdl,
689 void *pv_api_ip,
690 void *pv_api_op)
691 {
692 char au1_version_string[512];
693
694 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
695 impeg2d_ctl_getversioninfo_op_t *ps_op;
696
697 UNUSED(ps_dechdl);
698
699 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
700 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
701
702 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
703
704 VERSION(au1_version_string, CODEC_NAME, CODEC_RELEASE_TYPE, CODEC_RELEASE_VER,
705 CODEC_VENDOR);
706
707 if((WORD32)ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size <= 0)
708 {
709 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
710 return (IV_FAIL);
711 }
712
713 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_version_buffer_size
714 >= (strlen(au1_version_string) + 1))
715 {
716 memcpy(ps_ip->s_ivd_ctl_getversioninfo_ip_t.pv_version_buffer,
717 au1_version_string, (strlen(au1_version_string) + 1));
718 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_SUCCESS;
719 }
720 else
721 {
722 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = IV_FAIL;
723 }
724
725 return (IV_SUCCESS);
726 }
727
728 /*****************************************************************************/
729 /* */
730 /* Function Name : impeg2d_api_get_buf_info */
731 /* */
732 /* Description : */
733 /* */
734 /* Inputs : */
735 /* Globals : <Does it use any global variables?> */
736 /* Outputs : */
737 /* Returns : void */
738 /* */
739 /* Issues : none */
740 /* */
741 /* Revision History: */
742 /* */
743 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
744 /* 22 10 2008 100356 Draft */
745 /* */
746 /*****************************************************************************/
impeg2d_api_get_buf_info(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)747 IV_API_CALL_STATUS_T impeg2d_api_get_buf_info(iv_obj_t *ps_dechdl,
748 void *pv_api_ip,
749 void *pv_api_op)
750 {
751 dec_state_t *ps_dec_state;
752 dec_state_multi_core_t *ps_dec_state_multi_core;
753 impeg2d_ctl_getbufinfo_ip_t *ps_ctl_bufinfo_ip =
754 (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
755 impeg2d_ctl_getbufinfo_op_t *ps_ctl_bufinfo_op =
756 (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
757 UWORD32 u4_i, u4_stride, u4_height;
758 UNUSED(ps_ctl_bufinfo_ip);
759
760 ps_dec_state_multi_core =
761 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
762 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
763
764 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs = 1;
765 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs = 1;
766
767 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
768 {
769 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
770 MIN_OUT_BUFS_420;
771 }
772 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV)
773 || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
774 {
775 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
776 MIN_OUT_BUFS_420SP;
777 }
778 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
779 {
780 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
781 MIN_OUT_BUFS_422ILE;
782 }
783 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
784 {
785 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_out_bufs =
786 MIN_OUT_BUFS_RGB565;
787 }
788 else
789 {
790 //Invalid chroma format; Error code may be updated, verify in testing if needed
791 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code =
792 IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
793 return IV_FAIL;
794 }
795
796 for(u4_i = 0; u4_i < IVD_VIDDEC_MAX_IO_BUFFERS; u4_i++)
797 {
798 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
799 0;
800 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[u4_i] =
801 0;
802 }
803
804 for(u4_i = 0;
805 u4_i < ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_num_in_bufs;
806 u4_i++)
807 {
808 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_in_buf_size[u4_i] =
809 MAX_BITSTREAM_BUFFER_SIZE;
810 }
811
812 if (0 == ps_dec_state->u4_frm_buf_stride)
813 {
814 if (1 == ps_dec_state->u2_header_done)
815 {
816 u4_stride = ps_dec_state->u2_horizontal_size;
817 }
818 else
819 {
820 u4_stride = ps_dec_state->u2_create_max_width;
821 }
822 }
823 else
824 {
825 u4_stride = ps_dec_state->u4_frm_buf_stride;
826 }
827 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
828
829 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
830 {
831 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
832 (u4_stride * u4_height);
833 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
834 (u4_stride * u4_height) >> 2;
835 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] =
836 (u4_stride * u4_height) >> 2;
837 }
838 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV)
839 || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
840 {
841 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
842 (u4_stride * u4_height);
843 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
844 (u4_stride * u4_height) >> 1;
845 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] = 0;
846 }
847 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
848 {
849 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[0] =
850 (u4_stride * u4_height) * 2;
851 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[1] =
852 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_min_out_buf_size[2] =
853 0;
854 }
855
856 /* Adding initialization for 2 uninitialized values */
857 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs = 1;
858 if(ps_dec_state->u4_share_disp_buf)
859 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_num_disp_bufs =
860 NUM_INT_FRAME_BUFFERS;
861 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_size = MAX_FRM_SIZE;
862
863 ps_ctl_bufinfo_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = IV_SUCCESS;
864
865 return (IV_SUCCESS);
866 }
867
868 /*****************************************************************************/
869 /* */
870 /* Function Name : impeg2d_api_set_flush_mode */
871 /* */
872 /* Description : */
873 /* */
874 /* Inputs : */
875 /* Globals : <Does it use any global variables?> */
876 /* Outputs : */
877 /* Returns : void */
878 /* */
879 /* Issues : none */
880 /* */
881 /* Revision History: */
882 /* */
883 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
884 /* 08 06 2009 100356 RAVI */
885 /* */
886 /*****************************************************************************/
impeg2d_api_set_flush_mode(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)887 IV_API_CALL_STATUS_T impeg2d_api_set_flush_mode(iv_obj_t *ps_dechdl,
888 void *pv_api_ip,
889 void *pv_api_op)
890 {
891 dec_state_t *ps_dec_state;
892 dec_state_multi_core_t *ps_dec_state_multi_core;
893 impeg2d_ctl_flush_op_t *ps_ctl_dec_op =
894 (impeg2d_ctl_flush_op_t*)pv_api_op;
895
896 UNUSED(pv_api_ip);
897
898 ps_dec_state_multi_core =
899 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
900 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
901
902 ps_dec_state->u1_flushfrm = 1;
903
904 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_size =
905 sizeof(impeg2d_ctl_flush_op_t);
906 ps_ctl_dec_op->s_ivd_ctl_flush_op_t.u4_error_code = IV_SUCCESS;
907
908 return (IV_SUCCESS);
909 }
910
911 /*****************************************************************************/
912 /* */
913 /* Function Name : impeg2d_api_set_default */
914 /* */
915 /* Description : */
916 /* */
917 /* Inputs : */
918 /* Globals : <Does it use any global variables?> */
919 /* Outputs : */
920 /* Returns : void */
921 /* */
922 /* Issues : none */
923 /* */
924 /* Revision History: */
925 /* */
926 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
927 /* 08 06 2009 100356 RAVI */
928 /* */
929 /*****************************************************************************/
impeg2d_api_set_default(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)930 IV_API_CALL_STATUS_T impeg2d_api_set_default(iv_obj_t *ps_dechdl,
931 void *pv_api_ip,
932 void *pv_api_op)
933 {
934 dec_state_t *ps_dec_state;
935 dec_state_multi_core_t *ps_dec_state_multi_core;
936 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op =
937 (impeg2d_ctl_set_config_op_t *)pv_api_op;
938
939 UNUSED(pv_api_ip);
940
941 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
942 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_size =
943 sizeof(impeg2d_ctl_set_config_op_t);
944
945 ps_dec_state_multi_core =
946 (dec_state_multi_core_t *)(ps_dechdl->pv_codec_handle);
947 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
948
949 ps_dec_state->u1_flushfrm = 0;
950 ps_dec_state->u2_decode_header = 1;
951
952 if (1 == ps_dec_state->u2_header_done)
953 {
954 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
955 }
956
957 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
958
959 return (IV_SUCCESS);
960
961 }
962
963 /*****************************************************************************/
964 /* */
965 /* Function Name : impeg2d_api_reset */
966 /* */
967 /* Description : */
968 /* */
969 /* Inputs : */
970 /* Globals : <Does it use any global variables?> */
971 /* Outputs : */
972 /* Returns : void */
973 /* */
974 /* Issues : none */
975 /* */
976 /* Revision History: */
977 /* */
978 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
979 /* 08 06 2009 100356 RAVI */
980 /* */
981 /*****************************************************************************/
impeg2d_api_reset(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)982 IV_API_CALL_STATUS_T impeg2d_api_reset(iv_obj_t *ps_dechdl,
983 void *pv_api_ip,
984 void *pv_api_op)
985 {
986 dec_state_t *ps_dec_state;
987 dec_state_multi_core_t *ps_dec_state_multi_core;
988 UNUSED(pv_api_ip);
989 impeg2d_ctl_reset_op_t *s_ctl_reset_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
990
991 WORD32 i4_num_threads;
992
993 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
994 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
995
996 if(ps_dec_state_multi_core != NULL)
997 {
998 if(ps_dec_state->aps_ref_pics[1] != NULL)
999 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
1000 if(ps_dec_state->aps_ref_pics[0] != NULL)
1001 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
1002 while(1)
1003 {
1004 pic_buf_t *ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
1005 if(NULL == ps_disp_pic)
1006 break;
1007 if(0 == ps_dec_state->u4_share_disp_buf)
1008 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
1009
1010 }
1011
1012 if((ps_dec_state->u4_deinterlace) && (NULL != ps_dec_state->ps_deint_pic))
1013 {
1014 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
1015 ps_dec_state->ps_deint_pic->i4_buf_id,
1016 MPEG2_BUF_MGR_DEINT);
1017 }
1018
1019 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1020 {
1021 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1022
1023
1024 /* --------------------------------------------------------------------- */
1025 /* Initializations */
1026
1027 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1028 ps_dec_state->u4_frm_buf_stride = 0;
1029 ps_dec_state->u2_is_mpeg2 = 0;
1030 ps_dec_state->aps_ref_pics[0] = NULL;
1031 ps_dec_state->aps_ref_pics[1] = NULL;
1032 ps_dec_state->ps_deint_pic = NULL;
1033 }
1034 }
1035 else
1036 {
1037 s_ctl_reset_op->s_ivd_ctl_reset_op_t.u4_error_code =
1038 IMPEG2D_INIT_NOT_DONE;
1039 }
1040
1041 return(IV_SUCCESS);
1042 }
1043
1044 /*****************************************************************************/
1045 /* */
1046 /* Function Name : impeg2d_api_set_params */
1047 /* */
1048 /* Description : */
1049 /* */
1050 /* Inputs : */
1051 /* Globals : <Does it use any global variables?> */
1052 /* Outputs : */
1053 /* Returns : void */
1054 /* */
1055 /* Issues : none */
1056 /* */
1057 /* Revision History: */
1058 /* */
1059 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1060 /* 08 06 2009 100356 RAVI */
1061 /* */
1062 /*****************************************************************************/
impeg2d_api_set_params(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1063 IV_API_CALL_STATUS_T impeg2d_api_set_params(iv_obj_t *ps_dechdl,void *pv_api_ip,void *pv_api_op)
1064 {
1065 dec_state_t *ps_dec_state;
1066 dec_state_multi_core_t *ps_dec_state_multi_core;
1067 impeg2d_ctl_set_config_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
1068 impeg2d_ctl_set_config_op_t *ps_ctl_dec_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
1069
1070 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1071 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1072
1073 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_HEADER) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode != IVD_DECODE_FRAME))
1074 {
1075 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1076 return(IV_FAIL);
1077 }
1078
1079 if((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DISPLAY_FRAME_OUT) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_out_mode != IVD_DECODE_FRAME_OUT))
1080 {
1081 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1082 return(IV_FAIL);
1083 }
1084
1085 if( (WORD32) ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_frm_skip_mode < IVD_SKIP_NONE)
1086 {
1087 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1088 return(IV_FAIL);
1089 }
1090
1091 if(ps_dec_state->u2_header_done == 1)
1092 {
1093 if(((WORD32)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < 0) ||
1094 ((ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0) && (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd < ps_dec_state->u2_frame_width)))
1095 {
1096 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_FAIL;
1097 return(IV_FAIL);
1098 }
1099
1100 }
1101
1102
1103 ps_dec_state->u2_decode_header = (UWORD8)ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode;
1104
1105 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd != 0)
1106 {
1107 if(ps_dec_state->u2_header_done == 1)
1108 {
1109 if (ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd > ps_dec_state->u2_frame_width)
1110 {
1111 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1112 }
1113 }
1114 else
1115 {
1116 ps_dec_state->u4_frm_buf_stride = ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.u4_disp_wd;
1117 }
1118
1119 }
1120 else
1121 {
1122
1123 if(ps_dec_state->u2_header_done == 1)
1124 {
1125 ps_dec_state->u4_frm_buf_stride = ps_dec_state->u2_frame_width;
1126 }
1127 else
1128 {
1129 ps_dec_state->u4_frm_buf_stride = 0;
1130 }
1131 }
1132
1133
1134 if(ps_ctl_dec_ip->s_ivd_ctl_set_config_ip_t.e_vid_dec_mode == IVD_DECODE_FRAME)
1135 {
1136 ps_dec_state->u1_flushfrm = 0;
1137 }
1138
1139
1140 ps_ctl_dec_op->s_ivd_ctl_set_config_op_t.u4_error_code = IV_SUCCESS;
1141 return(IV_SUCCESS);
1142
1143 }
1144
1145 /*****************************************************************************/
1146 /* */
1147 /* Function Name : impeg2d_api_get_status */
1148 /* */
1149 /* Description : */
1150 /* */
1151 /* Inputs : */
1152 /* Globals : <Does it use any global variables?> */
1153 /* Outputs : */
1154 /* Returns : void */
1155 /* */
1156 /* Issues : none */
1157 /* */
1158 /* Revision History: */
1159 /* */
1160 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1161 /* 08 06 2009 100356 RAVI */
1162 /* */
1163 /*****************************************************************************/
impeg2d_api_get_status(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1164 IV_API_CALL_STATUS_T impeg2d_api_get_status(iv_obj_t *ps_dechdl,
1165 void *pv_api_ip,
1166 void *pv_api_op)
1167 {
1168 dec_state_t *ps_dec_state;
1169 dec_state_multi_core_t *ps_dec_state_multi_core;
1170 UWORD32 u4_i,u4_stride,u4_height;
1171 impeg2d_ctl_getstatus_ip_t *ps_ctl_dec_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
1172 impeg2d_ctl_getstatus_op_t *ps_ctl_dec_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
1173 UNUSED(ps_ctl_dec_ip);
1174
1175 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1176 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1177
1178 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_size = sizeof(impeg2d_ctl_getstatus_op_t);
1179 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_num_disp_bufs = 1;
1180 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_ht = ps_dec_state->u2_frame_height;
1181 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_pic_wd = ps_dec_state->u2_frame_width;
1182 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_frame_rate = ps_dec_state->u2_framePeriod;
1183
1184
1185 if(ps_dec_state->u2_progressive_sequence == 1)
1186 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_PROGRESSIVE ;
1187 else
1188 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_content_type = IV_INTERLACED;
1189
1190
1191 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.e_output_chroma_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
1192 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs = 1;
1193 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = 1;
1194
1195
1196 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1197 {
1198 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_420;
1199 }
1200 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1201 {
1202 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_422ILE;
1203 }
1204 else if(ps_dec_state->i4_chromaFormat == IV_RGB_565)
1205 {
1206 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_out_bufs = MIN_OUT_BUFS_RGB565;
1207 }
1208 else
1209 {
1210 //Invalid chroma format; Error code may be updated, verify in testing if needed
1211 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
1212 return IV_FAIL;
1213 }
1214
1215 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1216 memset(&ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0],0,(sizeof(UWORD32)*IVD_VIDDEC_MAX_IO_BUFFERS));
1217
1218 for(u4_i = 0; u4_i < ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_num_in_bufs; u4_i++)
1219 {
1220 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_in_buf_size[u4_i] = MAX_BITSTREAM_BUFFER_SIZE;
1221 }
1222
1223 u4_stride = ps_dec_state->u4_frm_buf_stride;
1224 u4_height = ((ps_dec_state->u2_frame_height + 15) >> 4) << 4;
1225
1226 if(ps_dec_state->i4_chromaFormat == IV_YUV_420P)
1227 {
1228 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1229 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>2 ;
1230 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = (u4_stride * u4_height)>>2;
1231 }
1232 else if((ps_dec_state->i4_chromaFormat == IV_YUV_420SP_UV) || (ps_dec_state->i4_chromaFormat == IV_YUV_420SP_VU))
1233 {
1234 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height);
1235 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = (u4_stride * u4_height)>>1 ;
1236 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1237 }
1238 else if(ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1239 {
1240 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[0] = (u4_stride * u4_height)*2;
1241 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[1] = ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_min_out_buf_size[2] = 0;
1242 }
1243
1244 ps_ctl_dec_op->s_ivd_ctl_getstatus_op_t.u4_error_code = IV_SUCCESS;
1245
1246 return(IV_SUCCESS);
1247
1248 }
1249
1250 /**
1251 *******************************************************************************
1252 *
1253 * @brief
1254 * Gets frame dimensions/offsets
1255 *
1256 * @par Description:
1257 * Gets frame buffer chararacteristics such a x & y offsets display and
1258 * buffer dimensions
1259 *
1260 * @param[in] ps_codec_obj
1261 * Pointer to codec object at API level
1262 *
1263 * @param[in] pv_api_ip
1264 * Pointer to input argument structure
1265 *
1266 * @param[out] pv_api_op
1267 * Pointer to output argument structure
1268 *
1269 * @returns Status
1270 *
1271 * @remarks
1272 *
1273 *
1274 *******************************************************************************
1275 */
impeg2d_get_frame_dimensions(iv_obj_t * ps_codec_obj,void * pv_api_ip,void * pv_api_op)1276 IV_API_CALL_STATUS_T impeg2d_get_frame_dimensions(iv_obj_t *ps_codec_obj,
1277 void *pv_api_ip,
1278 void *pv_api_op)
1279 {
1280 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
1281 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
1282 WORD32 disp_wd, disp_ht, buffer_wd, buffer_ht, x_offset, y_offset;
1283 dec_state_t *ps_codec;
1284 dec_state_multi_core_t *ps_dec_state_multi_core;
1285
1286 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_codec_obj->pv_codec_handle);
1287 ps_codec = ps_dec_state_multi_core->ps_dec_state[0];
1288
1289
1290 ps_ip = (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
1291 ps_op = (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
1292 UNUSED(ps_ip);
1293 if(ps_codec->u2_header_done)
1294 {
1295 disp_wd = ps_codec->u2_horizontal_size;
1296 disp_ht = ps_codec->u2_vertical_size;
1297
1298 if(0 == ps_codec->u4_share_disp_buf)
1299 {
1300 buffer_wd = disp_wd;
1301 buffer_ht = disp_ht;
1302 }
1303 else
1304 {
1305 buffer_wd = ps_codec->u2_frame_width;
1306 buffer_ht = ps_codec->u2_frame_height;
1307 }
1308 }
1309 else
1310 {
1311
1312 disp_wd = ps_codec->u2_create_max_width;
1313 disp_ht = ps_codec->u2_create_max_height;
1314
1315 if(0 == ps_codec->u4_share_disp_buf)
1316 {
1317 buffer_wd = disp_wd;
1318 buffer_ht = disp_ht;
1319 }
1320 else
1321 {
1322 buffer_wd = ALIGN16(disp_wd);
1323 buffer_ht = ALIGN16(disp_ht);
1324
1325 }
1326 }
1327 if(ps_codec->u2_frame_width > buffer_wd)
1328 buffer_wd = ps_codec->u2_frame_width;
1329
1330 x_offset = 0;
1331 y_offset = 0;
1332
1333
1334 ps_op->u4_disp_wd[0] = disp_wd;
1335 ps_op->u4_disp_ht[0] = disp_ht;
1336 ps_op->u4_buffer_wd[0] = buffer_wd;
1337 ps_op->u4_buffer_ht[0] = buffer_ht;
1338 ps_op->u4_x_offset[0] = x_offset;
1339 ps_op->u4_y_offset[0] = y_offset;
1340
1341 ps_op->u4_disp_wd[1] = ps_op->u4_disp_wd[2] = ((ps_op->u4_disp_wd[0] + 1)
1342 >> 1);
1343 ps_op->u4_disp_ht[1] = ps_op->u4_disp_ht[2] = ((ps_op->u4_disp_ht[0] + 1)
1344 >> 1);
1345 ps_op->u4_buffer_wd[1] = ps_op->u4_buffer_wd[2] = (ps_op->u4_buffer_wd[0]
1346 >> 1);
1347 ps_op->u4_buffer_ht[1] = ps_op->u4_buffer_ht[2] = (ps_op->u4_buffer_ht[0]
1348 >> 1);
1349 ps_op->u4_x_offset[1] = ps_op->u4_x_offset[2] = (ps_op->u4_x_offset[0]
1350 >> 1);
1351 ps_op->u4_y_offset[1] = ps_op->u4_y_offset[2] = (ps_op->u4_y_offset[0]
1352 >> 1);
1353
1354 if((ps_codec->i4_chromaFormat == IV_YUV_420SP_UV)
1355 || (ps_codec->i4_chromaFormat == IV_YUV_420SP_VU))
1356 {
1357 ps_op->u4_disp_wd[2] = 0;
1358 ps_op->u4_disp_ht[2] = 0;
1359 ps_op->u4_buffer_wd[2] = 0;
1360 ps_op->u4_buffer_ht[2] = 0;
1361 ps_op->u4_x_offset[2] = 0;
1362 ps_op->u4_y_offset[2] = 0;
1363
1364 ps_op->u4_disp_wd[1] <<= 1;
1365 ps_op->u4_buffer_wd[1] <<= 1;
1366 ps_op->u4_x_offset[1] <<= 1;
1367 }
1368
1369 return IV_SUCCESS;
1370
1371 }
1372
impeg2d_api_function(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1373 IV_API_CALL_STATUS_T impeg2d_api_function (iv_obj_t *ps_dechdl, void *pv_api_ip,void *pv_api_op)
1374 {
1375 WORD32 i4_cmd;
1376 IV_API_CALL_STATUS_T u4_error_code;
1377 UWORD32 *pu4_api_ip;
1378
1379 u4_error_code = impeg2d_api_check_struct_sanity(ps_dechdl,pv_api_ip,pv_api_op);
1380 if(IV_SUCCESS != u4_error_code)
1381 {
1382 return u4_error_code;
1383 }
1384
1385
1386 pu4_api_ip = (UWORD32 *)pv_api_ip;
1387 i4_cmd = *(pu4_api_ip + 1);
1388
1389 switch(i4_cmd)
1390 {
1391
1392 case IV_CMD_GET_NUM_MEM_REC:
1393 u4_error_code = impeg2d_api_num_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1394 break;
1395
1396 case IV_CMD_FILL_NUM_MEM_REC:
1397 u4_error_code = impeg2d_api_fill_mem_rec((void *)pv_api_ip,(void *)pv_api_op);
1398 break;
1399
1400 case IV_CMD_INIT:
1401 u4_error_code = impeg2d_api_init(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1402 break;
1403
1404 case IVD_CMD_SET_DISPLAY_FRAME:
1405 u4_error_code = impeg2d_api_set_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1406 break;
1407
1408 case IVD_CMD_REL_DISPLAY_FRAME:
1409 u4_error_code = impeg2d_api_rel_display_frame(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1410 break;
1411
1412 case IVD_CMD_VIDEO_DECODE:
1413 u4_error_code = impeg2d_api_entity(ps_dechdl, (void *)pv_api_ip,(void *)pv_api_op);
1414 break;
1415
1416 case IV_CMD_RETRIEVE_MEMREC:
1417 u4_error_code = impeg2d_api_retrieve_mem_rec(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1418 break;
1419
1420 case IVD_CMD_VIDEO_CTL:
1421 u4_error_code = impeg2d_api_ctl(ps_dechdl,(void *)pv_api_ip,(void *)pv_api_op);
1422 break;
1423
1424 default:
1425 break;
1426 }
1427
1428 return(u4_error_code);
1429
1430 }
1431
1432 /*****************************************************************************/
1433 /* */
1434 /* Function Name : impeg2d_api_num_mem_rec */
1435 /* */
1436 /* Description : The function get the number mem records library needs */
1437 /* Inputs : Error message */
1438 /* Globals : None */
1439 /* Processing : Just prints error message to console */
1440 /* Outputs : Error mesage to the console */
1441 /* Returns : None */
1442 /* */
1443 /* Issues : <List any issues or problems with this function> */
1444 /* */
1445 /* Revision History: */
1446 /* */
1447 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1448 /* 23 09 2010 Hamsalekha Creation */
1449 /* */
1450 /*****************************************************************************/
1451
1452
impeg2d_api_num_mem_rec(void * pv_api_ip,void * pv_api_op)1453 IV_API_CALL_STATUS_T impeg2d_api_num_mem_rec(void *pv_api_ip,void *pv_api_op)
1454 {
1455 /* To Query No of Memory Records */
1456 impeg2d_num_mem_rec_ip_t *ps_query_mem_rec_ip;
1457 impeg2d_num_mem_rec_op_t *ps_query_mem_rec_op;
1458
1459 ps_query_mem_rec_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
1460 ps_query_mem_rec_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
1461
1462 UNUSED(ps_query_mem_rec_ip);
1463 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_size = sizeof(impeg2d_num_mem_rec_op_t);
1464
1465 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_num_mem_rec = (UWORD32)NUM_MEM_RECORDS;
1466
1467 ps_query_mem_rec_op->s_ivd_num_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1468
1469
1470 return(IV_SUCCESS);
1471
1472 }
1473
1474
1475 /*****************************************************************************/
1476 /* */
1477 /* Function Name : impeg2d_api_fill_mem_rec */
1478 /* */
1479 /* Description : Thsi functions fills details of each mem record lib needs*/
1480 /* Inputs : Error message */
1481 /* Globals : None */
1482 /* Processing : Just prints error message to console */
1483 /* Outputs : Error mesage to the console */
1484 /* Returns : None */
1485 /* */
1486 /* Issues : <List any issues or problems with this function> */
1487 /* */
1488 /* Revision History: */
1489 /* */
1490 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1491 /* 23 09 2010 Hamsalekha Creation */
1492 /* */
1493 /*****************************************************************************/
1494
1495
impeg2d_api_fill_mem_rec(void * pv_api_ip,void * pv_api_op)1496 IV_API_CALL_STATUS_T impeg2d_api_fill_mem_rec(void *pv_api_ip,void *pv_api_op)
1497 {
1498
1499 impeg2d_fill_mem_rec_ip_t *ps_mem_q_ip;
1500 impeg2d_fill_mem_rec_op_t *ps_mem_q_op;
1501
1502
1503 ps_mem_q_ip = pv_api_ip;
1504 ps_mem_q_op = pv_api_op;
1505
1506
1507 impeg2d_fill_mem_rec((impeg2d_fill_mem_rec_ip_t *)ps_mem_q_ip,
1508 (impeg2d_fill_mem_rec_op_t *)ps_mem_q_op);
1509
1510
1511 return(IV_SUCCESS);
1512
1513 }
1514
1515
1516
1517 /*****************************************************************************/
1518 /* */
1519 /* Function Name : impeg2d_api_init */
1520 /* */
1521 /* Description : */
1522 /* Inputs : */
1523 /* Globals : */
1524 /* Processing : */
1525 /* Outputs : */
1526 /* Returns : */
1527 /* */
1528 /* Issues : */
1529 /* */
1530 /* Revision History: */
1531 /* */
1532 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1533 /* 17 09 2007 Rajendra C Y Draft */
1534 /* */
1535 /*****************************************************************************/
impeg2d_api_init(iv_obj_t * ps_dechdl,void * ps_ip,void * ps_op)1536 IV_API_CALL_STATUS_T impeg2d_api_init(iv_obj_t *ps_dechdl,
1537 void *ps_ip,
1538 void *ps_op)
1539 {
1540 UWORD32 i;
1541
1542 void *pv;
1543 UWORD32 u4_size;
1544
1545 dec_state_t *ps_dec_state;
1546 dec_state_multi_core_t *ps_dec_state_multi_core;
1547 UWORD32 u4_num_mem_rec;
1548 iv_mem_rec_t *ps_mem_rec ;
1549 iv_mem_rec_t *ps_frm_buf;
1550 iv_obj_t *ps_dec_handle;
1551 WORD32 i4_max_wd, i4_max_ht;
1552
1553 impeg2d_init_ip_t *ps_dec_init_ip;
1554 impeg2d_init_op_t *ps_dec_init_op;
1555 WORD32 i4_num_threads;
1556 UWORD32 u4_share_disp_buf, u4_chroma_format;
1557 UWORD32 u4_deinterlace;
1558
1559 ps_dec_init_ip = (impeg2d_init_ip_t *)ps_ip;
1560 ps_dec_init_op = (impeg2d_init_op_t *)ps_op;
1561
1562 i4_max_wd = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1563 i4_max_ht = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1564
1565 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_share_disp_buf))
1566 {
1567 #ifndef LOGO_EN
1568 u4_share_disp_buf = ps_dec_init_ip->u4_share_disp_buf;
1569 #else
1570 u4_share_disp_buf = 0;
1571 #endif
1572 }
1573 else
1574 {
1575 u4_share_disp_buf = 0;
1576 }
1577
1578 u4_chroma_format = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1579
1580 if(ps_dec_init_ip->s_ivd_init_ip_t.u4_size > offsetof(impeg2d_init_ip_t, u4_deinterlace))
1581 {
1582 u4_deinterlace = ps_dec_init_ip->u4_deinterlace;
1583 }
1584 else
1585 {
1586 u4_deinterlace = 0;
1587 }
1588
1589 if( (u4_chroma_format != IV_YUV_420P) &&
1590 (u4_chroma_format != IV_YUV_420SP_UV) &&
1591 (u4_chroma_format != IV_YUV_420SP_VU))
1592 {
1593 u4_share_disp_buf = 0;
1594 }
1595
1596 /* Disable deinterlacer in shared mode */
1597 if(u4_share_disp_buf)
1598 {
1599 u4_deinterlace = 0;
1600 }
1601
1602 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1603 ps_mem_rec ++;
1604
1605
1606 ps_dec_init_op->s_ivd_init_op_t.u4_size = sizeof(impeg2d_init_op_t);
1607
1608
1609 /* Except memTab[0], all other memTabs are initialized to zero */
1610 for(i = 1; i < ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
1611 {
1612 memset(ps_mem_rec->pv_base,0,ps_mem_rec->u4_mem_size);
1613 ps_mem_rec++;
1614 }
1615
1616 /* Reinitializing memTab[0] memory base address */
1617 ps_mem_rec = ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location;
1618
1619
1620 /* memTab[0] is for codec Handle,redundant currently not being used */
1621 ps_dec_handle = ps_mem_rec->pv_base;
1622 u4_num_mem_rec = 1;
1623 ps_mem_rec++;
1624
1625
1626
1627
1628
1629 /* decoder handle */
1630 ps_dec_state_multi_core = ps_mem_rec->pv_base;
1631 u4_num_mem_rec++;
1632 ps_mem_rec++;
1633
1634
1635 {
1636 ps_dec_handle->pv_codec_handle = (void *)ps_dec_state_multi_core; /* Initializing codec context */
1637
1638 ps_dechdl->pv_codec_handle = (void *)ps_dec_state_multi_core;
1639 ps_dechdl->pv_fxns = (void *)impeg2d_api_function;
1640 }
1641
1642
1643 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1644 {
1645 /*************************************************************************/
1646 /* For MPEG2 Decoder Context */
1647 /*************************************************************************/
1648 ps_dec_state = ps_mem_rec->pv_base;
1649
1650 ps_dec_state_multi_core->ps_dec_state[i4_num_threads] = ps_dec_state;
1651
1652 ps_dec_state->ps_dec_state_multi_core = ps_dec_state_multi_core;
1653
1654 ps_dec_state->i4_num_cores = 1;
1655 /* @ */ /* Used for storing MemRecords */
1656 u4_num_mem_rec++;
1657 ps_mem_rec++;
1658
1659 /* Thread handle */
1660 ps_dec_state->pv_codec_thread_handle = ps_mem_rec->pv_base;
1661 u4_num_mem_rec++;
1662 ps_mem_rec++;
1663
1664 /*************************************************************************/
1665 /* For Motion Compensation Buffers */
1666 /*************************************************************************/
1667 pv = ps_mem_rec->pv_base;
1668
1669 /* for mc_fw_buf.pu1_y */
1670
1671 ps_dec_state->s_mc_fw_buf.pu1_y = pv;
1672 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1673
1674 u4_size = sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1675 /* for mc_fw_buf.pu1_u */
1676
1677 ps_dec_state->s_mc_fw_buf.pu1_u = pv;
1678 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1679
1680 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1681
1682 /* for mc_fw_buf.pu1_v */
1683
1684 ps_dec_state->s_mc_fw_buf.pu1_v = pv;
1685 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1686
1687 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1688
1689 /* for mc_bk_buf.pu1_y */
1690
1691 ps_dec_state->s_mc_bk_buf.pu1_y = pv;
1692 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1693
1694 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1695
1696 /* for mc_bk_buf.pu1_u */
1697
1698 ps_dec_state->s_mc_bk_buf.pu1_u = pv;
1699 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1700
1701 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1702
1703 /* for mc_bk_buf.pu1_v */
1704
1705 ps_dec_state->s_mc_bk_buf.pu1_v = pv;
1706 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1707
1708 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1709
1710 /* for mc_buf.pu1_y */
1711
1712 ps_dec_state->s_mc_buf.pu1_y = pv;
1713 pv = (void *)((UWORD8 *)pv + MB_LUMA_MEM_SIZE);
1714
1715 u4_size += sizeof(UWORD8) * MB_LUMA_MEM_SIZE;
1716
1717 /* for mc_buf.pu1_u */
1718
1719 ps_dec_state->s_mc_buf.pu1_u = pv;
1720 pv = (void *)((UWORD8 *)pv + MB_CHROMA_MEM_SIZE);
1721
1722 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1723
1724 /* for mc_buf.pu1_v */
1725
1726 ps_dec_state->s_mc_buf.pu1_v = pv;
1727
1728 u4_size += sizeof(UWORD8) * MB_CHROMA_MEM_SIZE;
1729
1730 u4_num_mem_rec++;
1731 ps_mem_rec++;
1732
1733
1734
1735 ps_dec_state->pv_pic_buf_mg = 0;
1736
1737 /*************************************************************************/
1738 /* For saving stack context to support global error handling */
1739 /*************************************************************************/
1740 ps_dec_state->pv_stack_cntxt = ps_mem_rec->pv_base;
1741 u4_num_mem_rec++;
1742 ps_mem_rec++;
1743
1744 }
1745
1746
1747
1748
1749
1750 /*************************************************************************/
1751 /* For Picture Buffer Manager */
1752 /*************************************************************************/
1753 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1754
1755 ps_dec_state->pv_pic_buf_mg = ps_mem_rec->pv_base;
1756 ps_dec_state->pv_pic_buf_base = (UWORD8 *)ps_mem_rec->pv_base + sizeof(buf_mgr_t);
1757
1758 u4_num_mem_rec++;
1759 ps_mem_rec++;
1760
1761
1762
1763 for(i4_num_threads = 0; i4_num_threads < MAX_THREADS; i4_num_threads++)
1764 {
1765
1766 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[i4_num_threads];
1767
1768
1769 /* --------------------------------------------------------------------- */
1770 /* Initializations */
1771
1772 ps_dec_state->u2_header_done = 0; /* Header decoding not done */
1773
1774
1775 {
1776 UWORD32 u4_max_frm_width,u4_max_frm_height;
1777
1778 u4_max_frm_width = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_wd);
1779 u4_max_frm_height = ALIGN16(ps_dec_init_ip->s_ivd_init_ip_t.u4_frm_max_ht);
1780
1781 ps_dec_state->u2_create_max_width = u4_max_frm_width;
1782 ps_dec_state->u2_create_max_height = u4_max_frm_height;
1783
1784 ps_dec_state->i4_chromaFormat = ps_dec_init_ip->s_ivd_init_ip_t.e_output_format;
1785 ps_dec_state->u4_frm_buf_stride = 0 ;
1786 ps_dec_state->u2_frame_width = u4_max_frm_width;
1787 ps_dec_state->u2_picture_width = u4_max_frm_width;
1788 ps_dec_state->u2_horizontal_size = u4_max_frm_width;
1789
1790 ps_dec_state->u2_frame_height = u4_max_frm_height;
1791 ps_dec_state->u2_vertical_size = u4_max_frm_height;
1792 ps_dec_state->u4_share_disp_buf = u4_share_disp_buf;
1793 ps_dec_state->u4_deinterlace = u4_deinterlace;
1794 ps_dec_state->ps_deint_pic = NULL;
1795 }
1796 }
1797
1798
1799 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1800
1801 if((ps_dec_state->i4_chromaFormat == IV_YUV_422ILE)
1802 &&((ps_dec_state->u2_vertical_size & 0x1) != 0))
1803 {
1804 //printf("Error! Height should be multiple of 2 if Chroma format is 422ILE\n");
1805 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_CHROMA_FORMAT_HEIGHT_ERROR;
1806 return(IV_FAIL);
1807
1808
1809 }
1810
1811 /* --------------------------------------------------------------------- */
1812
1813
1814 /* ! */
1815 // picture buffer manager initialization will be done only for first thread
1816 impeg2_disp_mgr_init(&ps_dec_state->s_disp_mgr);
1817 impeg2_buf_mgr_init((buf_mgr_t *)ps_dec_state->pv_pic_buf_mg);
1818
1819 /*************************************************************************/
1820 /* Internal Frame Buffers */
1821 /*************************************************************************/
1822
1823
1824 /* Set first frame to grey */
1825 {
1826 ps_frm_buf = ps_mem_rec;
1827 memset(ps_frm_buf->pv_base, 128, ps_frm_buf->u4_mem_size);
1828 ps_frm_buf++;
1829 }
1830
1831 if(0 == ps_dec_state->u4_share_disp_buf)
1832 {
1833 pic_buf_t *ps_pic_buf;
1834 ps_pic_buf = (pic_buf_t *)ps_dec_state->pv_pic_buf_base;
1835 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1836 {
1837 UWORD8 *pu1_buf;
1838 pu1_buf = ps_mem_rec->pv_base;
1839
1840 ps_pic_buf->pu1_y = pu1_buf;
1841 pu1_buf += i4_max_ht * i4_max_wd;
1842
1843 ps_pic_buf->pu1_u = pu1_buf;
1844 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1845
1846 ps_pic_buf->pu1_v = pu1_buf;
1847 pu1_buf += i4_max_ht * i4_max_wd >> 2;
1848
1849 ps_pic_buf->i4_buf_id = i;
1850
1851 ps_pic_buf->u1_used_as_ref = 0;
1852
1853 ps_pic_buf->u4_ts = 0;
1854
1855 impeg2_buf_mgr_add(ps_dec_state->pv_pic_buf_mg, ps_pic_buf, i);
1856 ps_mem_rec++;
1857 ps_pic_buf++;
1858 }
1859 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1860 }
1861 else if (ps_dec_state->i4_chromaFormat != IV_YUV_420P)
1862 {
1863 for(i = 0; i < NUM_INT_FRAME_BUFFERS; i++)
1864 {
1865 ps_dec_state->pu1_chroma_ref_buf[i] = ps_mem_rec->pv_base;
1866 ps_mem_rec++;
1867 }
1868
1869 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1870 }
1871 else
1872 {
1873 ps_mem_rec+=NUM_INT_FRAME_BUFFERS;
1874 u4_num_mem_rec += NUM_INT_FRAME_BUFFERS;
1875 }
1876
1877
1878 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1879
1880
1881 ps_dec_state->pv_jobq_buf = ps_mem_rec->pv_base;
1882 ps_dec_state->i4_jobq_buf_size = ps_mem_rec->u4_mem_size;
1883 ps_mem_rec++;
1884
1885 if(u4_num_mem_rec > ps_dec_init_ip->s_ivd_init_ip_t.u4_num_mem_rec)
1886 {
1887 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IMPEG2D_INIT_NUM_MEM_REC_NOT_SUFFICIENT;
1888 return(IV_FAIL);
1889
1890 }
1891
1892 ps_dec_state->u1_flushfrm = 0;
1893 ps_dec_state->u1_flushcnt = 0;
1894 ps_dec_state->pv_jobq = impeg2_jobq_init(ps_dec_state->pv_jobq_buf, ps_dec_state->i4_jobq_buf_size);
1895
1896
1897 ps_dec_state->pv_deinterlacer_ctxt = ps_mem_rec->pv_base;
1898 ps_mem_rec++;
1899
1900 ps_dec_state->pu1_deint_fmt_buf = ps_mem_rec->pv_base;
1901 ps_mem_rec++;
1902
1903
1904 /*************************************************************************/
1905 /* Last MemTab is used for storing TabRecords */
1906 /*************************************************************************/
1907 ps_dec_state->pv_memTab = (void *)ps_mem_rec->pv_base;
1908 memcpy(ps_mem_rec->pv_base,ps_dec_init_ip->s_ivd_init_ip_t.pv_mem_rec_location, ps_mem_rec->u4_mem_size);
1909 /* Updating in Decoder Context with memRecords */
1910 u4_num_mem_rec++;
1911 ps_mem_rec++;
1912 ps_dec_state->u4_num_mem_records = u4_num_mem_rec;
1913
1914
1915 ps_dec_state->u4_num_frames_decoded = 0;
1916 ps_dec_state->aps_ref_pics[0] = NULL;
1917 ps_dec_state->aps_ref_pics[1] = NULL;
1918
1919 ps_dec_init_op->s_ivd_init_op_t.u4_error_code = IV_SUCCESS;
1920
1921 impeg2d_init_arch(ps_dec_state);
1922
1923 impeg2d_init_function_ptr(ps_dec_state);
1924
1925 return(IV_SUCCESS);
1926 }
1927
1928 /*****************************************************************************/
1929 /* */
1930 /* Function Name : impeg2d_api_retrieve_mem_rec */
1931 /* */
1932 /* Description : */
1933 /* */
1934 /* Inputs : */
1935 /* Globals : <Does it use any global variables?> */
1936 /* Outputs : */
1937 /* Returns : void */
1938 /* */
1939 /* Issues : none */
1940 /* */
1941 /* Revision History: */
1942 /* */
1943 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
1944 /* 22 10 2008 100356 Draft */
1945 /* */
1946 /*****************************************************************************/
impeg2d_api_retrieve_mem_rec(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)1947 IV_API_CALL_STATUS_T impeg2d_api_retrieve_mem_rec(iv_obj_t *ps_dechdl,
1948 void *pv_api_ip,
1949 void *pv_api_op)
1950 {
1951 UWORD32 u4_i;
1952 dec_state_t *ps_dec_state;
1953 dec_state_multi_core_t *ps_dec_state_multi_core;
1954 iv_mem_rec_t *ps_mem_rec;
1955 iv_mem_rec_t *ps_temp_rec;
1956
1957
1958
1959 impeg2d_retrieve_mem_rec_ip_t *ps_retr_mem_rec_ip;
1960 impeg2d_retrieve_mem_rec_op_t *ps_retr_mem_rec_op;
1961
1962 ps_retr_mem_rec_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
1963 ps_retr_mem_rec_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
1964
1965 ps_mem_rec = ps_retr_mem_rec_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
1966 ps_dec_state_multi_core = (dec_state_multi_core_t *) (ps_dechdl->pv_codec_handle);
1967 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
1968 ps_temp_rec = ps_dec_state->pv_memTab;
1969
1970 for(u4_i = 0; u4_i < (ps_dec_state->u4_num_mem_records);u4_i++)
1971 {
1972 ps_mem_rec[u4_i].u4_mem_size = ps_temp_rec[u4_i].u4_mem_size;
1973 ps_mem_rec[u4_i].u4_mem_alignment = ps_temp_rec[u4_i].u4_mem_alignment;
1974 ps_mem_rec[u4_i].e_mem_type = ps_temp_rec[u4_i].e_mem_type;
1975 ps_mem_rec[u4_i].pv_base = ps_temp_rec[u4_i].pv_base;
1976 }
1977
1978 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = IV_SUCCESS;
1979 ps_retr_mem_rec_op->s_ivd_retrieve_mem_rec_op_t.u4_num_mem_rec_filled = ps_dec_state->u4_num_mem_records;
1980
1981 impeg2_jobq_deinit(ps_dec_state->pv_jobq);
1982 IMPEG2D_PRINT_STATISTICS();
1983
1984
1985 return(IV_SUCCESS);
1986
1987 }
1988
1989 /*****************************************************************************/
1990 /* */
1991 /* Function Name : impeg2d_api_ctl */
1992 /* */
1993 /* Description : */
1994 /* */
1995 /* Inputs : */
1996 /* Globals : <Does it use any global variables?> */
1997 /* Outputs : */
1998 /* Returns : void */
1999 /* */
2000 /* Issues : none */
2001 /* */
2002 /* Revision History: */
2003 /* */
2004 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2005 /* 22 10 2008 100356 Draft */
2006 /* */
2007 /*****************************************************************************/
impeg2d_api_ctl(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)2008 IV_API_CALL_STATUS_T impeg2d_api_ctl(iv_obj_t *ps_dechdl,
2009 void *pv_api_ip,
2010 void *pv_api_op)
2011 {
2012 WORD32 i4_sub_cmd;
2013 UWORD32 *pu4_api_ip;
2014 IV_API_CALL_STATUS_T u4_error_code;
2015
2016 pu4_api_ip = (UWORD32 *)pv_api_ip;
2017 i4_sub_cmd = *(pu4_api_ip + 2);
2018
2019 switch(i4_sub_cmd)
2020 {
2021 case IVD_CMD_CTL_GETPARAMS:
2022 u4_error_code = impeg2d_api_get_status(ps_dechdl, (void *)pv_api_ip,
2023 (void *)pv_api_op);
2024 break;
2025
2026 case IVD_CMD_CTL_SETPARAMS:
2027 u4_error_code = impeg2d_api_set_params(ps_dechdl, (void *)pv_api_ip,
2028 (void *)pv_api_op);
2029 break;
2030
2031 case IVD_CMD_CTL_RESET:
2032 u4_error_code = impeg2d_api_reset(ps_dechdl, (void *)pv_api_ip,
2033 (void *)pv_api_op);
2034 break;
2035
2036 case IVD_CMD_CTL_SETDEFAULT:
2037 u4_error_code = impeg2d_api_set_default(ps_dechdl,
2038 (void *)pv_api_ip,
2039 (void *)pv_api_op);
2040 break;
2041
2042 case IVD_CMD_CTL_FLUSH:
2043 u4_error_code = impeg2d_api_set_flush_mode(ps_dechdl,
2044 (void *)pv_api_ip,
2045 (void *)pv_api_op);
2046 break;
2047
2048 case IVD_CMD_CTL_GETBUFINFO:
2049 u4_error_code = impeg2d_api_get_buf_info(ps_dechdl,
2050 (void *)pv_api_ip,
2051 (void *)pv_api_op);
2052 break;
2053
2054 case IVD_CMD_CTL_GETVERSION:
2055 u4_error_code = impeg2d_api_get_version(ps_dechdl, (void *)pv_api_ip,
2056 (void *)pv_api_op);
2057 break;
2058
2059 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2060 u4_error_code = impeg2d_api_set_num_cores(ps_dechdl,
2061 (void *)pv_api_ip,
2062 (void *)pv_api_op);
2063 break;
2064
2065 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2066 u4_error_code = impeg2d_get_frame_dimensions(ps_dechdl,
2067 (void *)pv_api_ip,
2068 (void *)pv_api_op);
2069 break;
2070
2071 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
2072 u4_error_code = impeg2d_api_get_seq_info(ps_dechdl,
2073 (void *)pv_api_ip,
2074 (void *)pv_api_op);
2075 break;
2076
2077 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
2078 u4_error_code = impeg2d_set_processor(ps_dechdl, (void *)pv_api_ip,
2079 (void *)pv_api_op);
2080 break;
2081
2082 default:
2083 u4_error_code = IV_FAIL;
2084 break;
2085 }
2086
2087 return (u4_error_code);
2088
2089 }
2090
2091 /*****************************************************************************/
2092 /* */
2093 /* Function Name : impeg2d_api_check_struct_sanity */
2094 /* */
2095 /* Description : */
2096 /* */
2097 /* Inputs : */
2098 /* Globals : <Does it use any global variables?> */
2099 /* Outputs : */
2100 /* Returns : void */
2101 /* */
2102 /* Issues : none */
2103 /* */
2104 /* Revision History: */
2105 /* */
2106 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
2107 /* 22 10 2008 100356 Draft */
2108 /* */
2109 /*****************************************************************************/
impeg2d_api_check_struct_sanity(iv_obj_t * ps_handle,void * pv_api_ip,void * pv_api_op)2110 IV_API_CALL_STATUS_T impeg2d_api_check_struct_sanity(iv_obj_t *ps_handle,
2111 void *pv_api_ip,
2112 void *pv_api_op)
2113 {
2114 WORD32 i4_cmd;
2115 UWORD32 *pu4_api_ip;
2116 UWORD32 *pu4_api_op;
2117 WORD32 i,j;
2118
2119 if(NULL == pv_api_op)
2120 return(IV_FAIL);
2121
2122 if(NULL == pv_api_ip)
2123 return(IV_FAIL);
2124
2125 pu4_api_ip = (UWORD32 *)pv_api_ip;
2126 pu4_api_op = (UWORD32 *)pv_api_op;
2127 i4_cmd = (IVD_API_COMMAND_TYPE_T)*(pu4_api_ip + 1);
2128
2129 /* error checks on handle */
2130 switch(i4_cmd)
2131 {
2132 case IV_CMD_GET_NUM_MEM_REC:
2133 case IV_CMD_FILL_NUM_MEM_REC:
2134 break;
2135 case IV_CMD_INIT:
2136 if(ps_handle == NULL)
2137 {
2138 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2139 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2140 return IV_FAIL;
2141 }
2142
2143 if(ps_handle->u4_size != sizeof(iv_obj_t))
2144 {
2145 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2146 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2147 return IV_FAIL;
2148 }
2149 break;
2150 case IVD_CMD_GET_DISPLAY_FRAME:
2151 case IVD_CMD_VIDEO_DECODE:
2152 case IV_CMD_RETRIEVE_MEMREC:
2153 case IVD_CMD_SET_DISPLAY_FRAME:
2154 case IVD_CMD_REL_DISPLAY_FRAME:
2155 case IVD_CMD_VIDEO_CTL:
2156 {
2157 if(ps_handle == NULL)
2158 {
2159 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2160 *(pu4_api_op + 1) |= IVD_HANDLE_NULL;
2161 return IV_FAIL;
2162 }
2163
2164 if(ps_handle->u4_size != sizeof(iv_obj_t))
2165 {
2166 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2167 *(pu4_api_op + 1) |= IVD_HANDLE_STRUCT_SIZE_INCORRECT;
2168 return IV_FAIL;
2169 }
2170 if(ps_handle->pv_fxns != impeg2d_api_function)
2171 {
2172 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2173 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2174 return IV_FAIL;
2175 }
2176
2177 if(ps_handle->pv_codec_handle == NULL)
2178 {
2179 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2180 *(pu4_api_op + 1) |= IVD_INVALID_HANDLE_NULL;
2181 return IV_FAIL;
2182 }
2183 }
2184 break;
2185 default:
2186 *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
2187 *(pu4_api_op + 1) |= IVD_INVALID_API_CMD;
2188 return IV_FAIL;
2189 }
2190
2191 switch(i4_cmd)
2192 {
2193 case IV_CMD_GET_NUM_MEM_REC:
2194 {
2195 impeg2d_num_mem_rec_ip_t *ps_ip = (impeg2d_num_mem_rec_ip_t *)pv_api_ip;
2196 impeg2d_num_mem_rec_op_t *ps_op = (impeg2d_num_mem_rec_op_t *)pv_api_op;
2197 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code = 0;
2198
2199 if(ps_ip->s_ivd_num_mem_rec_ip_t.u4_size != sizeof(impeg2d_num_mem_rec_ip_t))
2200 {
2201 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2202 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2203 return(IV_FAIL);
2204 }
2205
2206 if(ps_op->s_ivd_num_mem_rec_op_t.u4_size != sizeof(impeg2d_num_mem_rec_op_t))
2207 {
2208 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2209 ps_op->s_ivd_num_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2210 return(IV_FAIL);
2211 }
2212 }
2213 break;
2214 case IV_CMD_FILL_NUM_MEM_REC:
2215 {
2216 impeg2d_fill_mem_rec_ip_t *ps_ip = (impeg2d_fill_mem_rec_ip_t *)pv_api_ip;
2217 impeg2d_fill_mem_rec_op_t *ps_op = (impeg2d_fill_mem_rec_op_t *)pv_api_op;
2218 iv_mem_rec_t *ps_mem_rec;
2219
2220 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code = 0;
2221
2222 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_size != sizeof(impeg2d_fill_mem_rec_ip_t))
2223 {
2224 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2225 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2226 return(IV_FAIL);
2227 }
2228
2229 if(ps_op->s_ivd_fill_mem_rec_op_t.u4_size != sizeof(impeg2d_fill_mem_rec_op_t))
2230 {
2231 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2232 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2233 return(IV_FAIL);
2234 }
2235
2236 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd < MIN_WIDTH)
2237 {
2238 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2239 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2240 return(IV_FAIL);
2241 }
2242
2243 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd > MAX_WIDTH)
2244 {
2245 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2246 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_WIDTH_NOT_SUPPPORTED;
2247 return(IV_FAIL);
2248 }
2249
2250 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht < MIN_HEIGHT)
2251 {
2252 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2253 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2254 return(IV_FAIL);
2255 }
2256
2257 if(ps_ip->s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht > MAX_HEIGHT)
2258 {
2259 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2260 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_REQUESTED_HEIGHT_NOT_SUPPPORTED;
2261 return(IV_FAIL);
2262 }
2263
2264 if(NULL == ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location)
2265 {
2266 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2267 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2268 return(IV_FAIL);
2269 }
2270
2271 /* check memrecords sizes are correct */
2272 ps_mem_rec = ps_ip->s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location;
2273 for(i=0;i<NUM_MEM_RECORDS;i++)
2274 {
2275 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2276 {
2277 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2278 ps_op->s_ivd_fill_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2279 return IV_FAIL;
2280 }
2281 }
2282 }
2283 break;
2284
2285 case IV_CMD_INIT:
2286 {
2287 impeg2d_init_ip_t *ps_ip = (impeg2d_init_ip_t *)pv_api_ip;
2288 impeg2d_init_op_t *ps_op = (impeg2d_init_op_t *)pv_api_op;
2289 iv_mem_rec_t *ps_mem_rec;
2290 UWORD32 u4_tot_num_mem_recs;
2291
2292 ps_op->s_ivd_init_op_t.u4_error_code = 0;
2293
2294 if(ps_ip->s_ivd_init_ip_t.u4_size != sizeof(impeg2d_init_ip_t))
2295 {
2296 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2297 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2298 return(IV_FAIL);
2299 }
2300
2301 if(ps_op->s_ivd_init_op_t.u4_size != sizeof(impeg2d_init_op_t))
2302 {
2303 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2304 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2305 return(IV_FAIL);
2306 }
2307
2308 u4_tot_num_mem_recs = NUM_MEM_RECORDS;
2309
2310
2311
2312
2313 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec > u4_tot_num_mem_recs)
2314 {
2315 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2316 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_NOT_SUFFICIENT;
2317 return(IV_FAIL);
2318 }
2319
2320 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd < MIN_WIDTH)
2321 {
2322 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2323 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2324 return(IV_FAIL);
2325 }
2326
2327 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_wd > MAX_WIDTH)
2328 {
2329 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2330 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_WIDTH_NOT_SUPPPORTED;
2331 return(IV_FAIL);
2332 }
2333
2334 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht < MIN_HEIGHT)
2335 {
2336 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2337 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2338 return(IV_FAIL);
2339 }
2340
2341 if(ps_ip->s_ivd_init_ip_t.u4_frm_max_ht > MAX_HEIGHT)
2342 {
2343 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2344 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_HEIGHT_NOT_SUPPPORTED;
2345 return(IV_FAIL);
2346 }
2347
2348 if(NULL == ps_ip->s_ivd_init_ip_t.pv_mem_rec_location)
2349 {
2350 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2351 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_NUM_REC_NOT_SUFFICIENT;
2352 return(IV_FAIL);
2353 }
2354
2355 if((ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420P) &&
2356 (ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_422ILE)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_UV)&&(ps_ip->s_ivd_init_ip_t.e_output_format != IV_YUV_420SP_VU))
2357 {
2358 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2359 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_COL_FMT_NOT_SUPPORTED;
2360 return(IV_FAIL);
2361 }
2362
2363 /* verify number of mem records */
2364 if(ps_ip->s_ivd_init_ip_t.u4_num_mem_rec < NUM_MEM_RECORDS)
2365 {
2366 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2367 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_NOT_SUFFICIENT;
2368 return IV_FAIL;
2369 }
2370
2371 ps_mem_rec = ps_ip->s_ivd_init_ip_t.pv_mem_rec_location;
2372 /* verify wether first memrecord is handle or not */
2373 /*
2374 if(ps_mem_rec->pv_base != ps_handle)
2375 {
2376 // indicate the incorrect handle error
2377 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2378 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INVALID_HANDLE;
2379 return IV_FAIL;
2380 }
2381 */
2382 /* check memrecords sizes are correct */
2383 for(i=0;i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec ; i++)
2384 {
2385 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2386 {
2387 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2388 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2389 return IV_FAIL;
2390 }
2391 }
2392
2393 /* verify memtabs for overlapping regions */
2394 {
2395 UWORD8 *pau1_start[NUM_MEM_RECORDS];
2396 UWORD8 *pau1_end[NUM_MEM_RECORDS];
2397
2398
2399 pau1_start[0] = (UWORD8 *)(ps_mem_rec[0].pv_base);
2400 pau1_end[0] = (UWORD8 *)(ps_mem_rec[0].pv_base) + ps_mem_rec[0].u4_mem_size - 1;
2401 for(i = 1; i < (WORD32)ps_ip->s_ivd_init_ip_t.u4_num_mem_rec; i++)
2402 {
2403 /* This array is populated to check memtab overlapp */
2404 pau1_start[i] = (UWORD8 *)(ps_mem_rec[i].pv_base);
2405 pau1_end[i] = (UWORD8 *)(ps_mem_rec[i].pv_base) + ps_mem_rec[i].u4_mem_size - 1;
2406
2407 for(j = 0; j < i; j++)
2408 {
2409 if((pau1_start[i] >= pau1_start[j]) && (pau1_start[i] <= pau1_end[j]))
2410 {
2411 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2412 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2413 return IV_FAIL;
2414 }
2415
2416 if((pau1_end[i] >= pau1_start[j]) && (pau1_end[i] <= pau1_end[j]))
2417 {
2418 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2419 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2420 return IV_FAIL;
2421 }
2422
2423 if((pau1_start[i] < pau1_start[j]) && (pau1_end[i] > pau1_end[j]))
2424 {
2425 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2426 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_OVERLAP_ERR;
2427 return IV_FAIL;
2428 }
2429 }
2430 }
2431 }
2432
2433
2434
2435
2436 {
2437 iv_mem_rec_t as_mem_rec_ittiam_api[NUM_MEM_RECORDS];
2438
2439 impeg2d_fill_mem_rec_ip_t s_fill_mem_rec_ip;
2440 impeg2d_fill_mem_rec_op_t s_fill_mem_rec_op;
2441 IV_API_CALL_STATUS_T e_status;
2442 WORD32 i4_num_memrec;
2443 {
2444
2445 iv_num_mem_rec_ip_t s_no_of_mem_rec_query_ip;
2446 iv_num_mem_rec_op_t s_no_of_mem_rec_query_op;
2447
2448
2449 s_no_of_mem_rec_query_ip.u4_size = sizeof(iv_num_mem_rec_ip_t);
2450 s_no_of_mem_rec_query_op.u4_size = sizeof(iv_num_mem_rec_op_t);
2451
2452 s_no_of_mem_rec_query_ip.e_cmd = IV_CMD_GET_NUM_MEM_REC;
2453 impeg2d_api_function(NULL,
2454 (void *)&s_no_of_mem_rec_query_ip,
2455 (void *)&s_no_of_mem_rec_query_op);
2456
2457 i4_num_memrec = s_no_of_mem_rec_query_op.u4_num_mem_rec;
2458
2459
2460
2461 }
2462
2463
2464 /* initialize mem records array with sizes */
2465 for(i = 0; i < i4_num_memrec; i++)
2466 {
2467 as_mem_rec_ittiam_api[i].u4_size = sizeof(iv_mem_rec_t);
2468 }
2469
2470 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_size = sizeof(impeg2d_fill_mem_rec_ip_t);
2471 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.e_cmd = IV_CMD_FILL_NUM_MEM_REC;
2472 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_wd = ps_ip->s_ivd_init_ip_t.u4_frm_max_wd;
2473 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.u4_max_frm_ht = ps_ip->s_ivd_init_ip_t.u4_frm_max_ht;
2474 s_fill_mem_rec_ip.s_ivd_fill_mem_rec_ip_t.pv_mem_rec_location = as_mem_rec_ittiam_api;
2475 s_fill_mem_rec_ip.u4_share_disp_buf = ps_ip->u4_share_disp_buf;
2476 s_fill_mem_rec_ip.e_output_format = ps_ip->s_ivd_init_ip_t.e_output_format;
2477 s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_size = sizeof(impeg2d_fill_mem_rec_op_t);
2478
2479
2480 e_status = impeg2d_api_function(NULL,
2481 (void *)&s_fill_mem_rec_ip,
2482 (void *)&s_fill_mem_rec_op);
2483 if(IV_FAIL == e_status)
2484 {
2485 ps_op->s_ivd_init_op_t.u4_error_code = s_fill_mem_rec_op.s_ivd_fill_mem_rec_op_t.u4_error_code;
2486 return(IV_FAIL);
2487 }
2488
2489
2490
2491 for(i = 0; i < i4_num_memrec; i ++)
2492 {
2493 if(ps_mem_rec[i].pv_base == NULL)
2494 {
2495 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2496 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_BASE_NULL;
2497 return IV_FAIL;
2498 }
2499 #ifdef CHECK_ALIGN
2500
2501 if((UWORD32)(ps_mem_rec[i].pv_base) & (ps_mem_rec[i].u4_mem_alignment - 1))
2502 {
2503 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2504 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2505 return IV_FAIL;
2506 }
2507 #endif //CHECK_ALIGN
2508 if(ps_mem_rec[i].u4_mem_alignment != as_mem_rec_ittiam_api[i].u4_mem_alignment)
2509 {
2510 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2511 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_ALIGNMENT_ERR;
2512 return IV_FAIL;
2513 }
2514
2515 if(ps_mem_rec[i].u4_mem_size < as_mem_rec_ittiam_api[i].u4_mem_size)
2516 {
2517 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2518 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INSUFFICIENT_SIZE;
2519 return IV_FAIL;
2520 }
2521
2522 if(ps_mem_rec[i].e_mem_type != as_mem_rec_ittiam_api[i].e_mem_type)
2523 {
2524 if (IV_EXTERNAL_CACHEABLE_SCRATCH_MEM == as_mem_rec_ittiam_api[i].e_mem_type)
2525 {
2526 if (IV_EXTERNAL_CACHEABLE_PERSISTENT_MEM == ps_mem_rec[i].e_mem_type)
2527 {
2528 continue;
2529 }
2530 }
2531 ps_op->s_ivd_init_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2532 ps_op->s_ivd_init_op_t.u4_error_code |= IVD_INIT_DEC_MEM_REC_INCORRECT_TYPE;
2533 return IV_FAIL;
2534 }
2535 }
2536 }
2537
2538
2539 }
2540 break;
2541
2542 case IVD_CMD_GET_DISPLAY_FRAME:
2543 {
2544 impeg2d_get_display_frame_ip_t *ps_ip = (impeg2d_get_display_frame_ip_t *)pv_api_ip;
2545 impeg2d_get_display_frame_op_t *ps_op = (impeg2d_get_display_frame_op_t *)pv_api_op;
2546
2547 ps_op->s_ivd_get_display_frame_op_t.u4_error_code = 0;
2548
2549 if(ps_ip->s_ivd_get_display_frame_ip_t.u4_size != sizeof(impeg2d_get_display_frame_ip_t))
2550 {
2551 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2552 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2553 return(IV_FAIL);
2554 }
2555
2556 if(ps_op->s_ivd_get_display_frame_op_t.u4_size != sizeof(impeg2d_get_display_frame_op_t))
2557 {
2558 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2559 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2560 return(IV_FAIL);
2561 }
2562
2563 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs == 0)
2564 {
2565 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2566 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2567 return IV_FAIL;
2568 }
2569
2570 for(i = 0; i< (WORD32)ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_num_bufs;i++)
2571 {
2572 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.pu1_bufs[i] == NULL)
2573 {
2574 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2575 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2576 return IV_FAIL;
2577 }
2578
2579 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2580 {
2581 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2582 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2583 return IV_FAIL;
2584 }
2585 /*
2586 if(ps_ip->s_ivd_get_display_frame_ip_t.s_out_buffer.u4_min_out_buf_size[i] == 0)
2587 {
2588 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2589 ps_op->s_ivd_get_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2590 return IV_FAIL;
2591 }
2592 */
2593 }
2594 }
2595 break;
2596 case IVD_CMD_REL_DISPLAY_FRAME:
2597 {
2598 impeg2d_rel_display_frame_ip_t *ps_ip = (impeg2d_rel_display_frame_ip_t *)pv_api_ip;
2599 impeg2d_rel_display_frame_op_t *ps_op = (impeg2d_rel_display_frame_op_t *)pv_api_op;
2600
2601 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code = 0;
2602
2603 if ((ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(impeg2d_rel_display_frame_ip_t))
2604 && (ps_ip->s_ivd_rel_display_frame_ip_t.u4_size != sizeof(ivd_rel_display_frame_ip_t)))
2605 {
2606 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2607 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2608 return(IV_FAIL);
2609 }
2610
2611 if((ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(impeg2d_rel_display_frame_op_t)) &&
2612 (ps_op->s_ivd_rel_display_frame_op_t.u4_size != sizeof(ivd_rel_display_frame_op_t)))
2613 {
2614 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2615 ps_op->s_ivd_rel_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2616 return(IV_FAIL);
2617 }
2618
2619 }
2620 break;
2621
2622
2623 case IVD_CMD_SET_DISPLAY_FRAME:
2624 {
2625 impeg2d_set_display_frame_ip_t *ps_ip = (impeg2d_set_display_frame_ip_t *)pv_api_ip;
2626 impeg2d_set_display_frame_op_t *ps_op = (impeg2d_set_display_frame_op_t *)pv_api_op;
2627 UWORD32 j, i;
2628
2629 ps_op->s_ivd_set_display_frame_op_t.u4_error_code = 0;
2630
2631 if ((ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(impeg2d_set_display_frame_ip_t))
2632 && (ps_ip->s_ivd_set_display_frame_ip_t.u4_size != sizeof(ivd_set_display_frame_ip_t)))
2633 {
2634 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2635 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2636 return(IV_FAIL);
2637 }
2638
2639 if((ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(impeg2d_set_display_frame_op_t)) &&
2640 (ps_op->s_ivd_set_display_frame_op_t.u4_size != sizeof(ivd_set_display_frame_op_t)))
2641 {
2642 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2643 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2644 return(IV_FAIL);
2645 }
2646
2647 if(ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs == 0)
2648 {
2649 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2650 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2651 return IV_FAIL;
2652 }
2653
2654 for(j = 0; j < ps_ip->s_ivd_set_display_frame_ip_t.num_disp_bufs; j++)
2655 {
2656 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs == 0)
2657 {
2658 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2659 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUFS;
2660 return IV_FAIL;
2661 }
2662
2663 for(i=0;i< ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_num_bufs;i++)
2664 {
2665 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].pu1_bufs[i] == NULL)
2666 {
2667 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2668 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_OP_BUF_NULL;
2669 return IV_FAIL;
2670 }
2671
2672 if(ps_ip->s_ivd_set_display_frame_ip_t.s_disp_buffer[j].u4_min_out_buf_size[i] == 0)
2673 {
2674 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2675 ps_op->s_ivd_set_display_frame_op_t.u4_error_code |= IVD_DISP_FRM_ZERO_OP_BUF_SIZE;
2676 return IV_FAIL;
2677 }
2678 }
2679 }
2680 }
2681 break;
2682
2683 case IVD_CMD_VIDEO_DECODE:
2684 {
2685 impeg2d_video_decode_ip_t *ps_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
2686 impeg2d_video_decode_op_t *ps_op = (impeg2d_video_decode_op_t *)pv_api_op;
2687
2688 ps_op->s_ivd_video_decode_op_t.u4_error_code = 0;
2689
2690 if(ps_ip->s_ivd_video_decode_ip_t.u4_size != sizeof(impeg2d_video_decode_ip_t))
2691 {
2692 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2693 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2694 return(IV_FAIL);
2695 }
2696
2697 if(ps_op->s_ivd_video_decode_op_t.u4_size != sizeof(impeg2d_video_decode_op_t))
2698 {
2699 ps_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2700 ps_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2701 return(IV_FAIL);
2702 }
2703
2704 }
2705 break;
2706
2707 case IV_CMD_RETRIEVE_MEMREC:
2708 {
2709 impeg2d_retrieve_mem_rec_ip_t *ps_ip = (impeg2d_retrieve_mem_rec_ip_t *)pv_api_ip;
2710 impeg2d_retrieve_mem_rec_op_t *ps_op = (impeg2d_retrieve_mem_rec_op_t *)pv_api_op;
2711 iv_mem_rec_t *ps_mem_rec;
2712
2713 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code = 0;
2714
2715 if(ps_ip->s_ivd_retrieve_mem_rec_ip_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_ip_t))
2716 {
2717 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2718 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2719 return(IV_FAIL);
2720 }
2721
2722 if(ps_op->s_ivd_retrieve_mem_rec_op_t.u4_size != sizeof(impeg2d_retrieve_mem_rec_op_t))
2723 {
2724 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2725 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2726 return(IV_FAIL);
2727 }
2728
2729 ps_mem_rec = ps_ip->s_ivd_retrieve_mem_rec_ip_t.pv_mem_rec_location;
2730 /* check memrecords sizes are correct */
2731 for(i=0;i < NUM_MEM_RECORDS ; i++)
2732 {
2733 if(ps_mem_rec[i].u4_size != sizeof(iv_mem_rec_t))
2734 {
2735 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2736 ps_op->s_ivd_retrieve_mem_rec_op_t.u4_error_code |= IVD_MEM_REC_STRUCT_SIZE_INCORRECT;
2737 return IV_FAIL;
2738 }
2739 }
2740 }
2741 break;
2742
2743 case IVD_CMD_VIDEO_CTL:
2744 {
2745 UWORD32 *pu4_ptr_cmd;
2746 UWORD32 u4_sub_command;
2747
2748 pu4_ptr_cmd = (UWORD32 *)pv_api_ip;
2749 pu4_ptr_cmd += 2;
2750 u4_sub_command = *pu4_ptr_cmd;
2751
2752 switch(u4_sub_command)
2753 {
2754 case IVD_CMD_CTL_SETPARAMS:
2755 {
2756 impeg2d_ctl_set_config_ip_t *ps_ip;
2757 impeg2d_ctl_set_config_op_t *ps_op;
2758 ps_ip = (impeg2d_ctl_set_config_ip_t *)pv_api_ip;
2759 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2760
2761 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2762
2763 if(ps_ip->s_ivd_ctl_set_config_ip_t.u4_size != sizeof(impeg2d_ctl_set_config_ip_t))
2764 {
2765 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2766 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2767 return IV_FAIL;
2768 }
2769 }
2770 case IVD_CMD_CTL_SETDEFAULT:
2771 {
2772 impeg2d_ctl_set_config_op_t *ps_op;
2773 ps_op = (impeg2d_ctl_set_config_op_t *)pv_api_op;
2774 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code = 0;
2775
2776 if(ps_op->s_ivd_ctl_set_config_op_t.u4_size != sizeof(impeg2d_ctl_set_config_op_t))
2777 {
2778 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2779 ps_op->s_ivd_ctl_set_config_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2780 return IV_FAIL;
2781 }
2782 }
2783 break;
2784
2785 case IVD_CMD_CTL_GETPARAMS:
2786 {
2787 impeg2d_ctl_getstatus_ip_t *ps_ip;
2788 impeg2d_ctl_getstatus_op_t *ps_op;
2789
2790 ps_ip = (impeg2d_ctl_getstatus_ip_t *)pv_api_ip;
2791 ps_op = (impeg2d_ctl_getstatus_op_t *)pv_api_op;
2792
2793 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code = 0;
2794
2795 if(ps_ip->s_ivd_ctl_getstatus_ip_t.u4_size != sizeof(impeg2d_ctl_getstatus_ip_t))
2796 {
2797 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2798 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2799 return IV_FAIL;
2800 }
2801 if(ps_op->s_ivd_ctl_getstatus_op_t.u4_size != sizeof(impeg2d_ctl_getstatus_op_t))
2802 {
2803 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2804 ps_op->s_ivd_ctl_getstatus_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2805 return IV_FAIL;
2806 }
2807 }
2808 break;
2809
2810 case IVD_CMD_CTL_GETBUFINFO:
2811 {
2812 impeg2d_ctl_getbufinfo_ip_t *ps_ip;
2813 impeg2d_ctl_getbufinfo_op_t *ps_op;
2814 ps_ip = (impeg2d_ctl_getbufinfo_ip_t *)pv_api_ip;
2815 ps_op = (impeg2d_ctl_getbufinfo_op_t *)pv_api_op;
2816
2817 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code = 0;
2818
2819 if(ps_ip->s_ivd_ctl_getbufinfo_ip_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_ip_t))
2820 {
2821 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2822 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2823 return IV_FAIL;
2824 }
2825 if(ps_op->s_ivd_ctl_getbufinfo_op_t.u4_size != sizeof(impeg2d_ctl_getbufinfo_op_t))
2826 {
2827 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2828 ps_op->s_ivd_ctl_getbufinfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2829 return IV_FAIL;
2830 }
2831 }
2832 break;
2833
2834 case IVD_CMD_CTL_GETVERSION:
2835 {
2836 impeg2d_ctl_getversioninfo_ip_t *ps_ip;
2837 impeg2d_ctl_getversioninfo_op_t *ps_op;
2838 ps_ip = (impeg2d_ctl_getversioninfo_ip_t *)pv_api_ip;
2839 ps_op = (impeg2d_ctl_getversioninfo_op_t *)pv_api_op;
2840
2841 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code = 0;
2842
2843 if(ps_ip->s_ivd_ctl_getversioninfo_ip_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_ip_t))
2844 {
2845 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2846 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2847 return IV_FAIL;
2848 }
2849 if(ps_op->s_ivd_ctl_getversioninfo_op_t.u4_size != sizeof(impeg2d_ctl_getversioninfo_op_t))
2850 {
2851 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2852 ps_op->s_ivd_ctl_getversioninfo_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2853 return IV_FAIL;
2854 }
2855 }
2856 break;
2857
2858 case IVD_CMD_CTL_FLUSH:
2859 {
2860 impeg2d_ctl_flush_ip_t *ps_ip;
2861 impeg2d_ctl_flush_op_t *ps_op;
2862 ps_ip = (impeg2d_ctl_flush_ip_t *)pv_api_ip;
2863 ps_op = (impeg2d_ctl_flush_op_t *)pv_api_op;
2864
2865 ps_op->s_ivd_ctl_flush_op_t.u4_error_code = 0;
2866
2867 if(ps_ip->s_ivd_ctl_flush_ip_t.u4_size != sizeof(impeg2d_ctl_flush_ip_t))
2868 {
2869 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2870 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2871 return IV_FAIL;
2872 }
2873 if(ps_op->s_ivd_ctl_flush_op_t.u4_size != sizeof(impeg2d_ctl_flush_op_t))
2874 {
2875 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2876 ps_op->s_ivd_ctl_flush_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2877 return IV_FAIL;
2878 }
2879 }
2880 break;
2881
2882 case IVD_CMD_CTL_RESET:
2883 {
2884 impeg2d_ctl_reset_ip_t *ps_ip;
2885 impeg2d_ctl_reset_op_t *ps_op;
2886 ps_ip = (impeg2d_ctl_reset_ip_t *)pv_api_ip;
2887 ps_op = (impeg2d_ctl_reset_op_t *)pv_api_op;
2888
2889 ps_op->s_ivd_ctl_reset_op_t.u4_error_code = 0;
2890
2891 if(ps_ip->s_ivd_ctl_reset_ip_t.u4_size != sizeof(impeg2d_ctl_reset_ip_t))
2892 {
2893 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2894 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_IP_API_STRUCT_SIZE_INCORRECT;
2895 return IV_FAIL;
2896 }
2897 if(ps_op->s_ivd_ctl_reset_op_t.u4_size != sizeof(impeg2d_ctl_reset_op_t))
2898 {
2899 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2900 ps_op->s_ivd_ctl_reset_op_t.u4_error_code |= IVD_OP_API_STRUCT_SIZE_INCORRECT;
2901 return IV_FAIL;
2902 }
2903 }
2904 break;
2905
2906 case IMPEG2D_CMD_CTL_GET_BUFFER_DIMENSIONS:
2907 {
2908 impeg2d_ctl_get_frame_dimensions_ip_t *ps_ip;
2909 impeg2d_ctl_get_frame_dimensions_op_t *ps_op;
2910
2911 ps_ip =
2912 (impeg2d_ctl_get_frame_dimensions_ip_t *)pv_api_ip;
2913 ps_op =
2914 (impeg2d_ctl_get_frame_dimensions_op_t *)pv_api_op;
2915
2916 if(ps_ip->u4_size
2917 != sizeof(impeg2d_ctl_get_frame_dimensions_ip_t))
2918 {
2919 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2920 ps_op->u4_error_code |=
2921 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2922 return IV_FAIL;
2923 }
2924
2925 if(ps_op->u4_size
2926 != sizeof(impeg2d_ctl_get_frame_dimensions_op_t))
2927 {
2928 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2929 ps_op->u4_error_code |=
2930 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2931 return IV_FAIL;
2932 }
2933
2934 break;
2935 }
2936 case IMPEG2D_CMD_CTL_GET_SEQ_INFO:
2937 {
2938 impeg2d_ctl_get_seq_info_ip_t *ps_ip;
2939 impeg2d_ctl_get_seq_info_op_t *ps_op;
2940
2941 ps_ip =
2942 (impeg2d_ctl_get_seq_info_ip_t *)pv_api_ip;
2943 ps_op =
2944 (impeg2d_ctl_get_seq_info_op_t *)pv_api_op;
2945
2946 if(ps_ip->u4_size
2947 != sizeof(impeg2d_ctl_get_seq_info_ip_t))
2948 {
2949 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2950 ps_op->u4_error_code |=
2951 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2952 return IV_FAIL;
2953 }
2954
2955 if(ps_op->u4_size
2956 != sizeof(impeg2d_ctl_get_seq_info_op_t))
2957 {
2958 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2959 ps_op->u4_error_code |=
2960 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2961 return IV_FAIL;
2962 }
2963
2964 break;
2965 }
2966 case IMPEG2D_CMD_CTL_SET_NUM_CORES:
2967 {
2968 impeg2d_ctl_set_num_cores_ip_t *ps_ip;
2969 impeg2d_ctl_set_num_cores_op_t *ps_op;
2970
2971 ps_ip = (impeg2d_ctl_set_num_cores_ip_t *)pv_api_ip;
2972 ps_op = (impeg2d_ctl_set_num_cores_op_t *)pv_api_op;
2973
2974 if(ps_ip->u4_size
2975 != sizeof(impeg2d_ctl_set_num_cores_ip_t))
2976 {
2977 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2978 ps_op->u4_error_code |=
2979 IVD_IP_API_STRUCT_SIZE_INCORRECT;
2980 return IV_FAIL;
2981 }
2982
2983 if(ps_op->u4_size
2984 != sizeof(impeg2d_ctl_set_num_cores_op_t))
2985 {
2986 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2987 ps_op->u4_error_code |=
2988 IVD_OP_API_STRUCT_SIZE_INCORRECT;
2989 return IV_FAIL;
2990 }
2991
2992 #ifdef MULTICORE
2993 if((ps_ip->u4_num_cores < 1) || (ps_ip->u4_num_cores > MAX_THREADS))
2994 #else
2995 if(ps_ip->u4_num_cores != 1)
2996 #endif
2997 {
2998 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
2999 return IV_FAIL;
3000 }
3001 break;
3002 }
3003 case IMPEG2D_CMD_CTL_SET_PROCESSOR:
3004 {
3005 impeg2d_ctl_set_processor_ip_t *ps_ip;
3006 impeg2d_ctl_set_processor_op_t *ps_op;
3007
3008 ps_ip = (impeg2d_ctl_set_processor_ip_t *)pv_api_ip;
3009 ps_op = (impeg2d_ctl_set_processor_op_t *)pv_api_op;
3010
3011 if(ps_ip->u4_size
3012 != sizeof(impeg2d_ctl_set_processor_ip_t))
3013 {
3014 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3015 ps_op->u4_error_code |=
3016 IVD_IP_API_STRUCT_SIZE_INCORRECT;
3017 return IV_FAIL;
3018 }
3019
3020 if(ps_op->u4_size
3021 != sizeof(impeg2d_ctl_set_processor_op_t))
3022 {
3023 ps_op->u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3024 ps_op->u4_error_code |=
3025 IVD_OP_API_STRUCT_SIZE_INCORRECT;
3026 return IV_FAIL;
3027 }
3028
3029 break;
3030 }
3031 default:
3032 break;
3033
3034 }
3035 }
3036 break;
3037
3038 default:
3039 { *(pu4_api_op + 1) |= 1 << IVD_UNSUPPORTEDPARAM;
3040 *(pu4_api_op + 1) |= IVD_UNSUPPORTED_API_CMD;
3041 return IV_FAIL;
3042 }
3043
3044
3045 }
3046
3047 return IV_SUCCESS;
3048 }
3049
3050 /*****************************************************************************/
3051 /* */
3052 /* Function Name : impeg2d_api_entity */
3053 /* */
3054 /* Description : */
3055 /* */
3056 /* Inputs : */
3057 /* Globals : <Does it use any global variables?> */
3058 /* Outputs : */
3059 /* Returns : void */
3060 /* */
3061 /* Issues : none */
3062 /* */
3063 /* Revision History: */
3064 /* */
3065 /* DD MM YYYY Author(s) Changes (Describe the changes made) */
3066 /* 22 10 2008 100356 Draft */
3067 /* */
3068 /*****************************************************************************/
3069
3070
impeg2d_api_entity(iv_obj_t * ps_dechdl,void * pv_api_ip,void * pv_api_op)3071 IV_API_CALL_STATUS_T impeg2d_api_entity(iv_obj_t *ps_dechdl,
3072 void *pv_api_ip,
3073 void *pv_api_op)
3074 {
3075 iv_obj_t *ps_dec_handle;
3076 dec_state_t *ps_dec_state;
3077 dec_state_multi_core_t *ps_dec_state_multi_core;
3078
3079 impeg2d_video_decode_ip_t *ps_dec_ip;
3080
3081 impeg2d_video_decode_op_t *ps_dec_op;
3082 WORD32 bytes_remaining;
3083 pic_buf_t *ps_disp_pic;
3084
3085
3086
3087 ps_dec_ip = (impeg2d_video_decode_ip_t *)pv_api_ip;
3088 ps_dec_op = (impeg2d_video_decode_op_t *)pv_api_op;
3089
3090 memset(ps_dec_op,0,sizeof(impeg2d_video_decode_op_t));
3091
3092 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3093 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3094 bytes_remaining = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3095
3096 ps_dec_handle = (iv_obj_t *)ps_dechdl;
3097
3098 if(ps_dechdl == NULL)
3099 {
3100 return(IV_FAIL);
3101 }
3102
3103
3104
3105 ps_dec_state_multi_core = ps_dec_handle->pv_codec_handle;
3106 ps_dec_state = ps_dec_state_multi_core->ps_dec_state[0];
3107
3108 ps_dec_state->ps_disp_frm_buf = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3109 if(0 == ps_dec_state->u4_share_disp_buf)
3110 {
3111 ps_dec_state->ps_disp_frm_buf->pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3112 ps_dec_state->ps_disp_frm_buf->pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3113 ps_dec_state->ps_disp_frm_buf->pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3114 }
3115
3116 ps_dec_state->ps_disp_pic = NULL;
3117 ps_dec_state->i4_frame_decoded = 0;
3118 /*rest bytes consumed */
3119 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = 0;
3120
3121 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IV_SUCCESS;
3122
3123 if((ps_dec_ip->s_ivd_video_decode_ip_t.pv_stream_buffer == NULL)&&(ps_dec_state->u1_flushfrm==0))
3124 {
3125 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= 1 << IVD_UNSUPPORTEDPARAM;
3126 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code |= IVD_DEC_FRM_BS_BUF_NULL;
3127 return IV_FAIL;
3128 }
3129
3130
3131 if (ps_dec_state->u4_num_frames_decoded > NUM_FRAMES_LIMIT)
3132 {
3133 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code = IMPEG2D_SAMPLE_VERSION_LIMIT_ERR;
3134 return(IV_FAIL);
3135 }
3136
3137 if(((0 == ps_dec_state->u2_header_done) || (ps_dec_state->u2_decode_header == 1)) && (ps_dec_state->u1_flushfrm == 0))
3138 {
3139 impeg2d_dec_hdr(ps_dec_state,ps_dec_ip ,ps_dec_op);
3140 bytes_remaining -= ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed;
3141 }
3142
3143 if((1 != ps_dec_state->u2_decode_header) &&
3144 (((bytes_remaining > 0) && (1 == ps_dec_state->u2_header_done)) || ps_dec_state->u1_flushfrm))
3145 {
3146 if(ps_dec_state->u1_flushfrm)
3147 {
3148 if(ps_dec_state->aps_ref_pics[1] != NULL)
3149 {
3150 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[1], ps_dec_state->aps_ref_pics[1]->i4_buf_id);
3151 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[1]->i4_buf_id, BUF_MGR_REF);
3152 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3153
3154 ps_dec_state->aps_ref_pics[1] = NULL;
3155 ps_dec_state->aps_ref_pics[0] = NULL;
3156
3157 }
3158 else if(ps_dec_state->aps_ref_pics[0] != NULL)
3159 {
3160 impeg2_disp_mgr_add(&ps_dec_state->s_disp_mgr, ps_dec_state->aps_ref_pics[0], ps_dec_state->aps_ref_pics[0]->i4_buf_id);
3161 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->aps_ref_pics[0]->i4_buf_id, BUF_MGR_REF);
3162
3163 ps_dec_state->aps_ref_pics[0] = NULL;
3164 }
3165 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3166 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3167
3168 ps_disp_pic = impeg2_disp_mgr_get(&ps_dec_state->s_disp_mgr, &ps_dec_state->i4_disp_buf_id);
3169
3170 ps_dec_state->ps_disp_pic = ps_disp_pic;
3171 if(ps_disp_pic == NULL)
3172 {
3173 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3174 }
3175 else
3176 {
3177 WORD32 fmt_conv;
3178 if(0 == ps_dec_state->u4_share_disp_buf)
3179 {
3180 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0];
3181 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1];
3182 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2];
3183 fmt_conv = 1;
3184 }
3185 else
3186 {
3187 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_y_buf = ps_disp_pic->pu1_y;
3188 if(IV_YUV_420P == ps_dec_state->i4_chromaFormat)
3189 {
3190 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = ps_disp_pic->pu1_u;
3191 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = ps_disp_pic->pu1_v;
3192 fmt_conv = 0;
3193 }
3194 else
3195 {
3196 UWORD8 *pu1_buf;
3197
3198 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[1];
3199 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_u_buf = pu1_buf;
3200
3201 pu1_buf = ps_dec_state->as_disp_buffers[ps_disp_pic->i4_buf_id].pu1_bufs[2];
3202 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.pv_v_buf = pu1_buf;
3203 fmt_conv = 1;
3204 }
3205 }
3206
3207 if(fmt_conv == 1)
3208 {
3209 iv_yuv_buf_t *ps_dst;
3210
3211
3212 ps_dst = &(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3213 if(ps_dec_state->u4_deinterlace && (0 == ps_dec_state->u2_progressive_frame))
3214 {
3215 impeg2d_deinterlace(ps_dec_state,
3216 ps_disp_pic,
3217 ps_dst,
3218 0,
3219 ps_dec_state->u2_vertical_size);
3220
3221 }
3222 else
3223 {
3224 impeg2d_format_convert(ps_dec_state,
3225 ps_disp_pic,
3226 ps_dst,
3227 0,
3228 ps_dec_state->u2_vertical_size);
3229 }
3230 }
3231
3232 if(ps_dec_state->u4_deinterlace)
3233 {
3234 if(ps_dec_state->ps_deint_pic)
3235 {
3236 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3237 ps_dec_state->ps_deint_pic->i4_buf_id,
3238 MPEG2_BUF_MGR_DEINT);
3239 }
3240 ps_dec_state->ps_deint_pic = ps_disp_pic;
3241 }
3242 if(0 == ps_dec_state->u4_share_disp_buf)
3243 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3244
3245 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_ht = ps_dec_state->u2_vertical_size;
3246 ps_dec_op->s_ivd_video_decode_op_t.u4_pic_wd = ps_dec_state->u2_horizontal_size;
3247 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3248
3249 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_disp_pic->i4_buf_id;
3250 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_disp_pic->u4_ts;
3251
3252 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3253
3254 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3255
3256 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3257
3258 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3259 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3260 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3261
3262 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1;
3263 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3264 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1;
3265
3266 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1;
3267 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3268 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1;
3269 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3270
3271 switch(ps_dec_state->i4_chromaFormat)
3272 {
3273 case IV_YUV_420SP_UV:
3274 case IV_YUV_420SP_VU:
3275 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size;
3276 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3277 break;
3278 case IV_YUV_422ILE:
3279 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3280 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3281 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3282 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3283 break;
3284 default:
3285 break;
3286 }
3287
3288
3289 }
3290 if(ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3291 {
3292 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3293 {
3294 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3295 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3296 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3297 ps_dec_state->u4_frm_buf_stride,
3298 ps_dec_state->u2_horizontal_size,
3299 ps_dec_state->u2_vertical_size,
3300 ps_dec_state->i4_chromaFormat,
3301 ps_dec_state->u2_horizontal_size,
3302 ps_dec_state->u2_vertical_size);
3303 }
3304 return(IV_SUCCESS);
3305 }
3306 else
3307 {
3308 ps_dec_state->u1_flushfrm = 0;
3309
3310 return(IV_FAIL);
3311 }
3312
3313 }
3314 else if(ps_dec_state->u1_flushfrm==0)
3315 {
3316 ps_dec_ip->s_ivd_video_decode_ip_t.u4_size = sizeof(impeg2d_video_decode_ip_t);
3317 ps_dec_op->s_ivd_video_decode_op_t.u4_size = sizeof(impeg2d_video_decode_op_t);
3318 if(ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes < 4)
3319 {
3320 ps_dec_op->s_ivd_video_decode_op_t.u4_num_bytes_consumed = ps_dec_ip->s_ivd_video_decode_ip_t.u4_num_Bytes;
3321 return(IV_FAIL);
3322 }
3323
3324 if(1 == ps_dec_state->u4_share_disp_buf)
3325 {
3326 if(0 == impeg2_buf_mgr_check_free(ps_dec_state->pv_pic_buf_mg))
3327 {
3328 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code =
3329 (IMPEG2D_ERROR_CODES_T)IVD_DEC_REF_BUF_NULL;
3330 return IV_FAIL;
3331 }
3332 }
3333
3334
3335 ps_dec_op->s_ivd_video_decode_op_t.e_output_format = (IV_COLOR_FORMAT_T)ps_dec_state->i4_chromaFormat;
3336
3337 ps_dec_op->s_ivd_video_decode_op_t.u4_is_ref_flag = (B_PIC != ps_dec_state->e_pic_type);
3338
3339 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = IV_PROGRESSIVE;
3340
3341 if (0 == ps_dec_state->u4_frm_buf_stride)
3342 {
3343 ps_dec_state->u4_frm_buf_stride = (ps_dec_state->u2_horizontal_size);
3344 }
3345
3346 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_wd = ps_dec_state->u2_horizontal_size;
3347 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_strd = ps_dec_state->u4_frm_buf_stride;
3348 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_y_ht = ps_dec_state->u2_vertical_size;
3349
3350 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size >> 1;
3351 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3352 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = ps_dec_state->u2_vertical_size >> 1;
3353
3354 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = ps_dec_state->u2_horizontal_size >> 1;
3355 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_strd = ps_dec_state->u4_frm_buf_stride >> 1;
3356 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = ps_dec_state->u2_vertical_size >> 1;
3357 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_size = sizeof(ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf);
3358
3359 switch(ps_dec_state->i4_chromaFormat)
3360 {
3361 case IV_YUV_420SP_UV:
3362 case IV_YUV_420SP_VU:
3363 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = ps_dec_state->u2_horizontal_size;
3364 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_strd = ps_dec_state->u4_frm_buf_stride;
3365 break;
3366 case IV_YUV_422ILE:
3367 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_wd = 0;
3368 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_u_ht = 0;
3369 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_wd = 0;
3370 ps_dec_op->s_ivd_video_decode_op_t.s_disp_frm_buf.u4_v_ht = 0;
3371 break;
3372 default:
3373 break;
3374 }
3375
3376 if( ps_dec_state->u1_flushfrm == 0)
3377 {
3378 ps_dec_state->u1_flushcnt = 0;
3379
3380 /*************************************************************************/
3381 /* Frame Decode */
3382 /*************************************************************************/
3383
3384 impeg2d_dec_frm(ps_dec_state,ps_dec_ip,ps_dec_op);
3385
3386 if (IVD_ERROR_NONE ==
3387 ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3388 {
3389 if(ps_dec_state->u1_first_frame_done == 0)
3390 {
3391 ps_dec_state->u1_first_frame_done = 1;
3392 }
3393
3394 if(ps_dec_state->ps_disp_pic)
3395 {
3396 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 1;
3397 switch(ps_dec_state->ps_disp_pic->e_pic_type)
3398 {
3399 case I_PIC :
3400 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3401 break;
3402
3403 case P_PIC:
3404 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_P_FRAME;
3405 break;
3406
3407 case B_PIC:
3408 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_B_FRAME;
3409 break;
3410
3411 case D_PIC:
3412 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_I_FRAME;
3413 break;
3414
3415 default :
3416 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_FRAMETYPE_DEFAULT;
3417 break;
3418 }
3419 }
3420 else
3421 {
3422 ps_dec_op->s_ivd_video_decode_op_t.u4_output_present = 0;
3423 ps_dec_op->s_ivd_video_decode_op_t.e_pic_type = IV_NA_FRAME;
3424 }
3425
3426 ps_dec_state->u4_num_frames_decoded++;
3427 }
3428 }
3429 else
3430 {
3431 ps_dec_state->u1_flushcnt++;
3432 }
3433 }
3434 if(ps_dec_state->ps_disp_pic)
3435 {
3436 ps_dec_op->s_ivd_video_decode_op_t.u4_disp_buf_id = ps_dec_state->ps_disp_pic->i4_buf_id;
3437 ps_dec_op->s_ivd_video_decode_op_t.u4_ts = ps_dec_state->ps_disp_pic->u4_ts;
3438
3439 if(0 == ps_dec_state->u4_share_disp_buf)
3440 {
3441 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg, ps_dec_state->ps_disp_pic->i4_buf_id, BUF_MGR_DISP);
3442 }
3443 }
3444
3445 if(ps_dec_state->u4_deinterlace)
3446 {
3447 if(ps_dec_state->ps_deint_pic)
3448 {
3449 impeg2_buf_mgr_release(ps_dec_state->pv_pic_buf_mg,
3450 ps_dec_state->ps_deint_pic->i4_buf_id,
3451 MPEG2_BUF_MGR_DEINT);
3452 }
3453 ps_dec_state->ps_deint_pic = ps_dec_state->ps_disp_pic;
3454 }
3455
3456 if(1 == ps_dec_op->s_ivd_video_decode_op_t.u4_output_present)
3457 {
3458 INSERT_LOGO(ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[0],
3459 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[1],
3460 ps_dec_ip->s_ivd_video_decode_ip_t.s_out_buffer.pu1_bufs[2],
3461 ps_dec_state->u4_frm_buf_stride,
3462 ps_dec_state->u2_horizontal_size,
3463 ps_dec_state->u2_vertical_size,
3464 ps_dec_state->i4_chromaFormat,
3465 ps_dec_state->u2_horizontal_size,
3466 ps_dec_state->u2_vertical_size);
3467 }
3468
3469 }
3470
3471 ps_dec_op->s_ivd_video_decode_op_t.u4_progressive_frame_flag = 1;
3472 ps_dec_op->s_ivd_video_decode_op_t.e4_fld_type = ps_dec_state->s_disp_op.e4_fld_type;
3473
3474
3475 if(ps_dec_op->s_ivd_video_decode_op_t.u4_error_code)
3476 return IV_FAIL;
3477 else
3478 return IV_SUCCESS;
3479 }
3480