1; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s 2; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck -check-prefix=CHECK-SSE %s 3 4; CHECK-NOT: vunpck 5; CHECK: vinsertf128 $1 6define <8 x float> @A(<8 x float> %a) nounwind uwtable readnone ssp { 7entry: 8 %shuffle = shufflevector <8 x float> %a, <8 x float> undef, <8 x i32> <i32 8, i32 8, i32 8, i32 8, i32 0, i32 1, i32 2, i32 3> 9 ret <8 x float> %shuffle 10} 11 12; CHECK-NOT: vunpck 13; CHECK: vinsertf128 $1 14define <4 x double> @B(<4 x double> %a) nounwind uwtable readnone ssp { 15entry: 16 %shuffle = shufflevector <4 x double> %a, <4 x double> undef, <4 x i32> <i32 4, i32 4, i32 0, i32 1> 17 ret <4 x double> %shuffle 18} 19 20declare <2 x double> @llvm.x86.sse2.min.pd(<2 x double>, <2 x double>) nounwind readnone 21 22declare <2 x double> @llvm.x86.sse2.min.sd(<2 x double>, <2 x double>) nounwind readnone 23 24; Just check that no crash happens 25; CHECK-SSE: _insert_crash 26define void @insert_crash() nounwind { 27allocas: 28 %v1.i.i451 = shufflevector <4 x double> zeroinitializer, <4 x double> undef, <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> 29 %ret_0a.i.i.i452 = shufflevector <4 x double> %v1.i.i451, <4 x double> undef, <2 x i32> <i32 0, i32 1> 30 %vret_0.i.i.i454 = tail call <2 x double> @llvm.x86.sse2.min.pd(<2 x double> %ret_0a.i.i.i452, <2 x double> undef) nounwind 31 %ret_val.i.i.i463 = tail call <2 x double> @llvm.x86.sse2.min.sd(<2 x double> %vret_0.i.i.i454, <2 x double> undef) nounwind 32 %ret.i1.i.i464 = extractelement <2 x double> %ret_val.i.i.i463, i32 0 33 %double2float = fptrunc double %ret.i1.i.i464 to float 34 %smearinsert50 = insertelement <4 x float> undef, float %double2float, i32 3 35 %blendAsInt.i503 = bitcast <4 x float> %smearinsert50 to <4 x i32> 36 store <4 x i32> %blendAsInt.i503, <4 x i32>* undef, align 4 37 ret void 38} 39 40;; DAG Combine must remove useless vinsertf128 instructions 41 42; CHECK: DAGCombineA 43; CHECK-NOT: vinsertf128 $1 44define <4 x i32> @DAGCombineA(<4 x i32> %v1) nounwind readonly { 45 %1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 46 %2 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 47 ret <4 x i32> %2 48} 49 50; CHECK: DAGCombineB 51; CHECK: vpaddd %xmm 52; CHECK-NOT: vinsertf128 $1 53; CHECK: vpaddd %xmm 54define <8 x i32> @DAGCombineB(<8 x i32> %v1, <8 x i32> %v2) nounwind readonly { 55 %1 = add <8 x i32> %v1, %v2 56 %2 = add <8 x i32> %1, %v1 57 ret <8 x i32> %2 58} 59