1 #ifdef ALLMULTI
2 #error multicast support is not yet implemented
3 #endif
4 /*
5 DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00
6
7 This driver was ported from Marty Connor's Tulip Etherboot driver.
8 Thanks Marty Connor (mdc@etherboot.org)
9
10 This davicom etherboot driver supports DM9009/DM9102/DM9102A/
11 DM9102A+DM9801/DM9102A+DM9802 NICs.
12
13 This software may be used and distributed according to the terms
14 of the GNU Public License, incorporated herein by reference.
15
16 */
17
18 FILE_LICENCE ( GPL_ANY );
19
20 /*********************************************************************/
21 /* Revision History */
22 /*********************************************************************/
23
24 /*
25 19 OCT 2000 Sten 1.00
26 Different half and full duplex mode
27 Do the different programming for DM9801/DM9802
28
29 12 OCT 2000 Sten 0.90
30 This driver was ported from tulip driver and it
31 has the following difference.
32 Changed symbol tulip/TULIP to davicom/DAVICOM
33 Deleted some code that did not use in this driver.
34 Used chain-strcture to replace ring structure
35 for both TX/RX descriptor.
36 Allocated two tx descriptor.
37 According current media mode to set operating
38 register(CR6)
39 */
40
41
42 /*********************************************************************/
43 /* Declarations */
44 /*********************************************************************/
45
46 #include "etherboot.h"
47 #include "nic.h"
48 #include <gpxe/pci.h>
49 #include <gpxe/ethernet.h>
50
51 #undef DAVICOM_DEBUG
52 #undef DAVICOM_DEBUG_WHERE
53
54 #define TX_TIME_OUT 2*TICKS_PER_SEC
55
56 /* Register offsets for davicom device */
57 enum davicom_offsets {
58 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
59 CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
60 CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
61 };
62
63 /* EEPROM Address width definitions */
64 #define EEPROM_ADDRLEN 6
65 #define EEPROM_SIZE 32 /* 1 << EEPROM_ADDRLEN */
66 /* Used to be 128, but we only need to read enough to get the MAC
67 address at bytes 20..25 */
68
69 /* Data Read from the EEPROM */
70 static unsigned char ee_data[EEPROM_SIZE];
71
72 /* The EEPROM commands include the alway-set leading bit. */
73 #define EE_WRITE_CMD (5 << addr_len)
74 #define EE_READ_CMD (6 << addr_len)
75 #define EE_ERASE_CMD (7 << addr_len)
76
77 /* EEPROM_Ctrl bits. */
78 #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
79 #define EE_CS 0x01 /* EEPROM chip select. */
80 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
81 #define EE_WRITE_0 0x01
82 #define EE_WRITE_1 0x05
83 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
84 #define EE_ENB (0x4800 | EE_CS)
85
86 /* Sten 10/11 for phyxcer */
87 #define PHY_DATA_0 0x0
88 #define PHY_DATA_1 0x20000
89 #define MDCLKH 0x10000
90
91 /* Delay between EEPROM clock transitions. Even at 33Mhz current PCI
92 implementations don't overrun the EEPROM clock. We add a bus
93 turn-around to insure that this remains true. */
94 #define eeprom_delay() inl(ee_addr)
95
96 /* helpful macro if on a big_endian machine for changing byte order.
97 not strictly needed on Intel
98 Already defined in Etherboot includes
99 #define le16_to_cpu(val) (val)
100 */
101
102 /* transmit and receive descriptor format */
103 struct txdesc {
104 volatile unsigned long status; /* owner, status */
105 unsigned long buf1sz:11, /* size of buffer 1 */
106 buf2sz:11, /* size of buffer 2 */
107 control:10; /* control bits */
108 const unsigned char *buf1addr; /* buffer 1 address */
109 const unsigned char *buf2addr; /* buffer 2 address */
110 };
111
112 struct rxdesc {
113 volatile unsigned long status; /* owner, status */
114 unsigned long buf1sz:11, /* size of buffer 1 */
115 buf2sz:11, /* size of buffer 2 */
116 control:10; /* control bits */
117 unsigned char *buf1addr; /* buffer 1 address */
118 unsigned char *buf2addr; /* buffer 2 address */
119 };
120
121 /* Size of transmit and receive buffers */
122 #define BUFLEN 1536
123
124 /*********************************************************************/
125 /* Global Storage */
126 /*********************************************************************/
127
128 static struct nic_operations davicom_operations;
129
130 /* PCI Bus parameters */
131 static unsigned short vendor, dev_id;
132 static unsigned long ioaddr;
133
134 /* Note: transmit and receive buffers must be longword aligned and
135 longword divisable */
136
137 /* transmit descriptor and buffer */
138 #define NTXD 2
139 #define NRXD 4
140 struct {
141 struct txdesc txd[NTXD] __attribute__ ((aligned(4)));
142 unsigned char txb[BUFLEN] __attribute__ ((aligned(4)));
143 struct rxdesc rxd[NRXD] __attribute__ ((aligned(4)));
144 unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4)));
145 } davicom_bufs __shared;
146 #define txd davicom_bufs.txd
147 #define txb davicom_bufs.txb
148 #define rxd davicom_bufs.rxd
149 #define rxb davicom_bufs.rxb
150 static int rxd_tail;
151 static int TxPtr;
152
153
154 /*********************************************************************/
155 /* Function Prototypes */
156 /*********************************************************************/
157 static void whereami(const char *str);
158 static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
159 static int davicom_probe(struct nic *nic,struct pci_device *pci);
160 static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */
161 static void davicom_reset(struct nic *nic);
162 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
163 unsigned int s, const char *p);
164 static int davicom_poll(struct nic *nic, int retrieve);
165 static void davicom_disable(struct nic *nic);
166 #ifdef DAVICOM_DEBUG
167 static void davicom_more(void);
168 #endif /* DAVICOM_DEBUG */
169 static void davicom_wait(unsigned int nticks);
170 static int phy_read(int);
171 static void phy_write(int, u16);
172 static void phy_write_1bit(u32, u32);
173 static int phy_read_1bit(u32);
174 static void davicom_media_chk(struct nic *);
175
176
177 /*********************************************************************/
178 /* Utility Routines */
179 /*********************************************************************/
whereami(const char * str)180 static inline void whereami(const char *str)
181 {
182 printf("%s\n", str);
183 /* sleep(2); */
184 }
185
186 #ifdef DAVICOM_DEBUG
davicom_more()187 static void davicom_more()
188 {
189 printf("\n\n-- more --");
190 while (!iskey())
191 /* wait */;
192 getchar();
193 printf("\n\n");
194 }
195 #endif /* DAVICOM_DEBUG */
196
davicom_wait(unsigned int nticks)197 static void davicom_wait(unsigned int nticks)
198 {
199 unsigned int to = currticks() + nticks;
200 while (currticks() < to)
201 /* wait */ ;
202 }
203
204
205 /*********************************************************************/
206 /* For DAVICOM phyxcer register by MII interface */
207 /*********************************************************************/
208 /*
209 Read a word data from phy register
210 */
phy_read(int location)211 static int phy_read(int location)
212 {
213 int i, phy_addr=1;
214 u16 phy_data;
215 u32 io_dcr9;
216
217 whereami("phy_read\n");
218
219 io_dcr9 = ioaddr + CSR9;
220
221 /* Send 33 synchronization clock to Phy controller */
222 for (i=0; i<34; i++)
223 phy_write_1bit(io_dcr9, PHY_DATA_1);
224
225 /* Send start command(01) to Phy */
226 phy_write_1bit(io_dcr9, PHY_DATA_0);
227 phy_write_1bit(io_dcr9, PHY_DATA_1);
228
229 /* Send read command(10) to Phy */
230 phy_write_1bit(io_dcr9, PHY_DATA_1);
231 phy_write_1bit(io_dcr9, PHY_DATA_0);
232
233 /* Send Phy addres */
234 for (i=0x10; i>0; i=i>>1)
235 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
236
237 /* Send register addres */
238 for (i=0x10; i>0; i=i>>1)
239 phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
240
241 /* Skip transition state */
242 phy_read_1bit(io_dcr9);
243
244 /* read 16bit data */
245 for (phy_data=0, i=0; i<16; i++) {
246 phy_data<<=1;
247 phy_data|=phy_read_1bit(io_dcr9);
248 }
249
250 return phy_data;
251 }
252
253 /*
254 Write a word to Phy register
255 */
phy_write(int location,u16 phy_data)256 static void phy_write(int location, u16 phy_data)
257 {
258 u16 i, phy_addr=1;
259 u32 io_dcr9;
260
261 whereami("phy_write\n");
262
263 io_dcr9 = ioaddr + CSR9;
264
265 /* Send 33 synchronization clock to Phy controller */
266 for (i=0; i<34; i++)
267 phy_write_1bit(io_dcr9, PHY_DATA_1);
268
269 /* Send start command(01) to Phy */
270 phy_write_1bit(io_dcr9, PHY_DATA_0);
271 phy_write_1bit(io_dcr9, PHY_DATA_1);
272
273 /* Send write command(01) to Phy */
274 phy_write_1bit(io_dcr9, PHY_DATA_0);
275 phy_write_1bit(io_dcr9, PHY_DATA_1);
276
277 /* Send Phy addres */
278 for (i=0x10; i>0; i=i>>1)
279 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0);
280
281 /* Send register addres */
282 for (i=0x10; i>0; i=i>>1)
283 phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0);
284
285 /* written trasnition */
286 phy_write_1bit(io_dcr9, PHY_DATA_1);
287 phy_write_1bit(io_dcr9, PHY_DATA_0);
288
289 /* Write a word data to PHY controller */
290 for (i=0x8000; i>0; i>>=1)
291 phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0);
292 }
293
294 /*
295 Write one bit data to Phy Controller
296 */
phy_write_1bit(u32 ee_addr,u32 phy_data)297 static void phy_write_1bit(u32 ee_addr, u32 phy_data)
298 {
299 whereami("phy_write_1bit\n");
300 outl(phy_data, ee_addr); /* MII Clock Low */
301 eeprom_delay();
302 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */
303 eeprom_delay();
304 outl(phy_data, ee_addr); /* MII Clock Low */
305 eeprom_delay();
306 }
307
308 /*
309 Read one bit phy data from PHY controller
310 */
phy_read_1bit(u32 ee_addr)311 static int phy_read_1bit(u32 ee_addr)
312 {
313 int phy_data;
314
315 whereami("phy_read_1bit\n");
316
317 outl(0x50000, ee_addr);
318 eeprom_delay();
319
320 phy_data=(inl(ee_addr)>>19) & 0x1;
321
322 outl(0x40000, ee_addr);
323 eeprom_delay();
324
325 return phy_data;
326 }
327
328 /*
329 DM9801/DM9802 present check and program
330 */
HPNA_process(void)331 static void HPNA_process(void)
332 {
333
334 if ( (phy_read(3) & 0xfff0) == 0xb900 ) {
335 if ( phy_read(31) == 0x4404 ) {
336 /* DM9801 present */
337 if (phy_read(3) == 0xb901)
338 phy_write(16, 0x5); /* DM9801 E4 */
339 else
340 phy_write(16, 0x1005); /* DM9801 E3 and others */
341 phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000);
342 } else {
343 /* DM9802 present */
344 phy_write(16, 0x5);
345 phy_write(25, (phy_read(25) & 0xff00) + 2);
346 }
347 }
348 }
349
350 /*
351 Sense media mode and set CR6
352 */
davicom_media_chk(struct nic * nic __unused)353 static void davicom_media_chk(struct nic * nic __unused)
354 {
355 unsigned long to, csr6;
356
357 csr6 = 0x00200000; /* SF */
358 outl(csr6, ioaddr + CSR6);
359
360 #define PCI_DEVICE_ID_DM9009 0x9009
361 if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) {
362 /* Set to 10BaseT mode for DM9009 */
363 phy_write(0, 0);
364 } else {
365 /* For DM9102/DM9102A */
366 to = currticks() + 2 * TICKS_PER_SEC;
367 while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to))
368 /* wait */ ;
369
370 if ( (phy_read(1) & 0x24) == 0x24 ) {
371 if (phy_read(17) & 0xa000)
372 csr6 |= 0x00000200; /* Full Duplex mode */
373 } else
374 csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */
375 }
376
377 /* set the chip's operating mode */
378 outl(csr6, ioaddr + CSR6);
379
380 /* DM9801/DM9802 present check & program */
381 if (csr6 & 0x40000)
382 HPNA_process();
383 }
384
385
386 /*********************************************************************/
387 /* EEPROM Reading Code */
388 /*********************************************************************/
389 /* EEPROM routines adapted from the Linux Tulip Code */
390 /* Reading a serial EEPROM is a "bit" grungy, but we work our way
391 through:->.
392 */
read_eeprom(unsigned long ioaddr,int location,int addr_len)393 static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
394 {
395 int i;
396 unsigned short retval = 0;
397 long ee_addr = ioaddr + CSR9;
398 int read_cmd = location | EE_READ_CMD;
399
400 whereami("read_eeprom\n");
401
402 outl(EE_ENB & ~EE_CS, ee_addr);
403 outl(EE_ENB, ee_addr);
404
405 /* Shift the read command bits out. */
406 for (i = 4 + addr_len; i >= 0; i--) {
407 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
408 outl(EE_ENB | dataval, ee_addr);
409 eeprom_delay();
410 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
411 eeprom_delay();
412 }
413 outl(EE_ENB, ee_addr);
414
415 for (i = 16; i > 0; i--) {
416 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
417 eeprom_delay();
418 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
419 outl(EE_ENB, ee_addr);
420 eeprom_delay();
421 }
422
423 /* Terminate the EEPROM access. */
424 outl(EE_ENB & ~EE_CS, ee_addr);
425 return retval;
426 }
427
428 /*********************************************************************/
429 /* davicom_init_chain - setup the tx and rx descriptors */
430 /* Sten 10/9 */
431 /*********************************************************************/
davicom_init_chain(struct nic * nic)432 static void davicom_init_chain(struct nic *nic)
433 {
434 int i;
435
436 /* setup the transmit descriptor */
437 /* Sten: Set 2 TX descriptor but use one TX buffer because
438 it transmit a packet and wait complete every time. */
439 for (i=0; i<NTXD; i++) {
440 txd[i].buf1addr = (void *)virt_to_bus(&txb[0]); /* Used same TX buffer */
441 txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]); /* Point to Next TX desc */
442 txd[i].buf1sz = 0;
443 txd[i].buf2sz = 0;
444 txd[i].control = 0x184; /* Begin/End/Chain */
445 txd[i].status = 0x00000000; /* give ownership to Host */
446 }
447
448 /* construct perfect filter frame with mac address as first match
449 and broadcast address for all others */
450 for (i=0; i<192; i++) txb[i] = 0xFF;
451 txb[0] = nic->node_addr[0];
452 txb[1] = nic->node_addr[1];
453 txb[4] = nic->node_addr[2];
454 txb[5] = nic->node_addr[3];
455 txb[8] = nic->node_addr[4];
456 txb[9] = nic->node_addr[5];
457
458 /* setup receive descriptor */
459 for (i=0; i<NRXD; i++) {
460 rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]);
461 rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */
462 rxd[i].buf1sz = BUFLEN;
463 rxd[i].buf2sz = 0; /* not used */
464 rxd[i].control = 0x4; /* Chain Structure */
465 rxd[i].status = 0x80000000; /* give ownership to device */
466 }
467
468 /* Chain the last descriptor to first */
469 txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]);
470 rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]);
471 TxPtr = 0;
472 rxd_tail = 0;
473 }
474
475
476 /*********************************************************************/
477 /* davicom_reset - Reset adapter */
478 /*********************************************************************/
davicom_reset(struct nic * nic)479 static void davicom_reset(struct nic *nic)
480 {
481 unsigned long to;
482
483 whereami("davicom_reset\n");
484
485 /* Stop Tx and RX */
486 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
487
488 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
489 outl(0x00000001, ioaddr + CSR0);
490
491 davicom_wait(TICKS_PER_SEC);
492
493 /* TX/RX descriptor burst */
494 outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */
495
496 /* set up transmit and receive descriptors */
497 davicom_init_chain(nic); /* Sten 10/9 */
498
499 /* Point to receive descriptor */
500 outl(virt_to_bus(&rxd[0]), ioaddr + CSR3);
501 outl(virt_to_bus(&txd[0]), ioaddr + CSR4); /* Sten 10/9 */
502
503 /* According phyxcer media mode to set CR6,
504 DM9102/A phyxcer can auto-detect media mode */
505 davicom_media_chk(nic);
506
507 /* Prepare Setup Frame Sten 10/9 */
508 txd[TxPtr].buf1sz = 192;
509 txd[TxPtr].control = 0x024; /* SF/CE */
510 txd[TxPtr].status = 0x80000000; /* Give ownership to device */
511
512 /* Start Tx */
513 outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6);
514 /* immediate transmit demand */
515 outl(0, ioaddr + CSR1);
516
517 to = currticks() + TX_TIME_OUT;
518 while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */
519 /* wait */ ;
520
521 if (currticks() >= to) {
522 printf ("TX Setup Timeout!\n");
523 }
524 /* Point to next TX descriptor */
525 TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
526
527 #ifdef DAVICOM_DEBUG
528 printf("txd.status = %X\n", txd.status);
529 printf("ticks = %d\n", currticks() - (to - TX_TIME_OUT));
530 davicom_more();
531 #endif
532
533 /* enable RX */
534 outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6);
535 /* immediate poll demand */
536 outl(0, ioaddr + CSR2);
537 }
538
539
540 /*********************************************************************/
541 /* eth_transmit - Transmit a frame */
542 /*********************************************************************/
davicom_transmit(struct nic * nic,const char * d,unsigned int t,unsigned int s,const char * p)543 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t,
544 unsigned int s, const char *p)
545 {
546 unsigned long to;
547
548 whereami("davicom_transmit\n");
549
550 /* Stop Tx */
551 /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */
552
553 /* setup ethernet header */
554 memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */
555 memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/
556 txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */
557 txb[ETH_ALEN*2+1] = t & 0xFF;
558 memcpy(&txb[ETH_HLEN], p, s); /* Frame data */
559
560 /* setup the transmit descriptor */
561 txd[TxPtr].buf1sz = ETH_HLEN+s;
562 txd[TxPtr].control = 0x00000184; /* LS+FS+CE */
563 txd[TxPtr].status = 0x80000000; /* give ownership to device */
564
565 /* immediate transmit demand */
566 outl(0, ioaddr + CSR1);
567
568 to = currticks() + TX_TIME_OUT;
569 while ((txd[TxPtr].status & 0x80000000) && (currticks() < to))
570 /* wait */ ;
571
572 if (currticks() >= to) {
573 printf ("TX Timeout!\n");
574 }
575
576 /* Point to next TX descriptor */
577 TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */
578
579 }
580
581 /*********************************************************************/
582 /* eth_poll - Wait for a frame */
583 /*********************************************************************/
davicom_poll(struct nic * nic,int retrieve)584 static int davicom_poll(struct nic *nic, int retrieve)
585 {
586 whereami("davicom_poll\n");
587
588 if (rxd[rxd_tail].status & 0x80000000)
589 return 0;
590
591 if ( ! retrieve ) return 1;
592
593 whereami("davicom_poll got one\n");
594
595 nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16;
596
597 if( rxd[rxd_tail].status & 0x00008000){
598 rxd[rxd_tail].status = 0x80000000;
599 rxd_tail++;
600 if (rxd_tail == NRXD) rxd_tail = 0;
601 return 0;
602 }
603
604 /* copy packet to working buffer */
605 /* XXX - this copy could be avoided with a little more work
606 but for now we are content with it because the optimised
607 memcpy is quite fast */
608
609 memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen);
610
611 /* return the descriptor and buffer to receive ring */
612 rxd[rxd_tail].status = 0x80000000;
613 rxd_tail++;
614 if (rxd_tail == NRXD) rxd_tail = 0;
615
616 return 1;
617 }
618
619 /*********************************************************************/
620 /* eth_disable - Disable the interface */
621 /*********************************************************************/
davicom_disable(struct nic * nic)622 static void davicom_disable ( struct nic *nic ) {
623
624 whereami("davicom_disable\n");
625
626 davicom_reset(nic);
627
628 /* disable interrupts */
629 outl(0x00000000, ioaddr + CSR7);
630
631 /* Stop the chip's Tx and Rx processes. */
632 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
633
634 /* Clear the missed-packet counter. */
635 inl(ioaddr + CSR8);
636 }
637
638
639 /*********************************************************************/
640 /* eth_irq - enable, disable and force interrupts */
641 /*********************************************************************/
davicom_irq(struct nic * nic __unused,irq_action_t action __unused)642 static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused)
643 {
644 switch ( action ) {
645 case DISABLE :
646 break;
647 case ENABLE :
648 break;
649 case FORCE :
650 break;
651 }
652 }
653
654
655 /*********************************************************************/
656 /* eth_probe - Look for an adapter */
657 /*********************************************************************/
davicom_probe(struct nic * nic,struct pci_device * pci)658 static int davicom_probe ( struct nic *nic, struct pci_device *pci ) {
659
660 unsigned int i;
661
662 whereami("davicom_probe\n");
663
664 if (pci->ioaddr == 0)
665 return 0;
666
667 vendor = pci->vendor;
668 dev_id = pci->device;
669 ioaddr = pci->ioaddr;
670
671 nic->ioaddr = pci->ioaddr;
672 nic->irqno = 0;
673
674 /* wakeup chip */
675 pci_write_config_dword(pci, 0x40, 0x00000000);
676
677 /* Stop the chip's Tx and Rx processes. */
678 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
679
680 /* Clear the missed-packet counter. */
681 inl(ioaddr + CSR8);
682
683 /* Get MAC Address */
684 /* read EEPROM data */
685 for (i = 0; i < sizeof(ee_data)/2; i++)
686 ((unsigned short *)ee_data)[i] =
687 le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN));
688
689 /* extract MAC address from EEPROM buffer */
690 for (i=0; i<ETH_ALEN; i++)
691 nic->node_addr[i] = ee_data[20+i];
692
693 DBG ( "Davicom %s at IOADDR %4.4lx\n", eth_ntoa ( nic->node_addr ), ioaddr );
694
695 /* initialize device */
696 davicom_reset(nic);
697 nic->nic_op = &davicom_operations;
698 return 1;
699 }
700
701 static struct nic_operations davicom_operations = {
702 .connect = dummy_connect,
703 .poll = davicom_poll,
704 .transmit = davicom_transmit,
705 .irq = davicom_irq,
706
707 };
708
709 static struct pci_device_id davicom_nics[] = {
710 PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100", 0),
711 PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102", 0),
712 PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009", 0),
713 PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132", 0), /* Needs probably some fixing */
714 };
715
716 PCI_DRIVER ( davicom_driver, davicom_nics, PCI_NO_CLASS );
717
718 DRIVER ( "DAVICOM", nic_driver, pci_driver, davicom_driver,
719 davicom_probe, davicom_disable );
720
721 /*
722 * Local variables:
723 * c-basic-offset: 8
724 * c-indent-level: 8
725 * tab-width: 8
726 * End:
727 */
728