1 #objdump: -dr --prefix-addresses --show-raw-insn 2 #name: MIPS ALNV.PS instruction branch swapping 3 #as: -32 4 #source: alnv_ps-swap.s 5 6 # Check that a register dependency between ALNV.PS and the following 7 # branch prevents from branch swapping (microMIPS). 8 9 .*: +file format .*mips.* 10 11 Disassembly of section \.text: 12 ([0-9a-f]+) <[^>]*> cfff b \1 <foo> 13 [ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 foo 14 [0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1 15 ([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <foo\+0x[0-9a-f]+> 16 [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo 17 [0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1 18 ([0-9a-f]+) <[^>]*> 4023 fffe bltzal v1,\1 <foo\+0x[0-9a-f]+> 19 [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo 20 [0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1 21 [0-9a-f]+ <[^>]*> 45c3 jalr v1 22 [0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1 23 [0-9a-f]+ <[^>]*> 0083 0f3c jalr a0,v1 24 [0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1 25 [0-9a-f]+ <[^>]*> 5402 20d9 alnv\.ps \$f4,\$f2,\$f0,v1 26 [0-9a-f]+ <[^>]*> 007f 0f3c jalr v1,ra 27 [0-9a-f]+ <[^>]*> 0000 0000 nop 28 ([0-9a-f]+) <[^>]*> cfff b \1 <foo\+0x[0-9a-f]+> 29 [ ]*[0-9a-f]+: R_MICROMIPS_PC10_S1 foo 30 [0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra 31 [0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra 32 ([0-9a-f]+) <[^>]*> 4060 fffe bal \1 <foo\+0x[0-9a-f]+> 33 [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo 34 [0-9a-f]+ <[^>]*> 0000 0000 nop 35 [0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra 36 ([0-9a-f]+) <[^>]*> 4023 fffe bltzal v1,\1 <foo\+0x[0-9a-f]+> 37 [ ]*[0-9a-f]+: R_MICROMIPS_PC16_S1 foo 38 [0-9a-f]+ <[^>]*> 0000 0000 nop 39 [0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra 40 [0-9a-f]+ <[^>]*> 45c3 jalr v1 41 [0-9a-f]+ <[^>]*> 0000 0000 nop 42 [0-9a-f]+ <[^>]*> 0083 0f3c jalr a0,v1 43 [0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra 44 [0-9a-f]+ <[^>]*> 007f 0f3c jalr v1,ra 45 [0-9a-f]+ <[^>]*> 5402 27d9 alnv\.ps \$f4,\$f2,\$f0,ra 46 \.\.\. 47