Lines Matching refs:shamt
335 int shamt, in EmitR() argument
344 shamt << kShamtShift | in EmitR()
711 void MipsAssembler::Sll(Register rd, Register rt, int shamt) { in Sll() argument
712 CHECK(IsUint<5>(shamt)) << shamt; in Sll()
713 DsFsmInstrRrr(EmitR(0, static_cast<Register>(0), rt, rd, shamt, 0x00), rd, rt, rt); in Sll()
716 void MipsAssembler::Srl(Register rd, Register rt, int shamt) { in Srl() argument
717 CHECK(IsUint<5>(shamt)) << shamt; in Srl()
718 DsFsmInstrRrr(EmitR(0, static_cast<Register>(0), rt, rd, shamt, 0x02), rd, rt, rt); in Srl()
721 void MipsAssembler::Rotr(Register rd, Register rt, int shamt) { in Rotr() argument
722 CHECK(IsUint<5>(shamt)) << shamt; in Rotr()
723 DsFsmInstrRrr(EmitR(0, static_cast<Register>(1), rt, rd, shamt, 0x02), rd, rt, rt); in Rotr()
726 void MipsAssembler::Sra(Register rd, Register rt, int shamt) { in Sra() argument
727 CHECK(IsUint<5>(shamt)) << shamt; in Sra()
728 DsFsmInstrRrr(EmitR(0, static_cast<Register>(0), rt, rd, shamt, 0x03), rd, rt, rt); in Sra()
771 int shamt, in ShiftAndAdd() argument
773 CHECK(0 <= shamt && shamt <= 4) << shamt; in ShiftAndAdd()
775 if (shamt == TIMES_1) { in ShiftAndAdd()
779 Lsa(dst, src_idx, src_base, shamt); in ShiftAndAdd()
781 Sll(tmp, src_idx, shamt); in ShiftAndAdd()