Lines Matching refs:InVec

6 define <8 x i16> @test_sllw_1(<8 x i16> %InVec) {
11   %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
15 define <8 x i16> @test_sllw_2(<8 x i16> %InVec) {
21   %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
25 define <8 x i16> @test_sllw_3(<8 x i16> %InVec) {
31   %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
35 define <4 x i32> @test_slld_1(<4 x i32> %InVec) {
40   %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
44 define <4 x i32> @test_slld_2(<4 x i32> %InVec) {
50   %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
54 define <4 x i32> @test_slld_3(<4 x i32> %InVec) {
60   %shl = shl <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
64 define <2 x i64> @test_sllq_1(<2 x i64> %InVec) {
69   %shl = shl <2 x i64> %InVec, <i64 0, i64 0>
73 define <2 x i64> @test_sllq_2(<2 x i64> %InVec) {
79   %shl = shl <2 x i64> %InVec, <i64 1, i64 1>
83 define <2 x i64> @test_sllq_3(<2 x i64> %InVec) {
89   %shl = shl <2 x i64> %InVec, <i64 63, i64 63>
95 define <8 x i16> @test_sraw_1(<8 x i16> %InVec) {
100   %shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
104 define <8 x i16> @test_sraw_2(<8 x i16> %InVec) {
110   %shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
114 define <8 x i16> @test_sraw_3(<8 x i16> %InVec) {
120   %shl = ashr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
124 define <4 x i32> @test_srad_1(<4 x i32> %InVec) {
129   %shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
133 define <4 x i32> @test_srad_2(<4 x i32> %InVec) {
139   %shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
143 define <4 x i32> @test_srad_3(<4 x i32> %InVec) {
149   %shl = ashr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
155 define <8 x i16> @test_srlw_1(<8 x i16> %InVec) {
160   %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
164 define <8 x i16> @test_srlw_2(<8 x i16> %InVec) {
170   %shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
174 define <8 x i16> @test_srlw_3(<8 x i16> %InVec) {
180   %shl = lshr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>
184 define <4 x i32> @test_srld_1(<4 x i32> %InVec) {
189   %shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0>
193 define <4 x i32> @test_srld_2(<4 x i32> %InVec) {
199   %shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1>
203 define <4 x i32> @test_srld_3(<4 x i32> %InVec) {
209   %shl = lshr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31>
213 define <2 x i64> @test_srlq_1(<2 x i64> %InVec) {
218   %shl = lshr <2 x i64> %InVec, <i64 0, i64 0>
222 define <2 x i64> @test_srlq_2(<2 x i64> %InVec) {
228   %shl = lshr <2 x i64> %InVec, <i64 1, i64 1>
232 define <2 x i64> @test_srlq_3(<2 x i64> %InVec) {
238   %shl = lshr <2 x i64> %InVec, <i64 63, i64 63>