1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: llc < %s -mtriple=x86_64-pc-linux -mattr=+sse2 | FileCheck %s 3 4; SSE2 Logical Shift Left 5 6define <8 x i16> @test_sllw_1(<8 x i16> %InVec) { 7; CHECK-LABEL: test_sllw_1: 8; CHECK: # BB#0: # %entry 9; CHECK-NEXT: retq 10entry: 11 %shl = shl <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 12 ret <8 x i16> %shl 13} 14 15define <8 x i16> @test_sllw_2(<8 x i16> %InVec) { 16; CHECK-LABEL: test_sllw_2: 17; CHECK: # BB#0: # %entry 18; CHECK-NEXT: paddw %xmm0, %xmm0 19; CHECK-NEXT: retq 20entry: 21 %shl = shl <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 22 ret <8 x i16> %shl 23} 24 25define <8 x i16> @test_sllw_3(<8 x i16> %InVec) { 26; CHECK-LABEL: test_sllw_3: 27; CHECK: # BB#0: # %entry 28; CHECK-NEXT: psllw $15, %xmm0 29; CHECK-NEXT: retq 30entry: 31 %shl = shl <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 32 ret <8 x i16> %shl 33} 34 35define <4 x i32> @test_slld_1(<4 x i32> %InVec) { 36; CHECK-LABEL: test_slld_1: 37; CHECK: # BB#0: # %entry 38; CHECK-NEXT: retq 39entry: 40 %shl = shl <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0> 41 ret <4 x i32> %shl 42} 43 44define <4 x i32> @test_slld_2(<4 x i32> %InVec) { 45; CHECK-LABEL: test_slld_2: 46; CHECK: # BB#0: # %entry 47; CHECK-NEXT: paddd %xmm0, %xmm0 48; CHECK-NEXT: retq 49entry: 50 %shl = shl <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1> 51 ret <4 x i32> %shl 52} 53 54define <4 x i32> @test_slld_3(<4 x i32> %InVec) { 55; CHECK-LABEL: test_slld_3: 56; CHECK: # BB#0: # %entry 57; CHECK-NEXT: pslld $31, %xmm0 58; CHECK-NEXT: retq 59entry: 60 %shl = shl <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31> 61 ret <4 x i32> %shl 62} 63 64define <2 x i64> @test_sllq_1(<2 x i64> %InVec) { 65; CHECK-LABEL: test_sllq_1: 66; CHECK: # BB#0: # %entry 67; CHECK-NEXT: retq 68entry: 69 %shl = shl <2 x i64> %InVec, <i64 0, i64 0> 70 ret <2 x i64> %shl 71} 72 73define <2 x i64> @test_sllq_2(<2 x i64> %InVec) { 74; CHECK-LABEL: test_sllq_2: 75; CHECK: # BB#0: # %entry 76; CHECK-NEXT: paddq %xmm0, %xmm0 77; CHECK-NEXT: retq 78entry: 79 %shl = shl <2 x i64> %InVec, <i64 1, i64 1> 80 ret <2 x i64> %shl 81} 82 83define <2 x i64> @test_sllq_3(<2 x i64> %InVec) { 84; CHECK-LABEL: test_sllq_3: 85; CHECK: # BB#0: # %entry 86; CHECK-NEXT: psllq $63, %xmm0 87; CHECK-NEXT: retq 88entry: 89 %shl = shl <2 x i64> %InVec, <i64 63, i64 63> 90 ret <2 x i64> %shl 91} 92 93; SSE2 Arithmetic Shift 94 95define <8 x i16> @test_sraw_1(<8 x i16> %InVec) { 96; CHECK-LABEL: test_sraw_1: 97; CHECK: # BB#0: # %entry 98; CHECK-NEXT: retq 99entry: 100 %shl = ashr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 101 ret <8 x i16> %shl 102} 103 104define <8 x i16> @test_sraw_2(<8 x i16> %InVec) { 105; CHECK-LABEL: test_sraw_2: 106; CHECK: # BB#0: # %entry 107; CHECK-NEXT: psraw $1, %xmm0 108; CHECK-NEXT: retq 109entry: 110 %shl = ashr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 111 ret <8 x i16> %shl 112} 113 114define <8 x i16> @test_sraw_3(<8 x i16> %InVec) { 115; CHECK-LABEL: test_sraw_3: 116; CHECK: # BB#0: # %entry 117; CHECK-NEXT: psraw $15, %xmm0 118; CHECK-NEXT: retq 119entry: 120 %shl = ashr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 121 ret <8 x i16> %shl 122} 123 124define <4 x i32> @test_srad_1(<4 x i32> %InVec) { 125; CHECK-LABEL: test_srad_1: 126; CHECK: # BB#0: # %entry 127; CHECK-NEXT: retq 128entry: 129 %shl = ashr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0> 130 ret <4 x i32> %shl 131} 132 133define <4 x i32> @test_srad_2(<4 x i32> %InVec) { 134; CHECK-LABEL: test_srad_2: 135; CHECK: # BB#0: # %entry 136; CHECK-NEXT: psrad $1, %xmm0 137; CHECK-NEXT: retq 138entry: 139 %shl = ashr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1> 140 ret <4 x i32> %shl 141} 142 143define <4 x i32> @test_srad_3(<4 x i32> %InVec) { 144; CHECK-LABEL: test_srad_3: 145; CHECK: # BB#0: # %entry 146; CHECK-NEXT: psrad $31, %xmm0 147; CHECK-NEXT: retq 148entry: 149 %shl = ashr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31> 150 ret <4 x i32> %shl 151} 152 153; SSE Logical Shift Right 154 155define <8 x i16> @test_srlw_1(<8 x i16> %InVec) { 156; CHECK-LABEL: test_srlw_1: 157; CHECK: # BB#0: # %entry 158; CHECK-NEXT: retq 159entry: 160 %shl = lshr <8 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0> 161 ret <8 x i16> %shl 162} 163 164define <8 x i16> @test_srlw_2(<8 x i16> %InVec) { 165; CHECK-LABEL: test_srlw_2: 166; CHECK: # BB#0: # %entry 167; CHECK-NEXT: psrlw $1, %xmm0 168; CHECK-NEXT: retq 169entry: 170 %shl = lshr <8 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1> 171 ret <8 x i16> %shl 172} 173 174define <8 x i16> @test_srlw_3(<8 x i16> %InVec) { 175; CHECK-LABEL: test_srlw_3: 176; CHECK: # BB#0: # %entry 177; CHECK-NEXT: psrlw $15, %xmm0 178; CHECK-NEXT: retq 179entry: 180 %shl = lshr <8 x i16> %InVec, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15> 181 ret <8 x i16> %shl 182} 183 184define <4 x i32> @test_srld_1(<4 x i32> %InVec) { 185; CHECK-LABEL: test_srld_1: 186; CHECK: # BB#0: # %entry 187; CHECK-NEXT: retq 188entry: 189 %shl = lshr <4 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0> 190 ret <4 x i32> %shl 191} 192 193define <4 x i32> @test_srld_2(<4 x i32> %InVec) { 194; CHECK-LABEL: test_srld_2: 195; CHECK: # BB#0: # %entry 196; CHECK-NEXT: psrld $1, %xmm0 197; CHECK-NEXT: retq 198entry: 199 %shl = lshr <4 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1> 200 ret <4 x i32> %shl 201} 202 203define <4 x i32> @test_srld_3(<4 x i32> %InVec) { 204; CHECK-LABEL: test_srld_3: 205; CHECK: # BB#0: # %entry 206; CHECK-NEXT: psrld $31, %xmm0 207; CHECK-NEXT: retq 208entry: 209 %shl = lshr <4 x i32> %InVec, <i32 31, i32 31, i32 31, i32 31> 210 ret <4 x i32> %shl 211} 212 213define <2 x i64> @test_srlq_1(<2 x i64> %InVec) { 214; CHECK-LABEL: test_srlq_1: 215; CHECK: # BB#0: # %entry 216; CHECK-NEXT: retq 217entry: 218 %shl = lshr <2 x i64> %InVec, <i64 0, i64 0> 219 ret <2 x i64> %shl 220} 221 222define <2 x i64> @test_srlq_2(<2 x i64> %InVec) { 223; CHECK-LABEL: test_srlq_2: 224; CHECK: # BB#0: # %entry 225; CHECK-NEXT: psrlq $1, %xmm0 226; CHECK-NEXT: retq 227entry: 228 %shl = lshr <2 x i64> %InVec, <i64 1, i64 1> 229 ret <2 x i64> %shl 230} 231 232define <2 x i64> @test_srlq_3(<2 x i64> %InVec) { 233; CHECK-LABEL: test_srlq_3: 234; CHECK: # BB#0: # %entry 235; CHECK-NEXT: psrlq $63, %xmm0 236; CHECK-NEXT: retq 237entry: 238 %shl = lshr <2 x i64> %InVec, <i64 63, i64 63> 239 ret <2 x i64> %shl 240} 241 242define <4 x i32> @sra_sra_v4i32(<4 x i32> %x) nounwind { 243; CHECK-LABEL: sra_sra_v4i32: 244; CHECK: # BB#0: 245; CHECK-NEXT: psrad $6, %xmm0 246; CHECK-NEXT: retq 247 %sra0 = ashr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2> 248 %sra1 = ashr <4 x i32> %sra0, <i32 4, i32 4, i32 4, i32 4> 249 ret <4 x i32> %sra1 250} 251 252define <4 x i32> @srl_srl_v4i32(<4 x i32> %x) nounwind { 253; CHECK-LABEL: srl_srl_v4i32: 254; CHECK: # BB#0: 255; CHECK-NEXT: psrld $6, %xmm0 256; CHECK-NEXT: retq 257 %srl0 = lshr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2> 258 %srl1 = lshr <4 x i32> %srl0, <i32 4, i32 4, i32 4, i32 4> 259 ret <4 x i32> %srl1 260} 261 262define <4 x i32> @srl_shl_v4i32(<4 x i32> %x) nounwind { 263; CHECK-LABEL: srl_shl_v4i32: 264; CHECK: # BB#0: 265; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 266; CHECK-NEXT: retq 267 %srl0 = shl <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4> 268 %srl1 = lshr <4 x i32> %srl0, <i32 4, i32 4, i32 4, i32 4> 269 ret <4 x i32> %srl1 270} 271 272define <4 x i32> @srl_sra_31_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { 273; CHECK-LABEL: srl_sra_31_v4i32: 274; CHECK: # BB#0: 275; CHECK-NEXT: psrld $31, %xmm0 276; CHECK-NEXT: retq 277 %sra = ashr <4 x i32> %x, %y 278 %srl1 = lshr <4 x i32> %sra, <i32 31, i32 31, i32 31, i32 31> 279 ret <4 x i32> %srl1 280} 281 282define <4 x i32> @shl_shl_v4i32(<4 x i32> %x) nounwind { 283; CHECK-LABEL: shl_shl_v4i32: 284; CHECK: # BB#0: 285; CHECK-NEXT: pslld $6, %xmm0 286; CHECK-NEXT: retq 287 %shl0 = shl <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2> 288 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4> 289 ret <4 x i32> %shl1 290} 291 292define <4 x i32> @shl_sra_v4i32(<4 x i32> %x) nounwind { 293; CHECK-LABEL: shl_sra_v4i32: 294; CHECK: # BB#0: 295; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 296; CHECK-NEXT: retq 297 %shl0 = ashr <4 x i32> %x, <i32 4, i32 4, i32 4, i32 4> 298 %shl1 = shl <4 x i32> %shl0, <i32 4, i32 4, i32 4, i32 4> 299 ret <4 x i32> %shl1 300} 301 302define <4 x i32> @shl_srl_v4i32(<4 x i32> %x) nounwind { 303; CHECK-LABEL: shl_srl_v4i32: 304; CHECK: # BB#0: 305; CHECK-NEXT: pslld $3, %xmm0 306; CHECK-NEXT: pand {{.*}}(%rip), %xmm0 307; CHECK-NEXT: retq 308 %shl0 = lshr <4 x i32> %x, <i32 2, i32 2, i32 2, i32 2> 309 %shl1 = shl <4 x i32> %shl0, <i32 5, i32 5, i32 5, i32 5> 310 ret <4 x i32> %shl1 311} 312 313define <4 x i32> @shl_zext_srl_v4i32(<4 x i16> %x) nounwind { 314; CHECK-LABEL: shl_zext_srl_v4i32: 315; CHECK: # BB#0: 316; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 317; CHECK-NEXT: andps {{.*}}(%rip), %xmm0 318; CHECK-NEXT: retq 319 %srl = lshr <4 x i16> %x, <i16 2, i16 2, i16 2, i16 2> 320 %zext = zext <4 x i16> %srl to <4 x i32> 321 %shl = shl <4 x i32> %zext, <i32 2, i32 2, i32 2, i32 2> 322 ret <4 x i32> %shl 323} 324 325define <4 x i16> @sra_trunc_srl_v4i32(<4 x i32> %x) nounwind { 326; CHECK-LABEL: sra_trunc_srl_v4i32: 327; CHECK: # BB#0: 328; CHECK-NEXT: psrad $19, %xmm0 329; CHECK-NEXT: retq 330 %srl = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16> 331 %trunc = trunc <4 x i32> %srl to <4 x i16> 332 %sra = ashr <4 x i16> %trunc, <i16 3, i16 3, i16 3, i16 3> 333 ret <4 x i16> %sra 334} 335 336define <4 x i32> @shl_zext_shl_v4i32(<4 x i16> %x) nounwind { 337; CHECK-LABEL: shl_zext_shl_v4i32: 338; CHECK: # BB#0: 339; CHECK-NEXT: pand {{.*}}(%rip), %xmm0 340; CHECK-NEXT: pslld $19, %xmm0 341; CHECK-NEXT: retq 342 %shl0 = shl <4 x i16> %x, <i16 2, i16 2, i16 2, i16 2> 343 %ext = zext <4 x i16> %shl0 to <4 x i32> 344 %shl1 = shl <4 x i32> %ext, <i32 17, i32 17, i32 17, i32 17> 345 ret <4 x i32> %shl1 346} 347 348define <4 x i32> @sra_v4i32(<4 x i32> %x) nounwind { 349; CHECK-LABEL: sra_v4i32: 350; CHECK: # BB#0: 351; CHECK-NEXT: psrad $3, %xmm0 352; CHECK-NEXT: retq 353 %sra = ashr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3> 354 ret <4 x i32> %sra 355} 356 357define <4 x i32> @srl_v4i32(<4 x i32> %x) nounwind { 358; CHECK-LABEL: srl_v4i32: 359; CHECK: # BB#0: 360; CHECK-NEXT: psrld $3, %xmm0 361; CHECK-NEXT: retq 362 %sra = lshr <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3> 363 ret <4 x i32> %sra 364} 365 366define <4 x i32> @shl_v4i32(<4 x i32> %x) nounwind { 367; CHECK-LABEL: shl_v4i32: 368; CHECK: # BB#0: 369; CHECK-NEXT: pslld $3, %xmm0 370; CHECK-NEXT: retq 371 %sra = shl <4 x i32> %x, <i32 3, i32 3, i32 3, i32 3> 372 ret <4 x i32> %sra 373} 374