| /art/compiler/optimizing/ |
| D | intrinsics_mips.cc | 287 __ And(TMP, out, AT); in GenReverse() local
290 __ And(out, out, AT); in GenReverse() local
298 __ And(TMP, out, AT); in GenReverse() local
301 __ And(out, out, AT); in GenReverse() local
304 __ And(TMP, out, AT); in GenReverse() local
307 __ And(out, out, AT); in GenReverse() local
310 __ And(TMP, out, AT); in GenReverse() local
313 __ And(out, out, AT); in GenReverse() local
346 __ And(out_hi, TMP, AT); in GenReverse() local
349 __ And(TMP, TMP, AT); in GenReverse() local
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| D | intrinsics_mips64.cc | 423 __ And(TMP, TMP, AT); in GenBitCount() local
426 __ And(out, TMP, AT); in GenBitCount() local
428 __ And(TMP, TMP, AT); in GenBitCount() local
433 __ And(out, out, AT); in GenBitCount() local
440 __ And(TMP, TMP, AT); in GenBitCount() local
443 __ And(out, TMP, AT); in GenBitCount() local
445 __ And(TMP, TMP, AT); in GenBitCount() local
450 __ And(out, out, AT); in GenBitCount() local
2273 __ And(out, AT, in); in GenHighestOneBit() local
2307 __ And(out, TMP, in); in GenLowestOneBit() local
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| D | code_generator_arm_vixl.cc | 1591 __ And(out, first, second); in GenerateDataProcInstruction() local
4993 __ And(shift_right, RegisterFrom(rhs), 0x1F); in HandleLongRotate() local
5123 __ And(out_reg, second_reg, kMaxIntShiftDistance); in HandleShift() local
5159 __ And(o_l, second_reg, kMaxLongShiftDistance); in HandleShift() local
5178 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift() local
5197 __ And(o_h, second_reg, kMaxLongShiftDistance); in HandleShift() local
8320 __ And(out, first, value); in GenerateAndConst() local
8440 __ And(out_reg, first_reg, second_reg); in HandleBitwiseOperation() local
8456 __ And(out_low, first_low, second_low); in HandleBitwiseOperation() local
8457 __ And(out_high, first_high, second_high); in HandleBitwiseOperation() local
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| D | code_generator_vector_arm64.cc | 620 __ And(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter in VisitVecAnd() local
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| D | intrinsics_arm_vixl.cc | 566 __ And(temp1, temp1, temp2); in GenMinMaxFloat() local
1633 __ And(temp2, temp2, temp3); in VisitStringCompareTo() local
1634 __ And(out, out, temp3); in VisitStringCompareTo() local
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| D | code_generator_mips.cc | 2075 __ And(dst, lhs, rhs_reg); in HandleBinaryOp() local
2112 __ And(dst_low, lhs_low, rhs_low); in HandleBinaryOp() local
2113 __ And(dst_high, lhs_high, rhs_high); in HandleBinaryOp() local
2190 __ And(dst_low, lhs_low, TMP); in HandleBinaryOp() local
2200 __ And(dst_high, lhs_high, TMP); in HandleBinaryOp() local
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| D | code_generator_arm64.cc | 2441 __ And(dst, lhs, rhs); in HandleBinaryOp() local
2636 __ And(out, left, right_operand); in VisitDataProcWithShifterOp() local
3385 __ And(out, out, abs_imm - 1); in DivRemByPowerOfTwo() local
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| D | intrinsics_arm64.cc | 1620 __ And(temp1, temp, Operand(1)); // Extract compression flag. in VisitStringEquals() local
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| D | code_generator_mips64.cc | 1901 __ And(dst, lhs, rhs_reg); in HandleBinaryOp() local
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| /art/test/953-invoke-polymorphic-compiler/src/ |
| D | Main.java | 182 private static boolean And(boolean lhs, boolean rhs) { in And() method in Main
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| /art/compiler/utils/mips/ |
| D | assembler_mips_test.cc | 310 TEST_F(AssemblerMIPSTest, And) { in TEST_F() argument
2498 __ And(mips::T0, mips::T1, mips::T2); in TEST_F() local
2644 __ And(mips::T0, mips::T1, mips::T2); in TEST_F() local
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| D | assembler_mips.cc | 626 void MipsAssembler::And(Register rd, Register rs, Register rt) { in And() function in art::mips::MipsAssembler
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| /art/compiler/utils/mips64/ |
| D | assembler_mips64_test.cc | 1261 TEST_F(AssemblerMIPS64Test, And) { in TEST_F() argument
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| D | assembler_mips64.cc | 375 void Mips64Assembler::And(GpuRegister rd, GpuRegister rs, GpuRegister rt) { in And() function in art::mips64::Mips64Assembler
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