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Searched defs:Lane (Results 1 – 21 of 21) sorted by relevance

/external/llvm/lib/Target/ARM/
DA15SDOptimizer.cpp429 unsigned Lane, bool QPR) { in createDupLane()
446 const DebugLoc &DL, unsigned DReg, unsigned Lane, in createExtractSubreg()
493 const DebugLoc &DL, unsigned DReg, unsigned Lane, unsigned ToInsert) { in createInsertSubreg()
558 unsigned Lane; in optimizeAllLanesPattern() local
DARMBaseInstrInfo.cpp4218 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane()
4249 unsigned Lane, unsigned &ImplicitSReg) { in getImplicitSPRUseForDPRUse()
4277 unsigned Lane; in setExecutionDomain() local
DARMExpandPseudoInsts.cpp525 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); in ExpandLaneOp() local
DARMISelLowering.cpp6233 int Lane = SVN->getSplatIndex(); in LowerVECTOR_SHUFFLE() local
6390 SDValue Lane = Op.getOperand(2); in LowerINSERT_VECTOR_ELT() local
6399 SDValue Lane = Op.getOperand(1); in LowerEXTRACT_VECTOR_ELT() local
10757 SDValue Lane = N0.getOperand(1); in PerformExtendCombine() local
DARMISelDAGToDAG.cpp2109 unsigned Lane = in SelectVLDSTLane() local
/external/llvm/lib/Target/AMDGPU/
DSIMachineFunctionInfo.cpp200 unsigned Lane = (Offset / 4) % 64; in getSpilledReg() local
DSIMachineFunctionInfo.h125 int Lane; member
DSIISelLowering.cpp3107 unsigned Lane = 0; in adjustWritemask() local
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMExpandPseudoInsts.cpp535 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); in ExpandLaneOp() local
1040 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1; in ExpandMI() local
DARMCodeEmitter.cpp1830 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift; in emitNEONLaneInstruction() local
DARMISelLowering.cpp4346 int Lane = SVN->getSplatIndex(); in LowerVECTOR_SHUFFLE() local
4455 SDValue Lane = Op.getOperand(1); in LowerEXTRACT_VECTOR_ELT() local
7748 SDValue Lane = N0.getOperand(1); in PerformExtendCombine() local
DARMISelDAGToDAG.cpp1830 unsigned Lane = in SelectVLDSTLane() local
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3063 unsigned Lane = MI.getOperand(2).getImm(); in emitCOPY_FW() local
3108 unsigned Lane = MI.getOperand(2).getImm() * 2; in emitCOPY_FD() local
3138 unsigned Lane = MI.getOperand(2).getImm(); in emitINSERT_FW() local
3174 unsigned Lane = MI.getOperand(2).getImm(); in emitINSERT_FD() local
/external/llvm/lib/Transforms/Vectorize/
DSLPVectorizer.cpp501 int Lane; member
924 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) { in buildTree() local
2149 for (unsigned Lane = 0, LE = VL.size(); Lane != LE; ++Lane) { in Gather() local
2636 Value *Lane = Builder.getInt32(ExternalUse.Lane); in vectorizeTree() local
2683 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) { in vectorizeTree() local
/external/llvm/lib/Analysis/
DConstantFolding.cpp1850 SmallVector<Constant *, 4> Lane(Operands.size()); in ConstantFoldVectorCall() local
/external/gemmlowp/meta/generators/
Dneon_emitter.py825 def Lane(self, bits, value, lane): member in NeonEmitter
Dneon_emitter_64.py1267 def Lane(self, bits, value, lane): member in NeonEmitter64
/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp5472 SDValue Lane = DAG.getConstant(OpNum - OP_VDUP0, dl, MVT::i64); in GeneratePerfectShuffle() local
5595 int Lane = SVN->getSplatIndex(); in LowerVECTOR_SHUFFLE() local
6058 for (SDValue Lane : Op->ops()) { in NormalizeBuildVector() local
6349 SDValue Lane = Value.getOperand(1); in LowerBUILD_VECTOR() local
8146 SDValue Lane = Op1.getOperand(1); in tryCombineFixedPointConvert() local
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp2289 int Lane = SVN->getSplatIndex(); in LowerVECTOR_SHUFFLE() local
/external/clang/lib/CodeGen/
DCGBuiltin.cpp4455 uint32_t Lane = cast<ConstantInt>(Ops[2])->getZExtValue(); in EmitARMBuiltinExpr() local
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp11102 int Lane = i / NumLaneElts; in lowerShuffleAsRepeatedMaskAndLanePermute() local