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Searched defs:Opc (Results 1 – 25 of 232) sorted by relevance

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/external/llvm/lib/Target/ARM/
DARMBaseInstrInfo.h420 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
425 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
430 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
436 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
440 static inline bool isPopOpcode(int Opc) { in isPopOpcode()
446 static inline bool isPushOpcode(int Opc) { in isPushOpcode()
DARMISelDAGToDAG.cpp112 SDValue &Opc) { in SelectAddrMode2Base()
117 SDValue &Opc) { in SelectAddrMode2ShOp()
122 SDValue &Opc) { in SelectAddrMode2()
308 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { in isOpcWithIntImmediate()
533 SDValue &Opc, in SelectImmShifterOperand()
573 SDValue &Opc, in SelectRegShifterOperand()
652 SDValue &Opc) { in SelectLdStSOReg()
763 SDValue &Opc) { in SelectAddrMode2Worker()
900 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetReg()
936 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetImmPre()
[all …]
DARMFastISel.cpp436 unsigned Opc; in ARMMaterializeFP() local
461 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
480 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
496 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local
564 unsigned Opc; in ARMMaterializeGV() local
597 unsigned Opc = IsPositionIndependent ? ARM::t2LDRpci_pic : ARM::t2LDRpci; in ARMMaterializeGV() local
613 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; in ARMMaterializeGV() local
678 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in fastMaterializeAlloca() local
856 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress() local
921 unsigned Opc; in ARMEmitLoad() local
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/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.h258 static inline bool isUncondBranchOpcode(int Opc) { return Opc == AArch64::B; } in isUncondBranchOpcode()
260 static inline bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
277 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == AArch64::BR; } in isIndirectBranchOpcode()
DAArch64LoadStoreOptimizer.cpp199 static bool isNarrowStore(unsigned Opc) { in isNarrowStore()
211 static bool isNarrowLoad(unsigned Opc) { in isNarrowLoad()
231 static bool isNarrowLoadOrStore(unsigned Opc) { in isNarrowLoadOrStore()
293 static unsigned getMatchingNonSExtOpcode(unsigned Opc, in getMatchingNonSExtOpcode()
346 static unsigned getMatchingWideOpcode(unsigned Opc) { in getMatchingWideOpcode()
377 static unsigned getMatchingPairOpcode(unsigned Opc) { in getMatchingPairOpcode()
447 static unsigned getPreIndexedOpcode(unsigned Opc) { in getPreIndexedOpcode()
506 static unsigned getPostIndexedOpcode(unsigned Opc) { in getPostIndexedOpcode()
617 static bool isPromotableZeroStoreOpcode(unsigned Opc) { in isPromotableZeroStoreOpcode()
643 unsigned Opc = I->getOpcode(); in mergeNarrowInsns() local
[all …]
DAArch64ConditionOptimizer.cpp206 static int getComplementOpc(int Opc) { in getComplementOpc()
233 unsigned Opc = CmpMI->getOpcode(); in adjustCmp() local
262 unsigned Opc; in modifyCmp() local
DAArch64ISelDAGToDAG.cpp227 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc, in isOpcWithIntImmediate()
1019 void AArch64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectTable()
1134 void AArch64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc, in SelectLoad()
1156 unsigned Opc, unsigned SubRegIdx) { in SelectPostLoad()
1188 unsigned Opc) { in SelectStore()
1204 unsigned Opc) { in SelectPostStore()
1260 unsigned Opc) { in SelectLoadLane()
1299 unsigned Opc) { in SelectPostLoadLane()
1354 unsigned Opc) { in SelectStoreLane()
1384 unsigned Opc) { in SelectPostStoreLane()
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrInfo.cpp51 unsigned Opc = MI->getOpcode(); in isLoadFromStackSlot() local
76 unsigned Opc = MI->getOpcode(); in isStoreToStackSlot() local
106 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
172 unsigned Opc = 0; in storeRegToStackSlot() local
198 unsigned Opc = 0; in loadRegFromStackSlot() local
228 static unsigned GetAnalyzableBrOpc(unsigned Opc) { in GetAnalyzableBrOpc()
239 unsigned Mips::GetOppositeBranchOpc(unsigned Opc) in GetOppositeBranchOpc()
260 static void AnalyzeCondBr(const MachineInstr* Inst, unsigned Opc, in AnalyzeCondBr()
359 unsigned Opc = Cond[0].getImm(); in BuildCondBr() local
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMBaseInstrInfo.h315 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode()
320 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode()
325 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode()
331 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode()
DARMISelDAGToDAG.cpp120 SDValue &Opc) { in SelectAddrMode2Base()
125 SDValue &Opc) { in SelectAddrMode2ShOp()
130 SDValue &Opc) { in SelectAddrMode2()
307 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) { in isOpcWithIntImmediate()
392 SDValue &Opc, in SelectImmShifterOperand()
416 SDValue &Opc, in SelectRegShifterOperand()
492 SDValue &Opc) { in SelectLdStSOReg()
592 SDValue &Opc) { in SelectAddrMode2Worker()
725 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetReg()
761 SDValue &Offset, SDValue &Opc) { in SelectAddrMode2OffsetImmPre()
[all …]
DARMFastISel.cpp506 unsigned Opc; in ARMMaterializeFP() local
532 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local
553 unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local
610 unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; in ARMMaterializeGV() local
674 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; in TargetMaterializeAlloca() local
860 unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri; in ARMSimplifyAddress() local
920 unsigned Opc; in ARMEmitLoad() local
985 unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri; in ARMEmitStore() local
1345 unsigned Opc; in SelectSIToFP() local
1370 unsigned Opc; in SelectFPToSI() local
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonCFGOptimizer.cpp61 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch()
67 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump()
115 int Opc = MI.getOpcode(); in runOnMachineFunction() local
DHexagonGenPredicate.cpp118 unsigned HexagonGenPredicate::getPredForm(unsigned Opc) { in getPredForm()
164 unsigned Opc = MI->getOpcode(); in isConvertibleToPredForm() local
188 unsigned Opc = MI->getOpcode(); in collectPredicateGPR() local
236 unsigned Opc = DefI->getOpcode(); in getPredRegFor() local
265 bool HexagonGenPredicate::isScalarCmp(unsigned Opc) { in isScalarCmp()
351 unsigned Opc = MI->getOpcode(); in convertToPredForm() local
DHexagonBitSimplify.cpp414 bool HexagonBitSimplify::getUsedBitsInStore(unsigned Opc, BitVector &Bits, in getUsedBitsInStore()
574 bool HexagonBitSimplify::getUsedBits(unsigned Opc, unsigned OpN, in getUsedBits()
949 unsigned Opc = MI->getOpcode(); in runOnNode() local
1028 unsigned Opc = MI.getOpcode(); in isLossyShiftLeft() local
1088 unsigned Opc = MI.getOpcode(); in isLossyShiftRight() local
1198 unsigned Opc = MI.getOpcode(); in computeUsedBits() local
1350 unsigned Opc = MI.getOpcode(); in isTfrConst() local
1386 unsigned Opc = isInt<8>(Lo) ? Hexagon::A2_combineii in genTfrConst() local
1400 unsigned Opc; in genTfrConst() local
1545 unsigned Opc = I->getOpcode(); in processBlock() local
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp43 unsigned Opc = MI.getOpcode(); in isLoadFromStackSlot() local
65 unsigned Opc = MI.getOpcode(); in isStoreToStackSlot() local
83 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
190 unsigned Opc = 0; in storeRegToStack() local
258 unsigned Opc = 0; in loadRegFromStack() local
334 unsigned Opc; in expandPostRAPseudo() local
454 unsigned Opc = ABI.GetPtrAdduOp(); in adjustStackPtr() local
537 MipsSEInstrInfo::compareOpndSize(unsigned Opc, in compareOpndSize()
DMipsAnalyzeImmediate.h20 unsigned Opc, ImmOpnd; member
DMips16InstrInfo.cpp63 unsigned Opc = 0; in copyPhysReg() local
100 unsigned Opc = 0; in storeRegToStack() local
118 unsigned Opc = 0; in loadRegFromStack() local
203 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? Mips::Save16:Mips::SaveX16; in makeFrame() local
233 unsigned Opc = ((FrameSize <= 128) && !SaveS2)? in restoreFrame() local
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp331 unsigned Opc = Subtarget->hasAddr64() ? in materializeLoadStoreOperands() local
531 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeAlloca() local
547 unsigned Opc = Subtarget->hasAddr64() ? in fastMaterializeConstant() local
581 unsigned Opc; in fastLowerArguments() local
635 unsigned Opc; in selectCall() local
735 unsigned Opc; in selectSelect() local
822 unsigned Opc; in selectICmp() local
890 unsigned Opc; in selectFCmp() local
982 unsigned Opc; in selectLoad() local
1035 unsigned Opc; in selectStore() local
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrInfo.cpp1276 unsigned Opc = Orig->getOpcode(); in reMaterialize() local
1336 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() in convertToThreeAddressWithLEA() local
1503 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
1539 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r in convertToThreeAddress() local
1569 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r in convertToThreeAddress() local
1599 unsigned Opc; in convertToThreeAddress() local
1656 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
1704 unsigned Opc; in commuteInstruction() local
1773 unsigned Opc = 0; in commuteInstruction() local
2118 unsigned Opc = GetCondBranchFromCond(CC); in InsertBranch() local
[all …]
DX86FastISel.cpp179 unsigned Opc = 0; in X86FastEmitLoad() local
237 unsigned Opc = 0; in X86FastEmitStore() local
276 unsigned Opc = 0; in X86FastEmitStore() local
310 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend()
526 unsigned Opc = 0; in X86SelectAddress() local
1203 unsigned Opc = 0; in X86SelectSelect() local
1473 unsigned Opc = X86::SETBr; in X86VisitIntrinsicCall() local
1898 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; in DoSelectCall() local
1975 unsigned Opc = 0; in TargetMaterializeConstant() local
2083 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; in TargetMaterializeAlloca() local
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DX86FrameLowering.cpp103 unsigned Opc = MBBI->getOpcode(); in findDeadCallerSavedReg() local
148 unsigned Opc = isSub ? in emitSPUpdate() local
192 unsigned Opc = PI->getOpcode(); in mergeSPUpdatesUp() local
221 unsigned Opc = NI->getOpcode(); in mergeSPUpdatesDown() local
253 unsigned Opc = PI->getOpcode(); in mergeSPUpdates() local
498 unsigned Opc = MI.getOpcode(); in getCompactUnwindEncoding() local
989 unsigned Opc = PI->getOpcode(); in emitEpilogue() local
1021 unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; in emitEpilogue() local
1168 unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r; in spillCalleeSavedRegisters() local
1229 unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r; in restoreCalleeSavedRegisters() local
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrInfo.cpp51 unsigned Opc = 0; in storeRegToStackSlot() local
81 unsigned Opc = 0; in loadRegFromStackSlot() local
106 unsigned Opc; in copyPhysReg() local
/external/llvm/lib/Target/X86/
DX86FastISel.cpp357 unsigned Opc = 0; in X86FastEmitLoad() local
510 unsigned Opc = 0; in X86FastEmitStore() local
658 unsigned Opc = 0; in X86FastEmitStore() local
695 bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, in X86FastEmitExtend()
756 unsigned Opc = 0; in handleConstantAddresses() local
1491 unsigned Opc = X86::getSETFromCond(CC); in X86SelectCmp() local
2044 unsigned Opc = X86::getCMovFromCond(CC, RC->getSize()); in X86FastEmitCMoveSelect() local
2097 unsigned *Opc = nullptr; in X86FastEmitSSESelect() local
2163 unsigned Opc; in X86FastEmitPseudoSelect() local
2335 unsigned Opc = Subtarget->hasAVX() ? X86::VCVTSS2SDrr : X86::CVTSS2SDrr; in X86SelectFPExt() local
[all …]
DX86InstrInfo.cpp2566 unsigned Opc, bool AllowSP, unsigned &NewSrc, in classifyLEAReg()
2649 unsigned Opc, leaInReg; in convertToThreeAddressWithLEA() local
2800 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
2844 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r in convertToThreeAddress() local
2877 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r in convertToThreeAddress() local
2913 unsigned Opc; in convertToThreeAddress() local
2988 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r; in convertToThreeAddress() local
3203 unsigned Opc; in commuteInstructionImpl() local
3335 unsigned Opc; in commuteInstructionImpl() local
3394 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2); in commuteInstructionImpl() local
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeISelDAGToDAG.cpp101 unsigned Opc = N->getOpcode(); in isIntS32Immediate() local
213 unsigned Opc = MBlaze::ADDIK; in Select() local

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