/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | Thumb2InstrInfo.cpp | 55 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local 103 unsigned PredReg = 0; in isLegalToSplitMBBAt() local 177 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() 400 unsigned PredReg; in rewriteT2FrameIndex() local 572 unsigned PredReg = 0; in scheduleTwoAddrSource() local 606 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getITInstrPredicate()
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D | Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool()
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D | ARMLoadStoreOptimizer.cpp | 293 unsigned PredReg, unsigned Scratch, DebugLoc dl, in MergeOps() 373 ARMCC::CondCodes Pred, unsigned PredReg, in MergeOpsUpdate() 440 ARMCC::CondCodes Pred, unsigned PredReg, in MergeLDR_STR() 511 ARMCC::CondCodes Pred, unsigned PredReg){ in isMatchingDecrement() 534 ARMCC::CondCodes Pred, unsigned PredReg){ in isMatchingIncrement() 688 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local 843 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local 1051 ARMCC::CondCodes Pred, unsigned PredReg, in InsertLDR_STR() 1097 unsigned PredReg = 0; in FixInvalidRegPairOp() local 1208 unsigned PredReg = 0; in LoadStoreMultipleOpti() local [all …]
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D | ARMBaseRegisterInfo.cpp | 804 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() 838 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitSPUpdate() 878 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local 882 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local 1204 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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D | Thumb2SizeReduction.cpp | 533 unsigned PredReg = 0; in ReduceSpecial() local 614 unsigned PredReg = 0; in ReduceTo2Addr() local 705 unsigned PredReg = 0; in ReduceToNarrow() local
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D | Thumb2ITBlockPass.cpp | 172 unsigned PredReg = 0; in InsertITInstructions() local
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D | Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool() 412 unsigned PredReg; in rewriteFrameIndex() local
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D | MLxExpansionPass.cpp | 219 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
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D | ARMISelDAGToDAG.cpp | 2427 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local 2659 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local 2678 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local 2697 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
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D | ARMConstantIslandPass.cpp | 1228 unsigned PredReg = 0; in CreateNewWater() local 1654 unsigned PredReg = 0; in OptimizeThumb2Branches() local
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D | ARMExpandPseudoInsts.cpp | 647 unsigned PredReg = 0; in ExpandMOV32BitImm() local
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/external/llvm/lib/Target/ARM/ |
D | Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local 108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local 225 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() 468 unsigned PredReg; in rewriteT2FrameIndex() local 638 unsigned &PredReg) { in getITInstrPredicate()
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D | ARMLoadStoreOptimizer.cpp | 460 unsigned PredReg) { in UpdateBaseRegUses() 596 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreMulti() 793 ARMCC::CondCodes Pred, unsigned PredReg, const DebugLoc &DL, in CreateLoadStoreDouble() 860 unsigned PredReg = 0; in MergeOpsUpdate() local 1127 ARMCC::CondCodes Pred, unsigned PredReg) { in isIncrementOrDecrement() 1157 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecBefore() 1177 ARMCC::CondCodes Pred, unsigned PredReg, int &Offset) { in findIncDecAfter() 1211 unsigned PredReg = 0; in MergeBaseUpdateLSMultiple() local 1353 unsigned PredReg = 0; in MergeBaseUpdateLoadStore() local 1450 unsigned PredReg; in MergeBaseUpdateLSDouble() local [all …]
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D | Thumb2SizeReduction.cpp | 441 unsigned PredReg = MI->getOperand(5).getReg(); in ReduceLoadStore() local 647 unsigned PredReg = 0; in ReduceSpecial() local 752 unsigned PredReg = 0; in ReduceTo2Addr() local 848 unsigned PredReg = 0; in ReduceToNarrow() local
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D | ThumbRegisterInfo.cpp | 66 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb1LoadConstPool() 86 ARMCC::CondCodes Pred, unsigned PredReg, in emitThumb2LoadConstPool() 106 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool()
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D | Thumb2ITBlockPass.cpp | 189 unsigned PredReg = 0; in InsertITInstructions() local
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D | ARMFrameLowering.cpp | 126 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitRegPlusImmediate() 140 unsigned PredReg = 0) { in emitSPUpdate() 1772 unsigned PredReg = Old.getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local 1777 unsigned PredReg = Old.getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
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D | ARMBaseRegisterInfo.cpp | 414 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() 764 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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D | MLxExpansionPass.cpp | 285 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
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D | ARMBaseInstrInfo.cpp | 1720 unsigned PredReg = 0; in isProfitableToIfCvt() local 1777 unsigned &PredReg) { in getInstrPredicate() 1808 unsigned PredReg = 0; in commuteInstructionImpl() local 2001 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate()
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
D | HexagonMCDuplexInfo.cpp | 178 unsigned DstReg, PredReg, SrcReg, Src1Reg, Src2Reg; in getDuplexCandidateGroup() local
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D | HexagonMCCompound.cpp | 182 unsigned PredReg = Predicate.getReg(); in getCompoundOp() local
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D | HexagonMCChecker.h | 98 unsigned PredReg; member
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D | HexagonMCChecker.cpp | 58 unsigned PredReg = Hexagon::NoRegister; in init() local
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonGenPredicate.cpp | 302 bool HexagonGenPredicate::isScalarPred(Register PredReg) { in isScalarPred()
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